2 * SMSC 91C111 Ethernet interface emulation
4 * Copyright (c) 2005 CodeSourcery, LLC.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
13 #include "hw/devices.h"
18 /* Number of 2k memory pages available. */
22 # define logout(fmt, ...) \
23 fprintf(stderr, "SMC91C111\t%-24s %s:%u " fmt, __func__, __FILE__, __LINE__, ##__VA_ARGS__)
25 # define logout(fmt, ...) (void)0
43 /* PHY Register Addresses (LAN91C111 Internal PHY) */
45 /* PHY Configuration Register 1 */
46 #define PHY_CFG1_REG 0x10
47 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
48 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
49 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
50 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
51 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
52 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
53 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
54 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
55 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
56 #define PHY_CFG1_TLVL_MASK 0x003C
57 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
59 /* PHY Configuration Register 2 */
60 #define PHY_CFG2_REG 0x11
61 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
62 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
63 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
64 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
66 /* PHY Status Output (and Interrupt status) Register */
67 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
68 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
69 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
70 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
71 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
72 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
73 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
74 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
75 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
76 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
77 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
79 /* PHY Interrupt/Status Mask Register */
80 #define PHY_MASK_REG 0x13 /* Interrupt Mask */
81 /* Uses the same bit definitions as PHY_INT_REG */
95 /* Declarations from include/linux/mii.h. */
97 /* Generic MII registers. */
99 #define MII_BMCR 0x00 /* Basic mode control register */ // rw
100 #define MII_BMSR 0x01 /* Basic mode status register */ // r
101 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
102 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
103 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ // rw
104 #define MII_LPA 0x05 /* Link partner ability reg */
105 #define MII_EXPANSION 0x06 /* Expansion register */
106 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
107 #define MII_STAT1000 0x0a /* 1000BASE-T status */
108 #define MII_ESTATUS 0x0f /* Extended Status */
109 #define MII_DCOUNTER 0x12 /* Disconnect counter */
110 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
111 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
112 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
113 #define MII_SREVISION 0x16 /* Silicon revision */
114 #define MII_RESV1 0x17 /* Reserved... */
115 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
116 #define MII_PHYADDR 0x19 /* PHY address */
117 #define MII_RESV2 0x1a /* Reserved... */
118 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
119 #define MII_NCONFIG 0x1c /* Network interface config */
121 /* Basic mode control register. */
122 #define BMCR_RESV 0x003f /* Unused... */
123 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
124 #define BMCR_CTST 0x0080 /* Collision test */
125 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
126 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
127 #define BMCR_ISOLATE 0x0400 /* Disconnect PHY from MII */
128 #define BMCR_PDOWN 0x0800 /* Powerdown the */
129 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
130 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
131 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
132 #define BMCR_RESET 0x8000 /* Reset the PHY */
134 /* Basic mode status register. */
135 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
136 #define BMSR_JCD 0x0002 /* Jabber detected */
137 #define BMSR_LSTATUS 0x0004 /* Link status */
138 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
139 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
140 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
141 #define BMSR_RESV 0x00c0 /* Unused... */
142 #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
143 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
144 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
145 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
146 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
147 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
148 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
149 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
151 //~ #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
153 /* Advertisement control register. */
154 #define ADVERTISE_SLCT 0x001f /* Selector bits */
155 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
156 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
157 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
158 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
159 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
160 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
161 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
162 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
163 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
164 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
165 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
166 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
167 #define ADVERTISE_RESV 0x1000 /* Unused... */
168 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
169 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
170 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
172 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
174 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
175 ADVERTISE_100HALF | ADVERTISE_100FULL)
177 /* Link partner ability register. */
178 #define LPA_SLCT 0x001f /* Same as advertise selector */
179 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
180 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
181 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
182 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
183 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
184 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
185 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
186 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
187 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
188 #define LPA_PAUSE_CAP 0x0400 /* Can pause */
189 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
190 #define LPA_RESV 0x1000 /* Unused... */
191 #define LPA_RFAULT 0x2000 /* Link partner faulted */
192 #define LPA_LPACK 0x4000 /* Link partner acked us */
193 #define LPA_NPAGE 0x8000 /* Next page bit */
195 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
196 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
198 /* End of declarations from include/linux/mii.h. */
200 /* SMC 91C111 specific MII register. */
202 /* 0x06 ... 0x0f are reserved. */
203 #define MII_CONFIGURATION1 0x10 /* Configuration 1 */
204 #define MII_CONFIGURATION2 0x11 /* Configuration 2 */
205 #define MII_STATUSOUTPUT 0x12 /* Status Output */
206 //~ PHY_FCSCR = 0x13, /* Mask */
207 /* 0x14 is reserved. */
208 /* 0x15 ... 0x1f are unused. */
211 /* Default values for MII management registers (see IEEE 802.3-2008 22.2.4). */
213 static const uint16_t mii_regs_default
[] = {
214 [MII_BMCR
] = BMCR_ANENABLE
| BMCR_SPEED100
,
215 [MII_BMSR
] = BMSR_100FULL
| BMSR_100HALF
| BMSR_10FULL
| BMSR_10HALF
|
216 BMSR_ANEGCAPABLE
| BMSR_LSTATUS
| BMSR_ERCAP
,
217 [MII_ADVERTISE
] = ADVERTISE_PAUSE_CAP
| ADVERTISE_ALL
| ADVERTISE_CSMA
,
220 #define TYPE_SMC91C111 "smc91c111"
221 #define SMC91C111(obj) OBJECT_CHECK(smc91c111_state, (obj), TYPE_SMC91C111)
224 SysBusDevice parent_obj
;
239 /* Bitmask of allocated packets. */
242 int tx_fifo
[NUM_PACKETS
];
244 int rx_fifo
[NUM_PACKETS
];
245 int tx_fifo_done_len
;
246 int tx_fifo_done
[NUM_PACKETS
];
247 /* Packet buffer memory. */
248 uint8_t data
[NUM_PACKETS
][2048];
254 static const VMStateDescription vmstate_smc91c111
= {
257 .minimum_version_id
= 1,
258 .fields
= (VMStateField
[]) {
259 VMSTATE_UINT16(tcr
, smc91c111_state
),
260 VMSTATE_UINT16(rcr
, smc91c111_state
),
261 VMSTATE_UINT16(cr
, smc91c111_state
),
262 VMSTATE_UINT16(ctr
, smc91c111_state
),
263 VMSTATE_UINT16(gpr
, smc91c111_state
),
264 VMSTATE_UINT16(ptr
, smc91c111_state
),
265 VMSTATE_UINT16(ercv
, smc91c111_state
),
266 VMSTATE_INT32(bank
, smc91c111_state
),
267 VMSTATE_INT32(packet_num
, smc91c111_state
),
268 VMSTATE_INT32(tx_alloc
, smc91c111_state
),
269 VMSTATE_INT32(allocated
, smc91c111_state
),
270 VMSTATE_INT32(tx_fifo_len
, smc91c111_state
),
271 VMSTATE_INT32_ARRAY(tx_fifo
, smc91c111_state
, NUM_PACKETS
),
272 VMSTATE_INT32(rx_fifo_len
, smc91c111_state
),
273 VMSTATE_INT32_ARRAY(rx_fifo
, smc91c111_state
, NUM_PACKETS
),
274 VMSTATE_INT32(tx_fifo_done_len
, smc91c111_state
),
275 VMSTATE_INT32_ARRAY(tx_fifo_done
, smc91c111_state
, NUM_PACKETS
),
276 VMSTATE_BUFFER_UNSAFE(data
, smc91c111_state
, 0, NUM_PACKETS
* 2048),
277 VMSTATE_UINT8(int_level
, smc91c111_state
),
278 VMSTATE_UINT8(int_mask
, smc91c111_state
),
279 VMSTATE_END_OF_LIST()
283 #define RCR_SOFT_RST 0x8000
284 #define RCR_STRIP_CRC 0x0200
285 #define RCR_RXEN 0x0100
287 #define TCR_EPH_LOOP 0x2000
288 #define TCR_NOCRC 0x0100
289 #define TCR_PAD_EN 0x0080
290 #define TCR_FORCOL 0x0004
291 #define TCR_LOOP 0x0002
292 #define TCR_TXEN 0x0001
295 #define INT_ERCV 0x40
297 #define INT_RX_OVRN 0x10
298 #define INT_ALLOC 0x08
299 #define INT_TX_EMPTY 0x04
303 #define CTR_AUTO_RELEASE 0x0800
304 #define CTR_RELOAD 0x0002
305 #define CTR_STORE 0x0001
307 #define RS_ALGNERR 0x8000
308 #define RS_BRODCAST 0x4000
309 #define RS_BADCRC 0x2000
310 #define RS_ODDFRAME 0x1000
311 #define RS_TOOLONG 0x0800
312 #define RS_TOOSHORT 0x0400
313 #define RS_MULTICAST 0x0001
315 static void mii_write(MII
*mii
, uint32_t value
)
318 A timing diagram for a Ml serial port frame is shown in Figure 7.1. The Ml serial port is idle when at
319 least 32 continuous 1's are detected on MDIO and remains idle as long as continuous 1's are detected.
320 During idle, MDIO is in the high impedance state. When the Ml serial port is in the idle state, a 01
321 pattern on the MDIO initiates a serial shift cycle. Data on MDIO is then shifted in on the next 14 rising
322 edges of MDC (MDIO is high impedance). If the register access mode is not enabled, on the next 16
323 rising edges of MDC, data is either shifted in or out on MDIO, depending on whether a write or read
324 cycle was selected with the bits READ and WRITE. After the 32 MDC cycles have been completed,
325 one complete register has been read/written, the serial shift process is halted, data is latched into the
326 device, and MDIO goes into high impedance state. Another serial shift cycle cannot be initiated until
327 the idle condition (at least 32 continuous 1's) is detected.
329 bool clock
= !mii
->mclk
&& (value
& 4);
331 assert((value
& 0xfffffff0) == 0x30);
335 mii
->mdi
= value
& MII_MDI
;
336 mii
->mdoe
= value
& MII_MDOE
;
337 mii
->mdo
= value
& MII_MDO
;
338 mii
->data
= (mii
->data
<< 1) + (value
& 1);
339 logout("%u%u%u%u %08x\n",
340 mii
->mdoe
? 1 : 0, mii
->mclk
? 1 : 0,
341 mii
->mdi
? 1 : 0, mii
->mdo
? 1 : 0,
343 switch (mii
->status
) {
345 if (mii
->data
== 0xffffffff) {
346 logout("mii is idle\n");
348 mii
->status
= MII_IDLE
;
352 if (mii
->data
== 0xfffffffd) {
353 logout("mii got start bit pattern 01\n");
354 mii
->status
= MII_GOT_START
;
358 if ((mii
->data
& 0xffffc000) == 0xffff4000) {
359 unsigned op
= (mii
->data
>> 12) & 0x3;
360 unsigned phy
= (mii
->data
>> 7) & 0x1f;
361 unsigned reg
= (mii
->data
>> 2) & 0x1f;
362 logout("mii got 14 bits (op=%u, phy=%u, reg=%u, ta=%u)\n",
363 op
, phy
, reg
, mii
->data
& 0x3);
366 logout("Wrong phy %u, wait for idle\n", phy
);
367 mii
->status
= MII_WAITING
;
368 } else if (reg
>= ARRAY_SIZE(mii
->regs
)) {
369 logout("Wrong reg %u, wait for idle\n", reg
);
370 mii
->status
= MII_WAITING
;
371 } else if (op
== 1) {
372 mii
->status
= MII_WRITE
;
373 } else if (op
== 2) {
374 mii
->data
= mii
->regs
[reg
];
376 mii
->status
= MII_READ
;
378 logout("Illegal MII operation %u, wait for idle\n", op
);
379 mii
->status
= MII_WAITING
;
384 if ((mii
->data
& 0xc0000000) == 0x40000000) {
385 uint16_t data
= mii
->data
& 0xffff;
386 logout("mii wrote 16 bits (data=0x%04x=%u)\n", data
, data
);
387 mii
->regs
[mii
->reg
] = data
;
388 mii
->status
= MII_WAITING
;
392 if ((mii
->data
& 0x0000ffff) == 0x0000ffff) {
393 logout("mii read 16 bits\n");
395 mii
->status
= MII_WAITING
;
398 mii
->mdi
= (mii
->data
& 0x00010000) ? MII_MDI
: 0;
403 mii
->mclk
= value
& MII_MCLK
;
404 //~ assert(mii->mdoe);
407 static void mii_reset(MII
*mii
)
409 memcpy(mii
->regs
, mii_regs_default
, sizeof(mii
->regs
));
412 /* Update interrupt status. */
413 static void smc91c111_update(smc91c111_state
*s
)
417 if (s
->tx_fifo_len
== 0)
418 s
->int_level
|= INT_TX_EMPTY
;
419 if (s
->tx_fifo_done_len
!= 0)
420 s
->int_level
|= INT_TX
;
421 level
= (s
->int_level
& s
->int_mask
) != 0;
422 qemu_set_irq(s
->irq
, level
);
425 static int smc91c111_can_receive(smc91c111_state
*s
)
427 if ((s
->rcr
& RCR_RXEN
) == 0 || (s
->rcr
& RCR_SOFT_RST
)) {
430 if (s
->allocated
== (1 << NUM_PACKETS
) - 1 ||
431 s
->rx_fifo_len
== NUM_PACKETS
) {
437 static inline void smc91c111_flush_queued_packets(smc91c111_state
*s
)
439 if (smc91c111_can_receive(s
)) {
440 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
444 /* Try to allocate a packet. Returns 0x80 on failure. */
445 static int smc91c111_allocate_packet(smc91c111_state
*s
)
448 if (s
->allocated
== (1 << NUM_PACKETS
) - 1) {
452 for (i
= 0; i
< NUM_PACKETS
; i
++) {
453 if ((s
->allocated
& (1 << i
)) == 0)
456 s
->allocated
|= 1 << i
;
461 /* Process a pending TX allocate. */
462 static void smc91c111_tx_alloc(smc91c111_state
*s
)
464 s
->tx_alloc
= smc91c111_allocate_packet(s
);
465 if (s
->tx_alloc
== 0x80)
467 s
->int_level
|= INT_ALLOC
;
471 /* Remove and item from the RX FIFO. */
472 static void smc91c111_pop_rx_fifo(smc91c111_state
*s
)
477 if (s
->rx_fifo_len
) {
478 for (i
= 0; i
< s
->rx_fifo_len
; i
++)
479 s
->rx_fifo
[i
] = s
->rx_fifo
[i
+ 1];
480 s
->int_level
|= INT_RCV
;
482 s
->int_level
&= ~INT_RCV
;
484 smc91c111_flush_queued_packets(s
);
488 /* Remove an item from the TX completion FIFO. */
489 static void smc91c111_pop_tx_fifo_done(smc91c111_state
*s
)
493 if (s
->tx_fifo_done_len
== 0)
495 s
->tx_fifo_done_len
--;
496 for (i
= 0; i
< s
->tx_fifo_done_len
; i
++)
497 s
->tx_fifo_done
[i
] = s
->tx_fifo_done
[i
+ 1];
500 /* Release the memory allocated to a packet. */
501 static void smc91c111_release_packet(smc91c111_state
*s
, int packet
)
503 s
->allocated
&= ~(1 << packet
);
504 if (s
->tx_alloc
== 0x80)
505 smc91c111_tx_alloc(s
);
506 smc91c111_flush_queued_packets(s
);
509 /* Flush the TX FIFO. */
510 static void smc91c111_do_tx(smc91c111_state
*s
)
518 if ((s
->tcr
& TCR_TXEN
) == 0)
520 if (s
->tx_fifo_len
== 0)
522 for (i
= 0; i
< s
->tx_fifo_len
; i
++) {
523 packetnum
= s
->tx_fifo
[i
];
524 p
= &s
->data
[packetnum
][0];
525 /* Set status word. */
529 len
|= ((int)*(p
++)) << 8;
531 control
= p
[len
+ 1];
534 /* ??? This overwrites the data following the buffer.
535 Don't know what real hardware does. */
536 if (len
< 64 && (s
->tcr
& TCR_PAD_EN
)) {
537 memset(p
+ len
, 0, 64 - len
);
544 /* The card is supposed to append the CRC to the frame.
545 However none of the other network traffic has the CRC
546 appended. Suspect this is low level ethernet detail we
547 don't need to worry about. */
548 add_crc
= (control
& 0x10) || (s
->tcr
& TCR_NOCRC
) == 0;
552 crc
= crc32(~0, p
, len
);
553 memcpy(p
+ len
, &crc
, 4);
558 if (s
->ctr
& CTR_AUTO_RELEASE
)
560 smc91c111_release_packet(s
, packetnum
);
561 else if (s
->tx_fifo_done_len
< NUM_PACKETS
)
562 s
->tx_fifo_done
[s
->tx_fifo_done_len
++] = packetnum
;
563 qemu_send_packet(qemu_get_queue(s
->nic
), p
, len
);
569 /* Add a packet to the TX FIFO. */
570 static void smc91c111_queue_tx(smc91c111_state
*s
, int packet
)
572 if (s
->tx_fifo_len
== NUM_PACKETS
)
574 s
->tx_fifo
[s
->tx_fifo_len
++] = packet
;
578 static void smc91c111_reset(DeviceState
*dev
)
580 smc91c111_state
*s
= SMC91C111(dev
);
584 s
->tx_fifo_done_len
= 0;
595 s
->int_level
= INT_TX_EMPTY
;
601 #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
602 #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
604 static void smc91c111_writeb(void *opaque
, hwaddr offset
,
607 smc91c111_state
*s
= (smc91c111_state
*)opaque
;
609 offset
= offset
& 0xf;
623 SET_HIGH(tcr
, value
);
629 SET_HIGH(rcr
, value
);
630 if (s
->rcr
& RCR_SOFT_RST
) {
631 smc91c111_reset(DEVICE(s
));
633 smc91c111_flush_queued_packets(s
);
635 case 10: case 11: /* RPCR */
638 case 12: case 13: /* Reserved */
641 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
653 case 2: case 3: /* BASE */
654 case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
655 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
657 case 10: /* General Purpose */
661 SET_HIGH(gpr
, value
);
663 case 12: /* Control */
665 qemu_log_mask(LOG_UNIMP
,
666 "smc91c111: EEPROM store not implemented\n");
669 qemu_log_mask(LOG_UNIMP
,
670 "smc91c111: EEPROM reload not implemented\n");
676 SET_HIGH(ctr
, value
);
679 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
685 case 0: /* MMU Command */
686 switch (value
>> 5) {
689 case 1: /* Allocate for TX. */
691 s
->int_level
&= ~INT_ALLOC
;
693 smc91c111_tx_alloc(s
);
695 case 2: /* Reset MMU. */
698 s
->tx_fifo_done_len
= 0;
702 case 3: /* Remove from RX FIFO. */
703 smc91c111_pop_rx_fifo(s
);
705 case 4: /* Remove from RX FIFO and release. */
706 if (s
->rx_fifo_len
> 0) {
707 smc91c111_release_packet(s
, s
->rx_fifo
[0]);
709 smc91c111_pop_rx_fifo(s
);
711 case 5: /* Release. */
712 smc91c111_release_packet(s
, s
->packet_num
);
714 case 6: /* Add to TX FIFO. */
715 smc91c111_queue_tx(s
, s
->packet_num
);
717 case 7: /* Reset TX FIFO. */
719 s
->tx_fifo_done_len
= 0;
722 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
728 case 2: /* Packet Number Register */
729 s
->packet_num
= value
;
731 case 3: case 4: case 5:
732 /* Should be readonly, but linux writes to them anyway. Ignore. */
734 case 6: /* Pointer */
738 SET_HIGH(ptr
, value
);
740 case 8: case 9: case 10: case 11: /* Data */
750 if (s
->ptr
& 0x4000) {
751 s
->ptr
= (s
->ptr
& 0xf800) | ((s
->ptr
+ 1) & 0x7ff);
755 s
->data
[n
][p
] = value
;
758 case 12: /* Interrupt ACK. */
759 s
->int_level
&= ~(value
& 0xd6);
761 smc91c111_pop_tx_fifo_done(s
);
764 case 13: /* Interrupt mask. */
769 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
775 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
776 /* Multicast table. */
777 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
779 case 8: /* Management Interface (low). */
780 mii_write(&s
->mii
, value
);
782 case 9: /* Management Interface (high). */
784 /* MSK_CRS100 not implemented. */
785 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
788 case 12: /* Early receive. */
789 s
->ercv
= value
& 0x1f;
793 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
796 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
800 logout(TARGET_FMT_plx
"= %02" PRIx32
"\n", offset
, value
);
802 qemu_log_mask(LOG_GUEST_ERROR
, "smc91c111_write(bank:%d) Illegal register"
803 " 0x%" HWADDR_PRIx
" = 0x%x\n",
804 s
->bank
, offset
, value
);
807 static uint32_t smc91c111_readb(void *opaque
, hwaddr offset
)
809 smc91c111_state
*s
= (smc91c111_state
*)opaque
;
811 offset
= offset
& 0xf;
821 return s
->tcr
& 0xff;
824 case 2: /* EPH Status */
829 return s
->rcr
& 0xff;
832 case 6: /* Counter */
834 logout(TARGET_FMT_plx
"\n", offset
);
836 case 8: /* Memory size. */
838 case 9: /* Free memory available. */
843 for (i
= 0; i
< NUM_PACKETS
; i
++) {
844 if (s
->allocated
& (1 << i
))
849 case 10: case 11: /* RPCR */
850 logout(TARGET_FMT_plx
"\n", offset
);
852 case 12: case 13: /* Reserved */
855 logout(TARGET_FMT_plx
"\n", offset
);
865 case 2: case 3: /* BASE */
866 logout(TARGET_FMT_plx
"\n", offset
);
868 case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
869 return s
->conf
.macaddr
.a
[offset
- 4];
870 case 10: /* General Purpose */
871 return s
->gpr
& 0xff;
874 case 12: /* Control */
875 return s
->ctr
& 0xff;
879 logout(TARGET_FMT_plx
"\n", offset
);
885 case 0: case 1: /* MMUCR Busy bit. */
887 case 2: /* Packet Number. */
888 return s
->packet_num
;
889 case 3: /* Allocation Result. */
891 case 4: /* TX FIFO */
892 if (s
->tx_fifo_done_len
== 0)
895 return s
->tx_fifo_done
[0];
896 case 5: /* RX FIFO */
897 if (s
->rx_fifo_len
== 0)
900 return s
->rx_fifo
[0];
901 case 6: /* Pointer */
902 return s
->ptr
& 0xff;
904 return (s
->ptr
>> 8) & 0xf7;
905 case 8: case 9: case 10: case 11: /* Data */
915 if (s
->ptr
& 0x4000) {
916 s
->ptr
= (s
->ptr
& 0xf800) | ((s
->ptr
+ 1) & 0x07ff);
920 return s
->data
[n
][p
];
922 case 12: /* Interrupt status. */
924 case 13: /* Interrupt mask. */
927 logout(TARGET_FMT_plx
"\n", offset
);
933 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
934 /* Multicast table. */
935 logout(TARGET_FMT_plx
"\n", offset
);
937 case 8: /* Management Interface (low). */
938 logout(TARGET_FMT_plx
"\n", offset
);
939 return 0x30 + s
->mii
.mdi
;
940 case 9: /* Management Interface (high). */
942 case 10: /* Revision. */
951 logout(TARGET_FMT_plx
"\n", offset
);
955 logout(TARGET_FMT_plx
"\n", offset
);
957 qemu_log_mask(LOG_GUEST_ERROR
, "smc91c111_read(bank:%d) Illegal register"
958 " 0x%" HWADDR_PRIx
"\n",
963 static uint64_t smc91c111_readfn(void *opaque
, hwaddr addr
, unsigned size
)
968 for (i
= 0; i
< size
; i
++) {
969 val
|= smc91c111_readb(opaque
, addr
+ i
) << (i
* 8);
974 static void smc91c111_writefn(void *opaque
, hwaddr addr
,
975 uint64_t value
, unsigned size
)
979 /* 32-bit writes to offset 0xc only actually write to the bank select
980 * register (offset 0xe), so skip the first two bytes we would write.
982 if (addr
== 0xc && size
== 4) {
986 for (; i
< size
; i
++) {
987 smc91c111_writeb(opaque
, addr
+ i
,
988 extract32(value
, i
* 8, 8));
992 static int smc91c111_can_receive_nc(NetClientState
*nc
)
994 smc91c111_state
*s
= qemu_get_nic_opaque(nc
);
996 return smc91c111_can_receive(s
);
999 static ssize_t
smc91c111_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
1001 smc91c111_state
*s
= qemu_get_nic_opaque(nc
);
1008 if ((s
->rcr
& RCR_RXEN
) == 0 || (s
->rcr
& RCR_SOFT_RST
))
1010 /* Short packets are padded with zeros. Receiving a packet
1011 < 64 bytes long is considered an error condition. */
1015 packetsize
= (size
& ~1);
1017 crc
= (s
->rcr
& RCR_STRIP_CRC
) == 0;
1020 /* TODO: Flag overrun and receive errors. */
1021 if (packetsize
> 2048)
1023 packetnum
= smc91c111_allocate_packet(s
);
1024 if (packetnum
== 0x80)
1026 s
->rx_fifo
[s
->rx_fifo_len
++] = packetnum
;
1028 p
= &s
->data
[packetnum
][0];
1029 /* ??? Multicast packets? */
1032 status
|= RS_TOOLONG
;
1034 status
|= RS_ODDFRAME
;
1035 *(p
++) = status
& 0xff;
1036 *(p
++) = status
>> 8;
1037 *(p
++) = packetsize
& 0xff;
1038 *(p
++) = packetsize
>> 8;
1039 memcpy(p
, buf
, size
& ~1);
1041 /* Pad short packets. */
1046 *(p
++) = buf
[size
- 1];
1052 /* It's not clear if the CRC should go before or after the last byte in
1053 odd sized packets. Linux disables the CRC, so that's no help.
1054 The pictures in the documentation show the CRC aligned on a 16-bit
1055 boundary before the last odd byte, so that's what we do. */
1057 crc
= crc32(~0, buf
, size
);
1058 *(p
++) = crc
& 0xff; crc
>>= 8;
1059 *(p
++) = crc
& 0xff; crc
>>= 8;
1060 *(p
++) = crc
& 0xff; crc
>>= 8;
1061 *(p
++) = crc
& 0xff;
1064 *(p
++) = buf
[size
- 1];
1070 /* TODO: Raise early RX interrupt? */
1071 s
->int_level
|= INT_RCV
;
1072 smc91c111_update(s
);
1077 static const MemoryRegionOps smc91c111_mem_ops
= {
1078 /* The special case for 32 bit writes to 0xc means we can't just
1079 * set .impl.min/max_access_size to 1, unfortunately
1081 .read
= smc91c111_readfn
,
1082 .write
= smc91c111_writefn
,
1083 .valid
.min_access_size
= 1,
1084 .valid
.max_access_size
= 4,
1085 .endianness
= DEVICE_NATIVE_ENDIAN
,
1088 static NetClientInfo net_smc91c111_info
= {
1089 .type
= NET_CLIENT_DRIVER_NIC
,
1090 .size
= sizeof(NICState
),
1091 .can_receive
= smc91c111_can_receive_nc
,
1092 .receive
= smc91c111_receive
,
1095 static void smc91c111_realize(DeviceState
*dev
, Error
**errp
)
1097 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1098 smc91c111_state
*s
= SMC91C111(dev
);
1100 memory_region_init_io(&s
->mmio
, OBJECT(s
), &smc91c111_mem_ops
, s
,
1101 "smc91c111-mmio", 16);
1102 sysbus_init_mmio(sbd
, &s
->mmio
);
1103 sysbus_init_irq(sbd
, &s
->irq
);
1104 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1105 s
->nic
= qemu_new_nic(&net_smc91c111_info
, &s
->conf
,
1106 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
1107 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1108 /* ??? Save/restore. */
1111 static Property smc91c111_properties
[] = {
1112 DEFINE_NIC_PROPERTIES(smc91c111_state
, conf
),
1113 DEFINE_PROP_END_OF_LIST(),
1116 static void smc91c111_class_init(ObjectClass
*klass
, void *data
)
1118 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1120 dc
->realize
= smc91c111_realize
;
1121 dc
->reset
= smc91c111_reset
;
1122 dc
->vmsd
= &vmstate_smc91c111
;
1123 dc
->props
= smc91c111_properties
;
1126 static const TypeInfo smc91c111_info
= {
1127 .name
= TYPE_SMC91C111
,
1128 .parent
= TYPE_SYS_BUS_DEVICE
,
1129 .instance_size
= sizeof(smc91c111_state
),
1130 .class_init
= smc91c111_class_init
,
1133 static void smc91c111_register_types(void)
1135 type_register_static(&smc91c111_info
);
1138 /* Legacy helper function. Should go away when machine config files are
1140 void smc91c111_init(NICInfo
*nd
, uint32_t base
, qemu_irq irq
)
1145 qemu_check_nic_model(nd
, "smc91c111");
1146 dev
= qdev_create(NULL
, TYPE_SMC91C111
);
1147 qdev_set_nic_properties(dev
, nd
);
1148 qdev_init_nofail(dev
);
1149 s
= SYS_BUS_DEVICE(dev
);
1150 sysbus_mmio_map(s
, 0, base
);
1151 sysbus_connect_irq(s
, 0, irq
);
1154 type_init(smc91c111_register_types
)