hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/misc/unimp.h"
  19 #include "hw/arm/aspeed_soc.h"
  20 #include "hw/char/serial.h"
  21 #include "qemu/log.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "net/net.h"
  24
  25 #define ASPEED_SOC_UART_5_BASE      0x00184000
  26 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  27 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  28 #define ASPEED_SOC_FMC_BASE         0x1E620000
  29 #define ASPEED_SOC_SPI_BASE         0x1E630000
  30 #define ASPEED_SOC_SPI2_BASE        0x1E631000
  31 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  32 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  33 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  34 #define ASPEED_SOC_SRAM_BASE        0x1E720000
  35 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  36 #define ASPEED_SOC_WDT_BASE         0x1E785000
  37 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  38 #define ASPEED_SOC_ETH1_BASE        0x1E660000
  39 #define ASPEED_SOC_ETH2_BASE        0x1E680000
  40
  41 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  42 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  43
  44 #define AST2400_SDRAM_BASE       0x40000000
  45 #define AST2500_SDRAM_BASE       0x80000000
  46
  47 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  48 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
  49
  50 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
  51                                                        ASPEED_SOC_SPI2_BASE};
  52 static const char *aspeed_soc_ast2500_typenames[] = {
  53     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
  54
  55 static const AspeedSoCInfo aspeed_socs[] = {
  56     {
  57         .name         = "ast2400-a0",
  58         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  59         .silicon_rev  = AST2400_A0_SILICON_REV,
  60         .sdram_base   = AST2400_SDRAM_BASE,
  61         .sram_size    = 0x8000,
  62         .spis_num     = 1,
  63         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  64         .fmc_typename = "aspeed.smc.fmc",
  65         .spi_typename = aspeed_soc_ast2400_typenames,
  66         .wdts_num     = 2,
  67     }, {
  68         .name         = "ast2400-a1",
  69         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  70         .silicon_rev  = AST2400_A1_SILICON_REV,
  71         .sdram_base   = AST2400_SDRAM_BASE,
  72         .sram_size    = 0x8000,
  73         .spis_num     = 1,
  74         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  75         .fmc_typename = "aspeed.smc.fmc",
  76         .spi_typename = aspeed_soc_ast2400_typenames,
  77         .wdts_num     = 2,
  78     }, {
  79         .name         = "ast2400",
  80         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  81         .silicon_rev  = AST2400_A0_SILICON_REV,
  82         .sdram_base   = AST2400_SDRAM_BASE,
  83         .sram_size    = 0x8000,
  84         .spis_num     = 1,
  85         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  86         .fmc_typename = "aspeed.smc.fmc",
  87         .spi_typename = aspeed_soc_ast2400_typenames,
  88         .wdts_num     = 2,
  89     }, {
  90         .name         = "ast2500-a1",
  91         .cpu_type     = ARM_CPU_TYPE_NAME("arm1176"),
  92         .silicon_rev  = AST2500_A1_SILICON_REV,
  93         .sdram_base   = AST2500_SDRAM_BASE,
  94         .sram_size    = 0x9000,
  95         .spis_num     = 2,
  96         .spi_bases    = aspeed_soc_ast2500_spi_bases,
  97         .fmc_typename = "aspeed.smc.ast2500-fmc",
  98         .spi_typename = aspeed_soc_ast2500_typenames,
  99         .wdts_num     = 3,
 100     },
 101 };
 102
 103 static void aspeed_soc_init(Object *obj)
 104 {
 105     AspeedSoCState *s = ASPEED_SOC(obj);
 106     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 107     int i;
 108
 109     object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
 110     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
 111
 112     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
 113     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
 114     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 115     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 116                          sc->info->silicon_rev);
 117     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 118                               "hw-strap1", &error_abort);
 119     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 120                               "hw-strap2", &error_abort);
 121     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
 122                               "hw-prot-key", &error_abort);
 123
 124     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
 125     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
 126     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
 127
 128     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 129     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
 130     object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
 131                                    OBJECT(&s->scu), &error_abort);
 132     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
 133
 134     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
 135     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
 136     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
 137
 138     object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
 139     object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
 140     qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
 141     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
 142                               &error_abort);
 143
 144     for (i = 0; i < sc->info->spis_num; i++) {
 145         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 146                           sc->info->spi_typename[i]);
 147         object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
 148         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 149     }
 150
 151     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
 152     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
 153     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
 154     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 155                          sc->info->silicon_rev);
 156     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 157                               "ram-size", &error_abort);
 158     object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
 159                               "max-ram-size", &error_abort);
 160
 161     for (i = 0; i < sc->info->wdts_num; i++) {
 162         object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
 163         object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
 164         qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
 165         qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
 166                                     sc->info->silicon_rev);
 167     }
 168
 169     object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
 170     object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
 171     qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default());
 172 }
 173
 174 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 175 {
 176     int i;
 177     AspeedSoCState *s = ASPEED_SOC(dev);
 178     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 179     Error *err = NULL, *local_err = NULL;
 180
 181     /* IO space */
 182     create_unimplemented_device("aspeed_soc.io",
 183                                 ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
 184
 185     /* CPU */
 186     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
 187     if (err) {
 188         error_propagate(errp, err);
 189         return;
 190     }
 191
 192     /* SRAM */
 193     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 194                            sc->info->sram_size, &err);
 195     if (err) {
 196         error_propagate(errp, err);
 197         return;
 198     }
 199     memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
 200                                 &s->sram);
 201
 202     /* SCU */
 203     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 204     if (err) {
 205         error_propagate(errp, err);
 206         return;
 207     }
 208     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 209
 210     /* VIC */
 211     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 212     if (err) {
 213         error_propagate(errp, err);
 214         return;
 215     }
 216     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 217     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 218                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 219     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 220                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 221
 222     /* Timer */
 223     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 224     if (err) {
 225         error_propagate(errp, err);
 226         return;
 227     }
 228     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 229     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 230         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 231         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 232     }
 233
 234     /* UART - attach an 8250 to the IO space as our UART5 */
 235     if (serial_hd(0)) {
 236         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 237         serial_mm_init(get_system_memory(),
 238                        ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
 239                        uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 240     }
 241
 242     /* I2C */
 243     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 244     if (err) {
 245         error_propagate(errp, err);
 246         return;
 247     }
 248     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 249     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 250                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 251
 252     /* FMC, The number of CS is set at the board level */
 253     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
 254     if (err) {
 255         error_propagate(errp, err);
 256         return;
 257     }
 258     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 259     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 260                     s->fmc.ctrl->flash_window_base);
 261     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 262                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 263
 264     /* SPI */
 265     for (i = 0; i < sc->info->spis_num; i++) {
 266         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 267         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 268                                  &local_err);
 269         error_propagate(&err, local_err);
 270         if (err) {
 271             error_propagate(errp, err);
 272             return;
 273         }
 274         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 275         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 276                         s->spi[i].ctrl->flash_window_base);
 277     }
 278
 279     /* SDMC - SDRAM Memory Controller */
 280     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 281     if (err) {
 282         error_propagate(errp, err);
 283         return;
 284     }
 285     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 286
 287     /* Watch dog */
 288     for (i = 0; i < sc->info->wdts_num; i++) {
 289         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
 290         if (err) {
 291             error_propagate(errp, err);
 292             return;
 293         }
 294         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 295                         ASPEED_SOC_WDT_BASE + i * 0x20);
 296     }
 297
 298     /* Net */
 299     qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
 300     object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
 301     object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
 302                              &local_err);
 303     error_propagate(&err, local_err);
 304     if (err) {
 305         error_propagate(errp, err);
 306         return;
 307     }
 308     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
 309     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
 310                        qdev_get_gpio_in(DEVICE(&s->vic), 2));
 311 }
 312
 313 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 314 {
 315     DeviceClass *dc = DEVICE_CLASS(oc);
 316     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 317
 318     sc->info = (AspeedSoCInfo *) data;
 319     dc->realize = aspeed_soc_realize;
 320     /* Reason: Uses serial_hd and nd_table in realize() directly */
 321     dc->user_creatable = false;
 322 }
 323
 324 static const TypeInfo aspeed_soc_type_info = {
 325     .name           = TYPE_ASPEED_SOC,
 326     .parent         = TYPE_DEVICE,
 327     .instance_init  = aspeed_soc_init,
 328     .instance_size  = sizeof(AspeedSoCState),
 329     .class_size     = sizeof(AspeedSoCClass),
 330     .abstract       = true,
 331 };
 332
 333 static void aspeed_soc_register_types(void)
 334 {
 335     int i;
 336
 337     type_register_static(&aspeed_soc_type_info);
 338     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 339         TypeInfo ti = {
 340             .name       = aspeed_socs[i].name,
 341             .parent     = TYPE_ASPEED_SOC,
 342             .class_init = aspeed_soc_class_init,
 343             .class_data = (void *) &aspeed_socs[i],
 344         };
 345         type_register(&ti);
 346     }
 347 }
 348
 349 type_init(aspeed_soc_register_types)