3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
12 #include <zlib.h> /* For crc32 */
14 #ifndef CONFIG_USER_ONLY
15 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
16 int access_type
, int is_user
,
17 hwaddr
*phys_ptr
, int *prot
,
18 target_ulong
*page_size
);
20 /* Definitions for the PMCCNTR and PMCR registers */
26 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
30 /* VFP data registers are always little-endian. */
31 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
33 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
36 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
37 /* Aliases for Q regs. */
40 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
41 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
45 switch (reg
- nregs
) {
46 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
47 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
48 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
53 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
57 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
59 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
62 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
65 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
66 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
70 switch (reg
- nregs
) {
71 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
72 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
73 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
78 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 /* 128 bit FP register */
83 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
84 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
88 stl_p(buf
, vfp_get_fpsr(env
));
92 stl_p(buf
, vfp_get_fpcr(env
));
99 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
103 /* 128 bit FP register */
104 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
105 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
109 vfp_set_fpsr(env
, ldl_p(buf
));
113 vfp_set_fpcr(env
, ldl_p(buf
));
120 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
122 if (cpreg_field_is_64bit(ri
)) {
123 return CPREG_FIELD64(env
, ri
);
125 return CPREG_FIELD32(env
, ri
);
129 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
132 if (cpreg_field_is_64bit(ri
)) {
133 CPREG_FIELD64(env
, ri
) = value
;
135 CPREG_FIELD32(env
, ri
) = value
;
139 static uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
141 /* Raw read of a coprocessor register (as needed for migration, etc). */
142 if (ri
->type
& ARM_CP_CONST
) {
143 return ri
->resetvalue
;
144 } else if (ri
->raw_readfn
) {
145 return ri
->raw_readfn(env
, ri
);
146 } else if (ri
->readfn
) {
147 return ri
->readfn(env
, ri
);
149 return raw_read(env
, ri
);
153 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
156 /* Raw write of a coprocessor register (as needed for migration, etc).
157 * Note that constant registers are treated as write-ignored; the
158 * caller should check for success by whether a readback gives the
161 if (ri
->type
& ARM_CP_CONST
) {
163 } else if (ri
->raw_writefn
) {
164 ri
->raw_writefn(env
, ri
, v
);
165 } else if (ri
->writefn
) {
166 ri
->writefn(env
, ri
, v
);
168 raw_write(env
, ri
, v
);
172 bool write_cpustate_to_list(ARMCPU
*cpu
)
174 /* Write the coprocessor state from cpu->env to the (index,value) list. */
178 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
179 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
180 const ARMCPRegInfo
*ri
;
182 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
187 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
190 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
195 bool write_list_to_cpustate(ARMCPU
*cpu
)
200 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
201 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
202 uint64_t v
= cpu
->cpreg_values
[i
];
203 const ARMCPRegInfo
*ri
;
205 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
210 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
213 /* Write value and confirm it reads back as written
214 * (to catch read-only registers and partially read-only
215 * registers where the incoming migration value doesn't match)
217 write_raw_cp_reg(&cpu
->env
, ri
, v
);
218 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
225 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
227 ARMCPU
*cpu
= opaque
;
229 const ARMCPRegInfo
*ri
;
231 regidx
= *(uint32_t *)key
;
232 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
234 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
235 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
236 /* The value array need not be initialized at this point */
237 cpu
->cpreg_array_len
++;
241 static void count_cpreg(gpointer key
, gpointer opaque
)
243 ARMCPU
*cpu
= opaque
;
245 const ARMCPRegInfo
*ri
;
247 regidx
= *(uint32_t *)key
;
248 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
250 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
251 cpu
->cpreg_array_len
++;
255 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
257 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
258 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
269 static void cpreg_make_keylist(gpointer key
, gpointer value
, gpointer udata
)
271 GList
**plist
= udata
;
273 *plist
= g_list_prepend(*plist
, key
);
276 void init_cpreg_list(ARMCPU
*cpu
)
278 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
279 * Note that we require cpreg_tuples[] to be sorted by key ID.
284 g_hash_table_foreach(cpu
->cp_regs
, cpreg_make_keylist
, &keys
);
286 keys
= g_list_sort(keys
, cpreg_key_compare
);
288 cpu
->cpreg_array_len
= 0;
290 g_list_foreach(keys
, count_cpreg
, cpu
);
292 arraylen
= cpu
->cpreg_array_len
;
293 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
294 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
295 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
296 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
297 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
298 cpu
->cpreg_array_len
= 0;
300 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
302 assert(cpu
->cpreg_array_len
== arraylen
);
307 /* Return true if extended addresses are enabled.
308 * This is always the case if our translation regime is 64 bit,
309 * but depends on TTBCR.EAE for 32 bit.
311 static inline bool extended_addresses_enabled(CPUARMState
*env
)
313 return arm_el_is_aa64(env
, 1)
314 || ((arm_feature(env
, ARM_FEATURE_LPAE
)
315 && (env
->cp15
.c2_control
& TTBCR_EAE
)));
318 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
320 ARMCPU
*cpu
= arm_env_get_cpu(env
);
322 raw_write(env
, ri
, value
);
323 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
326 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
328 ARMCPU
*cpu
= arm_env_get_cpu(env
);
330 if (raw_read(env
, ri
) != value
) {
331 /* Unlike real hardware the qemu TLB uses virtual addresses,
332 * not modified virtual addresses, so this causes a TLB flush.
334 tlb_flush(CPU(cpu
), 1);
335 raw_write(env
, ri
, value
);
339 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
342 ARMCPU
*cpu
= arm_env_get_cpu(env
);
344 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
345 && !extended_addresses_enabled(env
)) {
346 /* For VMSA (when not using the LPAE long descriptor page table
347 * format) this register includes the ASID, so do a TLB flush.
348 * For PMSA it is purely a process ID and no action is needed.
350 tlb_flush(CPU(cpu
), 1);
352 raw_write(env
, ri
, value
);
355 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
358 /* Invalidate all (TLBIALL) */
359 ARMCPU
*cpu
= arm_env_get_cpu(env
);
361 tlb_flush(CPU(cpu
), 1);
364 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
367 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
368 ARMCPU
*cpu
= arm_env_get_cpu(env
);
370 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
373 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 /* Invalidate by ASID (TLBIASID) */
377 ARMCPU
*cpu
= arm_env_get_cpu(env
);
379 tlb_flush(CPU(cpu
), value
== 0);
382 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
385 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
388 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
391 static const ARMCPRegInfo cp_reginfo
[] = {
392 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
393 * version" bits will read as a reserved value, which should cause
394 * Linux to not try to use the debug hardware.
396 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
397 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
398 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
399 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
400 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
401 { .name
= "CONTEXTIDR", .state
= ARM_CP_STATE_BOTH
,
402 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
404 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el1
),
405 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
409 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
410 /* NB: Some of these registers exist in v8 but with more precise
411 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
413 /* MMU Domain access control / MPU write buffer control */
414 { .name
= "DACR", .cp
= 15,
415 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
416 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
417 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
418 /* ??? This covers not just the impdef TLB lockdown registers but also
419 * some v7VMSA registers relating to TEX remap, so it is overly broad.
421 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
422 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
423 /* MMU TLB control. Note that the wildcarding means we cover not just
424 * the unified TLB ops but also the dside/iside/inner-shareable variants.
426 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
427 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
428 .type
= ARM_CP_NO_MIGRATE
},
429 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
430 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
431 .type
= ARM_CP_NO_MIGRATE
},
432 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
433 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
434 .type
= ARM_CP_NO_MIGRATE
},
435 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
436 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
437 .type
= ARM_CP_NO_MIGRATE
},
438 /* Cache maintenance ops; some of this space may be overridden later. */
439 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
440 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
441 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
445 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
446 /* Not all pre-v6 cores implemented this WFI, so this is slightly
449 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
450 .access
= PL1_W
, .type
= ARM_CP_WFI
},
454 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
455 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
456 * is UNPREDICTABLE; we choose to NOP as most implementations do).
458 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
459 .access
= PL1_W
, .type
= ARM_CP_WFI
},
460 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
461 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
462 * OMAPCP will override this space.
464 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
465 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
467 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
468 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
470 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
471 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
472 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
477 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
482 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
483 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
484 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
485 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
486 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
488 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
489 /* VFP coprocessor: cp10 & cp11 [23:20] */
490 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
492 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
493 /* ASEDIS [31] bit is RAO/WI */
497 /* VFPv3 and upwards with NEON implement 32 double precision
498 * registers (D0-D31).
500 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
501 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
502 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
508 env
->cp15
.c1_coproc
= value
;
511 static const ARMCPRegInfo v6_cp_reginfo
[] = {
512 /* prefetch by MVA in v6, NOP in v7 */
513 { .name
= "MVA_prefetch",
514 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
515 .access
= PL1_W
, .type
= ARM_CP_NOP
},
516 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
517 .access
= PL0_W
, .type
= ARM_CP_NOP
},
518 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
519 .access
= PL0_W
, .type
= ARM_CP_NOP
},
520 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
521 .access
= PL0_W
, .type
= ARM_CP_NOP
},
522 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
524 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[1]),
526 /* Watchpoint Fault Address Register : should actually only be present
527 * for 1136, 1176, 11MPCore.
529 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
530 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
531 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
532 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
533 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
534 .resetvalue
= 0, .writefn
= cpacr_write
},
538 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
540 /* Performance monitor registers user accessibility is controlled
543 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
544 return CP_ACCESS_TRAP
;
549 #ifndef CONFIG_USER_ONLY
550 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
553 /* Don't computer the number of ticks in user mode */
556 temp_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
557 get_ticks_per_sec() / 1000000;
559 if (env
->cp15
.c9_pmcr
& PMCRE
) {
560 /* If the counter is enabled */
561 if (env
->cp15
.c9_pmcr
& PMCRD
) {
562 /* Increment once every 64 processor clock cycles */
563 env
->cp15
.c15_ccnt
= (temp_ticks
/64) - env
->cp15
.c15_ccnt
;
565 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
570 /* The counter has been reset */
571 env
->cp15
.c15_ccnt
= 0;
574 /* only the DP, X, D and E bits are writable */
575 env
->cp15
.c9_pmcr
&= ~0x39;
576 env
->cp15
.c9_pmcr
|= (value
& 0x39);
578 if (env
->cp15
.c9_pmcr
& PMCRE
) {
579 if (env
->cp15
.c9_pmcr
& PMCRD
) {
580 /* Increment once every 64 processor clock cycles */
583 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
587 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
589 uint32_t total_ticks
;
591 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
592 /* Counter is disabled, do not change value */
593 return env
->cp15
.c15_ccnt
;
596 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
597 get_ticks_per_sec() / 1000000;
599 if (env
->cp15
.c9_pmcr
& PMCRD
) {
600 /* Increment once every 64 processor clock cycles */
603 return total_ticks
- env
->cp15
.c15_ccnt
;
606 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
609 uint32_t total_ticks
;
611 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
612 /* Counter is disabled, set the absolute value */
613 env
->cp15
.c15_ccnt
= value
;
617 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
618 get_ticks_per_sec() / 1000000;
620 if (env
->cp15
.c9_pmcr
& PMCRD
) {
621 /* Increment once every 64 processor clock cycles */
624 env
->cp15
.c15_ccnt
= total_ticks
- value
;
628 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
632 env
->cp15
.c9_pmcnten
|= value
;
635 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
639 env
->cp15
.c9_pmcnten
&= ~value
;
642 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
645 env
->cp15
.c9_pmovsr
&= ~value
;
648 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
651 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
654 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
657 env
->cp15
.c9_pmuserenr
= value
& 1;
660 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
663 /* We have no event counters so only the C bit can be changed */
665 env
->cp15
.c9_pminten
|= value
;
668 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
672 env
->cp15
.c9_pminten
&= ~value
;
675 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
678 /* Note that even though the AArch64 view of this register has bits
679 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
680 * architectural requirements for bits which are RES0 only in some
681 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
682 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
684 raw_write(env
, ri
, value
& ~0x1FULL
);
687 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
689 ARMCPU
*cpu
= arm_env_get_cpu(env
);
690 return cpu
->ccsidr
[env
->cp15
.c0_cssel
];
693 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 raw_write(env
, ri
, value
& 0xf);
699 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
701 CPUState
*cs
= ENV_GET_CPU(env
);
704 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
707 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
710 /* External aborts are not possible in QEMU so A bit is always clear */
714 static const ARMCPRegInfo v7_cp_reginfo
[] = {
715 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
718 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
719 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
720 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
721 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
722 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
723 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
724 .access
= PL1_W
, .type
= ARM_CP_NOP
},
725 /* Performance monitors are implementation defined in v7,
726 * but with an ARM recommended set of registers, which we
727 * follow (although we don't actually implement any counters)
729 * Performance registers fall into three categories:
730 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
731 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
732 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
733 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
734 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
736 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
737 .access
= PL0_RW
, .resetvalue
= 0,
738 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
739 .writefn
= pmcntenset_write
,
740 .accessfn
= pmreg_access
,
741 .raw_writefn
= raw_write
},
742 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
743 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
744 .accessfn
= pmreg_access
,
745 .writefn
= pmcntenclr_write
,
746 .type
= ARM_CP_NO_MIGRATE
},
747 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
748 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
749 .accessfn
= pmreg_access
,
750 .writefn
= pmovsr_write
,
751 .raw_writefn
= raw_write
},
752 /* Unimplemented so WI. */
753 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
754 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
755 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
756 * We choose to RAZ/WI.
758 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
759 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
760 .accessfn
= pmreg_access
},
761 #ifndef CONFIG_USER_ONLY
762 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
763 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
764 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
765 .accessfn
= pmreg_access
},
767 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
769 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
770 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
771 .raw_writefn
= raw_write
},
772 /* Unimplemented, RAZ/WI. */
773 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
774 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
775 .accessfn
= pmreg_access
},
776 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
777 .access
= PL0_R
| PL1_RW
,
778 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
780 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
781 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
783 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
785 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
786 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
787 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
788 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
789 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
790 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
791 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
792 .access
= PL1_RW
, .writefn
= vbar_write
,
793 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[1]),
795 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
796 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
798 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
799 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
800 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
801 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
802 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
803 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
804 .writefn
= csselr_write
, .resetvalue
= 0 },
805 /* Auxiliary ID register: this actually has an IMPDEF value but for now
806 * just RAZ for all cores:
808 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
809 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
810 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
811 /* Auxiliary fault status registers: these also are IMPDEF, and we
812 * choose to RAZ/WI for all cores.
814 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
815 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
816 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
817 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
818 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
819 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
820 /* MAIR can just read-as-written because we don't implement caches
821 * and so don't need to care about memory attributes.
823 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
824 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
825 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el1
),
827 /* For non-long-descriptor page tables these are PRRR and NMRR;
828 * regardless they still act as reads-as-written for QEMU.
829 * The override is necessary because of the overly-broad TLB_LOCKDOWN
832 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
833 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
834 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mair_el1
),
835 .resetfn
= arm_cp_reset_ignore
},
836 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
837 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
838 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el1
),
839 .resetfn
= arm_cp_reset_ignore
},
840 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
841 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
842 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_R
, .readfn
= isr_read
},
846 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
853 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
855 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
856 return CP_ACCESS_TRAP
;
861 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
862 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
863 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
865 .writefn
= teecr_write
},
866 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
867 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
868 .accessfn
= teehbr_access
, .resetvalue
= 0 },
872 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
873 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
874 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
876 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el0
), .resetvalue
= 0 },
877 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
879 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidr_el0
),
880 .resetfn
= arm_cp_reset_ignore
},
881 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
882 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
883 .access
= PL0_R
|PL1_W
,
884 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el0
), .resetvalue
= 0 },
885 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
886 .access
= PL0_R
|PL1_W
,
887 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidrro_el0
),
888 .resetfn
= arm_cp_reset_ignore
},
889 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
890 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
892 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el1
), .resetvalue
= 0 },
896 #ifndef CONFIG_USER_ONLY
898 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
900 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
901 if (arm_current_pl(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
902 return CP_ACCESS_TRAP
;
907 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
909 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
910 if (arm_current_pl(env
) == 0 &&
911 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
912 return CP_ACCESS_TRAP
;
917 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
919 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
920 * EL0[PV]TEN is zero.
922 if (arm_current_pl(env
) == 0 &&
923 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
924 return CP_ACCESS_TRAP
;
929 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
930 const ARMCPRegInfo
*ri
)
932 return gt_counter_access(env
, GTIMER_PHYS
);
935 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
936 const ARMCPRegInfo
*ri
)
938 return gt_counter_access(env
, GTIMER_VIRT
);
941 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
943 return gt_timer_access(env
, GTIMER_PHYS
);
946 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 return gt_timer_access(env
, GTIMER_VIRT
);
951 static uint64_t gt_get_countervalue(CPUARMState
*env
)
953 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
956 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
958 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
961 /* Timer enabled: calculate and set current ISTATUS, irq, and
962 * reset timer to when ISTATUS next has to change
964 uint64_t count
= gt_get_countervalue(&cpu
->env
);
965 /* Note that this must be unsigned 64 bit arithmetic: */
966 int istatus
= count
>= gt
->cval
;
969 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
970 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
971 (istatus
&& !(gt
->ctl
& 2)));
973 /* Next transition is when count rolls back over to zero */
974 nexttick
= UINT64_MAX
;
976 /* Next transition is when we hit cval */
979 /* Note that the desired next expiry time might be beyond the
980 * signed-64-bit range of a QEMUTimer -- in this case we just
981 * set the timer for as far in the future as possible. When the
982 * timer expires we will reset the timer for any remaining period.
984 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
985 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
987 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
989 /* Timer disabled: ISTATUS and timer output always clear */
991 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
992 timer_del(cpu
->gt_timer
[timeridx
]);
996 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
998 ARMCPU
*cpu
= arm_env_get_cpu(env
);
999 int timeridx
= ri
->opc1
& 1;
1001 timer_del(cpu
->gt_timer
[timeridx
]);
1004 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1006 return gt_get_countervalue(env
);
1009 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1012 int timeridx
= ri
->opc1
& 1;
1014 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1015 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1018 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1020 int timeridx
= ri
->crm
& 1;
1022 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1023 gt_get_countervalue(env
));
1026 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1029 int timeridx
= ri
->crm
& 1;
1031 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
1032 + sextract64(value
, 0, 32);
1033 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1036 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1039 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1040 int timeridx
= ri
->crm
& 1;
1041 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1043 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1044 if ((oldval
^ value
) & 1) {
1045 /* Enable toggled */
1046 gt_recalc_timer(cpu
, timeridx
);
1047 } else if ((oldval
^ value
) & 2) {
1048 /* IMASK toggled: don't need to recalculate,
1049 * just set the interrupt line based on ISTATUS
1051 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1052 (oldval
& 4) && !(value
& 2));
1056 void arm_gt_ptimer_cb(void *opaque
)
1058 ARMCPU
*cpu
= opaque
;
1060 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1063 void arm_gt_vtimer_cb(void *opaque
)
1065 ARMCPU
*cpu
= opaque
;
1067 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1070 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1071 /* Note that CNTFRQ is purely reads-as-written for the benefit
1072 * of software; writing it doesn't actually change the timer frequency.
1073 * Our reset value matches the fixed frequency we implement the timer at.
1075 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1076 .type
= ARM_CP_NO_MIGRATE
,
1077 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1078 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1079 .resetfn
= arm_cp_reset_ignore
,
1081 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1082 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1083 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1085 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1087 /* overall control: mostly access permissions */
1088 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1089 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1091 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1094 /* per-timer control */
1095 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1096 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1097 .accessfn
= gt_ptimer_access
,
1098 .fieldoffset
= offsetoflow32(CPUARMState
,
1099 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1100 .resetfn
= arm_cp_reset_ignore
,
1101 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1103 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1104 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1105 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1106 .accessfn
= gt_ptimer_access
,
1107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1109 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1111 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1112 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1113 .accessfn
= gt_vtimer_access
,
1114 .fieldoffset
= offsetoflow32(CPUARMState
,
1115 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1116 .resetfn
= arm_cp_reset_ignore
,
1117 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1119 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1120 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1121 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1122 .accessfn
= gt_vtimer_access
,
1123 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1125 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1127 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1128 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1129 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1130 .accessfn
= gt_ptimer_access
,
1131 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1133 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1134 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1135 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1136 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1138 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1139 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1140 .accessfn
= gt_vtimer_access
,
1141 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1143 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1144 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1145 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1146 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1148 /* The counter itself */
1149 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1150 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1151 .accessfn
= gt_pct_access
,
1152 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1154 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1155 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1156 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1157 .accessfn
= gt_pct_access
,
1158 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1160 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1161 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1162 .accessfn
= gt_vct_access
,
1163 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1165 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1166 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1167 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1168 .accessfn
= gt_vct_access
,
1169 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1171 /* Comparison value, indicating when the timer goes off */
1172 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1173 .access
= PL1_RW
| PL0_R
,
1174 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1175 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1176 .accessfn
= gt_ptimer_access
, .resetfn
= arm_cp_reset_ignore
,
1177 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1179 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1180 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1181 .access
= PL1_RW
| PL0_R
,
1183 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1184 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1185 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1187 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1188 .access
= PL1_RW
| PL0_R
,
1189 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1191 .accessfn
= gt_vtimer_access
, .resetfn
= arm_cp_reset_ignore
,
1192 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1194 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1195 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1196 .access
= PL1_RW
| PL0_R
,
1198 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1199 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1200 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1206 /* In user-mode none of the generic timer registers are accessible,
1207 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1208 * so instead just don't register any of them.
1210 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1216 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1218 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1219 raw_write(env
, ri
, value
);
1220 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1221 raw_write(env
, ri
, value
& 0xfffff6ff);
1223 raw_write(env
, ri
, value
& 0xfffff1ff);
1227 #ifndef CONFIG_USER_ONLY
1228 /* get_phys_addr() isn't present for user-mode-only targets */
1230 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1233 /* Other states are only available with TrustZone; in
1234 * a non-TZ implementation these registers don't exist
1235 * at all, which is an Uncategorized trap. This underdecoding
1236 * is safe because the reginfo is NO_MIGRATE.
1238 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1240 return CP_ACCESS_OK
;
1243 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1246 target_ulong page_size
;
1248 int ret
, is_user
= ri
->opc2
& 2;
1249 int access_type
= ri
->opc2
& 1;
1251 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
1252 &phys_addr
, &prot
, &page_size
);
1253 if (extended_addresses_enabled(env
)) {
1254 /* ret is a DFSR/IFSR value for the long descriptor
1255 * translation table format, but with WnR always clear.
1256 * Convert it to a 64-bit PAR.
1258 uint64_t par64
= (1 << 11); /* LPAE bit always set */
1260 par64
|= phys_addr
& ~0xfffULL
;
1261 /* We don't set the ATTR or SH fields in the PAR. */
1264 par64
|= (ret
& 0x3f) << 1; /* FS */
1265 /* Note that S2WLK and FSTAGE are always zero, because we don't
1266 * implement virtualization and therefore there can't be a stage 2
1270 env
->cp15
.par_el1
= par64
;
1272 /* ret is a DFSR/IFSR value for the short descriptor
1273 * translation table format (with WnR always clear).
1274 * Convert it to a 32-bit PAR.
1277 /* We do not set any attribute bits in the PAR */
1278 if (page_size
== (1 << 24)
1279 && arm_feature(env
, ARM_FEATURE_V7
)) {
1280 env
->cp15
.par_el1
= (phys_addr
& 0xff000000) | 1 << 1;
1282 env
->cp15
.par_el1
= phys_addr
& 0xfffff000;
1285 env
->cp15
.par_el1
= ((ret
& (1 << 10)) >> 5) |
1286 ((ret
& (1 << 12)) >> 6) |
1287 ((ret
& 0xf) << 1) | 1;
1293 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1294 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1295 .access
= PL1_RW
, .resetvalue
= 0,
1296 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.par_el1
),
1297 .writefn
= par_write
},
1298 #ifndef CONFIG_USER_ONLY
1299 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1300 .access
= PL1_W
, .accessfn
= ats_access
,
1301 .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
1306 /* Return basic MPU access permission bits. */
1307 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1314 for (i
= 0; i
< 16; i
+= 2) {
1315 ret
|= (val
>> i
) & mask
;
1321 /* Pad basic MPU access permission bits to extended format. */
1322 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1329 for (i
= 0; i
< 16; i
+= 2) {
1330 ret
|= (val
& mask
) << i
;
1336 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1339 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
1342 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1344 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
1347 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1350 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
1353 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1355 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
1358 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1359 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1360 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1361 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1363 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1364 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1365 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1366 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1368 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1369 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1371 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1373 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1375 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1377 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1379 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1380 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1382 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1383 /* Protection region base and size registers */
1384 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
1385 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1386 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
1387 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
1388 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1389 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
1390 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
1391 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1392 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
1393 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
1394 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1395 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
1396 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
1397 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1398 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
1399 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
1400 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1401 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
1402 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
1403 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1404 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
1405 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
1406 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
1411 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1414 int maskshift
= extract32(value
, 0, 3);
1416 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
1417 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
1418 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1419 * using Long-desciptor translation table format */
1420 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1421 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1422 /* In an implementation that includes the Security Extensions
1423 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1424 * Short-descriptor translation table format.
1426 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
1432 /* Note that we always calculate c2_mask and c2_base_mask, but
1433 * they are only used for short-descriptor tables (ie if EAE is 0);
1434 * for long-descriptor tables the TTBCR fields are used differently
1435 * and the c2_mask and c2_base_mask values are meaningless.
1437 raw_write(env
, ri
, value
);
1438 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1439 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1442 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1445 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1447 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1448 /* With LPAE the TTBCR could result in a change of ASID
1449 * via the TTBCR.A1 bit, so do a TLB flush.
1451 tlb_flush(CPU(cpu
), 1);
1453 vmsa_ttbcr_raw_write(env
, ri
, value
);
1456 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1458 env
->cp15
.c2_base_mask
= 0xffffc000u
;
1459 raw_write(env
, ri
, 0);
1460 env
->cp15
.c2_mask
= 0;
1463 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1466 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1468 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1469 tlb_flush(CPU(cpu
), 1);
1470 raw_write(env
, ri
, value
);
1473 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1476 /* 64 bit accesses to the TTBRs can change the ASID and so we
1477 * must flush the TLB.
1479 if (cpreg_field_is_64bit(ri
)) {
1480 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1482 tlb_flush(CPU(cpu
), 1);
1484 raw_write(env
, ri
, value
);
1487 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1488 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1489 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1490 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
1491 .resetfn
= arm_cp_reset_ignore
, },
1492 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1494 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr_el2
), .resetvalue
= 0, },
1495 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
1496 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
1498 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
1499 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1500 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1501 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1502 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1503 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1504 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1505 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1506 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1507 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
1508 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1509 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
1510 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
1511 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
1512 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1513 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= vmsa_ttbcr_write
,
1514 .resetfn
= arm_cp_reset_ignore
, .raw_writefn
= vmsa_ttbcr_raw_write
,
1515 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c2_control
) },
1516 /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1517 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_BOTH
,
1518 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1519 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
1524 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1528 /* The OS_TYPE bit in this register changes the reported CPUID! */
1529 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1530 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1533 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1536 env
->cp15
.c15_threadid
= value
& 0xffff;
1539 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1542 /* Wait-for-interrupt (deprecated) */
1543 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1546 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1549 /* On OMAP there are registers indicating the max/min index of dcache lines
1550 * containing a dirty line; cache flush operations have to reset these.
1552 env
->cp15
.c15_i_max
= 0x000;
1553 env
->cp15
.c15_i_min
= 0xff0;
1556 static const ARMCPRegInfo omap_cp_reginfo
[] = {
1557 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
1558 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
1559 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
1561 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1562 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1563 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1565 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
1566 .writefn
= omap_ticonfig_write
},
1567 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1569 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1570 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1571 .access
= PL1_RW
, .resetvalue
= 0xff0,
1572 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1573 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1575 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1576 .writefn
= omap_threadid_write
},
1577 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1578 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1579 .type
= ARM_CP_NO_MIGRATE
,
1580 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1581 /* TODO: Peripheral port remap register:
1582 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1583 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1586 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1587 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1588 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
1589 .writefn
= omap_cachemaint_write
},
1590 { .name
= "C9", .cp
= 15, .crn
= 9,
1591 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1592 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1596 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1600 if (env
->cp15
.c15_cpar
!= value
) {
1601 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1603 env
->cp15
.c15_cpar
= value
;
1607 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1608 { .name
= "XSCALE_CPAR",
1609 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1610 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1611 .writefn
= xscale_cpar_write
, },
1612 { .name
= "XSCALE_AUXCR",
1613 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1614 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1616 /* XScale specific cache-lockdown: since we have no cache we NOP these
1617 * and hope the guest does not really rely on cache behaviour.
1619 { .name
= "XSCALE_LOCK_ICACHE_LINE",
1620 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1621 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1622 { .name
= "XSCALE_UNLOCK_ICACHE",
1623 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1624 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1625 { .name
= "XSCALE_DCACHE_LOCK",
1626 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
1627 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1628 { .name
= "XSCALE_UNLOCK_DCACHE",
1629 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
1630 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1634 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
1635 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1636 * implementation of this implementation-defined space.
1637 * Ideally this should eventually disappear in favour of actually
1638 * implementing the correct behaviour for all cores.
1640 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
1641 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1643 .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
| ARM_CP_OVERRIDE
,
1648 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
1649 /* Cache status: RAZ because we have no cache so it's always clean */
1650 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
1651 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1656 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
1657 /* We never have a a block transfer operation in progress */
1658 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
1659 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1661 /* The cache ops themselves: these all NOP for QEMU */
1662 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
1663 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1664 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
1665 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1666 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
1667 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1668 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
1669 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1670 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
1671 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1672 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
1673 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1677 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
1678 /* The cache test-and-clean instructions always return (1 << 30)
1679 * to indicate that there are no dirty cache lines.
1681 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
1682 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1683 .resetvalue
= (1 << 30) },
1684 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
1685 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1686 .resetvalue
= (1 << 30) },
1690 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
1691 /* Ignore ReadBuffer accesses */
1692 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
1693 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1694 .access
= PL1_RW
, .resetvalue
= 0,
1695 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
1699 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1701 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1702 uint32_t mpidr
= cs
->cpu_index
;
1703 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1704 * in later ARM ARM versions), or any of the higher affinity level fields,
1705 * so these bits always RAZ.
1707 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1708 mpidr
|= (1U << 31);
1709 /* Cores which are uniprocessor (non-coherent)
1710 * but still implement the MP extensions set
1711 * bit 30. (For instance, A9UP.) However we do
1712 * not currently model any of those cores.
1718 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
1719 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
1720 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
1721 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
1725 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1726 /* NOP AMAIR0/1: the override is because these clash with the rather
1727 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1729 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
1730 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1731 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1733 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1734 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1735 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1737 /* 64 bit access versions of the (dummy) debug registers */
1738 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1739 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1740 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1741 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1742 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1743 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1744 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el1
), .resetvalue
= 0 },
1745 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1746 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1747 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1748 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1749 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1750 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1751 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1752 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1756 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1758 return vfp_get_fpcr(env
);
1761 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1764 vfp_set_fpcr(env
, value
);
1767 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1769 return vfp_get_fpsr(env
);
1772 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1775 vfp_set_fpsr(env
, value
);
1778 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1780 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UMA
)) {
1781 return CP_ACCESS_TRAP
;
1783 return CP_ACCESS_OK
;
1786 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1789 env
->daif
= value
& PSTATE_DAIF
;
1792 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
1793 const ARMCPRegInfo
*ri
)
1795 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1796 * SCTLR_EL1.UCI is set.
1798 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCI
)) {
1799 return CP_ACCESS_TRAP
;
1801 return CP_ACCESS_OK
;
1804 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1805 * Page D4-1736 (DDI0487A.b)
1808 static void tlbi_aa64_va_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 /* Invalidate by VA (AArch64 version) */
1812 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1813 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
1815 tlb_flush_page(CPU(cpu
), pageaddr
);
1818 static void tlbi_aa64_vaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1821 /* Invalidate by VA, all ASIDs (AArch64 version) */
1822 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1823 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
1825 tlb_flush_page(CPU(cpu
), pageaddr
);
1828 static void tlbi_aa64_asid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1831 /* Invalidate by ASID (AArch64 version) */
1832 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1833 int asid
= extract64(value
, 48, 16);
1834 tlb_flush(CPU(cpu
), asid
== 0);
1837 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1839 /* We don't implement EL2, so the only control on DC ZVA is the
1840 * bit in the SCTLR which can prohibit access for EL0.
1842 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_DZE
)) {
1843 return CP_ACCESS_TRAP
;
1845 return CP_ACCESS_OK
;
1848 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1850 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1851 int dzp_bit
= 1 << 4;
1853 /* DZP indicates whether DC ZVA access is allowed */
1854 if (aa64_zva_access(env
, NULL
) != CP_ACCESS_OK
) {
1857 return cpu
->dcz_blocksize
| dzp_bit
;
1860 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1862 if (!(env
->pstate
& PSTATE_SP
)) {
1863 /* Access to SP_EL0 is undefined if it's being used as
1864 * the stack pointer.
1866 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1868 return CP_ACCESS_OK
;
1871 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1873 return env
->pstate
& PSTATE_SP
;
1876 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
1878 update_spsel(env
, val
);
1881 static const ARMCPRegInfo v8_cp_reginfo
[] = {
1882 /* Minimal set of EL0-visible registers. This will need to be expanded
1883 * significantly for system emulation of AArch64 CPUs.
1885 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
1886 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
1887 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
1888 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
1889 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
1890 .type
= ARM_CP_NO_MIGRATE
,
1891 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
1892 .fieldoffset
= offsetof(CPUARMState
, daif
),
1893 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
1894 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
1895 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
1896 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
1897 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
1898 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
1899 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
1900 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
1901 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
1902 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
,
1903 .readfn
= aa64_dczid_read
},
1904 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
1905 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
1906 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
1907 #ifndef CONFIG_USER_ONLY
1908 /* Avoid overhead of an access check that always passes in user-mode */
1909 .accessfn
= aa64_zva_access
,
1912 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
1913 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
1914 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
1915 /* Cache ops: all NOPs since we don't emulate caches */
1916 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
1917 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
1918 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1919 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
1920 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
1921 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1922 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
1923 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
1924 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1925 .accessfn
= aa64_cacheop_access
},
1926 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
1927 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
1928 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1929 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
1930 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
1931 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1932 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
1933 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
1934 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1935 .accessfn
= aa64_cacheop_access
},
1936 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
1937 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
1938 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1939 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
1940 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
1941 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1942 .accessfn
= aa64_cacheop_access
},
1943 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
1944 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
1945 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1946 .accessfn
= aa64_cacheop_access
},
1947 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
1948 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
1949 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1950 /* TLBI operations */
1951 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
1952 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1953 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1954 .writefn
= tlbiall_write
},
1955 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
1956 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1957 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1958 .writefn
= tlbi_aa64_va_write
},
1959 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
1960 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1961 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1962 .writefn
= tlbi_aa64_asid_write
},
1963 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
1964 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1965 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1966 .writefn
= tlbi_aa64_vaa_write
},
1967 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
1968 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
1969 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1970 .writefn
= tlbi_aa64_va_write
},
1971 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
1972 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
1973 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1974 .writefn
= tlbi_aa64_vaa_write
},
1975 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
1976 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1977 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1978 .writefn
= tlbiall_write
},
1979 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
1980 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1981 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1982 .writefn
= tlbi_aa64_va_write
},
1983 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
1984 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1985 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1986 .writefn
= tlbi_aa64_asid_write
},
1987 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
1988 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1989 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1990 .writefn
= tlbi_aa64_vaa_write
},
1991 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
1992 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
1993 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1994 .writefn
= tlbi_aa64_va_write
},
1995 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
1996 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
1997 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1998 .writefn
= tlbi_aa64_vaa_write
},
1999 #ifndef CONFIG_USER_ONLY
2000 /* 64 bit address translation operations */
2001 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
2002 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
2003 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= ats_write
},
2004 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
2005 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
2006 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= ats_write
},
2007 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
2008 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
2009 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= ats_write
},
2010 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
2011 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
2012 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= ats_write
},
2014 /* 32 bit TLB invalidates, Inner Shareable */
2015 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2016 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2017 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2018 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2019 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2020 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2021 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2022 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2023 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2024 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2025 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2026 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2027 /* 32 bit ITLB invalidates */
2028 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2029 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2030 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2031 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2032 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2033 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2034 /* 32 bit DTLB invalidates */
2035 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2036 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2037 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2038 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2039 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2040 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2041 /* 32 bit TLB invalidates */
2042 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2043 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2044 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2045 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2046 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2047 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2048 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2049 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2050 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2051 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2052 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2053 .type
= ARM_CP_NO_MIGRATE
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2054 /* 32 bit cache operations */
2055 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2056 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2057 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
2058 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2059 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2060 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2061 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
2062 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2063 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
2064 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2065 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
2066 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2067 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2068 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2069 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2070 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2071 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
2072 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2073 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2074 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2075 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
2076 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2077 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
2078 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2079 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2080 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2081 /* MMU Domain access control / MPU write buffer control */
2082 { .name
= "DACR", .cp
= 15,
2083 .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
2084 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
2085 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
2086 /* Dummy implementation of monitor debug system control register:
2087 * we don't support debug.
2089 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_AA64
,
2090 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
2091 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2092 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2093 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
2095 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2096 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
2097 .type
= ARM_CP_NO_MIGRATE
,
2098 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
2100 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
2101 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
2102 .type
= ARM_CP_NO_MIGRATE
,
2103 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
2104 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[0]) },
2105 /* We rely on the access checks not allowing the guest to write to the
2106 * state field when SPSel indicates that it's being used as the stack
2109 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
2110 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
2111 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
2112 .type
= ARM_CP_NO_MIGRATE
,
2113 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
2114 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
2115 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
2116 .type
= ARM_CP_NO_MIGRATE
,
2117 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
2121 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2122 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo
[] = {
2123 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2124 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2126 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
2130 static const ARMCPRegInfo v8_el2_cp_reginfo
[] = {
2131 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
2132 .type
= ARM_CP_NO_MIGRATE
,
2133 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
2135 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
2136 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
2137 .type
= ARM_CP_NO_MIGRATE
,
2138 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
2139 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
2140 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
2141 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
2142 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
2143 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
2144 .type
= ARM_CP_NO_MIGRATE
,
2145 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
2146 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[6]) },
2147 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2148 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2149 .access
= PL2_RW
, .writefn
= vbar_write
,
2150 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
2155 static const ARMCPRegInfo v8_el3_cp_reginfo
[] = {
2156 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
2157 .type
= ARM_CP_NO_MIGRATE
,
2158 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
2160 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
2161 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
2162 .type
= ARM_CP_NO_MIGRATE
,
2163 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
2164 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
2165 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
2166 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
2167 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
2168 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
2169 .type
= ARM_CP_NO_MIGRATE
,
2170 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
2171 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[7]) },
2172 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
2173 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
2174 .access
= PL3_RW
, .writefn
= vbar_write
,
2175 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
2180 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2183 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2185 if (raw_read(env
, ri
) == value
) {
2186 /* Skip the TLB flush if nothing actually changed; Linux likes
2187 * to do a lot of pointless SCTLR writes.
2192 raw_write(env
, ri
, value
);
2193 /* ??? Lots of these bits are not implemented. */
2194 /* This may enable/disable the MMU, so do a TLB flush. */
2195 tlb_flush(CPU(cpu
), 1);
2198 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2200 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2201 * but the AArch32 CTR has its own reginfo struct)
2203 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCT
)) {
2204 return CP_ACCESS_TRAP
;
2206 return CP_ACCESS_OK
;
2209 static void define_aarch64_debug_regs(ARMCPU
*cpu
)
2211 /* Define breakpoint and watchpoint registers. These do nothing
2212 * but read as written, for now.
2216 for (i
= 0; i
< 16; i
++) {
2217 ARMCPRegInfo dbgregs
[] = {
2218 { .name
= "DBGBVR", .state
= ARM_CP_STATE_AA64
,
2219 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
2221 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]) },
2222 { .name
= "DBGBCR", .state
= ARM_CP_STATE_AA64
,
2223 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
2225 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]) },
2226 { .name
= "DBGWVR", .state
= ARM_CP_STATE_AA64
,
2227 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
2229 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]) },
2230 { .name
= "DBGWCR", .state
= ARM_CP_STATE_AA64
,
2231 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
2233 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]) },
2236 define_arm_cp_regs(cpu
, dbgregs
);
2240 void register_cp_regs_for_features(ARMCPU
*cpu
)
2242 /* Register all the coprocessor registers based on feature bits */
2243 CPUARMState
*env
= &cpu
->env
;
2244 if (arm_feature(env
, ARM_FEATURE_M
)) {
2245 /* M profile has no coprocessor registers */
2249 define_arm_cp_regs(cpu
, cp_reginfo
);
2250 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2251 /* Must go early as it is full of wildcards that may be
2252 * overridden by later definitions.
2254 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
2257 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2258 /* The ID registers all have impdef reset values */
2259 ARMCPRegInfo v6_idregs
[] = {
2260 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
2261 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
2262 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2263 .resetvalue
= cpu
->id_pfr0
},
2264 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
2265 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
2266 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2267 .resetvalue
= cpu
->id_pfr1
},
2268 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
2269 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
2270 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2271 .resetvalue
= cpu
->id_dfr0
},
2272 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
2273 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
2274 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2275 .resetvalue
= cpu
->id_afr0
},
2276 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
2277 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
2278 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2279 .resetvalue
= cpu
->id_mmfr0
},
2280 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
2281 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
2282 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2283 .resetvalue
= cpu
->id_mmfr1
},
2284 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
2285 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
2286 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2287 .resetvalue
= cpu
->id_mmfr2
},
2288 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
2289 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
2290 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2291 .resetvalue
= cpu
->id_mmfr3
},
2292 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
2293 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
2294 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2295 .resetvalue
= cpu
->id_isar0
},
2296 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
2297 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
2298 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2299 .resetvalue
= cpu
->id_isar1
},
2300 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
2301 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
2302 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2303 .resetvalue
= cpu
->id_isar2
},
2304 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
2305 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
2306 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2307 .resetvalue
= cpu
->id_isar3
},
2308 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
2309 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
2310 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2311 .resetvalue
= cpu
->id_isar4
},
2312 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
2313 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
2314 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2315 .resetvalue
= cpu
->id_isar5
},
2316 /* 6..7 are as yet unallocated and must RAZ */
2317 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
2318 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
2320 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
2321 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
2325 define_arm_cp_regs(cpu
, v6_idregs
);
2326 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
2328 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
2330 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
2331 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
2333 if (arm_feature(env
, ARM_FEATURE_V7
)) {
2334 /* v7 performance monitor control register: same implementor
2335 * field as main ID register, and we implement only the cycle
2338 #ifndef CONFIG_USER_ONLY
2339 ARMCPRegInfo pmcr
= {
2340 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
2341 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
2343 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
2344 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
2345 .raw_writefn
= raw_write
,
2347 define_one_arm_cp_reg(cpu
, &pmcr
);
2349 ARMCPRegInfo clidr
= {
2350 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
2351 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
2352 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
2354 define_one_arm_cp_reg(cpu
, &clidr
);
2355 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
2357 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
2359 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2360 /* AArch64 ID registers, which all have impdef reset values */
2361 ARMCPRegInfo v8_idregs
[] = {
2362 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2363 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
2364 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2365 .resetvalue
= cpu
->id_aa64pfr0
},
2366 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2367 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
2368 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2369 .resetvalue
= cpu
->id_aa64pfr1
},
2370 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2371 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
2372 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2373 /* We mask out the PMUVer field, because we don't currently
2374 * implement the PMU. Not advertising it prevents the guest
2375 * from trying to use it and getting UNDEFs on registers we
2378 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
2379 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2380 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
2381 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2382 .resetvalue
= cpu
->id_aa64dfr1
},
2383 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2384 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
2385 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2386 .resetvalue
= cpu
->id_aa64afr0
},
2387 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2388 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
2389 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2390 .resetvalue
= cpu
->id_aa64afr1
},
2391 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
2392 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
2393 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2394 .resetvalue
= cpu
->id_aa64isar0
},
2395 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
2396 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
2397 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2398 .resetvalue
= cpu
->id_aa64isar1
},
2399 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2400 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
2401 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2402 .resetvalue
= cpu
->id_aa64mmfr0
},
2403 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2404 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
2405 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2406 .resetvalue
= cpu
->id_aa64mmfr1
},
2407 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2408 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
2409 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2410 .resetvalue
= cpu
->mvfr0
},
2411 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2412 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
2413 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2414 .resetvalue
= cpu
->mvfr1
},
2415 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
2416 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
2417 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2418 .resetvalue
= cpu
->mvfr2
},
2421 ARMCPRegInfo rvbar
= {
2422 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
2423 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
2424 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
2426 define_one_arm_cp_reg(cpu
, &rvbar
);
2427 define_arm_cp_regs(cpu
, v8_idregs
);
2428 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
2429 define_aarch64_debug_regs(cpu
);
2431 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2432 define_arm_cp_regs(cpu
, v8_el2_cp_reginfo
);
2434 /* If EL2 is missing but higher ELs are enabled, we need to
2435 * register the no_el2 reginfos.
2437 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2438 define_arm_cp_regs(cpu
, v8_el3_no_el2_cp_reginfo
);
2441 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2442 define_arm_cp_regs(cpu
, v8_el3_cp_reginfo
);
2444 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2445 /* These are the MPU registers prior to PMSAv6. Any new
2446 * PMSA core later than the ARM946 will require that we
2447 * implement the PMSAv6 or PMSAv7 registers, which are
2448 * completely different.
2450 assert(!arm_feature(env
, ARM_FEATURE_V6
));
2451 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
2453 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
2455 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
2456 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
2458 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
2459 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
2461 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
2462 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
2464 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
2465 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
2467 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
2468 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
2470 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
2471 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
2473 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2474 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
2476 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2477 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
2479 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2480 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
2482 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
2483 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
2485 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2486 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
2488 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2489 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2490 * be read-only (ie write causes UNDEF exception).
2493 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
2494 /* Pre-v8 MIDR space.
2495 * Note that the MIDR isn't a simple constant register because
2496 * of the TI925 behaviour where writes to another register can
2497 * cause the MIDR value to change.
2499 * Unimplemented registers in the c15 0 0 0 space default to
2500 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2501 * and friends override accordingly.
2504 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
2505 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
2506 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
2507 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
2508 .type
= ARM_CP_OVERRIDE
},
2509 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2511 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
2512 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2514 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
2515 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2517 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
2518 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2520 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
2521 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2523 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
2524 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2527 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
2528 /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2529 * variable-MIDR TI925 behaviour. Instead we have a single
2530 * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2532 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
2533 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
2534 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
},
2535 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
2536 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
2537 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
},
2540 ARMCPRegInfo id_cp_reginfo
[] = {
2541 /* These are common to v8 and pre-v8 */
2543 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
2544 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2545 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
2546 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
2547 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
2548 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2549 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2551 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
2552 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2554 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
2555 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2558 ARMCPRegInfo crn0_wi_reginfo
= {
2559 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
2560 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
2561 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
2563 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
2564 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2566 /* Register the blanket "writes ignored" value first to cover the
2567 * whole space. Then update the specific ID registers to allow write
2568 * access, so that they ignore writes rather than causing them to
2571 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
2572 for (r
= id_pre_v8_midr_cp_reginfo
;
2573 r
->type
!= ARM_CP_SENTINEL
; r
++) {
2576 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2580 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2581 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
2583 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
2585 define_arm_cp_regs(cpu
, id_cp_reginfo
);
2588 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
2589 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
2592 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
2593 ARMCPRegInfo auxcr
= {
2594 .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
2595 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
2596 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2597 .resetvalue
= cpu
->reset_auxcr
2599 define_one_arm_cp_reg(cpu
, &auxcr
);
2602 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
2603 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2604 /* 32 bit view is [31:18] 0...0 [43:32]. */
2605 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
2606 | extract64(cpu
->reset_cbar
, 32, 12);
2607 ARMCPRegInfo cbar_reginfo
[] = {
2609 .type
= ARM_CP_CONST
,
2610 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
2611 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
2612 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
2613 .type
= ARM_CP_CONST
,
2614 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
2615 .access
= PL1_R
, .resetvalue
= cbar32
},
2618 /* We don't implement a r/w 64 bit CBAR currently */
2619 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
2620 define_arm_cp_regs(cpu
, cbar_reginfo
);
2622 ARMCPRegInfo cbar
= {
2624 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
2625 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
2626 .fieldoffset
= offsetof(CPUARMState
,
2627 cp15
.c15_config_base_address
)
2629 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
2630 cbar
.access
= PL1_R
;
2631 cbar
.fieldoffset
= 0;
2632 cbar
.type
= ARM_CP_CONST
;
2634 define_one_arm_cp_reg(cpu
, &cbar
);
2638 /* Generic registers whose values depend on the implementation */
2640 ARMCPRegInfo sctlr
= {
2641 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
2642 .opc0
= 3, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
2643 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
2644 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
2645 .raw_writefn
= raw_write
,
2647 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2648 /* Normally we would always end the TB on an SCTLR write, but Linux
2649 * arch/arm/mach-pxa/sleep.S expects two instructions following
2650 * an MMU enable to execute from cache. Imitate this behaviour.
2652 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
2654 define_one_arm_cp_reg(cpu
, &sctlr
);
2658 ARMCPU
*cpu_arm_init(const char *cpu_model
)
2660 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
2663 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
2665 CPUState
*cs
= CPU(cpu
);
2666 CPUARMState
*env
= &cpu
->env
;
2668 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2669 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
2670 aarch64_fpu_gdb_set_reg
,
2671 34, "aarch64-fpu.xml", 0);
2672 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
2673 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2674 51, "arm-neon.xml", 0);
2675 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
2676 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2677 35, "arm-vfp3.xml", 0);
2678 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
2679 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2680 19, "arm-vfp.xml", 0);
2684 /* Sort alphabetically by type name, except for "any". */
2685 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2687 ObjectClass
*class_a
= (ObjectClass
*)a
;
2688 ObjectClass
*class_b
= (ObjectClass
*)b
;
2689 const char *name_a
, *name_b
;
2691 name_a
= object_class_get_name(class_a
);
2692 name_b
= object_class_get_name(class_b
);
2693 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
2695 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
2698 return strcmp(name_a
, name_b
);
2702 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
2704 ObjectClass
*oc
= data
;
2705 CPUListState
*s
= user_data
;
2706 const char *typename
;
2709 typename
= object_class_get_name(oc
);
2710 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2711 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
2716 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2720 .cpu_fprintf
= cpu_fprintf
,
2724 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2725 list
= g_slist_sort(list
, arm_cpu_list_compare
);
2726 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2727 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
2730 /* The 'host' CPU type is dynamically registered only if KVM is
2731 * enabled, so we have to special-case it here:
2733 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
2737 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
2739 ObjectClass
*oc
= data
;
2740 CpuDefinitionInfoList
**cpu_list
= user_data
;
2741 CpuDefinitionInfoList
*entry
;
2742 CpuDefinitionInfo
*info
;
2743 const char *typename
;
2745 typename
= object_class_get_name(oc
);
2746 info
= g_malloc0(sizeof(*info
));
2747 info
->name
= g_strndup(typename
,
2748 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2750 entry
= g_malloc0(sizeof(*entry
));
2751 entry
->value
= info
;
2752 entry
->next
= *cpu_list
;
2756 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2758 CpuDefinitionInfoList
*cpu_list
= NULL
;
2761 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2762 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
2768 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
2769 void *opaque
, int state
,
2770 int crm
, int opc1
, int opc2
)
2772 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2773 * add a single reginfo struct to the hash table.
2775 uint32_t *key
= g_new(uint32_t, 1);
2776 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
2777 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
2778 if (r
->state
== ARM_CP_STATE_BOTH
&& state
== ARM_CP_STATE_AA32
) {
2779 /* The AArch32 view of a shared register sees the lower 32 bits
2780 * of a 64 bit backing field. It is not migratable as the AArch64
2781 * view handles that. AArch64 also handles reset.
2782 * We assume it is a cp15 register.
2785 r2
->type
|= ARM_CP_NO_MIGRATE
;
2786 r2
->resetfn
= arm_cp_reset_ignore
;
2787 #ifdef HOST_WORDS_BIGENDIAN
2788 if (r2
->fieldoffset
) {
2789 r2
->fieldoffset
+= sizeof(uint32_t);
2793 if (state
== ARM_CP_STATE_AA64
) {
2794 /* To allow abbreviation of ARMCPRegInfo
2795 * definitions, we treat cp == 0 as equivalent to
2796 * the value for "standard guest-visible sysreg".
2799 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
2801 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
2802 r2
->opc0
, opc1
, opc2
);
2804 *key
= ENCODE_CP_REG(r2
->cp
, is64
, r2
->crn
, crm
, opc1
, opc2
);
2807 r2
->opaque
= opaque
;
2809 /* reginfo passed to helpers is correct for the actual access,
2810 * and is never ARM_CP_STATE_BOTH:
2813 /* Make sure reginfo passed to helpers for wildcarded regs
2814 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2819 /* By convention, for wildcarded registers only the first
2820 * entry is used for migration; the others are marked as
2821 * NO_MIGRATE so we don't try to transfer the register
2822 * multiple times. Special registers (ie NOP/WFI) are
2825 if ((r
->type
& ARM_CP_SPECIAL
) ||
2826 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
2827 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
2828 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
2829 r2
->type
|= ARM_CP_NO_MIGRATE
;
2832 /* Overriding of an existing definition must be explicitly
2835 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
2836 ARMCPRegInfo
*oldreg
;
2837 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
2838 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
2839 fprintf(stderr
, "Register redefined: cp=%d %d bit "
2840 "crn=%d crm=%d opc1=%d opc2=%d, "
2841 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
2842 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
2843 oldreg
->name
, r2
->name
);
2844 g_assert_not_reached();
2847 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
2851 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
2852 const ARMCPRegInfo
*r
, void *opaque
)
2854 /* Define implementations of coprocessor registers.
2855 * We store these in a hashtable because typically
2856 * there are less than 150 registers in a space which
2857 * is 16*16*16*8*8 = 262144 in size.
2858 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2859 * If a register is defined twice then the second definition is
2860 * used, so this can be used to define some generic registers and
2861 * then override them with implementation specific variations.
2862 * At least one of the original and the second definition should
2863 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2864 * against accidental use.
2866 * The state field defines whether the register is to be
2867 * visible in the AArch32 or AArch64 execution state. If the
2868 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2869 * reginfo structure for the AArch32 view, which sees the lower
2870 * 32 bits of the 64 bit register.
2872 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2873 * be wildcarded. AArch64 registers are always considered to be 64
2874 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2875 * the register, if any.
2877 int crm
, opc1
, opc2
, state
;
2878 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
2879 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
2880 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
2881 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
2882 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
2883 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
2884 /* 64 bit registers have only CRm and Opc1 fields */
2885 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
2886 /* op0 only exists in the AArch64 encodings */
2887 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
2888 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2889 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
2890 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2891 * encodes a minimum access level for the register. We roll this
2892 * runtime check into our general permission check code, so check
2893 * here that the reginfo's specified permissions are strict enough
2894 * to encompass the generic architectural permission check.
2896 if (r
->state
!= ARM_CP_STATE_AA32
) {
2899 case 0: case 1: case 2:
2912 /* unallocated encoding, so not possible */
2920 /* min_EL EL1, secure mode only (we don't check the latter) */
2924 /* broken reginfo with out-of-range opc1 */
2928 /* assert our permissions are not too lax (stricter is fine) */
2929 assert((r
->access
& ~mask
) == 0);
2932 /* Check that the register definition has enough info to handle
2933 * reads and writes if they are permitted.
2935 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
2936 if (r
->access
& PL3_R
) {
2937 assert(r
->fieldoffset
|| r
->readfn
);
2939 if (r
->access
& PL3_W
) {
2940 assert(r
->fieldoffset
|| r
->writefn
);
2943 /* Bad type field probably means missing sentinel at end of reg list */
2944 assert(cptype_valid(r
->type
));
2945 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
2946 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
2947 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
2948 for (state
= ARM_CP_STATE_AA32
;
2949 state
<= ARM_CP_STATE_AA64
; state
++) {
2950 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
2953 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
2961 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
2962 const ARMCPRegInfo
*regs
, void *opaque
)
2964 /* Define a whole list of registers */
2965 const ARMCPRegInfo
*r
;
2966 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2967 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
2971 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
2973 return g_hash_table_lookup(cpregs
, &encoded_cp
);
2976 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2979 /* Helper coprocessor write function for write-ignore registers */
2982 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2984 /* Helper coprocessor write function for read-as-zero registers */
2988 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2990 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2993 static int bad_mode_switch(CPUARMState
*env
, int mode
)
2995 /* Return true if it is not valid for us to switch to
2996 * this CPU mode (ie all the UNPREDICTABLE cases in
2997 * the ARM ARM CPSRWriteByInstr pseudocode).
3000 case ARM_CPU_MODE_USR
:
3001 case ARM_CPU_MODE_SYS
:
3002 case ARM_CPU_MODE_SVC
:
3003 case ARM_CPU_MODE_ABT
:
3004 case ARM_CPU_MODE_UND
:
3005 case ARM_CPU_MODE_IRQ
:
3006 case ARM_CPU_MODE_FIQ
:
3013 uint32_t cpsr_read(CPUARMState
*env
)
3016 ZF
= (env
->ZF
== 0);
3017 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
3018 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
3019 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
3020 | ((env
->condexec_bits
& 0xfc) << 8)
3021 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
3024 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
3026 if (mask
& CPSR_NZCV
) {
3027 env
->ZF
= (~val
) & CPSR_Z
;
3029 env
->CF
= (val
>> 29) & 1;
3030 env
->VF
= (val
<< 3) & 0x80000000;
3033 env
->QF
= ((val
& CPSR_Q
) != 0);
3035 env
->thumb
= ((val
& CPSR_T
) != 0);
3036 if (mask
& CPSR_IT_0_1
) {
3037 env
->condexec_bits
&= ~3;
3038 env
->condexec_bits
|= (val
>> 25) & 3;
3040 if (mask
& CPSR_IT_2_7
) {
3041 env
->condexec_bits
&= 3;
3042 env
->condexec_bits
|= (val
>> 8) & 0xfc;
3044 if (mask
& CPSR_GE
) {
3045 env
->GE
= (val
>> 16) & 0xf;
3048 env
->daif
&= ~(CPSR_AIF
& mask
);
3049 env
->daif
|= val
& CPSR_AIF
& mask
;
3051 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
3052 if (bad_mode_switch(env
, val
& CPSR_M
)) {
3053 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3054 * We choose to ignore the attempt and leave the CPSR M field
3059 switch_mode(env
, val
& CPSR_M
);
3062 mask
&= ~CACHED_CPSR_BITS
;
3063 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
3066 /* Sign/zero extend */
3067 uint32_t HELPER(sxtb16
)(uint32_t x
)
3070 res
= (uint16_t)(int8_t)x
;
3071 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
3075 uint32_t HELPER(uxtb16
)(uint32_t x
)
3078 res
= (uint16_t)(uint8_t)x
;
3079 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
3083 uint32_t HELPER(clz
)(uint32_t x
)
3088 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
3092 if (num
== INT_MIN
&& den
== -1)
3097 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
3104 uint32_t HELPER(rbit
)(uint32_t x
)
3106 x
= ((x
& 0xff000000) >> 24)
3107 | ((x
& 0x00ff0000) >> 8)
3108 | ((x
& 0x0000ff00) << 8)
3109 | ((x
& 0x000000ff) << 24);
3110 x
= ((x
& 0xf0f0f0f0) >> 4)
3111 | ((x
& 0x0f0f0f0f) << 4);
3112 x
= ((x
& 0x88888888) >> 3)
3113 | ((x
& 0x44444444) >> 1)
3114 | ((x
& 0x22222222) << 1)
3115 | ((x
& 0x11111111) << 3);
3119 #if defined(CONFIG_USER_ONLY)
3121 void arm_cpu_do_interrupt(CPUState
*cs
)
3123 cs
->exception_index
= -1;
3126 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
3129 ARMCPU
*cpu
= ARM_CPU(cs
);
3130 CPUARMState
*env
= &cpu
->env
;
3132 env
->exception
.vaddress
= address
;
3134 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
3136 cs
->exception_index
= EXCP_DATA_ABORT
;
3141 /* These should probably raise undefined insn exceptions. */
3142 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
3144 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3146 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
3149 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
3151 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3153 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
3157 void switch_mode(CPUARMState
*env
, int mode
)
3159 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3161 if (mode
!= ARM_CPU_MODE_USR
) {
3162 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
3166 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
3168 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3170 cpu_abort(CPU(cpu
), "banked r13 write\n");
3173 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
3175 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3177 cpu_abort(CPU(cpu
), "banked r13 read\n");
3183 /* Map CPU modes onto saved register banks. */
3184 int bank_number(int mode
)
3187 case ARM_CPU_MODE_USR
:
3188 case ARM_CPU_MODE_SYS
:
3190 case ARM_CPU_MODE_SVC
:
3192 case ARM_CPU_MODE_ABT
:
3194 case ARM_CPU_MODE_UND
:
3196 case ARM_CPU_MODE_IRQ
:
3198 case ARM_CPU_MODE_FIQ
:
3200 case ARM_CPU_MODE_HYP
:
3202 case ARM_CPU_MODE_MON
:
3205 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
3208 void switch_mode(CPUARMState
*env
, int mode
)
3213 old_mode
= env
->uncached_cpsr
& CPSR_M
;
3214 if (mode
== old_mode
)
3217 if (old_mode
== ARM_CPU_MODE_FIQ
) {
3218 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
3219 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
3220 } else if (mode
== ARM_CPU_MODE_FIQ
) {
3221 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
3222 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
3225 i
= bank_number(old_mode
);
3226 env
->banked_r13
[i
] = env
->regs
[13];
3227 env
->banked_r14
[i
] = env
->regs
[14];
3228 env
->banked_spsr
[i
] = env
->spsr
;
3230 i
= bank_number(mode
);
3231 env
->regs
[13] = env
->banked_r13
[i
];
3232 env
->regs
[14] = env
->banked_r14
[i
];
3233 env
->spsr
= env
->banked_spsr
[i
];
3236 static void v7m_push(CPUARMState
*env
, uint32_t val
)
3238 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3241 stl_phys(cs
->as
, env
->regs
[13], val
);
3244 static uint32_t v7m_pop(CPUARMState
*env
)
3246 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3249 val
= ldl_phys(cs
->as
, env
->regs
[13]);
3254 /* Switch to V7M main or process stack pointer. */
3255 static void switch_v7m_sp(CPUARMState
*env
, int process
)
3258 if (env
->v7m
.current_sp
!= process
) {
3259 tmp
= env
->v7m
.other_sp
;
3260 env
->v7m
.other_sp
= env
->regs
[13];
3261 env
->regs
[13] = tmp
;
3262 env
->v7m
.current_sp
= process
;
3266 static void do_v7m_exception_exit(CPUARMState
*env
)
3271 type
= env
->regs
[15];
3272 if (env
->v7m
.exception
!= 0)
3273 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
3275 /* Switch to the target stack. */
3276 switch_v7m_sp(env
, (type
& 4) != 0);
3277 /* Pop registers. */
3278 env
->regs
[0] = v7m_pop(env
);
3279 env
->regs
[1] = v7m_pop(env
);
3280 env
->regs
[2] = v7m_pop(env
);
3281 env
->regs
[3] = v7m_pop(env
);
3282 env
->regs
[12] = v7m_pop(env
);
3283 env
->regs
[14] = v7m_pop(env
);
3284 env
->regs
[15] = v7m_pop(env
);
3285 xpsr
= v7m_pop(env
);
3286 xpsr_write(env
, xpsr
, 0xfffffdff);
3287 /* Undo stack alignment. */
3290 /* ??? The exception return type specifies Thread/Handler mode. However
3291 this is also implied by the xPSR value. Not sure what to do
3292 if there is a mismatch. */
3293 /* ??? Likewise for mismatches between the CONTROL register and the stack
3297 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
3299 ARMCPU
*cpu
= ARM_CPU(cs
);
3300 CPUARMState
*env
= &cpu
->env
;
3301 uint32_t xpsr
= xpsr_read(env
);
3305 arm_log_exception(cs
->exception_index
);
3308 if (env
->v7m
.current_sp
)
3310 if (env
->v7m
.exception
== 0)
3313 /* For exceptions we just mark as pending on the NVIC, and let that
3315 /* TODO: Need to escalate if the current priority is higher than the
3316 one we're raising. */
3317 switch (cs
->exception_index
) {
3319 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
3322 /* The PC already points to the next instruction. */
3323 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
3325 case EXCP_PREFETCH_ABORT
:
3326 case EXCP_DATA_ABORT
:
3327 /* TODO: if we implemented the MPU registers, this is where we
3328 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3330 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
3333 if (semihosting_enabled
) {
3335 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
3338 env
->regs
[0] = do_arm_semihosting(env
);
3339 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3343 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
3346 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
3348 case EXCP_EXCEPTION_EXIT
:
3349 do_v7m_exception_exit(env
);
3352 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
3353 return; /* Never happens. Keep compiler happy. */
3356 /* Align stack pointer. */
3357 /* ??? Should only do this if Configuration Control Register
3358 STACKALIGN bit is set. */
3359 if (env
->regs
[13] & 4) {
3363 /* Switch to the handler mode. */
3364 v7m_push(env
, xpsr
);
3365 v7m_push(env
, env
->regs
[15]);
3366 v7m_push(env
, env
->regs
[14]);
3367 v7m_push(env
, env
->regs
[12]);
3368 v7m_push(env
, env
->regs
[3]);
3369 v7m_push(env
, env
->regs
[2]);
3370 v7m_push(env
, env
->regs
[1]);
3371 v7m_push(env
, env
->regs
[0]);
3372 switch_v7m_sp(env
, 0);
3374 env
->condexec_bits
= 0;
3376 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
3377 env
->regs
[15] = addr
& 0xfffffffe;
3378 env
->thumb
= addr
& 1;
3381 /* Handle a CPU exception. */
3382 void arm_cpu_do_interrupt(CPUState
*cs
)
3384 ARMCPU
*cpu
= ARM_CPU(cs
);
3385 CPUARMState
*env
= &cpu
->env
;
3393 arm_log_exception(cs
->exception_index
);
3395 /* TODO: Vectored interrupt controller. */
3396 switch (cs
->exception_index
) {
3398 new_mode
= ARM_CPU_MODE_UND
;
3407 if (semihosting_enabled
) {
3408 /* Check for semihosting interrupt. */
3410 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
3413 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
3416 /* Only intercept calls from privileged modes, to provide some
3417 semblance of security. */
3418 if (((mask
== 0x123456 && !env
->thumb
)
3419 || (mask
== 0xab && env
->thumb
))
3420 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3421 env
->regs
[0] = do_arm_semihosting(env
);
3422 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3426 new_mode
= ARM_CPU_MODE_SVC
;
3429 /* The PC already points to the next instruction. */
3433 /* See if this is a semihosting syscall. */
3434 if (env
->thumb
&& semihosting_enabled
) {
3435 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
3437 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3439 env
->regs
[0] = do_arm_semihosting(env
);
3440 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3444 env
->exception
.fsr
= 2;
3445 /* Fall through to prefetch abort. */
3446 case EXCP_PREFETCH_ABORT
:
3447 env
->cp15
.ifsr_el2
= env
->exception
.fsr
;
3448 env
->cp15
.far_el
[1] = deposit64(env
->cp15
.far_el
[1], 32, 32,
3449 env
->exception
.vaddress
);
3450 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
3451 env
->cp15
.ifsr_el2
, (uint32_t)env
->exception
.vaddress
);
3452 new_mode
= ARM_CPU_MODE_ABT
;
3454 mask
= CPSR_A
| CPSR_I
;
3457 case EXCP_DATA_ABORT
:
3458 env
->cp15
.esr_el
[1] = env
->exception
.fsr
;
3459 env
->cp15
.far_el
[1] = deposit64(env
->cp15
.far_el
[1], 0, 32,
3460 env
->exception
.vaddress
);
3461 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
3462 (uint32_t)env
->cp15
.esr_el
[1],
3463 (uint32_t)env
->exception
.vaddress
);
3464 new_mode
= ARM_CPU_MODE_ABT
;
3466 mask
= CPSR_A
| CPSR_I
;
3470 new_mode
= ARM_CPU_MODE_IRQ
;
3472 /* Disable IRQ and imprecise data aborts. */
3473 mask
= CPSR_A
| CPSR_I
;
3477 new_mode
= ARM_CPU_MODE_FIQ
;
3479 /* Disable FIQ, IRQ and imprecise data aborts. */
3480 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
3484 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
3485 return; /* Never happens. Keep compiler happy. */
3488 if (env
->cp15
.c1_sys
& SCTLR_V
) {
3489 /* when enabled, base address cannot be remapped. */
3492 /* ARM v7 architectures provide a vector base address register to remap
3493 * the interrupt vector table.
3494 * This register is only followed in non-monitor mode, and has a secure
3495 * and un-secure copy. Since the cpu is always in a un-secure operation
3496 * and is never in monitor mode this feature is always active.
3497 * Note: only bits 31:5 are valid.
3499 addr
+= env
->cp15
.vbar_el
[1];
3501 switch_mode (env
, new_mode
);
3502 env
->spsr
= cpsr_read(env
);
3503 /* Clear IT bits. */
3504 env
->condexec_bits
= 0;
3505 /* Switch to the new mode, and to the correct instruction set. */
3506 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
3508 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3509 * and we should just guard the thumb mode on V4 */
3510 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
3511 env
->thumb
= (env
->cp15
.c1_sys
& SCTLR_TE
) != 0;
3513 env
->regs
[14] = env
->regs
[15] + offset
;
3514 env
->regs
[15] = addr
;
3515 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
3518 /* Check section/page access permissions.
3519 Returns the page protection flags, or zero if the access is not
3521 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
3522 int access_type
, int is_user
)
3526 if (domain_prot
== 3) {
3527 return PAGE_READ
| PAGE_WRITE
;
3530 if (access_type
== 1)
3533 prot_ro
= PAGE_READ
;
3537 if (arm_feature(env
, ARM_FEATURE_V7
)) {
3540 if (access_type
== 1)
3542 switch (env
->cp15
.c1_sys
& (SCTLR_S
| SCTLR_R
)) {
3544 return is_user
? 0 : PAGE_READ
;
3551 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
3556 return PAGE_READ
| PAGE_WRITE
;
3558 return PAGE_READ
| PAGE_WRITE
;
3559 case 4: /* Reserved. */
3562 return is_user
? 0 : prot_ro
;
3566 if (!arm_feature (env
, ARM_FEATURE_V6K
))
3574 static bool get_level1_table_address(CPUARMState
*env
, uint32_t *table
,
3577 if (address
& env
->cp15
.c2_mask
) {
3578 if ((env
->cp15
.c2_control
& TTBCR_PD1
)) {
3579 /* Translation table walk disabled for TTBR1 */
3582 *table
= env
->cp15
.ttbr1_el1
& 0xffffc000;
3584 if ((env
->cp15
.c2_control
& TTBCR_PD0
)) {
3585 /* Translation table walk disabled for TTBR0 */
3588 *table
= env
->cp15
.ttbr0_el1
& env
->cp15
.c2_base_mask
;
3590 *table
|= (address
>> 18) & 0x3ffc;
3594 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
3595 int is_user
, hwaddr
*phys_ptr
,
3596 int *prot
, target_ulong
*page_size
)
3598 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3608 /* Pagetable walk. */
3609 /* Lookup l1 descriptor. */
3610 if (!get_level1_table_address(env
, &table
, address
)) {
3611 /* Section translation fault if page walk is disabled by PD0 or PD1 */
3615 desc
= ldl_phys(cs
->as
, table
);
3617 domain
= (desc
>> 5) & 0x0f;
3618 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3620 /* Section translation fault. */
3624 if (domain_prot
== 0 || domain_prot
== 2) {
3626 code
= 9; /* Section domain fault. */
3628 code
= 11; /* Page domain fault. */
3633 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3634 ap
= (desc
>> 10) & 3;
3636 *page_size
= 1024 * 1024;
3638 /* Lookup l2 entry. */
3640 /* Coarse pagetable. */
3641 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3643 /* Fine pagetable. */
3644 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
3646 desc
= ldl_phys(cs
->as
, table
);
3648 case 0: /* Page translation fault. */
3651 case 1: /* 64k page. */
3652 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3653 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
3654 *page_size
= 0x10000;
3656 case 2: /* 4k page. */
3657 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3658 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
3659 *page_size
= 0x1000;
3661 case 3: /* 1k page. */
3663 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3664 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3666 /* Page translation fault. */
3671 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
3673 ap
= (desc
>> 4) & 3;
3677 /* Never happens, but compiler isn't smart enough to tell. */
3682 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3684 /* Access permission fault. */
3688 *phys_ptr
= phys_addr
;
3691 return code
| (domain
<< 4);
3694 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
3695 int is_user
, hwaddr
*phys_ptr
,
3696 int *prot
, target_ulong
*page_size
)
3698 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3710 /* Pagetable walk. */
3711 /* Lookup l1 descriptor. */
3712 if (!get_level1_table_address(env
, &table
, address
)) {
3713 /* Section translation fault if page walk is disabled by PD0 or PD1 */
3717 desc
= ldl_phys(cs
->as
, table
);
3719 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
3720 /* Section translation fault, or attempt to use the encoding
3721 * which is Reserved on implementations without PXN.
3726 if ((type
== 1) || !(desc
& (1 << 18))) {
3727 /* Page or Section. */
3728 domain
= (desc
>> 5) & 0x0f;
3730 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3731 if (domain_prot
== 0 || domain_prot
== 2) {
3733 code
= 9; /* Section domain fault. */
3735 code
= 11; /* Page domain fault. */
3740 if (desc
& (1 << 18)) {
3742 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
3743 *page_size
= 0x1000000;
3746 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3747 *page_size
= 0x100000;
3749 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
3750 xn
= desc
& (1 << 4);
3754 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
3755 pxn
= (desc
>> 2) & 1;
3757 /* Lookup l2 entry. */
3758 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3759 desc
= ldl_phys(cs
->as
, table
);
3760 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
3762 case 0: /* Page translation fault. */
3765 case 1: /* 64k page. */
3766 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3767 xn
= desc
& (1 << 15);
3768 *page_size
= 0x10000;
3770 case 2: case 3: /* 4k page. */
3771 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3773 *page_size
= 0x1000;
3776 /* Never happens, but compiler isn't smart enough to tell. */
3781 if (domain_prot
== 3) {
3782 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3784 if (pxn
&& !is_user
) {
3787 if (xn
&& access_type
== 2)
3790 /* The simplified model uses AP[0] as an access control bit. */
3791 if ((env
->cp15
.c1_sys
& SCTLR_AFE
) && (ap
& 1) == 0) {
3792 /* Access flag fault. */
3793 code
= (code
== 15) ? 6 : 3;
3796 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3798 /* Access permission fault. */
3805 *phys_ptr
= phys_addr
;
3808 return code
| (domain
<< 4);
3811 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3812 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3815 translation_fault
= 1,
3817 permission_fault
= 3,
3820 static int get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
3821 int access_type
, int is_user
,
3822 hwaddr
*phys_ptr
, int *prot
,
3823 target_ulong
*page_size_ptr
)
3825 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3826 /* Read an LPAE long-descriptor translation table. */
3827 MMUFaultType fault_type
= translation_fault
;
3834 hwaddr descaddr
, descmask
;
3835 uint32_t tableattrs
;
3836 target_ulong page_size
;
3838 int32_t granule_sz
= 9;
3839 int32_t va_size
= 32;
3842 if (arm_el_is_aa64(env
, 1)) {
3844 if (extract64(address
, 55, 1))
3845 tbi
= extract64(env
->cp15
.c2_control
, 38, 1);
3847 tbi
= extract64(env
->cp15
.c2_control
, 37, 1);
3851 /* Determine whether this address is in the region controlled by
3852 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3853 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3854 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3856 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 6);
3857 if (arm_el_is_aa64(env
, 1)) {
3858 t0sz
= MIN(t0sz
, 39);
3859 t0sz
= MAX(t0sz
, 16);
3861 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 6);
3862 if (arm_el_is_aa64(env
, 1)) {
3863 t1sz
= MIN(t1sz
, 39);
3864 t1sz
= MAX(t1sz
, 16);
3866 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
3867 /* there is a ttbr0 region and we are in it (high bits all zero) */
3869 } else if (t1sz
&& !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
3870 /* there is a ttbr1 region and we are in it (high bits all one) */
3873 /* ttbr0 region is "everything not in the ttbr1 region" */
3876 /* ttbr1 region is "everything not in the ttbr0 region" */
3879 /* in the gap between the two regions, this is a Translation fault */
3880 fault_type
= translation_fault
;
3884 /* Note that QEMU ignores shareability and cacheability attributes,
3885 * so we don't need to do anything with the SH, ORGN, IRGN fields
3886 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3887 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3888 * implement any ASID-like capability so we can ignore it (instead
3889 * we will always flush the TLB any time the ASID is changed).
3891 if (ttbr_select
== 0) {
3892 ttbr
= env
->cp15
.ttbr0_el1
;
3893 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
3896 tg
= extract32(env
->cp15
.c2_control
, 14, 2);
3897 if (tg
== 1) { /* 64KB pages */
3900 if (tg
== 2) { /* 16KB pages */
3904 ttbr
= env
->cp15
.ttbr1_el1
;
3905 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
3908 tg
= extract32(env
->cp15
.c2_control
, 30, 2);
3909 if (tg
== 3) { /* 64KB pages */
3912 if (tg
== 1) { /* 16KB pages */
3918 /* Translation table walk disabled => Translation fault on TLB miss */
3922 /* The starting level depends on the virtual address size which can be
3923 * up to 48-bits and the translation granule size.
3925 if ((va_size
- tsz
) > (granule_sz
* 4 + 3)) {
3927 } else if ((va_size
- tsz
) > (granule_sz
* 3 + 3)) {
3933 /* Clear the vaddr bits which aren't part of the within-region address,
3934 * so that we don't have to special case things when calculating the
3935 * first descriptor address.
3938 address
&= (1ULL << (va_size
- tsz
)) - 1;
3941 descmask
= (1ULL << (granule_sz
+ 3)) - 1;
3943 /* Now we can extract the actual base address from the TTBR */
3944 descaddr
= extract64(ttbr
, 0, 48);
3945 descaddr
&= ~((1ULL << (va_size
- tsz
- (granule_sz
* (4 - level
)))) - 1);
3949 uint64_t descriptor
;
3951 descaddr
|= (address
>> (granule_sz
* (4 - level
))) & descmask
;
3953 descriptor
= ldq_phys(cs
->as
, descaddr
);
3954 if (!(descriptor
& 1) ||
3955 (!(descriptor
& 2) && (level
== 3))) {
3956 /* Invalid, or the Reserved level 3 encoding */
3959 descaddr
= descriptor
& 0xfffffff000ULL
;
3961 if ((descriptor
& 2) && (level
< 3)) {
3962 /* Table entry. The top five bits are attributes which may
3963 * propagate down through lower levels of the table (and
3964 * which are all arranged so that 0 means "no effect", so
3965 * we can gather them up by ORing in the bits at each level).
3967 tableattrs
|= extract64(descriptor
, 59, 5);
3971 /* Block entry at level 1 or 2, or page entry at level 3.
3972 * These are basically the same thing, although the number
3973 * of bits we pull in from the vaddr varies.
3975 page_size
= (1ULL << ((granule_sz
* (4 - level
)) + 3));
3976 descaddr
|= (address
& (page_size
- 1));
3977 /* Extract attributes from the descriptor and merge with table attrs */
3978 attrs
= extract64(descriptor
, 2, 10)
3979 | (extract64(descriptor
, 52, 12) << 10);
3980 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
3981 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
3982 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3983 * means "force PL1 access only", which means forcing AP[1] to 0.
3985 if (extract32(tableattrs
, 2, 1)) {
3988 /* Since we're always in the Non-secure state, NSTable is ignored. */
3991 /* Here descaddr is the final physical address, and attributes
3994 fault_type
= access_fault
;
3995 if ((attrs
& (1 << 8)) == 0) {
3999 fault_type
= permission_fault
;
4000 if (is_user
&& !(attrs
& (1 << 4))) {
4001 /* Unprivileged access not enabled */
4004 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
4005 if ((arm_feature(env
, ARM_FEATURE_V8
) && is_user
&& (attrs
& (1 << 12))) ||
4006 (!arm_feature(env
, ARM_FEATURE_V8
) && (attrs
& (1 << 12))) ||
4007 (!is_user
&& (attrs
& (1 << 11)))) {
4008 /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4009 * treat XN/UXN as UXN for v8.
4011 if (access_type
== 2) {
4014 *prot
&= ~PAGE_EXEC
;
4016 if (attrs
& (1 << 5)) {
4017 /* Write access forbidden */
4018 if (access_type
== 1) {
4021 *prot
&= ~PAGE_WRITE
;
4024 *phys_ptr
= descaddr
;
4025 *page_size_ptr
= page_size
;
4029 /* Long-descriptor format IFSR/DFSR value */
4030 return (1 << 9) | (fault_type
<< 2) | level
;
4033 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
4034 int access_type
, int is_user
,
4035 hwaddr
*phys_ptr
, int *prot
)
4041 *phys_ptr
= address
;
4042 for (n
= 7; n
>= 0; n
--) {
4043 base
= env
->cp15
.c6_region
[n
];
4044 if ((base
& 1) == 0)
4046 mask
= 1 << ((base
>> 1) & 0x1f);
4047 /* Keep this shift separate from the above to avoid an
4048 (undefined) << 32. */
4049 mask
= (mask
<< 1) - 1;
4050 if (((base
^ address
) & ~mask
) == 0)
4056 if (access_type
== 2) {
4057 mask
= env
->cp15
.pmsav5_insn_ap
;
4059 mask
= env
->cp15
.pmsav5_data_ap
;
4061 mask
= (mask
>> (n
* 4)) & 0xf;
4068 *prot
= PAGE_READ
| PAGE_WRITE
;
4073 *prot
|= PAGE_WRITE
;
4076 *prot
= PAGE_READ
| PAGE_WRITE
;
4087 /* Bad permission. */
4094 /* get_phys_addr - get the physical address for this virtual address
4096 * Find the physical address corresponding to the given virtual address,
4097 * by doing a translation table walk on MMU based systems or using the
4098 * MPU state on MPU based systems.
4100 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4101 * prot and page_size are not filled in, and the return value provides
4102 * information on why the translation aborted, in the format of a
4103 * DFSR/IFSR fault register, with the following caveats:
4104 * * we honour the short vs long DFSR format differences.
4105 * * the WnR bit is never set (the caller must do this).
4106 * * for MPU based systems we don't bother to return a full FSR format
4110 * @address: virtual address to get physical address for
4111 * @access_type: 0 for read, 1 for write, 2 for execute
4112 * @is_user: 0 for privileged access, 1 for user
4113 * @phys_ptr: set to the physical address corresponding to the virtual address
4114 * @prot: set to the permissions for the page containing phys_ptr
4115 * @page_size: set to the size of the page containing phys_ptr
4117 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
4118 int access_type
, int is_user
,
4119 hwaddr
*phys_ptr
, int *prot
,
4120 target_ulong
*page_size
)
4122 /* Fast Context Switch Extension. */
4123 if (address
< 0x02000000)
4124 address
+= env
->cp15
.c13_fcse
;
4126 if ((env
->cp15
.c1_sys
& SCTLR_M
) == 0) {
4127 /* MMU/MPU disabled. */
4128 *phys_ptr
= address
;
4129 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
4130 *page_size
= TARGET_PAGE_SIZE
;
4132 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
4133 *page_size
= TARGET_PAGE_SIZE
;
4134 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
4136 } else if (extended_addresses_enabled(env
)) {
4137 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
4139 } else if (env
->cp15
.c1_sys
& SCTLR_XP
) {
4140 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
4143 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
4148 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
,
4149 int access_type
, int mmu_idx
)
4151 ARMCPU
*cpu
= ARM_CPU(cs
);
4152 CPUARMState
*env
= &cpu
->env
;
4154 target_ulong page_size
;
4158 bool same_el
= (arm_current_pl(env
) != 0);
4160 is_user
= mmu_idx
== MMU_USER_IDX
;
4161 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
4164 /* Map a single [sub]page. */
4165 phys_addr
&= TARGET_PAGE_MASK
;
4166 address
&= TARGET_PAGE_MASK
;
4167 tlb_set_page(cs
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
4171 /* AArch64 syndrome does not have an LPAE bit */
4172 syn
= ret
& ~(1 << 9);
4174 /* For insn and data aborts we assume there is no instruction syndrome
4175 * information; this is always true for exceptions reported to EL1.
4177 if (access_type
== 2) {
4178 syn
= syn_insn_abort(same_el
, 0, 0, syn
);
4179 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
4181 syn
= syn_data_abort(same_el
, 0, 0, 0, access_type
== 1, syn
);
4182 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
)) {
4185 cs
->exception_index
= EXCP_DATA_ABORT
;
4188 env
->exception
.syndrome
= syn
;
4189 env
->exception
.vaddress
= address
;
4190 env
->exception
.fsr
= ret
;
4194 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
4196 ARMCPU
*cpu
= ARM_CPU(cs
);
4198 target_ulong page_size
;
4202 ret
= get_phys_addr(&cpu
->env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
4211 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
4213 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
4214 env
->regs
[13] = val
;
4216 env
->banked_r13
[bank_number(mode
)] = val
;
4220 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
4222 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
4223 return env
->regs
[13];
4225 return env
->banked_r13
[bank_number(mode
)];
4229 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
4231 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4235 return xpsr_read(env
) & 0xf8000000;
4237 return xpsr_read(env
) & 0xf80001ff;
4239 return xpsr_read(env
) & 0xff00fc00;
4241 return xpsr_read(env
) & 0xff00fdff;
4243 return xpsr_read(env
) & 0x000001ff;
4245 return xpsr_read(env
) & 0x0700fc00;
4247 return xpsr_read(env
) & 0x0700edff;
4249 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
4251 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
4252 case 16: /* PRIMASK */
4253 return (env
->daif
& PSTATE_I
) != 0;
4254 case 17: /* BASEPRI */
4255 case 18: /* BASEPRI_MAX */
4256 return env
->v7m
.basepri
;
4257 case 19: /* FAULTMASK */
4258 return (env
->daif
& PSTATE_F
) != 0;
4259 case 20: /* CONTROL */
4260 return env
->v7m
.control
;
4262 /* ??? For debugging only. */
4263 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
4268 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
4270 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4274 xpsr_write(env
, val
, 0xf8000000);
4277 xpsr_write(env
, val
, 0xf8000000);
4280 xpsr_write(env
, val
, 0xfe00fc00);
4283 xpsr_write(env
, val
, 0xfe00fc00);
4286 /* IPSR bits are readonly. */
4289 xpsr_write(env
, val
, 0x0600fc00);
4292 xpsr_write(env
, val
, 0x0600fc00);
4295 if (env
->v7m
.current_sp
)
4296 env
->v7m
.other_sp
= val
;
4298 env
->regs
[13] = val
;
4301 if (env
->v7m
.current_sp
)
4302 env
->regs
[13] = val
;
4304 env
->v7m
.other_sp
= val
;
4306 case 16: /* PRIMASK */
4308 env
->daif
|= PSTATE_I
;
4310 env
->daif
&= ~PSTATE_I
;
4313 case 17: /* BASEPRI */
4314 env
->v7m
.basepri
= val
& 0xff;
4316 case 18: /* BASEPRI_MAX */
4318 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
4319 env
->v7m
.basepri
= val
;
4321 case 19: /* FAULTMASK */
4323 env
->daif
|= PSTATE_F
;
4325 env
->daif
&= ~PSTATE_F
;
4328 case 20: /* CONTROL */
4329 env
->v7m
.control
= val
& 3;
4330 switch_v7m_sp(env
, (val
& 2) != 0);
4333 /* ??? For debugging only. */
4334 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
4341 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
4343 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4344 * Note that we do not implement the (architecturally mandated)
4345 * alignment fault for attempts to use this on Device memory
4346 * (which matches the usual QEMU behaviour of not implementing either
4347 * alignment faults or any memory attribute handling).
4350 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4351 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
4352 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
4354 #ifndef CONFIG_USER_ONLY
4356 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4357 * the block size so we might have to do more than one TLB lookup.
4358 * We know that in fact for any v8 CPU the page size is at least 4K
4359 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4360 * 1K as an artefact of legacy v5 subpage support being present in the
4361 * same QEMU executable.
4363 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
4364 void *hostaddr
[maxidx
];
4367 for (try = 0; try < 2; try++) {
4369 for (i
= 0; i
< maxidx
; i
++) {
4370 hostaddr
[i
] = tlb_vaddr_to_host(env
,
4371 vaddr
+ TARGET_PAGE_SIZE
* i
,
4372 1, cpu_mmu_index(env
));
4378 /* If it's all in the TLB it's fair game for just writing to;
4379 * we know we don't need to update dirty status, etc.
4381 for (i
= 0; i
< maxidx
- 1; i
++) {
4382 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
4384 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
4387 /* OK, try a store and see if we can populate the tlb. This
4388 * might cause an exception if the memory isn't writable,
4389 * in which case we will longjmp out of here. We must for
4390 * this purpose use the actual register value passed to us
4391 * so that we get the fault address right.
4393 helper_ret_stb_mmu(env
, vaddr_in
, 0, cpu_mmu_index(env
), GETRA());
4394 /* Now we can populate the other TLB entries, if any */
4395 for (i
= 0; i
< maxidx
; i
++) {
4396 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
4397 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
4398 helper_ret_stb_mmu(env
, va
, 0, cpu_mmu_index(env
), GETRA());
4403 /* Slow path (probably attempt to do this to an I/O device or
4404 * similar, or clearing of a block of code we have translations
4405 * cached for). Just do a series of byte writes as the architecture
4406 * demands. It's not worth trying to use a cpu_physical_memory_map(),
4407 * memset(), unmap() sequence here because:
4408 * + we'd need to account for the blocksize being larger than a page
4409 * + the direct-RAM access case is almost always going to be dealt
4410 * with in the fastpath code above, so there's no speed benefit
4411 * + we would have to deal with the map returning NULL because the
4412 * bounce buffer was in use
4414 for (i
= 0; i
< blocklen
; i
++) {
4415 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, cpu_mmu_index(env
), GETRA());
4419 memset(g2h(vaddr
), 0, blocklen
);
4423 /* Note that signed overflow is undefined in C. The following routines are
4424 careful to use unsigned types where modulo arithmetic is required.
4425 Failure to do so _will_ break on newer gcc. */
4427 /* Signed saturating arithmetic. */
4429 /* Perform 16-bit signed saturating addition. */
4430 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
4435 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
4444 /* Perform 8-bit signed saturating addition. */
4445 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
4450 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
4459 /* Perform 16-bit signed saturating subtraction. */
4460 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
4465 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
4474 /* Perform 8-bit signed saturating subtraction. */
4475 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
4480 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
4489 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4490 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4491 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
4492 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
4495 #include "op_addsub.h"
4497 /* Unsigned saturating arithmetic. */
4498 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
4507 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
4515 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
4524 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
4532 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4533 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4534 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
4535 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
4538 #include "op_addsub.h"
4540 /* Signed modulo arithmetic. */
4541 #define SARITH16(a, b, n, op) do { \
4543 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4544 RESULT(sum, n, 16); \
4546 ge |= 3 << (n * 2); \
4549 #define SARITH8(a, b, n, op) do { \
4551 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4552 RESULT(sum, n, 8); \
4558 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4559 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4560 #define ADD8(a, b, n) SARITH8(a, b, n, +)
4561 #define SUB8(a, b, n) SARITH8(a, b, n, -)
4565 #include "op_addsub.h"
4567 /* Unsigned modulo arithmetic. */
4568 #define ADD16(a, b, n) do { \
4570 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4571 RESULT(sum, n, 16); \
4572 if ((sum >> 16) == 1) \
4573 ge |= 3 << (n * 2); \
4576 #define ADD8(a, b, n) do { \
4578 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4579 RESULT(sum, n, 8); \
4580 if ((sum >> 8) == 1) \
4584 #define SUB16(a, b, n) do { \
4586 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4587 RESULT(sum, n, 16); \
4588 if ((sum >> 16) == 0) \
4589 ge |= 3 << (n * 2); \
4592 #define SUB8(a, b, n) do { \
4594 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4595 RESULT(sum, n, 8); \
4596 if ((sum >> 8) == 0) \
4603 #include "op_addsub.h"
4605 /* Halved signed arithmetic. */
4606 #define ADD16(a, b, n) \
4607 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4608 #define SUB16(a, b, n) \
4609 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4610 #define ADD8(a, b, n) \
4611 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4612 #define SUB8(a, b, n) \
4613 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4616 #include "op_addsub.h"
4618 /* Halved unsigned arithmetic. */
4619 #define ADD16(a, b, n) \
4620 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4621 #define SUB16(a, b, n) \
4622 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4623 #define ADD8(a, b, n) \
4624 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4625 #define SUB8(a, b, n) \
4626 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4629 #include "op_addsub.h"
4631 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
4639 /* Unsigned sum of absolute byte differences. */
4640 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
4643 sum
= do_usad(a
, b
);
4644 sum
+= do_usad(a
>> 8, b
>> 8);
4645 sum
+= do_usad(a
>> 16, b
>>16);
4646 sum
+= do_usad(a
>> 24, b
>> 24);
4650 /* For ARMv6 SEL instruction. */
4651 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
4664 return (a
& mask
) | (b
& ~mask
);
4667 /* VFP support. We follow the convention used for VFP instructions:
4668 Single precision routines have a "s" suffix, double precision a
4671 /* Convert host exception flags to vfp form. */
4672 static inline int vfp_exceptbits_from_host(int host_bits
)
4674 int target_bits
= 0;
4676 if (host_bits
& float_flag_invalid
)
4678 if (host_bits
& float_flag_divbyzero
)
4680 if (host_bits
& float_flag_overflow
)
4682 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
4684 if (host_bits
& float_flag_inexact
)
4685 target_bits
|= 0x10;
4686 if (host_bits
& float_flag_input_denormal
)
4687 target_bits
|= 0x80;
4691 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
4696 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
4697 | (env
->vfp
.vec_len
<< 16)
4698 | (env
->vfp
.vec_stride
<< 20);
4699 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
4700 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
4701 fpscr
|= vfp_exceptbits_from_host(i
);
4705 uint32_t vfp_get_fpscr(CPUARMState
*env
)
4707 return HELPER(vfp_get_fpscr
)(env
);
4710 /* Convert vfp exception flags to target form. */
4711 static inline int vfp_exceptbits_to_host(int target_bits
)
4715 if (target_bits
& 1)
4716 host_bits
|= float_flag_invalid
;
4717 if (target_bits
& 2)
4718 host_bits
|= float_flag_divbyzero
;
4719 if (target_bits
& 4)
4720 host_bits
|= float_flag_overflow
;
4721 if (target_bits
& 8)
4722 host_bits
|= float_flag_underflow
;
4723 if (target_bits
& 0x10)
4724 host_bits
|= float_flag_inexact
;
4725 if (target_bits
& 0x80)
4726 host_bits
|= float_flag_input_denormal
;
4730 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
4735 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
4736 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
4737 env
->vfp
.vec_len
= (val
>> 16) & 7;
4738 env
->vfp
.vec_stride
= (val
>> 20) & 3;
4741 if (changed
& (3 << 22)) {
4742 i
= (val
>> 22) & 3;
4744 case FPROUNDING_TIEEVEN
:
4745 i
= float_round_nearest_even
;
4747 case FPROUNDING_POSINF
:
4750 case FPROUNDING_NEGINF
:
4751 i
= float_round_down
;
4753 case FPROUNDING_ZERO
:
4754 i
= float_round_to_zero
;
4757 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
4759 if (changed
& (1 << 24)) {
4760 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4761 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4763 if (changed
& (1 << 25))
4764 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
4766 i
= vfp_exceptbits_to_host(val
);
4767 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
4768 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
4771 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
4773 HELPER(vfp_set_fpscr
)(env
, val
);
4776 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4778 #define VFP_BINOP(name) \
4779 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4781 float_status *fpst = fpstp; \
4782 return float32_ ## name(a, b, fpst); \
4784 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4786 float_status *fpst = fpstp; \
4787 return float64_ ## name(a, b, fpst); \
4799 float32
VFP_HELPER(neg
, s
)(float32 a
)
4801 return float32_chs(a
);
4804 float64
VFP_HELPER(neg
, d
)(float64 a
)
4806 return float64_chs(a
);
4809 float32
VFP_HELPER(abs
, s
)(float32 a
)
4811 return float32_abs(a
);
4814 float64
VFP_HELPER(abs
, d
)(float64 a
)
4816 return float64_abs(a
);
4819 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
4821 return float32_sqrt(a
, &env
->vfp
.fp_status
);
4824 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
4826 return float64_sqrt(a
, &env
->vfp
.fp_status
);
4829 /* XXX: check quiet/signaling case */
4830 #define DO_VFP_cmp(p, type) \
4831 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4834 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4835 case 0: flags = 0x6; break; \
4836 case -1: flags = 0x8; break; \
4837 case 1: flags = 0x2; break; \
4838 default: case 2: flags = 0x3; break; \
4840 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4841 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4843 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4846 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4847 case 0: flags = 0x6; break; \
4848 case -1: flags = 0x8; break; \
4849 case 1: flags = 0x2; break; \
4850 default: case 2: flags = 0x3; break; \
4852 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4853 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4855 DO_VFP_cmp(s
, float32
)
4856 DO_VFP_cmp(d
, float64
)
4859 /* Integer to float and float to integer conversions */
4861 #define CONV_ITOF(name, fsz, sign) \
4862 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4864 float_status *fpst = fpstp; \
4865 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4868 #define CONV_FTOI(name, fsz, sign, round) \
4869 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4871 float_status *fpst = fpstp; \
4872 if (float##fsz##_is_any_nan(x)) { \
4873 float_raise(float_flag_invalid, fpst); \
4876 return float##fsz##_to_##sign##int32##round(x, fpst); \
4879 #define FLOAT_CONVS(name, p, fsz, sign) \
4880 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4881 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4882 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4884 FLOAT_CONVS(si
, s
, 32, )
4885 FLOAT_CONVS(si
, d
, 64, )
4886 FLOAT_CONVS(ui
, s
, 32, u
)
4887 FLOAT_CONVS(ui
, d
, 64, u
)
4893 /* floating point conversion */
4894 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
4896 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
4897 /* ARM requires that S<->D conversion of any kind of NaN generates
4898 * a quiet NaN by forcing the most significant frac bit to 1.
4900 return float64_maybe_silence_nan(r
);
4903 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
4905 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
4906 /* ARM requires that S<->D conversion of any kind of NaN generates
4907 * a quiet NaN by forcing the most significant frac bit to 1.
4909 return float32_maybe_silence_nan(r
);
4912 /* VFP3 fixed point conversion. */
4913 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4914 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4917 float_status *fpst = fpstp; \
4919 tmp = itype##_to_##float##fsz(x, fpst); \
4920 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4923 /* Notice that we want only input-denormal exception flags from the
4924 * scalbn operation: the other possible flags (overflow+inexact if
4925 * we overflow to infinity, output-denormal) aren't correct for the
4926 * complete scale-and-convert operation.
4928 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4929 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4933 float_status *fpst = fpstp; \
4934 int old_exc_flags = get_float_exception_flags(fpst); \
4936 if (float##fsz##_is_any_nan(x)) { \
4937 float_raise(float_flag_invalid, fpst); \
4940 tmp = float##fsz##_scalbn(x, shift, fpst); \
4941 old_exc_flags |= get_float_exception_flags(fpst) \
4942 & float_flag_input_denormal; \
4943 set_float_exception_flags(old_exc_flags, fpst); \
4944 return float##fsz##_to_##itype##round(tmp, fpst); \
4947 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4948 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4949 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4950 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4952 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4953 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4954 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4956 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
4957 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
4958 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
4959 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
4960 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
4961 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
4962 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
4963 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
4964 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
4965 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
4966 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
4967 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
4969 #undef VFP_CONV_FIX_FLOAT
4970 #undef VFP_CONV_FLOAT_FIX_ROUND
4972 /* Set the current fp rounding mode and return the old one.
4973 * The argument is a softfloat float_round_ value.
4975 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4977 float_status
*fp_status
= &env
->vfp
.fp_status
;
4979 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4980 set_float_rounding_mode(rmode
, fp_status
);
4985 /* Set the current fp rounding mode in the standard fp status and return
4986 * the old one. This is for NEON instructions that need to change the
4987 * rounding mode but wish to use the standard FPSCR values for everything
4988 * else. Always set the rounding mode back to the correct value after
4990 * The argument is a softfloat float_round_ value.
4992 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4994 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
4996 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4997 set_float_rounding_mode(rmode
, fp_status
);
5002 /* Half precision conversions. */
5003 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
5005 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
5006 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
5008 return float32_maybe_silence_nan(r
);
5013 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
5015 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
5016 float16 r
= float32_to_float16(a
, ieee
, s
);
5018 r
= float16_maybe_silence_nan(r
);
5020 return float16_val(r
);
5023 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
5025 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
5028 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
5030 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
5033 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
5035 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
5038 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
5040 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
5043 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
5045 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
5046 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
5048 return float64_maybe_silence_nan(r
);
5053 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
5055 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
5056 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
5058 r
= float16_maybe_silence_nan(r
);
5060 return float16_val(r
);
5063 #define float32_two make_float32(0x40000000)
5064 #define float32_three make_float32(0x40400000)
5065 #define float32_one_point_five make_float32(0x3fc00000)
5067 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
5069 float_status
*s
= &env
->vfp
.standard_fp_status
;
5070 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
5071 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
5072 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
5073 float_raise(float_flag_input_denormal
, s
);
5077 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
5080 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
5082 float_status
*s
= &env
->vfp
.standard_fp_status
;
5084 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
5085 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
5086 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
5087 float_raise(float_flag_input_denormal
, s
);
5089 return float32_one_point_five
;
5091 product
= float32_mul(a
, b
, s
);
5092 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
5097 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5098 * int->float conversions at run-time. */
5099 #define float64_256 make_float64(0x4070000000000000LL)
5100 #define float64_512 make_float64(0x4080000000000000LL)
5101 #define float32_maxnorm make_float32(0x7f7fffff)
5102 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5104 /* Reciprocal functions
5106 * The algorithm that must be used to calculate the estimate
5107 * is specified by the ARM ARM, see FPRecipEstimate()
5110 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
5112 /* These calculations mustn't set any fp exception flags,
5113 * so we use a local copy of the fp_status.
5115 float_status dummy_status
= *real_fp_status
;
5116 float_status
*s
= &dummy_status
;
5117 /* q = (int)(a * 512.0) */
5118 float64 q
= float64_mul(float64_512
, a
, s
);
5119 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
5121 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5122 q
= int64_to_float64(q_int
, s
);
5123 q
= float64_add(q
, float64_half
, s
);
5124 q
= float64_div(q
, float64_512
, s
);
5125 q
= float64_div(float64_one
, q
, s
);
5127 /* s = (int)(256.0 * r + 0.5) */
5128 q
= float64_mul(q
, float64_256
, s
);
5129 q
= float64_add(q
, float64_half
, s
);
5130 q_int
= float64_to_int64_round_to_zero(q
, s
);
5132 /* return (double)s / 256.0 */
5133 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
5136 /* Common wrapper to call recip_estimate */
5137 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
5139 uint64_t val64
= float64_val(num
);
5140 uint64_t frac
= extract64(val64
, 0, 52);
5141 int64_t exp
= extract64(val64
, 52, 11);
5143 float64 scaled
, estimate
;
5145 /* Generate the scaled number for the estimate function */
5147 if (extract64(frac
, 51, 1) == 0) {
5149 frac
= extract64(frac
, 0, 50) << 2;
5151 frac
= extract64(frac
, 0, 51) << 1;
5155 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5156 scaled
= make_float64((0x3feULL
<< 52)
5157 | extract64(frac
, 44, 8) << 44);
5159 estimate
= recip_estimate(scaled
, fpst
);
5161 /* Build new result */
5162 val64
= float64_val(estimate
);
5163 sbit
= 0x8000000000000000ULL
& val64
;
5165 frac
= extract64(val64
, 0, 52);
5168 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
5169 } else if (exp
== -1) {
5170 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
5174 return make_float64(sbit
| (exp
<< 52) | frac
);
5177 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
5179 switch (fpst
->float_rounding_mode
) {
5180 case float_round_nearest_even
: /* Round to Nearest */
5182 case float_round_up
: /* Round to +Inf */
5184 case float_round_down
: /* Round to -Inf */
5186 case float_round_to_zero
: /* Round to Zero */
5190 g_assert_not_reached();
5193 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
5195 float_status
*fpst
= fpstp
;
5196 float32 f32
= float32_squash_input_denormal(input
, fpst
);
5197 uint32_t f32_val
= float32_val(f32
);
5198 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
5199 int32_t f32_exp
= extract32(f32_val
, 23, 8);
5200 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
5206 if (float32_is_any_nan(f32
)) {
5208 if (float32_is_signaling_nan(f32
)) {
5209 float_raise(float_flag_invalid
, fpst
);
5210 nan
= float32_maybe_silence_nan(f32
);
5212 if (fpst
->default_nan_mode
) {
5213 nan
= float32_default_nan
;
5216 } else if (float32_is_infinity(f32
)) {
5217 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
5218 } else if (float32_is_zero(f32
)) {
5219 float_raise(float_flag_divbyzero
, fpst
);
5220 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
5221 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
5222 /* Abs(value) < 2.0^-128 */
5223 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
5224 if (round_to_inf(fpst
, f32_sbit
)) {
5225 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
5227 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
5229 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
5230 float_raise(float_flag_underflow
, fpst
);
5231 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
5235 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
5236 r64
= call_recip_estimate(f64
, 253, fpst
);
5237 r64_val
= float64_val(r64
);
5238 r64_exp
= extract64(r64_val
, 52, 11);
5239 r64_frac
= extract64(r64_val
, 0, 52);
5241 /* result = sign : result_exp<7:0> : fraction<51:29>; */
5242 return make_float32(f32_sbit
|
5243 (r64_exp
& 0xff) << 23 |
5244 extract64(r64_frac
, 29, 24));
5247 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
5249 float_status
*fpst
= fpstp
;
5250 float64 f64
= float64_squash_input_denormal(input
, fpst
);
5251 uint64_t f64_val
= float64_val(f64
);
5252 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
5253 int64_t f64_exp
= extract64(f64_val
, 52, 11);
5259 /* Deal with any special cases */
5260 if (float64_is_any_nan(f64
)) {
5262 if (float64_is_signaling_nan(f64
)) {
5263 float_raise(float_flag_invalid
, fpst
);
5264 nan
= float64_maybe_silence_nan(f64
);
5266 if (fpst
->default_nan_mode
) {
5267 nan
= float64_default_nan
;
5270 } else if (float64_is_infinity(f64
)) {
5271 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
5272 } else if (float64_is_zero(f64
)) {
5273 float_raise(float_flag_divbyzero
, fpst
);
5274 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
5275 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
5276 /* Abs(value) < 2.0^-1024 */
5277 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
5278 if (round_to_inf(fpst
, f64_sbit
)) {
5279 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
5281 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
5283 } else if (f64_exp
>= 1023 && fpst
->flush_to_zero
) {
5284 float_raise(float_flag_underflow
, fpst
);
5285 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
5288 r64
= call_recip_estimate(f64
, 2045, fpst
);
5289 r64_val
= float64_val(r64
);
5290 r64_exp
= extract64(r64_val
, 52, 11);
5291 r64_frac
= extract64(r64_val
, 0, 52);
5293 /* result = sign : result_exp<10:0> : fraction<51:0> */
5294 return make_float64(f64_sbit
|
5295 ((r64_exp
& 0x7ff) << 52) |
5299 /* The algorithm that must be used to calculate the estimate
5300 * is specified by the ARM ARM.
5302 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
5304 /* These calculations mustn't set any fp exception flags,
5305 * so we use a local copy of the fp_status.
5307 float_status dummy_status
= *real_fp_status
;
5308 float_status
*s
= &dummy_status
;
5312 if (float64_lt(a
, float64_half
, s
)) {
5313 /* range 0.25 <= a < 0.5 */
5315 /* a in units of 1/512 rounded down */
5316 /* q0 = (int)(a * 512.0); */
5317 q
= float64_mul(float64_512
, a
, s
);
5318 q_int
= float64_to_int64_round_to_zero(q
, s
);
5320 /* reciprocal root r */
5321 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
5322 q
= int64_to_float64(q_int
, s
);
5323 q
= float64_add(q
, float64_half
, s
);
5324 q
= float64_div(q
, float64_512
, s
);
5325 q
= float64_sqrt(q
, s
);
5326 q
= float64_div(float64_one
, q
, s
);
5328 /* range 0.5 <= a < 1.0 */
5330 /* a in units of 1/256 rounded down */
5331 /* q1 = (int)(a * 256.0); */
5332 q
= float64_mul(float64_256
, a
, s
);
5333 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
5335 /* reciprocal root r */
5336 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5337 q
= int64_to_float64(q_int
, s
);
5338 q
= float64_add(q
, float64_half
, s
);
5339 q
= float64_div(q
, float64_256
, s
);
5340 q
= float64_sqrt(q
, s
);
5341 q
= float64_div(float64_one
, q
, s
);
5343 /* r in units of 1/256 rounded to nearest */
5344 /* s = (int)(256.0 * r + 0.5); */
5346 q
= float64_mul(q
, float64_256
,s
);
5347 q
= float64_add(q
, float64_half
, s
);
5348 q_int
= float64_to_int64_round_to_zero(q
, s
);
5350 /* return (double)s / 256.0;*/
5351 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
5354 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
5356 float_status
*s
= fpstp
;
5357 float32 f32
= float32_squash_input_denormal(input
, s
);
5358 uint32_t val
= float32_val(f32
);
5359 uint32_t f32_sbit
= 0x80000000 & val
;
5360 int32_t f32_exp
= extract32(val
, 23, 8);
5361 uint32_t f32_frac
= extract32(val
, 0, 23);
5367 if (float32_is_any_nan(f32
)) {
5369 if (float32_is_signaling_nan(f32
)) {
5370 float_raise(float_flag_invalid
, s
);
5371 nan
= float32_maybe_silence_nan(f32
);
5373 if (s
->default_nan_mode
) {
5374 nan
= float32_default_nan
;
5377 } else if (float32_is_zero(f32
)) {
5378 float_raise(float_flag_divbyzero
, s
);
5379 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
5380 } else if (float32_is_neg(f32
)) {
5381 float_raise(float_flag_invalid
, s
);
5382 return float32_default_nan
;
5383 } else if (float32_is_infinity(f32
)) {
5384 return float32_zero
;
5387 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5388 * preserving the parity of the exponent. */
5390 f64_frac
= ((uint64_t) f32_frac
) << 29;
5392 while (extract64(f64_frac
, 51, 1) == 0) {
5393 f64_frac
= f64_frac
<< 1;
5394 f32_exp
= f32_exp
-1;
5396 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
5399 if (extract64(f32_exp
, 0, 1) == 0) {
5400 f64
= make_float64(((uint64_t) f32_sbit
) << 32
5404 f64
= make_float64(((uint64_t) f32_sbit
) << 32
5409 result_exp
= (380 - f32_exp
) / 2;
5411 f64
= recip_sqrt_estimate(f64
, s
);
5413 val64
= float64_val(f64
);
5415 val
= ((result_exp
& 0xff) << 23)
5416 | ((val64
>> 29) & 0x7fffff);
5417 return make_float32(val
);
5420 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
5422 float_status
*s
= fpstp
;
5423 float64 f64
= float64_squash_input_denormal(input
, s
);
5424 uint64_t val
= float64_val(f64
);
5425 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
5426 int64_t f64_exp
= extract64(val
, 52, 11);
5427 uint64_t f64_frac
= extract64(val
, 0, 52);
5429 uint64_t result_frac
;
5431 if (float64_is_any_nan(f64
)) {
5433 if (float64_is_signaling_nan(f64
)) {
5434 float_raise(float_flag_invalid
, s
);
5435 nan
= float64_maybe_silence_nan(f64
);
5437 if (s
->default_nan_mode
) {
5438 nan
= float64_default_nan
;
5441 } else if (float64_is_zero(f64
)) {
5442 float_raise(float_flag_divbyzero
, s
);
5443 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
5444 } else if (float64_is_neg(f64
)) {
5445 float_raise(float_flag_invalid
, s
);
5446 return float64_default_nan
;
5447 } else if (float64_is_infinity(f64
)) {
5448 return float64_zero
;
5451 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5452 * preserving the parity of the exponent. */
5455 while (extract64(f64_frac
, 51, 1) == 0) {
5456 f64_frac
= f64_frac
<< 1;
5457 f64_exp
= f64_exp
- 1;
5459 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
5462 if (extract64(f64_exp
, 0, 1) == 0) {
5463 f64
= make_float64(f64_sbit
5467 f64
= make_float64(f64_sbit
5472 result_exp
= (3068 - f64_exp
) / 2;
5474 f64
= recip_sqrt_estimate(f64
, s
);
5476 result_frac
= extract64(float64_val(f64
), 0, 52);
5478 return make_float64(f64_sbit
|
5479 ((result_exp
& 0x7ff) << 52) |
5483 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
5485 float_status
*s
= fpstp
;
5488 if ((a
& 0x80000000) == 0) {
5492 f64
= make_float64((0x3feULL
<< 52)
5493 | ((int64_t)(a
& 0x7fffffff) << 21));
5495 f64
= recip_estimate(f64
, s
);
5497 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
5500 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
5502 float_status
*fpst
= fpstp
;
5505 if ((a
& 0xc0000000) == 0) {
5509 if (a
& 0x80000000) {
5510 f64
= make_float64((0x3feULL
<< 52)
5511 | ((uint64_t)(a
& 0x7fffffff) << 21));
5512 } else { /* bits 31-30 == '01' */
5513 f64
= make_float64((0x3fdULL
<< 52)
5514 | ((uint64_t)(a
& 0x3fffffff) << 22));
5517 f64
= recip_sqrt_estimate(f64
, fpst
);
5519 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
5522 /* VFPv4 fused multiply-accumulate */
5523 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
5525 float_status
*fpst
= fpstp
;
5526 return float32_muladd(a
, b
, c
, 0, fpst
);
5529 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
5531 float_status
*fpst
= fpstp
;
5532 return float64_muladd(a
, b
, c
, 0, fpst
);
5535 /* ARMv8 round to integral */
5536 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
5538 return float32_round_to_int(x
, fp_status
);
5541 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
5543 return float64_round_to_int(x
, fp_status
);
5546 float32
HELPER(rints
)(float32 x
, void *fp_status
)
5548 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
5551 ret
= float32_round_to_int(x
, fp_status
);
5553 /* Suppress any inexact exceptions the conversion produced */
5554 if (!(old_flags
& float_flag_inexact
)) {
5555 new_flags
= get_float_exception_flags(fp_status
);
5556 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
5562 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
5564 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
5567 ret
= float64_round_to_int(x
, fp_status
);
5569 new_flags
= get_float_exception_flags(fp_status
);
5571 /* Suppress any inexact exceptions the conversion produced */
5572 if (!(old_flags
& float_flag_inexact
)) {
5573 new_flags
= get_float_exception_flags(fp_status
);
5574 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
5580 /* Convert ARM rounding mode to softfloat */
5581 int arm_rmode_to_sf(int rmode
)
5584 case FPROUNDING_TIEAWAY
:
5585 rmode
= float_round_ties_away
;
5587 case FPROUNDING_ODD
:
5588 /* FIXME: add support for TIEAWAY and ODD */
5589 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
5591 case FPROUNDING_TIEEVEN
:
5593 rmode
= float_round_nearest_even
;
5595 case FPROUNDING_POSINF
:
5596 rmode
= float_round_up
;
5598 case FPROUNDING_NEGINF
:
5599 rmode
= float_round_down
;
5601 case FPROUNDING_ZERO
:
5602 rmode
= float_round_to_zero
;
5609 * The upper bytes of val (above the number specified by 'bytes') must have
5610 * been zeroed out by the caller.
5612 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
5618 /* zlib crc32 converts the accumulator and output to one's complement. */
5619 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
5622 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
5628 /* Linux crc32c converts the output to one's complement. */
5629 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;