4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "user-internals.h"
24 #include "cpu_loop-common.h"
25 #include "signal-common.h"
26 #include "semihosting/common-semi.h"
27 #include "target/arm/syndrome.h"
29 #define get_user_code_u32(x, gaddr, env) \
30 ({ abi_long __r = get_user_u32((x), (gaddr)); \
31 if (!__r && bswap_code(arm_sctlr_b(env))) { \
37 #define get_user_code_u16(x, gaddr, env) \
38 ({ abi_long __r = get_user_u16((x), (gaddr)); \
39 if (!__r && bswap_code(arm_sctlr_b(env))) { \
45 #define get_user_data_u32(x, gaddr, env) \
46 ({ abi_long __r = get_user_u32((x), (gaddr)); \
47 if (!__r && arm_cpu_bswap_data(env)) { \
53 #define get_user_data_u16(x, gaddr, env) \
54 ({ abi_long __r = get_user_u16((x), (gaddr)); \
55 if (!__r && arm_cpu_bswap_data(env)) { \
61 #define put_user_data_u32(x, gaddr, env) \
62 ({ typeof(x) __x = (x); \
63 if (arm_cpu_bswap_data(env)) { \
66 put_user_u32(__x, (gaddr)); \
69 #define put_user_data_u16(x, gaddr, env) \
70 ({ typeof(x) __x = (x); \
71 if (arm_cpu_bswap_data(env)) { \
74 put_user_u16(__x, (gaddr)); \
78 * Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
79 * Must be called with mmap_lock.
80 * We get the PC of the entry address - which is as good as anything,
81 * on a real kernel what you get depends on which mode it uses.
83 static void *atomic_mmu_lookup(CPUArchState
*env
, uint32_t addr
, int size
)
85 int need_flags
= PAGE_READ
| PAGE_WRITE_ORG
| PAGE_VALID
;
88 /* Enforce guest required alignment. */
89 if (unlikely(addr
& (size
- 1))) {
90 force_sig_fault(TARGET_SIGBUS
, TARGET_BUS_ADRALN
, addr
);
94 page_flags
= page_get_flags(addr
);
95 if (unlikely((page_flags
& need_flags
) != need_flags
)) {
96 force_sig_fault(TARGET_SIGSEGV
,
97 page_flags
& PAGE_VALID
?
98 TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
, addr
);
102 return g2h(env_cpu(env
), addr
);
106 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
110 * r2 = pointer to target value
113 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
114 * C set if *ptr was changed, clear if no exchange happened
116 static void arm_kernel_cmpxchg32_helper(CPUARMState
*env
)
118 uint32_t oldval
, newval
, val
, addr
, cpsr
, *host_addr
;
120 oldval
= env
->regs
[0];
121 newval
= env
->regs
[1];
125 host_addr
= atomic_mmu_lookup(env
, addr
, 4);
131 val
= qatomic_cmpxchg__nocheck(host_addr
, oldval
, newval
);
134 cpsr
= (val
== oldval
) * CPSR_C
;
135 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
136 env
->regs
[0] = cpsr
? 0 : -1;
140 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
142 * r0 = pointer to oldval
143 * r1 = pointer to newval
144 * r2 = pointer to target value
147 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
148 * C set if *ptr was changed, clear if no exchange happened
150 * Note segv's in kernel helpers are a bit tricky, we can set the
151 * data address sensibly but the PC address is just the entry point.
153 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
155 uint64_t oldval
, newval
, val
;
160 if (get_user_u64(oldval
, addr
)) {
165 if (get_user_u64(newval
, addr
)) {
171 host_addr
= atomic_mmu_lookup(env
, addr
, 8);
177 #ifdef CONFIG_ATOMIC64
178 val
= qatomic_cmpxchg__nocheck(host_addr
, oldval
, newval
);
179 cpsr
= (val
== oldval
) * CPSR_C
;
182 * This only works between threads, not between processes, but since
183 * the host has no 64-bit cmpxchg, it is the best that we can do.
197 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
198 env
->regs
[0] = cpsr
? 0 : -1;
202 force_sig_fault(TARGET_SIGSEGV
,
203 page_get_flags(addr
) & PAGE_VALID
?
204 TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
, addr
);
207 /* Handle a jump to the kernel code page. */
209 do_kernel_trap(CPUARMState
*env
)
213 switch (env
->regs
[15]) {
214 case 0xffff0fa0: /* __kernel_memory_barrier */
217 case 0xffff0fc0: /* __kernel_cmpxchg */
218 arm_kernel_cmpxchg32_helper(env
);
220 case 0xffff0fe0: /* __kernel_get_tls */
221 env
->regs
[0] = cpu_get_tls(env
);
223 case 0xffff0f60: /* __kernel_cmpxchg64 */
224 arm_kernel_cmpxchg64_helper(env
);
230 /* Jump back to the caller. */
231 addr
= env
->regs
[14];
236 env
->regs
[15] = addr
;
241 static bool insn_is_linux_bkpt(uint32_t opcode
, bool is_thumb
)
244 * Return true if this insn is one of the three magic UDF insns
245 * which the kernel treats as breakpoint insns.
248 return (opcode
& 0x0fffffff) == 0x07f001f0;
251 * Note that we get the two halves of the 32-bit T32 insn
252 * in the opposite order to the value the kernel uses in
253 * its undef_hook struct.
255 return ((opcode
& 0xffff) == 0xde01) || (opcode
== 0xa000f7f0);
259 static bool emulate_arm_fpa11(CPUARMState
*env
, uint32_t opcode
)
261 TaskState
*ts
= env_cpu(env
)->opaque
;
262 int rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
266 /* Illegal instruction */
279 /* Translate softfloat flags to FPSR flags */
280 if (rc
& float_flag_invalid
) {
283 if (rc
& float_flag_divbyzero
) {
286 if (rc
& float_flag_overflow
) {
289 if (rc
& float_flag_underflow
) {
292 if (rc
& float_flag_inexact
) {
296 /* Accumulate unenabled exceptions */
297 enabled
= ts
->fpa
.fpsr
>> 16;
298 ts
->fpa
.fpsr
|= raise
& ~enabled
;
300 if (raise
& enabled
) {
302 * The kernel's nwfpe emulator does not pass a real si_code.
303 * It merely uses send_sig(SIGFPE, current, 1), which results in
304 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under
305 * the "SEND_SIG_PRIV" case). That's what our force_sig() does.
307 force_sig(TARGET_SIGFPE
);
314 void cpu_loop(CPUARMState
*env
)
316 CPUState
*cs
= env_cpu(env
);
317 int trapnr
, si_signo
, si_code
;
318 unsigned int n
, insn
;
323 trapnr
= cpu_exec(cs
);
325 process_queued_cpu_work(cs
);
334 /* we handle the FPU emulation here, as Linux */
335 /* we get the opcode */
336 /* FIXME - what to do if get_user() fails? */
337 get_user_code_u32(opcode
, env
->regs
[15], env
);
340 * The Linux kernel treats some UDF patterns specially
341 * to use as breakpoints (instead of the architectural
342 * bkpt insn). These should trigger a SIGTRAP rather
345 if (insn_is_linux_bkpt(opcode
, env
->thumb
)) {
349 if (!env
->thumb
&& emulate_arm_fpa11(env
, opcode
)) {
353 force_sig_fault(TARGET_SIGILL
, TARGET_ILL_ILLOPN
,
362 /* Thumb is always EABI style with syscall number in r7 */
366 * Equivalent of kernel CONFIG_OABI_COMPAT: read the
367 * Arm SVC insn to extract the immediate, which is the
368 * syscall number in OABI.
370 /* FIXME - what to do if get_user() fails? */
371 get_user_code_u32(insn
, env
->regs
[15] - 4, env
);
374 /* zero immediate: EABI, syscall number in r7 */
378 * This XOR matches the kernel code: an immediate
379 * in the valid range (0x900000 .. 0x9fffff) is
380 * converted into the correct EABI-style syscall
381 * number; invalid immediates end up as values
382 * > 0xfffff and are handled below as out-of-range.
384 n
^= ARM_SYSCALL_BASE
;
389 if (n
> ARM_NR_BASE
) {
391 case ARM_NR_cacheflush
:
395 cpu_set_tls(env
, env
->regs
[0]);
398 case ARM_NR_breakpoint
:
399 env
->regs
[15] -= env
->thumb
? 2 : 4;
402 env
->regs
[0] = cpu_get_tls(env
);
407 * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
408 * 0x9f07ff in OABI numbering) are defined
409 * to return -ENOSYS rather than raising
410 * SIGILL. Note that we have already
411 * removed the 0x900000 prefix.
413 qemu_log_mask(LOG_UNIMP
,
414 "qemu: Unsupported ARM syscall: 0x%x\n",
416 env
->regs
[0] = -TARGET_ENOSYS
;
419 * Otherwise SIGILL. This includes any SWI with
420 * immediate not originally 0x9fxxxx, because
421 * of the earlier XOR.
422 * Like the real kernel, we report the addr of the
423 * SWI in the siginfo si_addr but leave the PC
424 * pointing at the insn after the SWI.
426 abi_ulong faultaddr
= env
->regs
[15];
427 faultaddr
-= env
->thumb
? 2 : 4;
428 force_sig_fault(TARGET_SIGILL
, TARGET_ILL_ILLTRP
,
434 ret
= do_syscall(env
,
443 if (ret
== -QEMU_ERESTARTSYS
) {
444 env
->regs
[15] -= env
->thumb
? 2 : 4;
445 } else if (ret
!= -QEMU_ESIGRETURN
) {
452 do_common_semihosting(cs
);
453 env
->regs
[15] += env
->thumb
? 2 : 4;
456 /* just indicate that signals should be handled asap */
458 case EXCP_PREFETCH_ABORT
:
459 case EXCP_DATA_ABORT
:
460 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */
461 switch (env
->exception
.fsr
& 0x1f) {
462 case 0x1: /* Alignment */
463 si_signo
= TARGET_SIGBUS
;
464 si_code
= TARGET_BUS_ADRALN
;
466 case 0x3: /* Access flag fault, level 1 */
467 case 0x6: /* Access flag fault, level 2 */
468 case 0x9: /* Domain fault, level 1 */
469 case 0xb: /* Domain fault, level 2 */
470 case 0xd: /* Permission fault, level 1 */
471 case 0xf: /* Permission fault, level 2 */
472 si_signo
= TARGET_SIGSEGV
;
473 si_code
= TARGET_SEGV_ACCERR
;
475 case 0x5: /* Translation fault, level 1 */
476 case 0x7: /* Translation fault, level 2 */
477 si_signo
= TARGET_SIGSEGV
;
478 si_code
= TARGET_SEGV_MAPERR
;
481 g_assert_not_reached();
483 force_sig_fault(si_signo
, si_code
, env
->exception
.vaddress
);
488 force_sig_fault(TARGET_SIGTRAP
, TARGET_TRAP_BRKPT
, env
->regs
[15]);
490 case EXCP_KERNEL_TRAP
:
491 if (do_kernel_trap(env
))
495 /* nothing to do here for user-mode, just resume guest code */
498 cpu_exec_step_atomic(cs
);
502 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
505 process_pending_signals(env
);
509 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
511 CPUState
*cpu
= env_cpu(env
);
512 TaskState
*ts
= cpu
->opaque
;
513 struct image_info
*info
= ts
->info
;
516 cpsr_write(env
, regs
->uregs
[16], CPSR_USER
| CPSR_EXEC
,
518 for(i
= 0; i
< 16; i
++) {
519 env
->regs
[i
] = regs
->uregs
[i
];
521 #if TARGET_BIG_ENDIAN
523 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
524 && (info
->elf_flags
& EF_ARM_BE8
)) {
525 env
->uncached_cpsr
|= CPSR_E
;
526 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
528 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
530 arm_rebuild_hflags(env
);
533 ts
->stack_base
= info
->start_stack
;
534 ts
->heap_base
= info
->brk
;
535 /* This will be filled in on the first SYS_HEAPINFO call. */