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xen/MSI: don't open-code pass-through of enable bit modifications
[qemu/ar7.git] / tci.c
bloba14717d0d57629e87790e6d6f5ebf0e1f4df2c9e
1 /*
2 * Tiny Code Interpreter for QEMU
3 *
4 * Copyright (c) 2009, 2011 Stefan Weil
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "config.h"
21
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
24 # define NDEBUG
25 #endif
26
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
29 #include "exec/cpu_ldst.h"
30 #include "tcg-op.h"
31
32 /* Marker for missing code. */
33 #define TODO() \
34 do { \
35 fprintf(stderr, "TODO %s:%u: %s()\n", \
36 __FILE__, __LINE__, __func__); \
37 tcg_abort(); \
38 } while (0)
39
40 #if MAX_OPC_PARAM_IARGS != 5
41 # error Fix needed, number of supported input arguments changed!
42 #endif
43 #if TCG_TARGET_REG_BITS == 32
44 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
45 tcg_target_ulong, tcg_target_ulong,
46 tcg_target_ulong, tcg_target_ulong,
47 tcg_target_ulong, tcg_target_ulong,
48 tcg_target_ulong, tcg_target_ulong);
49 #else
50 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
51 tcg_target_ulong, tcg_target_ulong,
52 tcg_target_ulong);
53 #endif
54
55 /* Targets which don't use GETPC also don't need tci_tb_ptr
56 which makes them a little faster. */
57 #if defined(GETPC)
58 uintptr_t tci_tb_ptr;
59 #endif
60
61 static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
62
63 static tcg_target_ulong tci_read_reg(TCGReg index)
64 {
65 assert(index < ARRAY_SIZE(tci_reg));
66 return tci_reg[index];
67 }
68
69 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
70 static int8_t tci_read_reg8s(TCGReg index)
71 {
72 return (int8_t)tci_read_reg(index);
73 }
74 #endif
75
76 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
77 static int16_t tci_read_reg16s(TCGReg index)
78 {
79 return (int16_t)tci_read_reg(index);
80 }
81 #endif
82
83 #if TCG_TARGET_REG_BITS == 64
84 static int32_t tci_read_reg32s(TCGReg index)
85 {
86 return (int32_t)tci_read_reg(index);
87 }
88 #endif
89
90 static uint8_t tci_read_reg8(TCGReg index)
91 {
92 return (uint8_t)tci_read_reg(index);
93 }
94
95 static uint16_t tci_read_reg16(TCGReg index)
96 {
97 return (uint16_t)tci_read_reg(index);
98 }
99
100 static uint32_t tci_read_reg32(TCGReg index)
101 {
102 return (uint32_t)tci_read_reg(index);
103 }
104
105 #if TCG_TARGET_REG_BITS == 64
106 static uint64_t tci_read_reg64(TCGReg index)
107 {
108 return tci_read_reg(index);
109 }
110 #endif
111
112 static void tci_write_reg(TCGReg index, tcg_target_ulong value)
113 {
114 assert(index < ARRAY_SIZE(tci_reg));
115 assert(index != TCG_AREG0);
116 assert(index != TCG_REG_CALL_STACK);
117 tci_reg[index] = value;
118 }
119
120 #if TCG_TARGET_REG_BITS == 64
121 static void tci_write_reg32s(TCGReg index, int32_t value)
122 {
123 tci_write_reg(index, value);
124 }
125 #endif
126
127 static void tci_write_reg8(TCGReg index, uint8_t value)
128 {
129 tci_write_reg(index, value);
130 }
131
132 static void tci_write_reg32(TCGReg index, uint32_t value)
133 {
134 tci_write_reg(index, value);
135 }
136
137 #if TCG_TARGET_REG_BITS == 32
138 static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
139 uint64_t value)
140 {
141 tci_write_reg(low_index, value);
142 tci_write_reg(high_index, value >> 32);
143 }
144 #elif TCG_TARGET_REG_BITS == 64
145 static void tci_write_reg64(TCGReg index, uint64_t value)
146 {
147 tci_write_reg(index, value);
148 }
149 #endif
150
151 #if TCG_TARGET_REG_BITS == 32
152 /* Create a 64 bit value from two 32 bit values. */
153 static uint64_t tci_uint64(uint32_t high, uint32_t low)
154 {
155 return ((uint64_t)high << 32) + low;
156 }
157 #endif
158
159 /* Read constant (native size) from bytecode. */
160 static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
161 {
162 tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
163 *tb_ptr += sizeof(value);
164 return value;
165 }
166
167 /* Read unsigned constant (32 bit) from bytecode. */
168 static uint32_t tci_read_i32(uint8_t **tb_ptr)
169 {
170 uint32_t value = *(uint32_t *)(*tb_ptr);
171 *tb_ptr += sizeof(value);
172 return value;
173 }
174
175 /* Read signed constant (32 bit) from bytecode. */
176 static int32_t tci_read_s32(uint8_t **tb_ptr)
177 {
178 int32_t value = *(int32_t *)(*tb_ptr);
179 *tb_ptr += sizeof(value);
180 return value;
181 }
182
183 #if TCG_TARGET_REG_BITS == 64
184 /* Read constant (64 bit) from bytecode. */
185 static uint64_t tci_read_i64(uint8_t **tb_ptr)
186 {
187 uint64_t value = *(uint64_t *)(*tb_ptr);
188 *tb_ptr += sizeof(value);
189 return value;
190 }
191 #endif
192
193 /* Read indexed register (native size) from bytecode. */
194 static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
195 {
196 tcg_target_ulong value = tci_read_reg(**tb_ptr);
197 *tb_ptr += 1;
198 return value;
199 }
200
201 /* Read indexed register (8 bit) from bytecode. */
202 static uint8_t tci_read_r8(uint8_t **tb_ptr)
203 {
204 uint8_t value = tci_read_reg8(**tb_ptr);
205 *tb_ptr += 1;
206 return value;
207 }
208
209 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
210 /* Read indexed register (8 bit signed) from bytecode. */
211 static int8_t tci_read_r8s(uint8_t **tb_ptr)
212 {
213 int8_t value = tci_read_reg8s(**tb_ptr);
214 *tb_ptr += 1;
215 return value;
216 }
217 #endif
218
219 /* Read indexed register (16 bit) from bytecode. */
220 static uint16_t tci_read_r16(uint8_t **tb_ptr)
221 {
222 uint16_t value = tci_read_reg16(**tb_ptr);
223 *tb_ptr += 1;
224 return value;
225 }
226
227 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
228 /* Read indexed register (16 bit signed) from bytecode. */
229 static int16_t tci_read_r16s(uint8_t **tb_ptr)
230 {
231 int16_t value = tci_read_reg16s(**tb_ptr);
232 *tb_ptr += 1;
233 return value;
234 }
235 #endif
236
237 /* Read indexed register (32 bit) from bytecode. */
238 static uint32_t tci_read_r32(uint8_t **tb_ptr)
239 {
240 uint32_t value = tci_read_reg32(**tb_ptr);
241 *tb_ptr += 1;
242 return value;
243 }
244
245 #if TCG_TARGET_REG_BITS == 32
246 /* Read two indexed registers (2 * 32 bit) from bytecode. */
247 static uint64_t tci_read_r64(uint8_t **tb_ptr)
248 {
249 uint32_t low = tci_read_r32(tb_ptr);
250 return tci_uint64(tci_read_r32(tb_ptr), low);
251 }
252 #elif TCG_TARGET_REG_BITS == 64
253 /* Read indexed register (32 bit signed) from bytecode. */
254 static int32_t tci_read_r32s(uint8_t **tb_ptr)
255 {
256 int32_t value = tci_read_reg32s(**tb_ptr);
257 *tb_ptr += 1;
258 return value;
259 }
260
261 /* Read indexed register (64 bit) from bytecode. */
262 static uint64_t tci_read_r64(uint8_t **tb_ptr)
263 {
264 uint64_t value = tci_read_reg64(**tb_ptr);
265 *tb_ptr += 1;
266 return value;
267 }
268 #endif
269
270 /* Read indexed register(s) with target address from bytecode. */
271 static target_ulong tci_read_ulong(uint8_t **tb_ptr)
272 {
273 target_ulong taddr = tci_read_r(tb_ptr);
274 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
275 taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
276 #endif
277 return taddr;
278 }
279
280 /* Read indexed register or constant (native size) from bytecode. */
281 static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
282 {
283 tcg_target_ulong value;
284 TCGReg r = **tb_ptr;
285 *tb_ptr += 1;
286 if (r == TCG_CONST) {
287 value = tci_read_i(tb_ptr);
288 } else {
289 value = tci_read_reg(r);
290 }
291 return value;
292 }
293
294 /* Read indexed register or constant (32 bit) from bytecode. */
295 static uint32_t tci_read_ri32(uint8_t **tb_ptr)
296 {
297 uint32_t value;
298 TCGReg r = **tb_ptr;
299 *tb_ptr += 1;
300 if (r == TCG_CONST) {
301 value = tci_read_i32(tb_ptr);
302 } else {
303 value = tci_read_reg32(r);
304 }
305 return value;
306 }
307
308 #if TCG_TARGET_REG_BITS == 32
309 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
310 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
311 {
312 uint32_t low = tci_read_ri32(tb_ptr);
313 return tci_uint64(tci_read_ri32(tb_ptr), low);
314 }
315 #elif TCG_TARGET_REG_BITS == 64
316 /* Read indexed register or constant (64 bit) from bytecode. */
317 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
318 {
319 uint64_t value;
320 TCGReg r = **tb_ptr;
321 *tb_ptr += 1;
322 if (r == TCG_CONST) {
323 value = tci_read_i64(tb_ptr);
324 } else {
325 value = tci_read_reg64(r);
326 }
327 return value;
328 }
329 #endif
330
331 static tcg_target_ulong tci_read_label(uint8_t **tb_ptr)
332 {
333 tcg_target_ulong label = tci_read_i(tb_ptr);
334 assert(label != 0);
335 return label;
336 }
337
338 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
339 {
340 bool result = false;
341 int32_t i0 = u0;
342 int32_t i1 = u1;
343 switch (condition) {
344 case TCG_COND_EQ:
345 result = (u0 == u1);
346 break;
347 case TCG_COND_NE:
348 result = (u0 != u1);
349 break;
350 case TCG_COND_LT:
351 result = (i0 < i1);
352 break;
353 case TCG_COND_GE:
354 result = (i0 >= i1);
355 break;
356 case TCG_COND_LE:
357 result = (i0 <= i1);
358 break;
359 case TCG_COND_GT:
360 result = (i0 > i1);
361 break;
362 case TCG_COND_LTU:
363 result = (u0 < u1);
364 break;
365 case TCG_COND_GEU:
366 result = (u0 >= u1);
367 break;
368 case TCG_COND_LEU:
369 result = (u0 <= u1);
370 break;
371 case TCG_COND_GTU:
372 result = (u0 > u1);
373 break;
374 default:
375 TODO();
376 }
377 return result;
378 }
379
380 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
381 {
382 bool result = false;
383 int64_t i0 = u0;
384 int64_t i1 = u1;
385 switch (condition) {
386 case TCG_COND_EQ:
387 result = (u0 == u1);
388 break;
389 case TCG_COND_NE:
390 result = (u0 != u1);
391 break;
392 case TCG_COND_LT:
393 result = (i0 < i1);
394 break;
395 case TCG_COND_GE:
396 result = (i0 >= i1);
397 break;
398 case TCG_COND_LE:
399 result = (i0 <= i1);
400 break;
401 case TCG_COND_GT:
402 result = (i0 > i1);
403 break;
404 case TCG_COND_LTU:
405 result = (u0 < u1);
406 break;
407 case TCG_COND_GEU:
408 result = (u0 >= u1);
409 break;
410 case TCG_COND_LEU:
411 result = (u0 <= u1);
412 break;
413 case TCG_COND_GTU:
414 result = (u0 > u1);
415 break;
416 default:
417 TODO();
418 }
419 return result;
420 }
421
422 #ifdef CONFIG_SOFTMMU
423 # define qemu_ld_ub \
424 helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
425 # define qemu_ld_leuw \
426 helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
427 # define qemu_ld_leul \
428 helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
429 # define qemu_ld_leq \
430 helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
431 # define qemu_ld_beuw \
432 helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
433 # define qemu_ld_beul \
434 helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
435 # define qemu_ld_beq \
436 helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
437 # define qemu_st_b(X) \
438 helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
439 # define qemu_st_lew(X) \
440 helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
441 # define qemu_st_lel(X) \
442 helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
443 # define qemu_st_leq(X) \
444 helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
445 # define qemu_st_bew(X) \
446 helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
447 # define qemu_st_bel(X) \
448 helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
449 # define qemu_st_beq(X) \
450 helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
451 #else
452 # define qemu_ld_ub ldub_p(g2h(taddr))
453 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
454 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
455 # define qemu_ld_leq ldq_le_p(g2h(taddr))
456 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
457 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
458 # define qemu_ld_beq ldq_be_p(g2h(taddr))
459 # define qemu_st_b(X) stb_p(g2h(taddr), X)
460 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
461 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
462 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
463 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
464 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
465 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
466 #endif
467
468 /* Interpret pseudo code in tb. */
469 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
470 {
471 long tcg_temps[CPU_TEMP_BUF_NLONGS];
472 uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
473 uintptr_t next_tb = 0;
474
475 tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
476 tci_reg[TCG_REG_CALL_STACK] = sp_value;
477 assert(tb_ptr);
478
479 for (;;) {
480 TCGOpcode opc = tb_ptr[0];
481 #if !defined(NDEBUG)
482 uint8_t op_size = tb_ptr[1];
483 uint8_t *old_code_ptr = tb_ptr;
484 #endif
485 tcg_target_ulong t0;
486 tcg_target_ulong t1;
487 tcg_target_ulong t2;
488 tcg_target_ulong label;
489 TCGCond condition;
490 target_ulong taddr;
491 uint8_t tmp8;
492 uint16_t tmp16;
493 uint32_t tmp32;
494 uint64_t tmp64;
495 #if TCG_TARGET_REG_BITS == 32
496 uint64_t v64;
497 #endif
498 TCGMemOpIdx oi;
499
500 #if defined(GETPC)
501 tci_tb_ptr = (uintptr_t)tb_ptr;
502 #endif
503
504 /* Skip opcode and size entry. */
505 tb_ptr += 2;
506
507 switch (opc) {
508 case INDEX_op_call:
509 t0 = tci_read_ri(&tb_ptr);
510 #if TCG_TARGET_REG_BITS == 32
511 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
512 tci_read_reg(TCG_REG_R1),
513 tci_read_reg(TCG_REG_R2),
514 tci_read_reg(TCG_REG_R3),
515 tci_read_reg(TCG_REG_R5),
516 tci_read_reg(TCG_REG_R6),
517 tci_read_reg(TCG_REG_R7),
518 tci_read_reg(TCG_REG_R8),
519 tci_read_reg(TCG_REG_R9),
520 tci_read_reg(TCG_REG_R10));
521 tci_write_reg(TCG_REG_R0, tmp64);
522 tci_write_reg(TCG_REG_R1, tmp64 >> 32);
523 #else
524 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
525 tci_read_reg(TCG_REG_R1),
526 tci_read_reg(TCG_REG_R2),
527 tci_read_reg(TCG_REG_R3),
528 tci_read_reg(TCG_REG_R5));
529 tci_write_reg(TCG_REG_R0, tmp64);
530 #endif
531 break;
532 case INDEX_op_br:
533 label = tci_read_label(&tb_ptr);
534 assert(tb_ptr == old_code_ptr + op_size);
535 tb_ptr = (uint8_t *)label;
536 continue;
537 case INDEX_op_setcond_i32:
538 t0 = *tb_ptr++;
539 t1 = tci_read_r32(&tb_ptr);
540 t2 = tci_read_ri32(&tb_ptr);
541 condition = *tb_ptr++;
542 tci_write_reg32(t0, tci_compare32(t1, t2, condition));
543 break;
544 #if TCG_TARGET_REG_BITS == 32
545 case INDEX_op_setcond2_i32:
546 t0 = *tb_ptr++;
547 tmp64 = tci_read_r64(&tb_ptr);
548 v64 = tci_read_ri64(&tb_ptr);
549 condition = *tb_ptr++;
550 tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
551 break;
552 #elif TCG_TARGET_REG_BITS == 64
553 case INDEX_op_setcond_i64:
554 t0 = *tb_ptr++;
555 t1 = tci_read_r64(&tb_ptr);
556 t2 = tci_read_ri64(&tb_ptr);
557 condition = *tb_ptr++;
558 tci_write_reg64(t0, tci_compare64(t1, t2, condition));
559 break;
560 #endif
561 case INDEX_op_mov_i32:
562 t0 = *tb_ptr++;
563 t1 = tci_read_r32(&tb_ptr);
564 tci_write_reg32(t0, t1);
565 break;
566 case INDEX_op_movi_i32:
567 t0 = *tb_ptr++;
568 t1 = tci_read_i32(&tb_ptr);
569 tci_write_reg32(t0, t1);
570 break;
571
572 /* Load/store operations (32 bit). */
573
574 case INDEX_op_ld8u_i32:
575 t0 = *tb_ptr++;
576 t1 = tci_read_r(&tb_ptr);
577 t2 = tci_read_s32(&tb_ptr);
578 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
579 break;
580 case INDEX_op_ld8s_i32:
581 case INDEX_op_ld16u_i32:
582 TODO();
583 break;
584 case INDEX_op_ld16s_i32:
585 TODO();
586 break;
587 case INDEX_op_ld_i32:
588 t0 = *tb_ptr++;
589 t1 = tci_read_r(&tb_ptr);
590 t2 = tci_read_s32(&tb_ptr);
591 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
592 break;
593 case INDEX_op_st8_i32:
594 t0 = tci_read_r8(&tb_ptr);
595 t1 = tci_read_r(&tb_ptr);
596 t2 = tci_read_s32(&tb_ptr);
597 *(uint8_t *)(t1 + t2) = t0;
598 break;
599 case INDEX_op_st16_i32:
600 t0 = tci_read_r16(&tb_ptr);
601 t1 = tci_read_r(&tb_ptr);
602 t2 = tci_read_s32(&tb_ptr);
603 *(uint16_t *)(t1 + t2) = t0;
604 break;
605 case INDEX_op_st_i32:
606 t0 = tci_read_r32(&tb_ptr);
607 t1 = tci_read_r(&tb_ptr);
608 t2 = tci_read_s32(&tb_ptr);
609 assert(t1 != sp_value || (int32_t)t2 < 0);
610 *(uint32_t *)(t1 + t2) = t0;
611 break;
612
613 /* Arithmetic operations (32 bit). */
614
615 case INDEX_op_add_i32:
616 t0 = *tb_ptr++;
617 t1 = tci_read_ri32(&tb_ptr);
618 t2 = tci_read_ri32(&tb_ptr);
619 tci_write_reg32(t0, t1 + t2);
620 break;
621 case INDEX_op_sub_i32:
622 t0 = *tb_ptr++;
623 t1 = tci_read_ri32(&tb_ptr);
624 t2 = tci_read_ri32(&tb_ptr);
625 tci_write_reg32(t0, t1 - t2);
626 break;
627 case INDEX_op_mul_i32:
628 t0 = *tb_ptr++;
629 t1 = tci_read_ri32(&tb_ptr);
630 t2 = tci_read_ri32(&tb_ptr);
631 tci_write_reg32(t0, t1 * t2);
632 break;
633 #if TCG_TARGET_HAS_div_i32
634 case INDEX_op_div_i32:
635 t0 = *tb_ptr++;
636 t1 = tci_read_ri32(&tb_ptr);
637 t2 = tci_read_ri32(&tb_ptr);
638 tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
639 break;
640 case INDEX_op_divu_i32:
641 t0 = *tb_ptr++;
642 t1 = tci_read_ri32(&tb_ptr);
643 t2 = tci_read_ri32(&tb_ptr);
644 tci_write_reg32(t0, t1 / t2);
645 break;
646 case INDEX_op_rem_i32:
647 t0 = *tb_ptr++;
648 t1 = tci_read_ri32(&tb_ptr);
649 t2 = tci_read_ri32(&tb_ptr);
650 tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
651 break;
652 case INDEX_op_remu_i32:
653 t0 = *tb_ptr++;
654 t1 = tci_read_ri32(&tb_ptr);
655 t2 = tci_read_ri32(&tb_ptr);
656 tci_write_reg32(t0, t1 % t2);
657 break;
658 #elif TCG_TARGET_HAS_div2_i32
659 case INDEX_op_div2_i32:
660 case INDEX_op_divu2_i32:
661 TODO();
662 break;
663 #endif
664 case INDEX_op_and_i32:
665 t0 = *tb_ptr++;
666 t1 = tci_read_ri32(&tb_ptr);
667 t2 = tci_read_ri32(&tb_ptr);
668 tci_write_reg32(t0, t1 & t2);
669 break;
670 case INDEX_op_or_i32:
671 t0 = *tb_ptr++;
672 t1 = tci_read_ri32(&tb_ptr);
673 t2 = tci_read_ri32(&tb_ptr);
674 tci_write_reg32(t0, t1 | t2);
675 break;
676 case INDEX_op_xor_i32:
677 t0 = *tb_ptr++;
678 t1 = tci_read_ri32(&tb_ptr);
679 t2 = tci_read_ri32(&tb_ptr);
680 tci_write_reg32(t0, t1 ^ t2);
681 break;
682
683 /* Shift/rotate operations (32 bit). */
684
685 case INDEX_op_shl_i32:
686 t0 = *tb_ptr++;
687 t1 = tci_read_ri32(&tb_ptr);
688 t2 = tci_read_ri32(&tb_ptr);
689 tci_write_reg32(t0, t1 << (t2 & 31));
690 break;
691 case INDEX_op_shr_i32:
692 t0 = *tb_ptr++;
693 t1 = tci_read_ri32(&tb_ptr);
694 t2 = tci_read_ri32(&tb_ptr);
695 tci_write_reg32(t0, t1 >> (t2 & 31));
696 break;
697 case INDEX_op_sar_i32:
698 t0 = *tb_ptr++;
699 t1 = tci_read_ri32(&tb_ptr);
700 t2 = tci_read_ri32(&tb_ptr);
701 tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
702 break;
703 #if TCG_TARGET_HAS_rot_i32
704 case INDEX_op_rotl_i32:
705 t0 = *tb_ptr++;
706 t1 = tci_read_ri32(&tb_ptr);
707 t2 = tci_read_ri32(&tb_ptr);
708 tci_write_reg32(t0, rol32(t1, t2 & 31));
709 break;
710 case INDEX_op_rotr_i32:
711 t0 = *tb_ptr++;
712 t1 = tci_read_ri32(&tb_ptr);
713 t2 = tci_read_ri32(&tb_ptr);
714 tci_write_reg32(t0, ror32(t1, t2 & 31));
715 break;
716 #endif
717 #if TCG_TARGET_HAS_deposit_i32
718 case INDEX_op_deposit_i32:
719 t0 = *tb_ptr++;
720 t1 = tci_read_r32(&tb_ptr);
721 t2 = tci_read_r32(&tb_ptr);
722 tmp16 = *tb_ptr++;
723 tmp8 = *tb_ptr++;
724 tmp32 = (((1 << tmp8) - 1) << tmp16);
725 tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
726 break;
727 #endif
728 case INDEX_op_brcond_i32:
729 t0 = tci_read_r32(&tb_ptr);
730 t1 = tci_read_ri32(&tb_ptr);
731 condition = *tb_ptr++;
732 label = tci_read_label(&tb_ptr);
733 if (tci_compare32(t0, t1, condition)) {
734 assert(tb_ptr == old_code_ptr + op_size);
735 tb_ptr = (uint8_t *)label;
736 continue;
737 }
738 break;
739 #if TCG_TARGET_REG_BITS == 32
740 case INDEX_op_add2_i32:
741 t0 = *tb_ptr++;
742 t1 = *tb_ptr++;
743 tmp64 = tci_read_r64(&tb_ptr);
744 tmp64 += tci_read_r64(&tb_ptr);
745 tci_write_reg64(t1, t0, tmp64);
746 break;
747 case INDEX_op_sub2_i32:
748 t0 = *tb_ptr++;
749 t1 = *tb_ptr++;
750 tmp64 = tci_read_r64(&tb_ptr);
751 tmp64 -= tci_read_r64(&tb_ptr);
752 tci_write_reg64(t1, t0, tmp64);
753 break;
754 case INDEX_op_brcond2_i32:
755 tmp64 = tci_read_r64(&tb_ptr);
756 v64 = tci_read_ri64(&tb_ptr);
757 condition = *tb_ptr++;
758 label = tci_read_label(&tb_ptr);
759 if (tci_compare64(tmp64, v64, condition)) {
760 assert(tb_ptr == old_code_ptr + op_size);
761 tb_ptr = (uint8_t *)label;
762 continue;
763 }
764 break;
765 case INDEX_op_mulu2_i32:
766 t0 = *tb_ptr++;
767 t1 = *tb_ptr++;
768 t2 = tci_read_r32(&tb_ptr);
769 tmp64 = tci_read_r32(&tb_ptr);
770 tci_write_reg64(t1, t0, t2 * tmp64);
771 break;
772 #endif /* TCG_TARGET_REG_BITS == 32 */
773 #if TCG_TARGET_HAS_ext8s_i32
774 case INDEX_op_ext8s_i32:
775 t0 = *tb_ptr++;
776 t1 = tci_read_r8s(&tb_ptr);
777 tci_write_reg32(t0, t1);
778 break;
779 #endif
780 #if TCG_TARGET_HAS_ext16s_i32
781 case INDEX_op_ext16s_i32:
782 t0 = *tb_ptr++;
783 t1 = tci_read_r16s(&tb_ptr);
784 tci_write_reg32(t0, t1);
785 break;
786 #endif
787 #if TCG_TARGET_HAS_ext8u_i32
788 case INDEX_op_ext8u_i32:
789 t0 = *tb_ptr++;
790 t1 = tci_read_r8(&tb_ptr);
791 tci_write_reg32(t0, t1);
792 break;
793 #endif
794 #if TCG_TARGET_HAS_ext16u_i32
795 case INDEX_op_ext16u_i32:
796 t0 = *tb_ptr++;
797 t1 = tci_read_r16(&tb_ptr);
798 tci_write_reg32(t0, t1);
799 break;
800 #endif
801 #if TCG_TARGET_HAS_bswap16_i32
802 case INDEX_op_bswap16_i32:
803 t0 = *tb_ptr++;
804 t1 = tci_read_r16(&tb_ptr);
805 tci_write_reg32(t0, bswap16(t1));
806 break;
807 #endif
808 #if TCG_TARGET_HAS_bswap32_i32
809 case INDEX_op_bswap32_i32:
810 t0 = *tb_ptr++;
811 t1 = tci_read_r32(&tb_ptr);
812 tci_write_reg32(t0, bswap32(t1));
813 break;
814 #endif
815 #if TCG_TARGET_HAS_not_i32
816 case INDEX_op_not_i32:
817 t0 = *tb_ptr++;
818 t1 = tci_read_r32(&tb_ptr);
819 tci_write_reg32(t0, ~t1);
820 break;
821 #endif
822 #if TCG_TARGET_HAS_neg_i32
823 case INDEX_op_neg_i32:
824 t0 = *tb_ptr++;
825 t1 = tci_read_r32(&tb_ptr);
826 tci_write_reg32(t0, -t1);
827 break;
828 #endif
829 #if TCG_TARGET_REG_BITS == 64
830 case INDEX_op_mov_i64:
831 t0 = *tb_ptr++;
832 t1 = tci_read_r64(&tb_ptr);
833 tci_write_reg64(t0, t1);
834 break;
835 case INDEX_op_movi_i64:
836 t0 = *tb_ptr++;
837 t1 = tci_read_i64(&tb_ptr);
838 tci_write_reg64(t0, t1);
839 break;
840
841 /* Load/store operations (64 bit). */
842
843 case INDEX_op_ld8u_i64:
844 t0 = *tb_ptr++;
845 t1 = tci_read_r(&tb_ptr);
846 t2 = tci_read_s32(&tb_ptr);
847 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
848 break;
849 case INDEX_op_ld8s_i64:
850 case INDEX_op_ld16u_i64:
851 case INDEX_op_ld16s_i64:
852 TODO();
853 break;
854 case INDEX_op_ld32u_i64:
855 t0 = *tb_ptr++;
856 t1 = tci_read_r(&tb_ptr);
857 t2 = tci_read_s32(&tb_ptr);
858 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
859 break;
860 case INDEX_op_ld32s_i64:
861 t0 = *tb_ptr++;
862 t1 = tci_read_r(&tb_ptr);
863 t2 = tci_read_s32(&tb_ptr);
864 tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
865 break;
866 case INDEX_op_ld_i64:
867 t0 = *tb_ptr++;
868 t1 = tci_read_r(&tb_ptr);
869 t2 = tci_read_s32(&tb_ptr);
870 tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
871 break;
872 case INDEX_op_st8_i64:
873 t0 = tci_read_r8(&tb_ptr);
874 t1 = tci_read_r(&tb_ptr);
875 t2 = tci_read_s32(&tb_ptr);
876 *(uint8_t *)(t1 + t2) = t0;
877 break;
878 case INDEX_op_st16_i64:
879 t0 = tci_read_r16(&tb_ptr);
880 t1 = tci_read_r(&tb_ptr);
881 t2 = tci_read_s32(&tb_ptr);
882 *(uint16_t *)(t1 + t2) = t0;
883 break;
884 case INDEX_op_st32_i64:
885 t0 = tci_read_r32(&tb_ptr);
886 t1 = tci_read_r(&tb_ptr);
887 t2 = tci_read_s32(&tb_ptr);
888 *(uint32_t *)(t1 + t2) = t0;
889 break;
890 case INDEX_op_st_i64:
891 t0 = tci_read_r64(&tb_ptr);
892 t1 = tci_read_r(&tb_ptr);
893 t2 = tci_read_s32(&tb_ptr);
894 assert(t1 != sp_value || (int32_t)t2 < 0);
895 *(uint64_t *)(t1 + t2) = t0;
896 break;
897
898 /* Arithmetic operations (64 bit). */
899
900 case INDEX_op_add_i64:
901 t0 = *tb_ptr++;
902 t1 = tci_read_ri64(&tb_ptr);
903 t2 = tci_read_ri64(&tb_ptr);
904 tci_write_reg64(t0, t1 + t2);
905 break;
906 case INDEX_op_sub_i64:
907 t0 = *tb_ptr++;
908 t1 = tci_read_ri64(&tb_ptr);
909 t2 = tci_read_ri64(&tb_ptr);
910 tci_write_reg64(t0, t1 - t2);
911 break;
912 case INDEX_op_mul_i64:
913 t0 = *tb_ptr++;
914 t1 = tci_read_ri64(&tb_ptr);
915 t2 = tci_read_ri64(&tb_ptr);
916 tci_write_reg64(t0, t1 * t2);
917 break;
918 #if TCG_TARGET_HAS_div_i64
919 case INDEX_op_div_i64:
920 case INDEX_op_divu_i64:
921 case INDEX_op_rem_i64:
922 case INDEX_op_remu_i64:
923 TODO();
924 break;
925 #elif TCG_TARGET_HAS_div2_i64
926 case INDEX_op_div2_i64:
927 case INDEX_op_divu2_i64:
928 TODO();
929 break;
930 #endif
931 case INDEX_op_and_i64:
932 t0 = *tb_ptr++;
933 t1 = tci_read_ri64(&tb_ptr);
934 t2 = tci_read_ri64(&tb_ptr);
935 tci_write_reg64(t0, t1 & t2);
936 break;
937 case INDEX_op_or_i64:
938 t0 = *tb_ptr++;
939 t1 = tci_read_ri64(&tb_ptr);
940 t2 = tci_read_ri64(&tb_ptr);
941 tci_write_reg64(t0, t1 | t2);
942 break;
943 case INDEX_op_xor_i64:
944 t0 = *tb_ptr++;
945 t1 = tci_read_ri64(&tb_ptr);
946 t2 = tci_read_ri64(&tb_ptr);
947 tci_write_reg64(t0, t1 ^ t2);
948 break;
949
950 /* Shift/rotate operations (64 bit). */
951
952 case INDEX_op_shl_i64:
953 t0 = *tb_ptr++;
954 t1 = tci_read_ri64(&tb_ptr);
955 t2 = tci_read_ri64(&tb_ptr);
956 tci_write_reg64(t0, t1 << (t2 & 63));
957 break;
958 case INDEX_op_shr_i64:
959 t0 = *tb_ptr++;
960 t1 = tci_read_ri64(&tb_ptr);
961 t2 = tci_read_ri64(&tb_ptr);
962 tci_write_reg64(t0, t1 >> (t2 & 63));
963 break;
964 case INDEX_op_sar_i64:
965 t0 = *tb_ptr++;
966 t1 = tci_read_ri64(&tb_ptr);
967 t2 = tci_read_ri64(&tb_ptr);
968 tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
969 break;
970 #if TCG_TARGET_HAS_rot_i64
971 case INDEX_op_rotl_i64:
972 t0 = *tb_ptr++;
973 t1 = tci_read_ri64(&tb_ptr);
974 t2 = tci_read_ri64(&tb_ptr);
975 tci_write_reg64(t0, rol64(t1, t2 & 63));
976 break;
977 case INDEX_op_rotr_i64:
978 t0 = *tb_ptr++;
979 t1 = tci_read_ri64(&tb_ptr);
980 t2 = tci_read_ri64(&tb_ptr);
981 tci_write_reg64(t0, ror64(t1, t2 & 63));
982 break;
983 #endif
984 #if TCG_TARGET_HAS_deposit_i64
985 case INDEX_op_deposit_i64:
986 t0 = *tb_ptr++;
987 t1 = tci_read_r64(&tb_ptr);
988 t2 = tci_read_r64(&tb_ptr);
989 tmp16 = *tb_ptr++;
990 tmp8 = *tb_ptr++;
991 tmp64 = (((1ULL << tmp8) - 1) << tmp16);
992 tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
993 break;
994 #endif
995 case INDEX_op_brcond_i64:
996 t0 = tci_read_r64(&tb_ptr);
997 t1 = tci_read_ri64(&tb_ptr);
998 condition = *tb_ptr++;
999 label = tci_read_label(&tb_ptr);
1000 if (tci_compare64(t0, t1, condition)) {
1001 assert(tb_ptr == old_code_ptr + op_size);
1002 tb_ptr = (uint8_t *)label;
1003 continue;
1004 }
1005 break;
1006 #if TCG_TARGET_HAS_ext8u_i64
1007 case INDEX_op_ext8u_i64:
1008 t0 = *tb_ptr++;
1009 t1 = tci_read_r8(&tb_ptr);
1010 tci_write_reg64(t0, t1);
1011 break;
1012 #endif
1013 #if TCG_TARGET_HAS_ext8s_i64
1014 case INDEX_op_ext8s_i64:
1015 t0 = *tb_ptr++;
1016 t1 = tci_read_r8s(&tb_ptr);
1017 tci_write_reg64(t0, t1);
1018 break;
1019 #endif
1020 #if TCG_TARGET_HAS_ext16s_i64
1021 case INDEX_op_ext16s_i64:
1022 t0 = *tb_ptr++;
1023 t1 = tci_read_r16s(&tb_ptr);
1024 tci_write_reg64(t0, t1);
1025 break;
1026 #endif
1027 #if TCG_TARGET_HAS_ext16u_i64
1028 case INDEX_op_ext16u_i64:
1029 t0 = *tb_ptr++;
1030 t1 = tci_read_r16(&tb_ptr);
1031 tci_write_reg64(t0, t1);
1032 break;
1033 #endif
1034 #if TCG_TARGET_HAS_ext32s_i64
1035 case INDEX_op_ext32s_i64:
1036 t0 = *tb_ptr++;
1037 t1 = tci_read_r32s(&tb_ptr);
1038 tci_write_reg64(t0, t1);
1039 break;
1040 #endif
1041 #if TCG_TARGET_HAS_ext32u_i64
1042 case INDEX_op_ext32u_i64:
1043 t0 = *tb_ptr++;
1044 t1 = tci_read_r32(&tb_ptr);
1045 tci_write_reg64(t0, t1);
1046 break;
1047 #endif
1048 #if TCG_TARGET_HAS_bswap16_i64
1049 case INDEX_op_bswap16_i64:
1050 TODO();
1051 t0 = *tb_ptr++;
1052 t1 = tci_read_r16(&tb_ptr);
1053 tci_write_reg64(t0, bswap16(t1));
1054 break;
1055 #endif
1056 #if TCG_TARGET_HAS_bswap32_i64
1057 case INDEX_op_bswap32_i64:
1058 t0 = *tb_ptr++;
1059 t1 = tci_read_r32(&tb_ptr);
1060 tci_write_reg64(t0, bswap32(t1));
1061 break;
1062 #endif
1063 #if TCG_TARGET_HAS_bswap64_i64
1064 case INDEX_op_bswap64_i64:
1065 t0 = *tb_ptr++;
1066 t1 = tci_read_r64(&tb_ptr);
1067 tci_write_reg64(t0, bswap64(t1));
1068 break;
1069 #endif
1070 #if TCG_TARGET_HAS_not_i64
1071 case INDEX_op_not_i64:
1072 t0 = *tb_ptr++;
1073 t1 = tci_read_r64(&tb_ptr);
1074 tci_write_reg64(t0, ~t1);
1075 break;
1076 #endif
1077 #if TCG_TARGET_HAS_neg_i64
1078 case INDEX_op_neg_i64:
1079 t0 = *tb_ptr++;
1080 t1 = tci_read_r64(&tb_ptr);
1081 tci_write_reg64(t0, -t1);
1082 break;
1083 #endif
1084 #endif /* TCG_TARGET_REG_BITS == 64 */
1085
1086 /* QEMU specific operations. */
1087
1088 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1089 case INDEX_op_debug_insn_start:
1090 TODO();
1091 break;
1092 #else
1093 case INDEX_op_debug_insn_start:
1094 TODO();
1095 break;
1096 #endif
1097 case INDEX_op_exit_tb:
1098 next_tb = *(uint64_t *)tb_ptr;
1099 goto exit;
1100 break;
1101 case INDEX_op_goto_tb:
1102 t0 = tci_read_i32(&tb_ptr);
1103 assert(tb_ptr == old_code_ptr + op_size);
1104 tb_ptr += (int32_t)t0;
1105 continue;
1106 case INDEX_op_qemu_ld_i32:
1107 t0 = *tb_ptr++;
1108 taddr = tci_read_ulong(&tb_ptr);
1109 oi = tci_read_i(&tb_ptr);
1110 switch (get_memop(oi)) {
1111 case MO_UB:
1112 tmp32 = qemu_ld_ub;
1113 break;
1114 case MO_SB:
1115 tmp32 = (int8_t)qemu_ld_ub;
1116 break;
1117 case MO_LEUW:
1118 tmp32 = qemu_ld_leuw;
1119 break;
1120 case MO_LESW:
1121 tmp32 = (int16_t)qemu_ld_leuw;
1122 break;
1123 case MO_LEUL:
1124 tmp32 = qemu_ld_leul;
1125 break;
1126 case MO_BEUW:
1127 tmp32 = qemu_ld_beuw;
1128 break;
1129 case MO_BESW:
1130 tmp32 = (int16_t)qemu_ld_beuw;
1131 break;
1132 case MO_BEUL:
1133 tmp32 = qemu_ld_beul;
1134 break;
1135 default:
1136 tcg_abort();
1137 }
1138 tci_write_reg(t0, tmp32);
1139 break;
1140 case INDEX_op_qemu_ld_i64:
1141 t0 = *tb_ptr++;
1142 if (TCG_TARGET_REG_BITS == 32) {
1143 t1 = *tb_ptr++;
1144 }
1145 taddr = tci_read_ulong(&tb_ptr);
1146 oi = tci_read_i(&tb_ptr);
1147 switch (get_memop(oi)) {
1148 case MO_UB:
1149 tmp64 = qemu_ld_ub;
1150 break;
1151 case MO_SB:
1152 tmp64 = (int8_t)qemu_ld_ub;
1153 break;
1154 case MO_LEUW:
1155 tmp64 = qemu_ld_leuw;
1156 break;
1157 case MO_LESW:
1158 tmp64 = (int16_t)qemu_ld_leuw;
1159 break;
1160 case MO_LEUL:
1161 tmp64 = qemu_ld_leul;
1162 break;
1163 case MO_LESL:
1164 tmp64 = (int32_t)qemu_ld_leul;
1165 break;
1166 case MO_LEQ:
1167 tmp64 = qemu_ld_leq;
1168 break;
1169 case MO_BEUW:
1170 tmp64 = qemu_ld_beuw;
1171 break;
1172 case MO_BESW:
1173 tmp64 = (int16_t)qemu_ld_beuw;
1174 break;
1175 case MO_BEUL:
1176 tmp64 = qemu_ld_beul;
1177 break;
1178 case MO_BESL:
1179 tmp64 = (int32_t)qemu_ld_beul;
1180 break;
1181 case MO_BEQ:
1182 tmp64 = qemu_ld_beq;
1183 break;
1184 default:
1185 tcg_abort();
1186 }
1187 tci_write_reg(t0, tmp64);
1188 if (TCG_TARGET_REG_BITS == 32) {
1189 tci_write_reg(t1, tmp64 >> 32);
1190 }
1191 break;
1192 case INDEX_op_qemu_st_i32:
1193 t0 = tci_read_r(&tb_ptr);
1194 taddr = tci_read_ulong(&tb_ptr);
1195 oi = tci_read_i(&tb_ptr);
1196 switch (get_memop(oi)) {
1197 case MO_UB:
1198 qemu_st_b(t0);
1199 break;
1200 case MO_LEUW:
1201 qemu_st_lew(t0);
1202 break;
1203 case MO_LEUL:
1204 qemu_st_lel(t0);
1205 break;
1206 case MO_BEUW:
1207 qemu_st_bew(t0);
1208 break;
1209 case MO_BEUL:
1210 qemu_st_bel(t0);
1211 break;
1212 default:
1213 tcg_abort();
1214 }
1215 break;
1216 case INDEX_op_qemu_st_i64:
1217 tmp64 = tci_read_r64(&tb_ptr);
1218 taddr = tci_read_ulong(&tb_ptr);
1219 oi = tci_read_i(&tb_ptr);
1220 switch (get_memop(oi)) {
1221 case MO_UB:
1222 qemu_st_b(tmp64);
1223 break;
1224 case MO_LEUW:
1225 qemu_st_lew(tmp64);
1226 break;
1227 case MO_LEUL:
1228 qemu_st_lel(tmp64);
1229 break;
1230 case MO_LEQ:
1231 qemu_st_leq(tmp64);
1232 break;
1233 case MO_BEUW:
1234 qemu_st_bew(tmp64);
1235 break;
1236 case MO_BEUL:
1237 qemu_st_bel(tmp64);
1238 break;
1239 case MO_BEQ:
1240 qemu_st_beq(tmp64);
1241 break;
1242 default:
1243 tcg_abort();
1244 }
1245 break;
1246 default:
1247 TODO();
1248 break;
1249 }
1250 assert(tb_ptr == old_code_ptr + op_size);
1251 }
1252 exit:
1253 return next_tb;
1254 }
AR7 emulation for QEMU