2 * RISC-V GDB Server Stub
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "exec/gdbstub.h"
24 * The GDB CSR xml files list them in documentation order, not numerical order,
25 * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
26 * to the hardware numbers.
29 static int csr_register_map
[] = {
272 int riscv_cpu_gdb_read_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
274 RISCVCPU
*cpu
= RISCV_CPU(cs
);
275 CPURISCVState
*env
= &cpu
->env
;
278 return gdb_get_regl(mem_buf
, env
->gpr
[n
]);
279 } else if (n
== 32) {
280 return gdb_get_regl(mem_buf
, env
->pc
);
285 int riscv_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
287 RISCVCPU
*cpu
= RISCV_CPU(cs
);
288 CPURISCVState
*env
= &cpu
->env
;
291 /* discard writes to x0 */
292 return sizeof(target_ulong
);
294 env
->gpr
[n
] = ldtul_p(mem_buf
);
295 return sizeof(target_ulong
);
296 } else if (n
== 32) {
297 env
->pc
= ldtul_p(mem_buf
);
298 return sizeof(target_ulong
);
303 static int riscv_gdb_get_fpu(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
306 if (env
->misa
& RVD
) {
307 return gdb_get_reg64(mem_buf
, env
->fpr
[n
]);
309 if (env
->misa
& RVF
) {
310 return gdb_get_reg32(mem_buf
, env
->fpr
[n
]);
312 /* there is hole between ft11 and fflags in fpu.xml */
313 } else if (n
< 36 && n
> 32) {
314 target_ulong val
= 0;
317 * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
318 * register 33, so we recalculate the map index.
319 * This also works for CSR_FRM and CSR_FCSR.
321 result
= riscv_csrrw_debug(env
, n
- 33 + csr_register_map
[8], &val
,
324 return gdb_get_regl(mem_buf
, val
);
330 static int riscv_gdb_set_fpu(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
333 env
->fpr
[n
] = ldq_p(mem_buf
); /* always 64-bit */
334 return sizeof(uint64_t);
335 /* there is hole between ft11 and fflags in fpu.xml */
336 } else if (n
< 36 && n
> 32) {
337 target_ulong val
= ldtul_p(mem_buf
);
340 * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
341 * register 33, so we recalculate the map index.
342 * This also works for CSR_FRM and CSR_FCSR.
344 result
= riscv_csrrw_debug(env
, n
- 33 + csr_register_map
[8], NULL
,
347 return sizeof(target_ulong
);
353 static int riscv_gdb_get_csr(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
355 if (n
< ARRAY_SIZE(csr_register_map
)) {
356 target_ulong val
= 0;
359 result
= riscv_csrrw_debug(env
, csr_register_map
[n
], &val
, 0, 0);
361 return gdb_get_regl(mem_buf
, val
);
367 static int riscv_gdb_set_csr(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
369 if (n
< ARRAY_SIZE(csr_register_map
)) {
370 target_ulong val
= ldtul_p(mem_buf
);
373 result
= riscv_csrrw_debug(env
, csr_register_map
[n
], NULL
, val
, -1);
375 return sizeof(target_ulong
);
381 static int riscv_gdb_get_virtual(CPURISCVState
*cs
, uint8_t *mem_buf
, int n
)
384 #ifdef CONFIG_USER_ONLY
385 return gdb_get_regl(mem_buf
, 0);
387 return gdb_get_regl(mem_buf
, cs
->priv
);
393 static int riscv_gdb_set_virtual(CPURISCVState
*cs
, uint8_t *mem_buf
, int n
)
396 #ifndef CONFIG_USER_ONLY
397 cs
->priv
= ldtul_p(mem_buf
) & 0x3;
398 if (cs
->priv
== PRV_H
) {
402 return sizeof(target_ulong
);
407 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
)
409 RISCVCPU
*cpu
= RISCV_CPU(cs
);
410 CPURISCVState
*env
= &cpu
->env
;
411 if (env
->misa
& RVD
) {
412 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
413 36, "riscv-64bit-fpu.xml", 0);
414 } else if (env
->misa
& RVF
) {
415 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
416 36, "riscv-32bit-fpu.xml", 0);
418 #if defined(TARGET_RISCV32)
419 gdb_register_coprocessor(cs
, riscv_gdb_get_csr
, riscv_gdb_set_csr
,
420 240, "riscv-32bit-csr.xml", 0);
422 gdb_register_coprocessor(cs
, riscv_gdb_get_virtual
, riscv_gdb_set_virtual
,
423 1, "riscv-32bit-virtual.xml", 0);
424 #elif defined(TARGET_RISCV64)
425 gdb_register_coprocessor(cs
, riscv_gdb_get_csr
, riscv_gdb_set_csr
,
426 240, "riscv-64bit-csr.xml", 0);
428 gdb_register_coprocessor(cs
, riscv_gdb_get_virtual
, riscv_gdb_set_virtual
,
429 1, "riscv-64bit-virtual.xml", 0);