include/hw/arm/xlnx-versal.h

   1 /*
   2  * Model of the Xilinx Versal
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef XLNX_VERSAL_H
  13 #define XLNX_VERSAL_H
  14
  15 #include "hw/sysbus.h"
  16 #include "hw/arm/arm.h"
  17 #include "hw/intc/arm_gicv3.h"
  18
  19 #define TYPE_XLNX_VERSAL "xlnx-versal"
  20 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
  21
  22 #define XLNX_VERSAL_NR_ACPUS   2
  23 #define XLNX_VERSAL_NR_UARTS   2
  24 #define XLNX_VERSAL_NR_GEMS    2
  25 #define XLNX_VERSAL_NR_IRQS    192
  26
  27 typedef struct Versal {
  28     /*< private >*/
  29     SysBusDevice parent_obj;
  30
  31     /*< public >*/
  32     struct {
  33         struct {
  34             MemoryRegion mr;
  35             ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
  36             GICv3State gic;
  37         } apu;
  38     } fpd;
  39
  40     MemoryRegion mr_ps;
  41
  42     struct {
  43         /* 4 ranges to access DDR.  */
  44         MemoryRegion mr_ddr_ranges[4];
  45     } noc;
  46
  47     struct {
  48         MemoryRegion mr_ocm;
  49
  50         struct {
  51             SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
  52             SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
  53         } iou;
  54     } lpd;
  55
  56     struct {
  57         MemoryRegion *mr_ddr;
  58         uint32_t psci_conduit;
  59     } cfg;
  60 } Versal;
  61
  62 /* Memory-map and IRQ definitions. Copied a subset from
  63  * auto-generated files.  */
  64
  65 #define VERSAL_GIC_MAINT_IRQ        9
  66 #define VERSAL_TIMER_VIRT_IRQ       11
  67 #define VERSAL_TIMER_S_EL1_IRQ      13
  68 #define VERSAL_TIMER_NS_EL1_IRQ     14
  69 #define VERSAL_TIMER_NS_EL2_IRQ     10
  70
  71 #define VERSAL_UART0_IRQ_0         18
  72 #define VERSAL_UART1_IRQ_0         19
  73 #define VERSAL_GEM0_IRQ_0          56
  74 #define VERSAL_GEM0_WAKE_IRQ_0     57
  75 #define VERSAL_GEM1_IRQ_0          58
  76 #define VERSAL_GEM1_WAKE_IRQ_0     59
  77
  78 /* Architecturally reserved IRQs suitable for virtualization.  */
  79 #define VERSAL_RSVD_IRQ_FIRST 111
  80 #define VERSAL_RSVD_IRQ_LAST  118
  81
  82 #define MM_TOP_RSVD                 0xa0000000U
  83 #define MM_TOP_RSVD_SIZE            0x4000000
  84 #define MM_GIC_APU_DIST_MAIN        0xf9000000U
  85 #define MM_GIC_APU_DIST_MAIN_SIZE   0x10000
  86 #define MM_GIC_APU_REDIST_0         0xf9080000U
  87 #define MM_GIC_APU_REDIST_0_SIZE    0x80000
  88
  89 #define MM_UART0                    0xff000000U
  90 #define MM_UART0_SIZE               0x10000
  91 #define MM_UART1                    0xff010000U
  92 #define MM_UART1_SIZE               0x10000
  93
  94 #define MM_GEM0                     0xff0c0000U
  95 #define MM_GEM0_SIZE                0x10000
  96 #define MM_GEM1                     0xff0d0000U
  97 #define MM_GEM1_SIZE                0x10000
  98
  99 #define MM_OCM                      0xfffc0000U
 100 #define MM_OCM_SIZE                 0x40000
 101
 102 #define MM_TOP_DDR                  0x0
 103 #define MM_TOP_DDR_SIZE             0x80000000U
 104 #define MM_TOP_DDR_2                0x800000000ULL
 105 #define MM_TOP_DDR_2_SIZE           0x800000000ULL
 106 #define MM_TOP_DDR_3                0xc000000000ULL
 107 #define MM_TOP_DDR_3_SIZE           0x4000000000ULL
 108 #define MM_TOP_DDR_4                0x10000000000ULL
 109 #define MM_TOP_DDR_4_SIZE           0xb780000000ULL
 110
 111 #define MM_PSM_START                0xffc80000U
 112 #define MM_PSM_END                  0xffcf0000U
 113
 114 #define MM_CRL                      0xff5e0000U
 115 #define MM_CRL_SIZE                 0x300000
 116 #define MM_IOU_SCNTR                0xff130000U
 117 #define MM_IOU_SCNTR_SIZE           0x10000
 118 #define MM_IOU_SCNTRS               0xff140000U
 119 #define MM_IOU_SCNTRS_SIZE          0x10000
 120 #define MM_FPD_CRF                  0xfd1a0000U
 121 #define MM_FPD_CRF_SIZE             0x140000
 122 #endif