2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "hw/scsi/esp.h"
31 #include "qemu/module.h"
34 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
35 * also produced as NCR89C100. See
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
41 static void esp_raise_irq(ESPState
*s
)
43 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
44 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
45 qemu_irq_raise(s
->irq
);
46 trace_esp_raise_irq();
50 static void esp_lower_irq(ESPState
*s
)
52 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
53 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
54 qemu_irq_lower(s
->irq
);
55 trace_esp_lower_irq();
59 void esp_dma_enable(ESPState
*s
, int irq
, int level
)
63 trace_esp_dma_enable();
69 trace_esp_dma_disable();
74 void esp_request_cancelled(SCSIRequest
*req
)
76 ESPState
*s
= req
->hba_private
;
78 if (req
== s
->current_req
) {
79 scsi_req_unref(s
->current_req
);
80 s
->current_req
= NULL
;
81 s
->current_dev
= NULL
;
85 static uint32_t get_cmd(ESPState
*s
, uint8_t *buf
, uint8_t buflen
)
90 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
92 dmalen
= s
->rregs
[ESP_TCLO
];
93 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
94 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
95 if (dmalen
> buflen
) {
98 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
101 if (dmalen
> TI_BUFSZ
) {
104 memcpy(buf
, s
->ti_buf
, dmalen
);
105 buf
[0] = buf
[2] >> 5;
107 trace_esp_get_cmd(dmalen
, target
);
113 if (s
->current_req
) {
114 /* Started a new command before the old one finished. Cancel it. */
115 scsi_req_cancel(s
->current_req
);
119 s
->current_dev
= scsi_device_find(&s
->bus
, 0, target
, 0);
120 if (!s
->current_dev
) {
122 s
->rregs
[ESP_RSTAT
] = 0;
123 s
->rregs
[ESP_RINTR
] = INTR_DC
;
124 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
131 static void do_busid_cmd(ESPState
*s
, uint8_t *buf
, uint8_t busid
)
135 SCSIDevice
*current_lun
;
137 trace_esp_do_busid_cmd(busid
);
139 current_lun
= scsi_device_find(&s
->bus
, 0, s
->current_dev
->id
, lun
);
140 s
->current_req
= scsi_req_new(current_lun
, 0, lun
, buf
, s
);
141 datalen
= scsi_req_enqueue(s
->current_req
);
142 s
->ti_size
= datalen
;
144 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
148 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
150 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
152 scsi_req_continue(s
->current_req
);
154 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
155 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
159 static void do_cmd(ESPState
*s
, uint8_t *buf
)
161 uint8_t busid
= buf
[0];
163 do_busid_cmd(s
, &buf
[1], busid
);
166 static void handle_satn(ESPState
*s
)
171 if (s
->dma
&& !s
->dma_enabled
) {
172 s
->dma_cb
= handle_satn
;
175 len
= get_cmd(s
, buf
, sizeof(buf
));
180 static void handle_s_without_atn(ESPState
*s
)
185 if (s
->dma
&& !s
->dma_enabled
) {
186 s
->dma_cb
= handle_s_without_atn
;
189 len
= get_cmd(s
, buf
, sizeof(buf
));
191 do_busid_cmd(s
, buf
, 0);
195 static void handle_satn_stop(ESPState
*s
)
197 if (s
->dma
&& !s
->dma_enabled
) {
198 s
->dma_cb
= handle_satn_stop
;
201 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
, sizeof(s
->cmdbuf
));
203 trace_esp_handle_satn_stop(s
->cmdlen
);
205 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
206 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
207 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
212 static void write_response(ESPState
*s
)
214 trace_esp_write_response(s
->status
);
215 s
->ti_buf
[0] = s
->status
;
218 s
->dma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
219 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
220 s
->rregs
[ESP_RINTR
] = INTR_BS
| INTR_FC
;
221 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
226 s
->rregs
[ESP_RFLAGS
] = 2;
231 static void esp_dma_done(ESPState
*s
)
233 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
234 s
->rregs
[ESP_RINTR
] = INTR_BS
;
235 s
->rregs
[ESP_RSEQ
] = 0;
236 s
->rregs
[ESP_RFLAGS
] = 0;
237 s
->rregs
[ESP_TCLO
] = 0;
238 s
->rregs
[ESP_TCMID
] = 0;
239 s
->rregs
[ESP_TCHI
] = 0;
243 static void esp_do_dma(ESPState
*s
)
250 trace_esp_do_dma(s
->cmdlen
, len
);
251 assert (s
->cmdlen
<= sizeof(s
->cmdbuf
) &&
252 len
<= sizeof(s
->cmdbuf
) - s
->cmdlen
);
253 s
->dma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
256 if (s
->async_len
== 0) {
257 /* Defer until data is available. */
260 if (len
> s
->async_len
) {
263 to_device
= (s
->ti_size
< 0);
265 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
267 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
276 if (s
->async_len
== 0) {
277 scsi_req_continue(s
->current_req
);
278 /* If there is still data to be read from the device then
279 complete the DMA operation immediately. Otherwise defer
280 until the scsi layer has completed. */
281 if (to_device
|| s
->dma_left
!= 0 || s
->ti_size
== 0) {
286 /* Partially filled a scsi buffer. Complete immediately. */
290 static void esp_report_command_complete(ESPState
*s
, uint32_t status
)
292 trace_esp_command_complete();
293 if (s
->ti_size
!= 0) {
294 trace_esp_command_complete_unexpected();
300 trace_esp_command_complete_fail();
303 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
305 if (s
->current_req
) {
306 scsi_req_unref(s
->current_req
);
307 s
->current_req
= NULL
;
308 s
->current_dev
= NULL
;
312 void esp_command_complete(SCSIRequest
*req
, uint32_t status
,
315 ESPState
*s
= req
->hba_private
;
317 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
318 /* Defer handling command complete until the previous
319 * interrupt has been handled.
321 trace_esp_command_complete_deferred();
322 s
->deferred_status
= status
;
323 s
->deferred_complete
= true;
326 esp_report_command_complete(s
, status
);
329 void esp_transfer_data(SCSIRequest
*req
, uint32_t len
)
331 ESPState
*s
= req
->hba_private
;
334 trace_esp_transfer_data(s
->dma_left
, s
->ti_size
);
336 s
->async_buf
= scsi_req_get_buf(req
);
339 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
340 /* If this was the last part of a DMA transfer then the
341 completion interrupt is deferred to here. */
346 static void handle_ti(ESPState
*s
)
348 uint32_t dmalen
, minlen
;
350 if (s
->dma
&& !s
->dma_enabled
) {
351 s
->dma_cb
= handle_ti
;
355 dmalen
= s
->rregs
[ESP_TCLO
];
356 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
357 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
361 s
->dma_counter
= dmalen
;
364 minlen
= (dmalen
< ESP_CMDBUF_SZ
) ? dmalen
: ESP_CMDBUF_SZ
;
365 else if (s
->ti_size
< 0)
366 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
368 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
369 trace_esp_handle_ti(minlen
);
371 s
->dma_left
= minlen
;
372 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
376 trace_esp_handle_ti_cmd(s
->cmdlen
);
380 do_cmd(s
, s
->cmdbuf
);
384 void esp_hard_reset(ESPState
*s
)
386 memset(s
->rregs
, 0, ESP_REGS
);
387 memset(s
->wregs
, 0, ESP_REGS
);
396 s
->rregs
[ESP_CFG1
] = 7;
399 static void esp_soft_reset(ESPState
*s
)
401 qemu_irq_lower(s
->irq
);
405 static void parent_esp_reset(ESPState
*s
, int irq
, int level
)
412 uint64_t esp_reg_read(ESPState
*s
, uint32_t saddr
)
416 trace_esp_mem_readb(saddr
, s
->rregs
[saddr
]);
419 if ((s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
421 qemu_log_mask(LOG_UNIMP
, "esp: PIO data read not implemented\n");
422 s
->rregs
[ESP_FIFO
] = 0;
423 } else if (s
->ti_rptr
< s
->ti_wptr
) {
425 s
->rregs
[ESP_FIFO
] = s
->ti_buf
[s
->ti_rptr
++];
427 if (s
->ti_rptr
== s
->ti_wptr
) {
433 /* Clear sequence step, interrupt register and all status bits
435 old_val
= s
->rregs
[ESP_RINTR
];
436 s
->rregs
[ESP_RINTR
] = 0;
437 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
438 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
440 if (s
->deferred_complete
) {
441 esp_report_command_complete(s
, s
->deferred_status
);
442 s
->deferred_complete
= false;
446 /* Return the unique id if the value has never been written */
447 if (!s
->tchi_written
) {
453 return s
->rregs
[saddr
];
456 void esp_reg_write(ESPState
*s
, uint32_t saddr
, uint64_t val
)
458 trace_esp_mem_writeb(saddr
, s
->wregs
[saddr
], val
);
461 s
->tchi_written
= true;
465 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
469 if (s
->cmdlen
< ESP_CMDBUF_SZ
) {
470 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
472 trace_esp_error_fifo_overrun();
474 } else if (s
->ti_wptr
== TI_BUFSZ
- 1) {
475 trace_esp_error_fifo_overrun();
478 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
482 s
->rregs
[saddr
] = val
;
485 /* Reload DMA counter. */
486 s
->rregs
[ESP_TCLO
] = s
->wregs
[ESP_TCLO
];
487 s
->rregs
[ESP_TCMID
] = s
->wregs
[ESP_TCMID
];
488 s
->rregs
[ESP_TCHI
] = s
->wregs
[ESP_TCHI
];
492 switch(val
& CMD_CMD
) {
494 trace_esp_mem_writeb_cmd_nop(val
);
497 trace_esp_mem_writeb_cmd_flush(val
);
499 s
->rregs
[ESP_RINTR
] = INTR_FC
;
500 s
->rregs
[ESP_RSEQ
] = 0;
501 s
->rregs
[ESP_RFLAGS
] = 0;
504 trace_esp_mem_writeb_cmd_reset(val
);
508 trace_esp_mem_writeb_cmd_bus_reset(val
);
509 s
->rregs
[ESP_RINTR
] = INTR_RST
;
510 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
518 trace_esp_mem_writeb_cmd_iccs(val
);
520 s
->rregs
[ESP_RINTR
] = INTR_FC
;
521 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
524 trace_esp_mem_writeb_cmd_msgacc(val
);
525 s
->rregs
[ESP_RINTR
] = INTR_DC
;
526 s
->rregs
[ESP_RSEQ
] = 0;
527 s
->rregs
[ESP_RFLAGS
] = 0;
531 trace_esp_mem_writeb_cmd_pad(val
);
532 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
533 s
->rregs
[ESP_RINTR
] = INTR_FC
;
534 s
->rregs
[ESP_RSEQ
] = 0;
537 trace_esp_mem_writeb_cmd_satn(val
);
540 trace_esp_mem_writeb_cmd_rstatn(val
);
543 trace_esp_mem_writeb_cmd_sel(val
);
544 handle_s_without_atn(s
);
547 trace_esp_mem_writeb_cmd_selatn(val
);
551 trace_esp_mem_writeb_cmd_selatns(val
);
555 trace_esp_mem_writeb_cmd_ensel(val
);
556 s
->rregs
[ESP_RINTR
] = 0;
559 trace_esp_mem_writeb_cmd_dissel(val
);
560 s
->rregs
[ESP_RINTR
] = 0;
564 trace_esp_error_unhandled_command(val
);
568 case ESP_WBUSID
... ESP_WSYNO
:
571 case ESP_CFG2
: case ESP_CFG3
:
572 case ESP_RES3
: case ESP_RES4
:
573 s
->rregs
[saddr
] = val
;
575 case ESP_WCCF
... ESP_WTEST
:
578 trace_esp_error_invalid_write(val
, saddr
);
581 s
->wregs
[saddr
] = val
;
584 static bool esp_mem_accepts(void *opaque
, hwaddr addr
,
585 unsigned size
, bool is_write
,
588 return (size
== 1) || (is_write
&& size
== 4);
591 const VMStateDescription vmstate_esp
= {
594 .minimum_version_id
= 3,
595 .fields
= (VMStateField
[]) {
596 VMSTATE_BUFFER(rregs
, ESPState
),
597 VMSTATE_BUFFER(wregs
, ESPState
),
598 VMSTATE_INT32(ti_size
, ESPState
),
599 VMSTATE_UINT32(ti_rptr
, ESPState
),
600 VMSTATE_UINT32(ti_wptr
, ESPState
),
601 VMSTATE_BUFFER(ti_buf
, ESPState
),
602 VMSTATE_UINT32(status
, ESPState
),
603 VMSTATE_UINT32(deferred_status
, ESPState
),
604 VMSTATE_BOOL(deferred_complete
, ESPState
),
605 VMSTATE_UINT32(dma
, ESPState
),
606 VMSTATE_PARTIAL_BUFFER(cmdbuf
, ESPState
, 16),
607 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf
, ESPState
, 16, 4),
608 VMSTATE_UINT32(cmdlen
, ESPState
),
609 VMSTATE_UINT32(do_cmd
, ESPState
),
610 VMSTATE_UINT32(dma_left
, ESPState
),
611 VMSTATE_END_OF_LIST()
615 static void sysbus_esp_mem_write(void *opaque
, hwaddr addr
,
616 uint64_t val
, unsigned int size
)
618 SysBusESPState
*sysbus
= opaque
;
621 saddr
= addr
>> sysbus
->it_shift
;
622 esp_reg_write(&sysbus
->esp
, saddr
, val
);
625 static uint64_t sysbus_esp_mem_read(void *opaque
, hwaddr addr
,
628 SysBusESPState
*sysbus
= opaque
;
631 saddr
= addr
>> sysbus
->it_shift
;
632 return esp_reg_read(&sysbus
->esp
, saddr
);
635 static const MemoryRegionOps sysbus_esp_mem_ops
= {
636 .read
= sysbus_esp_mem_read
,
637 .write
= sysbus_esp_mem_write
,
638 .endianness
= DEVICE_NATIVE_ENDIAN
,
639 .valid
.accepts
= esp_mem_accepts
,
642 static const struct SCSIBusInfo esp_scsi_info
= {
644 .max_target
= ESP_MAX_DEVS
,
647 .transfer_data
= esp_transfer_data
,
648 .complete
= esp_command_complete
,
649 .cancel
= esp_request_cancelled
652 static void sysbus_esp_gpio_demux(void *opaque
, int irq
, int level
)
654 SysBusESPState
*sysbus
= ESP_STATE(opaque
);
655 ESPState
*s
= &sysbus
->esp
;
659 parent_esp_reset(s
, irq
, level
);
662 esp_dma_enable(opaque
, irq
, level
);
667 static void sysbus_esp_realize(DeviceState
*dev
, Error
**errp
)
669 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
670 SysBusESPState
*sysbus
= ESP_STATE(dev
);
671 ESPState
*s
= &sysbus
->esp
;
673 sysbus_init_irq(sbd
, &s
->irq
);
674 assert(sysbus
->it_shift
!= -1);
676 s
->chip_id
= TCHI_FAS100A
;
677 memory_region_init_io(&sysbus
->iomem
, OBJECT(sysbus
), &sysbus_esp_mem_ops
,
678 sysbus
, "esp", ESP_REGS
<< sysbus
->it_shift
);
679 sysbus_init_mmio(sbd
, &sysbus
->iomem
);
681 qdev_init_gpio_in(dev
, sysbus_esp_gpio_demux
, 2);
683 scsi_bus_new(&s
->bus
, sizeof(s
->bus
), dev
, &esp_scsi_info
, NULL
);
686 static void sysbus_esp_hard_reset(DeviceState
*dev
)
688 SysBusESPState
*sysbus
= ESP_STATE(dev
);
689 esp_hard_reset(&sysbus
->esp
);
692 static const VMStateDescription vmstate_sysbus_esp_scsi
= {
693 .name
= "sysbusespscsi",
695 .minimum_version_id
= 1,
696 .fields
= (VMStateField
[]) {
697 VMSTATE_STRUCT(esp
, SysBusESPState
, 0, vmstate_esp
, ESPState
),
698 VMSTATE_END_OF_LIST()
702 static void sysbus_esp_class_init(ObjectClass
*klass
, void *data
)
704 DeviceClass
*dc
= DEVICE_CLASS(klass
);
706 dc
->realize
= sysbus_esp_realize
;
707 dc
->reset
= sysbus_esp_hard_reset
;
708 dc
->vmsd
= &vmstate_sysbus_esp_scsi
;
709 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
712 static const TypeInfo sysbus_esp_info
= {
714 .parent
= TYPE_SYS_BUS_DEVICE
,
715 .instance_size
= sizeof(SysBusESPState
),
716 .class_init
= sysbus_esp_class_init
,
719 static void esp_register_types(void)
721 type_register_static(&sysbus_esp_info
);
724 type_init(esp_register_types
)