?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Revert xen/io/ring.h of "Clean up a few header guard symbols"
[qemu/ar7.git] / hw / net / e1000e_core.c
blob2a221c2ef99587c4a75e91877f92491ae1220373
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "sysemu/sysemu.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/pci/msi.h"
41 #include "hw/pci/msix.h"
42
43 #include "net_tx_pkt.h"
44 #include "net_rx_pkt.h"
45
46 #include "e1000x_common.h"
47 #include "e1000e_core.h"
48
49 #include "trace.h"
50
51 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per
52 second according to spec 10.2.4.2 */
53 #define E1000E_MAX_TX_FRAGS (64)
54
55 static inline void
56 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
57
58 static inline void
59 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
60 {
61 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
62 trace_e1000e_wrn_no_ts_support();
63 }
64 }
65
66 static inline void
67 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
68 {
69 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
70 trace_e1000e_wrn_no_snap_support();
71 }
72 }
73
74 static inline void
75 e1000e_raise_legacy_irq(E1000ECore *core)
76 {
77 trace_e1000e_irq_legacy_notify(true);
78 e1000x_inc_reg_if_not_full(core->mac, IAC);
79 pci_set_irq(core->owner, 1);
80 }
81
82 static inline void
83 e1000e_lower_legacy_irq(E1000ECore *core)
84 {
85 trace_e1000e_irq_legacy_notify(false);
86 pci_set_irq(core->owner, 0);
87 }
88
89 static inline void
90 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
91 {
92 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
93 timer->delay_resolution_ns;
94
95 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
96
97 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
98
99 timer->running = true;
100 }
101
102 static void
103 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
104 {
105 if (timer->running) {
106 e1000e_intrmgr_rearm_timer(timer);
107 }
108 }
109
110 static void
111 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
112 {
113 if (timer->running) {
114 timer_del(timer->timer);
115 }
116 }
117
118 static inline void
119 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
120 {
121 if (timer->running) {
122 timer_del(timer->timer);
123 timer->running = false;
124 }
125 }
126
127 static inline void
128 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
129 {
130 trace_e1000e_irq_fire_delayed_interrupts();
131 e1000e_set_interrupt_cause(core, 0);
132 }
133
134 static void
135 e1000e_intrmgr_on_timer(void *opaque)
136 {
137 E1000IntrDelayTimer *timer = opaque;
138
139 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
140
141 timer->running = false;
142 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
143 }
144
145 static void
146 e1000e_intrmgr_on_throttling_timer(void *opaque)
147 {
148 E1000IntrDelayTimer *timer = opaque;
149
150 assert(!msix_enabled(timer->core->owner));
151
152 timer->running = false;
153
154 if (!timer->core->itr_intr_pending) {
155 trace_e1000e_irq_throttling_no_pending_interrupts();
156 return;
157 }
158
159 if (msi_enabled(timer->core->owner)) {
160 trace_e1000e_irq_msi_notify_postponed();
161 e1000e_set_interrupt_cause(timer->core, 0);
162 } else {
163 trace_e1000e_irq_legacy_notify_postponed();
164 e1000e_set_interrupt_cause(timer->core, 0);
165 }
166 }
167
168 static void
169 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
170 {
171 E1000IntrDelayTimer *timer = opaque;
172 int idx = timer - &timer->core->eitr[0];
173
174 assert(msix_enabled(timer->core->owner));
175
176 timer->running = false;
177
178 if (!timer->core->eitr_intr_pending[idx]) {
179 trace_e1000e_irq_throttling_no_pending_vec(idx);
180 return;
181 }
182
183 trace_e1000e_irq_msix_notify_postponed_vec(idx);
184 msix_notify(timer->core->owner, idx);
185 }
186
187 static void
188 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
189 {
190 int i;
191
192 core->radv.delay_reg = RADV;
193 core->rdtr.delay_reg = RDTR;
194 core->raid.delay_reg = RAID;
195 core->tadv.delay_reg = TADV;
196 core->tidv.delay_reg = TIDV;
197
198 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
199 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
200 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
201 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
202 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203
204 core->radv.core = core;
205 core->rdtr.core = core;
206 core->raid.core = core;
207 core->tadv.core = core;
208 core->tidv.core = core;
209
210 core->itr.core = core;
211 core->itr.delay_reg = ITR;
212 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
213
214 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
215 core->eitr[i].core = core;
216 core->eitr[i].delay_reg = EITR + i;
217 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
218 }
219
220 if (!create) {
221 return;
222 }
223
224 core->radv.timer =
225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
226 core->rdtr.timer =
227 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
228 core->raid.timer =
229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
230
231 core->tadv.timer =
232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
233 core->tidv.timer =
234 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
235
236 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
237 e1000e_intrmgr_on_throttling_timer,
238 &core->itr);
239
240 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
241 core->eitr[i].timer =
242 timer_new_ns(QEMU_CLOCK_VIRTUAL,
243 e1000e_intrmgr_on_msix_throttling_timer,
244 &core->eitr[i]);
245 }
246 }
247
248 static inline void
249 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
250 {
251 e1000e_intrmgr_stop_timer(&core->radv);
252 e1000e_intrmgr_stop_timer(&core->rdtr);
253 e1000e_intrmgr_stop_timer(&core->raid);
254 e1000e_intrmgr_stop_timer(&core->tidv);
255 e1000e_intrmgr_stop_timer(&core->tadv);
256 }
257
258 static bool
259 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
260 {
261 uint32_t delayable_causes;
262 uint32_t rdtr = core->mac[RDTR];
263 uint32_t radv = core->mac[RADV];
264 uint32_t raid = core->mac[RAID];
265
266 if (msix_enabled(core->owner)) {
267 return false;
268 }
269
270 delayable_causes = E1000_ICR_RXQ0 |
271 E1000_ICR_RXQ1 |
272 E1000_ICR_RXT0;
273
274 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
275 delayable_causes |= E1000_ICR_ACK;
276 }
277
278 /* Clean up all causes that may be delayed */
279 core->delayed_causes |= *causes & delayable_causes;
280 *causes &= ~delayable_causes;
281
282 /* Check if delayed RX interrupts disabled by client
283 or if there are causes that cannot be delayed */
284 if ((rdtr == 0) || (*causes != 0)) {
285 return false;
286 }
287
288 /* Check if delayed RX ACK interrupts disabled by client
289 and there is an ACK packet received */
290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
291 return false;
292 }
293
294 /* All causes delayed */
295 e1000e_intrmgr_rearm_timer(&core->rdtr);
296
297 if (!core->radv.running && (radv != 0)) {
298 e1000e_intrmgr_rearm_timer(&core->radv);
299 }
300
301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
302 e1000e_intrmgr_rearm_timer(&core->raid);
303 }
304
305 return true;
306 }
307
308 static bool
309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
310 {
311 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
312 E1000_ICR_TXQ1 |
313 E1000_ICR_TXQE |
314 E1000_ICR_TXDW;
315
316 if (msix_enabled(core->owner)) {
317 return false;
318 }
319
320 /* Clean up all causes that may be delayed */
321 core->delayed_causes |= *causes & delayable_causes;
322 *causes &= ~delayable_causes;
323
324 /* If there are causes that cannot be delayed */
325 if (*causes != 0) {
326 return false;
327 }
328
329 /* All causes delayed */
330 e1000e_intrmgr_rearm_timer(&core->tidv);
331
332 if (!core->tadv.running && (core->mac[TADV] != 0)) {
333 e1000e_intrmgr_rearm_timer(&core->tadv);
334 }
335
336 return true;
337 }
338
339 static uint32_t
340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
341 {
342 uint32_t res;
343
344 if (msix_enabled(core->owner)) {
345 assert(core->delayed_causes == 0);
346 return 0;
347 }
348
349 res = core->delayed_causes;
350 core->delayed_causes = 0;
351
352 e1000e_intrmgr_stop_delay_timers(core);
353
354 return res;
355 }
356
357 static void
358 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
359 {
360 int i;
361 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
362
363 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
364 core->mac[ICR] |= val;
365
366 if (core->itr.running) {
367 timer_del(core->itr.timer);
368 e1000e_intrmgr_on_throttling_timer(&core->itr);
369 }
370
371 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
372 if (core->eitr[i].running) {
373 timer_del(core->eitr[i].timer);
374 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
375 }
376 }
377 }
378
379 static void
380 e1000e_intrmgr_resume(E1000ECore *core)
381 {
382 int i;
383
384 e1000e_intmgr_timer_resume(&core->radv);
385 e1000e_intmgr_timer_resume(&core->rdtr);
386 e1000e_intmgr_timer_resume(&core->raid);
387 e1000e_intmgr_timer_resume(&core->tidv);
388 e1000e_intmgr_timer_resume(&core->tadv);
389
390 e1000e_intmgr_timer_resume(&core->itr);
391
392 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
393 e1000e_intmgr_timer_resume(&core->eitr[i]);
394 }
395 }
396
397 static void
398 e1000e_intrmgr_pause(E1000ECore *core)
399 {
400 int i;
401
402 e1000e_intmgr_timer_pause(&core->radv);
403 e1000e_intmgr_timer_pause(&core->rdtr);
404 e1000e_intmgr_timer_pause(&core->raid);
405 e1000e_intmgr_timer_pause(&core->tidv);
406 e1000e_intmgr_timer_pause(&core->tadv);
407
408 e1000e_intmgr_timer_pause(&core->itr);
409
410 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
411 e1000e_intmgr_timer_pause(&core->eitr[i]);
412 }
413 }
414
415 static void
416 e1000e_intrmgr_reset(E1000ECore *core)
417 {
418 int i;
419
420 core->delayed_causes = 0;
421
422 e1000e_intrmgr_stop_delay_timers(core);
423
424 e1000e_intrmgr_stop_timer(&core->itr);
425
426 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
427 e1000e_intrmgr_stop_timer(&core->eitr[i]);
428 }
429 }
430
431 static void
432 e1000e_intrmgr_pci_unint(E1000ECore *core)
433 {
434 int i;
435
436 timer_del(core->radv.timer);
437 timer_free(core->radv.timer);
438 timer_del(core->rdtr.timer);
439 timer_free(core->rdtr.timer);
440 timer_del(core->raid.timer);
441 timer_free(core->raid.timer);
442
443 timer_del(core->tadv.timer);
444 timer_free(core->tadv.timer);
445 timer_del(core->tidv.timer);
446 timer_free(core->tidv.timer);
447
448 timer_del(core->itr.timer);
449 timer_free(core->itr.timer);
450
451 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
452 timer_del(core->eitr[i].timer);
453 timer_free(core->eitr[i].timer);
454 }
455 }
456
457 static void
458 e1000e_intrmgr_pci_realize(E1000ECore *core)
459 {
460 e1000e_intrmgr_initialize_all_timers(core, true);
461 }
462
463 static inline bool
464 e1000e_rx_csum_enabled(E1000ECore *core)
465 {
466 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
467 }
468
469 static inline bool
470 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
471 {
472 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
473 }
474
475 static inline bool
476 e1000e_rx_use_ps_descriptor(E1000ECore *core)
477 {
478 return !e1000e_rx_use_legacy_descriptor(core) &&
479 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
480 }
481
482 static inline bool
483 e1000e_rss_enabled(E1000ECore *core)
484 {
485 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
486 !e1000e_rx_csum_enabled(core) &&
487 !e1000e_rx_use_legacy_descriptor(core);
488 }
489
490 typedef struct E1000E_RSSInfo_st {
491 bool enabled;
492 uint32_t hash;
493 uint32_t queue;
494 uint32_t type;
495 } E1000E_RSSInfo;
496
497 static uint32_t
498 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
499 {
500 bool isip4, isip6, isudp, istcp;
501
502 assert(e1000e_rss_enabled(core));
503
504 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
505
506 if (isip4) {
507 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
508
509 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC],
510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
511 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
512
513 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
514 return E1000_MRQ_RSS_TYPE_IPV4TCP;
515 }
516
517 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
518 return E1000_MRQ_RSS_TYPE_IPV4;
519 }
520 } else if (isip6) {
521 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
522
523 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
524 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
525
526 /*
527 * Following two traces must not be combined because resulting
528 * event will have 11 arguments totally and some trace backends
529 * (at least "ust") have limitation of maximum 10 arguments per
530 * event. Events with more arguments fail to compile for
531 * backends like these.
532 */
533 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
534 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp,
535 ip6info->has_ext_hdrs,
536 ip6info->rss_ex_dst_valid,
537 ip6info->rss_ex_src_valid,
538 core->mac[MRQC],
539 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
540 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
541 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
542
543 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
544 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
545 ip6info->rss_ex_src_valid))) {
546
547 if (istcp && !ip6info->fragment &&
548 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
549 return E1000_MRQ_RSS_TYPE_IPV6TCP;
550 }
551
552 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
553 return E1000_MRQ_RSS_TYPE_IPV6EX;
554 }
555
556 }
557
558 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
559 return E1000_MRQ_RSS_TYPE_IPV6;
560 }
561
562 }
563
564 return E1000_MRQ_RSS_TYPE_NONE;
565 }
566
567 static uint32_t
568 e1000e_rss_calc_hash(E1000ECore *core,
569 struct NetRxPkt *pkt,
570 E1000E_RSSInfo *info)
571 {
572 NetRxPktRssType type;
573
574 assert(e1000e_rss_enabled(core));
575
576 switch (info->type) {
577 case E1000_MRQ_RSS_TYPE_IPV4:
578 type = NetPktRssIpV4;
579 break;
580 case E1000_MRQ_RSS_TYPE_IPV4TCP:
581 type = NetPktRssIpV4Tcp;
582 break;
583 case E1000_MRQ_RSS_TYPE_IPV6TCP:
584 type = NetPktRssIpV6Tcp;
585 break;
586 case E1000_MRQ_RSS_TYPE_IPV6:
587 type = NetPktRssIpV6;
588 break;
589 case E1000_MRQ_RSS_TYPE_IPV6EX:
590 type = NetPktRssIpV6Ex;
591 break;
592 default:
593 assert(false);
594 return 0;
595 }
596
597 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
598 }
599
600 static void
601 e1000e_rss_parse_packet(E1000ECore *core,
602 struct NetRxPkt *pkt,
603 E1000E_RSSInfo *info)
604 {
605 trace_e1000e_rx_rss_started();
606
607 if (!e1000e_rss_enabled(core)) {
608 info->enabled = false;
609 info->hash = 0;
610 info->queue = 0;
611 info->type = 0;
612 trace_e1000e_rx_rss_disabled();
613 return;
614 }
615
616 info->enabled = true;
617
618 info->type = e1000e_rss_get_hash_type(core, pkt);
619
620 trace_e1000e_rx_rss_type(info->type);
621
622 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
623 info->hash = 0;
624 info->queue = 0;
625 return;
626 }
627
628 info->hash = e1000e_rss_calc_hash(core, pkt, info);
629 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
630 }
631
632 static void
633 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
634 {
635 if (tx->props.tse && tx->cptse) {
636 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss);
637 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
638 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
639 return;
640 }
641
642 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
643 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0);
644 }
645
646 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
647 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
648 }
649 }
650
651 static bool
652 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
653 {
654 int target_queue = MIN(core->max_queue_num, queue_index);
655 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
656
657 e1000e_setup_tx_offloads(core, tx);
658
659 net_tx_pkt_dump(tx->tx_pkt);
660
661 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) ||
662 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
663 return net_tx_pkt_send_loopback(tx->tx_pkt, queue);
664 } else {
665 return net_tx_pkt_send(tx->tx_pkt, queue);
666 }
667 }
668
669 static void
670 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
671 {
672 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
673 PTC1023, PTC1522 };
674
675 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt);
676
677 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
678 e1000x_inc_reg_if_not_full(core->mac, TPT);
679 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
680
681 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
682 case ETH_PKT_BCAST:
683 e1000x_inc_reg_if_not_full(core->mac, BPTC);
684 break;
685 case ETH_PKT_MCAST:
686 e1000x_inc_reg_if_not_full(core->mac, MPTC);
687 break;
688 case ETH_PKT_UCAST:
689 break;
690 default:
691 g_assert_not_reached();
692 }
693
694 core->mac[GPTC] = core->mac[TPT];
695 core->mac[GOTCL] = core->mac[TOTL];
696 core->mac[GOTCH] = core->mac[TOTH];
697 }
698
699 static void
700 e1000e_process_tx_desc(E1000ECore *core,
701 struct e1000e_tx *tx,
702 struct e1000_tx_desc *dp,
703 int queue_index)
704 {
705 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
706 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
707 unsigned int split_size = txd_lower & 0xffff;
708 uint64_t addr;
709 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
710 bool eop = txd_lower & E1000_TXD_CMD_EOP;
711
712 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
713 e1000x_read_tx_ctx_descr(xp, &tx->props);
714 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
715 return;
716 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
717 /* data descriptor */
718 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
719 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
720 e1000e_process_ts_option(core, dp);
721 } else {
722 /* legacy descriptor */
723 e1000e_process_ts_option(core, dp);
724 tx->cptse = 0;
725 }
726
727 addr = le64_to_cpu(dp->buffer_addr);
728
729 if (!tx->skip_cp) {
730 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
731 tx->skip_cp = true;
732 }
733 }
734
735 if (eop) {
736 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
737 if (e1000x_vlan_enabled(core->mac) &&
738 e1000x_is_vlan_txd(txd_lower)) {
739 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
740 le16_to_cpu(dp->upper.fields.special), core->vet);
741 }
742 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
743 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
744 }
745 }
746
747 tx->skip_cp = false;
748 net_tx_pkt_reset(tx->tx_pkt);
749
750 tx->sum_needed = 0;
751 tx->cptse = 0;
752 }
753 }
754
755 static inline uint32_t
756 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
757 {
758 if (!msix_enabled(core->owner)) {
759 return E1000_ICR_TXDW;
760 }
761
762 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
763 }
764
765 static inline uint32_t
766 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
767 bool min_threshold_hit)
768 {
769 if (!msix_enabled(core->owner)) {
770 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
771 }
772
773 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
774 }
775
776 static uint32_t
777 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
778 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
779 {
780 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
781
782 if (!(txd_lower & E1000_TXD_CMD_RS) &&
783 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
784 return 0;
785 }
786
787 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
788
789 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
790
791 dp->upper.data = cpu_to_le32(txd_upper);
792 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
793 &dp->upper, sizeof(dp->upper));
794 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
795 }
796
797 typedef struct E1000E_RingInfo_st {
798 int dbah;
799 int dbal;
800 int dlen;
801 int dh;
802 int dt;
803 int idx;
804 } E1000E_RingInfo;
805
806 static inline bool
807 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
808 {
809 return core->mac[r->dh] == core->mac[r->dt] ||
810 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
811 }
812
813 static inline uint64_t
814 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
815 {
816 uint64_t bah = core->mac[r->dbah];
817 uint64_t bal = core->mac[r->dbal];
818
819 return (bah << 32) + bal;
820 }
821
822 static inline uint64_t
823 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
824 {
825 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
826 }
827
828 static inline void
829 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
830 {
831 core->mac[r->dh] += count;
832
833 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
834 core->mac[r->dh] = 0;
835 }
836 }
837
838 static inline uint32_t
839 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
840 {
841 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
842 core->mac[r->dh], core->mac[r->dt]);
843
844 if (core->mac[r->dh] <= core->mac[r->dt]) {
845 return core->mac[r->dt] - core->mac[r->dh];
846 }
847
848 if (core->mac[r->dh] > core->mac[r->dt]) {
849 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
850 core->mac[r->dt] - core->mac[r->dh];
851 }
852
853 g_assert_not_reached();
854 return 0;
855 }
856
857 static inline bool
858 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
859 {
860 return core->mac[r->dlen] > 0;
861 }
862
863 static inline uint32_t
864 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
865 {
866 return core->mac[r->dlen];
867 }
868
869 typedef struct E1000E_TxRing_st {
870 const E1000E_RingInfo *i;
871 struct e1000e_tx *tx;
872 } E1000E_TxRing;
873
874 static inline int
875 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
876 {
877 return (reg_idx - base_reg_idx) / (0x100 >> 2);
878 }
879
880 static inline void
881 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
882 {
883 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
884 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
885 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
886 };
887
888 assert(idx < ARRAY_SIZE(i));
889
890 txr->i = &i[idx];
891 txr->tx = &core->tx[idx];
892 }
893
894 typedef struct E1000E_RxRing_st {
895 const E1000E_RingInfo *i;
896 } E1000E_RxRing;
897
898 static inline void
899 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
900 {
901 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
902 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
903 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
904 };
905
906 assert(idx < ARRAY_SIZE(i));
907
908 rxr->i = &i[idx];
909 }
910
911 static void
912 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
913 {
914 dma_addr_t base;
915 struct e1000_tx_desc desc;
916 bool ide = false;
917 const E1000E_RingInfo *txi = txr->i;
918 uint32_t cause = E1000_ICS_TXQE;
919
920 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
921 trace_e1000e_tx_disabled();
922 return;
923 }
924
925 while (!e1000e_ring_empty(core, txi)) {
926 base = e1000e_ring_head_descr(core, txi);
927
928 pci_dma_read(core->owner, base, &desc, sizeof(desc));
929
930 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
931 desc.lower.data, desc.upper.data);
932
933 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
934 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
935
936 e1000e_ring_advance(core, txi, 1);
937 }
938
939 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
940 e1000e_set_interrupt_cause(core, cause);
941 }
942 }
943
944 static bool
945 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
946 size_t total_size)
947 {
948 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
949
950 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
951 core->rx_desc_buf_size);
952
953 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
954 core->rx_desc_buf_size;
955 }
956
957 void
958 e1000e_start_recv(E1000ECore *core)
959 {
960 int i;
961
962 trace_e1000e_rx_start_recv();
963
964 for (i = 0; i <= core->max_queue_num; i++) {
965 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
966 }
967 }
968
969 int
970 e1000e_can_receive(E1000ECore *core)
971 {
972 int i;
973
974 if (!e1000x_rx_ready(core->owner, core->mac)) {
975 return false;
976 }
977
978 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
979 E1000E_RxRing rxr;
980
981 e1000e_rx_ring_init(core, &rxr, i);
982 if (e1000e_ring_enabled(core, rxr.i) &&
983 e1000e_has_rxbufs(core, rxr.i, 1)) {
984 trace_e1000e_rx_can_recv();
985 return true;
986 }
987 }
988
989 trace_e1000e_rx_can_recv_rings_full();
990 return false;
991 }
992
993 ssize_t
994 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
995 {
996 const struct iovec iov = {
997 .iov_base = (uint8_t *)buf,
998 .iov_len = size
999 };
1000
1001 return e1000e_receive_iov(core, &iov, 1);
1002 }
1003
1004 static inline bool
1005 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1006 {
1007 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1008 }
1009
1010 static inline bool
1011 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1012 {
1013 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1014 }
1015
1016 static bool
1017 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1018 {
1019 uint32_t rctl = core->mac[RCTL];
1020
1021 if (e1000x_is_vlan_packet(buf, core->vet) &&
1022 e1000x_vlan_rx_filter_enabled(core->mac)) {
1023 uint16_t vid = lduw_be_p(buf + 14);
1024 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) +
1025 ((vid >> 5) & 0x7f));
1026 if ((vfta & (1 << (vid & 0x1f))) == 0) {
1027 trace_e1000e_rx_flt_vlan_mismatch(vid);
1028 return false;
1029 } else {
1030 trace_e1000e_rx_flt_vlan_match(vid);
1031 }
1032 }
1033
1034 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1035 case ETH_PKT_UCAST:
1036 if (rctl & E1000_RCTL_UPE) {
1037 return true; /* promiscuous ucast */
1038 }
1039 break;
1040
1041 case ETH_PKT_BCAST:
1042 if (rctl & E1000_RCTL_BAM) {
1043 return true; /* broadcast enabled */
1044 }
1045 break;
1046
1047 case ETH_PKT_MCAST:
1048 if (rctl & E1000_RCTL_MPE) {
1049 return true; /* promiscuous mcast */
1050 }
1051 break;
1052
1053 default:
1054 g_assert_not_reached();
1055 }
1056
1057 return e1000x_rx_group_filter(core->mac, buf);
1058 }
1059
1060 static inline void
1061 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1062 {
1063 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1064 *buff_addr = le64_to_cpu(d->buffer_addr);
1065 }
1066
1067 static inline void
1068 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1069 {
1070 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1071 *buff_addr = le64_to_cpu(d->read.buffer_addr);
1072 }
1073
1074 static inline void
1075 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1076 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1077 {
1078 int i;
1079 union e1000_rx_desc_packet_split *d =
1080 (union e1000_rx_desc_packet_split *) desc;
1081
1082 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1083 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]);
1084 }
1085
1086 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1],
1087 (*buff_addr)[2], (*buff_addr)[3]);
1088 }
1089
1090 static inline void
1091 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
1092 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1093 {
1094 if (e1000e_rx_use_legacy_descriptor(core)) {
1095 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]);
1096 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1097 } else {
1098 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1099 e1000e_read_ps_rx_descr(core, desc, buff_addr);
1100 } else {
1101 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]);
1102 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1103 }
1104 }
1105 }
1106
1107 static void
1108 e1000e_verify_csum_in_sw(E1000ECore *core,
1109 struct NetRxPkt *pkt,
1110 uint32_t *status_flags,
1111 bool istcp, bool isudp)
1112 {
1113 bool csum_valid;
1114 uint32_t csum_error;
1115
1116 if (e1000e_rx_l3_cso_enabled(core)) {
1117 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1118 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1119 } else {
1120 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1121 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1122 }
1123 } else {
1124 trace_e1000e_rx_metadata_l3_cso_disabled();
1125 }
1126
1127 if (!e1000e_rx_l4_cso_enabled(core)) {
1128 trace_e1000e_rx_metadata_l4_cso_disabled();
1129 return;
1130 }
1131
1132 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1133 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1134 return;
1135 }
1136
1137 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1138
1139 if (istcp) {
1140 *status_flags |= E1000_RXD_STAT_TCPCS |
1141 csum_error;
1142 } else if (isudp) {
1143 *status_flags |= E1000_RXD_STAT_TCPCS |
1144 E1000_RXD_STAT_UDPCS |
1145 csum_error;
1146 }
1147 }
1148
1149 static inline bool
1150 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1151 {
1152 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1153 return false;
1154 }
1155
1156 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1157 return !net_rx_pkt_has_tcp_data(rx_pkt);
1158 }
1159
1160 return true;
1161 }
1162
1163 static void
1164 e1000e_build_rx_metadata(E1000ECore *core,
1165 struct NetRxPkt *pkt,
1166 bool is_eop,
1167 const E1000E_RSSInfo *rss_info,
1168 uint32_t *rss, uint32_t *mrq,
1169 uint32_t *status_flags,
1170 uint16_t *ip_id,
1171 uint16_t *vlan_tag)
1172 {
1173 struct virtio_net_hdr *vhdr;
1174 bool isip4, isip6, istcp, isudp;
1175 uint32_t pkt_type;
1176
1177 *status_flags = E1000_RXD_STAT_DD;
1178
1179 /* No additional metadata needed for non-EOP descriptors */
1180 if (!is_eop) {
1181 goto func_exit;
1182 }
1183
1184 *status_flags |= E1000_RXD_STAT_EOP;
1185
1186 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1187 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp);
1188
1189 /* VLAN state */
1190 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1191 *status_flags |= E1000_RXD_STAT_VP;
1192 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1193 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1194 }
1195
1196 /* Packet parsing results */
1197 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1198 if (rss_info->enabled) {
1199 *rss = cpu_to_le32(rss_info->hash);
1200 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1201 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1202 }
1203 } else if (isip4) {
1204 *status_flags |= E1000_RXD_STAT_IPIDV;
1205 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1206 trace_e1000e_rx_metadata_ip_id(*ip_id);
1207 }
1208
1209 if (istcp && e1000e_is_tcp_ack(core, pkt)) {
1210 *status_flags |= E1000_RXD_STAT_ACK;
1211 trace_e1000e_rx_metadata_ack();
1212 }
1213
1214 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1215 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1216 pkt_type = E1000_RXD_PKT_MAC;
1217 } else if (istcp || isudp) {
1218 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1219 } else if (isip4 || isip6) {
1220 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1221 } else {
1222 pkt_type = E1000_RXD_PKT_MAC;
1223 }
1224
1225 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1226 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1227
1228 /* RX CSO information */
1229 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1230 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1231 goto func_exit;
1232 }
1233
1234 if (!net_rx_pkt_has_virt_hdr(pkt)) {
1235 trace_e1000e_rx_metadata_no_virthdr();
1236 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1237 goto func_exit;
1238 }
1239
1240 vhdr = net_rx_pkt_get_vhdr(pkt);
1241
1242 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1243 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1244 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1245 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1246 goto func_exit;
1247 }
1248
1249 if (e1000e_rx_l3_cso_enabled(core)) {
1250 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0;
1251 } else {
1252 trace_e1000e_rx_metadata_l3_cso_disabled();
1253 }
1254
1255 if (e1000e_rx_l4_cso_enabled(core)) {
1256 if (istcp) {
1257 *status_flags |= E1000_RXD_STAT_TCPCS;
1258 } else if (isudp) {
1259 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1260 }
1261 } else {
1262 trace_e1000e_rx_metadata_l4_cso_disabled();
1263 }
1264
1265 trace_e1000e_rx_metadata_status_flags(*status_flags);
1266
1267 func_exit:
1268 *status_flags = cpu_to_le32(*status_flags);
1269 }
1270
1271 static inline void
1272 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc,
1273 struct NetRxPkt *pkt,
1274 const E1000E_RSSInfo *rss_info,
1275 uint16_t length)
1276 {
1277 uint32_t status_flags, rss, mrq;
1278 uint16_t ip_id;
1279
1280 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1281
1282 assert(!rss_info->enabled);
1283
1284 d->length = cpu_to_le16(length);
1285 d->csum = 0;
1286
1287 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1288 rss_info,
1289 &rss, &mrq,
1290 &status_flags, &ip_id,
1291 &d->special);
1292 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1293 d->status = (uint8_t) le32_to_cpu(status_flags);
1294 d->special = 0;
1295 }
1296
1297 static inline void
1298 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc,
1299 struct NetRxPkt *pkt,
1300 const E1000E_RSSInfo *rss_info,
1301 uint16_t length)
1302 {
1303 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1304
1305 memset(&d->wb, 0, sizeof(d->wb));
1306
1307 d->wb.upper.length = cpu_to_le16(length);
1308
1309 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1310 rss_info,
1311 &d->wb.lower.hi_dword.rss,
1312 &d->wb.lower.mrq,
1313 &d->wb.upper.status_error,
1314 &d->wb.lower.hi_dword.csum_ip.ip_id,
1315 &d->wb.upper.vlan);
1316 }
1317
1318 static inline void
1319 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1320 struct NetRxPkt *pkt,
1321 const E1000E_RSSInfo *rss_info,
1322 size_t ps_hdr_len,
1323 uint16_t(*written)[MAX_PS_BUFFERS])
1324 {
1325 int i;
1326 union e1000_rx_desc_packet_split *d =
1327 (union e1000_rx_desc_packet_split *) desc;
1328
1329 memset(&d->wb, 0, sizeof(d->wb));
1330
1331 d->wb.middle.length0 = cpu_to_le16((*written)[0]);
1332
1333 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1334 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1335 }
1336
1337 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1338 rss_info,
1339 &d->wb.lower.hi_dword.rss,
1340 &d->wb.lower.mrq,
1341 &d->wb.middle.status_error,
1342 &d->wb.lower.hi_dword.csum_ip.ip_id,
1343 &d->wb.middle.vlan);
1344
1345 d->wb.upper.header_status =
1346 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1347
1348 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1349 (*written)[2], (*written)[3]);
1350 }
1351
1352 static inline void
1353 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc,
1354 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1355 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1356 {
1357 if (e1000e_rx_use_legacy_descriptor(core)) {
1358 assert(ps_hdr_len == 0);
1359 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]);
1360 } else {
1361 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1362 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info,
1363 ps_hdr_len, written);
1364 } else {
1365 assert(ps_hdr_len == 0);
1366 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info,
1367 (*written)[0]);
1368 }
1369 }
1370 }
1371
1372 typedef struct e1000e_ba_state_st {
1373 uint16_t written[MAX_PS_BUFFERS];
1374 uint8_t cur_idx;
1375 } e1000e_ba_state;
1376
1377 static inline void
1378 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1379 hwaddr (*ba)[MAX_PS_BUFFERS],
1380 e1000e_ba_state *bastate,
1381 const char *data,
1382 dma_addr_t data_len)
1383 {
1384 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1385
1386 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len);
1387 bastate->written[0] += data_len;
1388
1389 bastate->cur_idx = 1;
1390 }
1391
1392 static void
1393 e1000e_write_to_rx_buffers(E1000ECore *core,
1394 hwaddr (*ba)[MAX_PS_BUFFERS],
1395 e1000e_ba_state *bastate,
1396 const char *data,
1397 dma_addr_t data_len)
1398 {
1399 while (data_len > 0) {
1400 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1401 uint32_t cur_buf_bytes_left = cur_buf_len -
1402 bastate->written[bastate->cur_idx];
1403 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1404
1405 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1406 (*ba)[bastate->cur_idx],
1407 bastate->written[bastate->cur_idx],
1408 data,
1409 bytes_to_write);
1410
1411 pci_dma_write(core->owner,
1412 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1413 data, bytes_to_write);
1414
1415 bastate->written[bastate->cur_idx] += bytes_to_write;
1416 data += bytes_to_write;
1417 data_len -= bytes_to_write;
1418
1419 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1420 bastate->cur_idx++;
1421 }
1422
1423 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1424 }
1425 }
1426
1427 static void
1428 e1000e_update_rx_stats(E1000ECore *core,
1429 size_t data_size,
1430 size_t data_fcs_size)
1431 {
1432 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1433
1434 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1435 case ETH_PKT_BCAST:
1436 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1437 break;
1438
1439 case ETH_PKT_MCAST:
1440 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1441 break;
1442
1443 default:
1444 break;
1445 }
1446 }
1447
1448 static inline bool
1449 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1450 {
1451 return e1000e_ring_free_descr_num(core, rxi) ==
1452 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1453 }
1454
1455 static bool
1456 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1457 {
1458 bool isip4, isip6, isudp, istcp;
1459 bool fragment;
1460
1461 if (!e1000e_rx_use_ps_descriptor(core)) {
1462 return false;
1463 }
1464
1465 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1466
1467 if (isip4) {
1468 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1469 } else if (isip6) {
1470 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1471 } else {
1472 return false;
1473 }
1474
1475 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1476 return false;
1477 }
1478
1479 if (!fragment && (isudp || istcp)) {
1480 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1481 } else {
1482 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1483 }
1484
1485 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1486 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1487 return false;
1488 }
1489
1490 return true;
1491 }
1492
1493 static void
1494 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1495 const E1000E_RxRing *rxr,
1496 const E1000E_RSSInfo *rss_info)
1497 {
1498 PCIDevice *d = core->owner;
1499 dma_addr_t base;
1500 uint8_t desc[E1000_MAX_RX_DESC_LEN];
1501 size_t desc_size;
1502 size_t desc_offset = 0;
1503 size_t iov_ofs = 0;
1504
1505 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1506 size_t size = net_rx_pkt_get_total_len(pkt);
1507 size_t total_size = size + e1000x_fcs_len(core->mac);
1508 const E1000E_RingInfo *rxi;
1509 size_t ps_hdr_len = 0;
1510 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1511 bool is_first = true;
1512
1513 rxi = rxr->i;
1514
1515 do {
1516 hwaddr ba[MAX_PS_BUFFERS];
1517 e1000e_ba_state bastate = { { 0 } };
1518 bool is_last = false;
1519
1520 desc_size = total_size - desc_offset;
1521
1522 if (desc_size > core->rx_desc_buf_size) {
1523 desc_size = core->rx_desc_buf_size;
1524 }
1525
1526 if (e1000e_ring_empty(core, rxi)) {
1527 return;
1528 }
1529
1530 base = e1000e_ring_head_descr(core, rxi);
1531
1532 pci_dma_read(d, base, &desc, core->rx_desc_len);
1533
1534 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1535
1536 e1000e_read_rx_descr(core, desc, &ba);
1537
1538 if (ba[0]) {
1539 if (desc_offset < size) {
1540 static const uint32_t fcs_pad;
1541 size_t iov_copy;
1542 size_t copy_size = size - desc_offset;
1543 if (copy_size > core->rx_desc_buf_size) {
1544 copy_size = core->rx_desc_buf_size;
1545 }
1546
1547 /* For PS mode copy the packet header first */
1548 if (do_ps) {
1549 if (is_first) {
1550 size_t ps_hdr_copied = 0;
1551 do {
1552 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1553 iov->iov_len - iov_ofs);
1554
1555 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1556 iov->iov_base, iov_copy);
1557
1558 copy_size -= iov_copy;
1559 ps_hdr_copied += iov_copy;
1560
1561 iov_ofs += iov_copy;
1562 if (iov_ofs == iov->iov_len) {
1563 iov++;
1564 iov_ofs = 0;
1565 }
1566 } while (ps_hdr_copied < ps_hdr_len);
1567
1568 is_first = false;
1569 } else {
1570 /* Leave buffer 0 of each descriptor except first */
1571 /* empty as per spec 7.1.5.1 */
1572 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1573 NULL, 0);
1574 }
1575 }
1576
1577 /* Copy packet payload */
1578 while (copy_size) {
1579 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1580
1581 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1582 iov->iov_base + iov_ofs, iov_copy);
1583
1584 copy_size -= iov_copy;
1585 iov_ofs += iov_copy;
1586 if (iov_ofs == iov->iov_len) {
1587 iov++;
1588 iov_ofs = 0;
1589 }
1590 }
1591
1592 if (desc_offset + desc_size >= total_size) {
1593 /* Simulate FCS checksum presence in the last descriptor */
1594 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1595 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1596 }
1597 }
1598 desc_offset += desc_size;
1599 if (desc_offset >= total_size) {
1600 is_last = true;
1601 }
1602 } else { /* as per intel docs; skip descriptors with null buf addr */
1603 trace_e1000e_rx_null_descriptor();
1604 }
1605
1606 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL,
1607 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1608 pci_dma_write(d, base, &desc, core->rx_desc_len);
1609
1610 e1000e_ring_advance(core, rxi,
1611 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1612
1613 } while (desc_offset < total_size);
1614
1615 e1000e_update_rx_stats(core, size, total_size);
1616 }
1617
1618 static inline void
1619 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1620 {
1621 if (net_rx_pkt_has_virt_hdr(pkt)) {
1622 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1623
1624 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1625 net_rx_pkt_fix_l4_csum(pkt);
1626 }
1627 }
1628 }
1629
1630 ssize_t
1631 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1632 {
1633 static const int maximum_ethernet_hdr_len = (14 + 4);
1634 /* Min. octets in an ethernet frame sans FCS */
1635 static const int min_buf_size = 60;
1636
1637 uint32_t n = 0;
1638 uint8_t min_buf[min_buf_size];
1639 struct iovec min_iov;
1640 uint8_t *filter_buf;
1641 size_t size, orig_size;
1642 size_t iov_ofs = 0;
1643 E1000E_RxRing rxr;
1644 E1000E_RSSInfo rss_info;
1645 size_t total_size;
1646 ssize_t retval;
1647 bool rdmts_hit;
1648
1649 trace_e1000e_rx_receive_iov(iovcnt);
1650
1651 if (!e1000x_hw_rx_enabled(core->mac)) {
1652 return -1;
1653 }
1654
1655 /* Pull virtio header in */
1656 if (core->has_vnet) {
1657 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1658 iov_ofs = sizeof(struct virtio_net_hdr);
1659 }
1660
1661 filter_buf = iov->iov_base + iov_ofs;
1662 orig_size = iov_size(iov, iovcnt);
1663 size = orig_size - iov_ofs;
1664
1665 /* Pad to minimum Ethernet frame length */
1666 if (size < sizeof(min_buf)) {
1667 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1668 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1669 e1000x_inc_reg_if_not_full(core->mac, RUC);
1670 min_iov.iov_base = filter_buf = min_buf;
1671 min_iov.iov_len = size = sizeof(min_buf);
1672 iovcnt = 1;
1673 iov = &min_iov;
1674 iov_ofs = 0;
1675 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1676 /* This is very unlikely, but may happen. */
1677 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1678 filter_buf = min_buf;
1679 }
1680
1681 /* Discard oversized packets if !LPE and !SBP. */
1682 if (e1000x_is_oversized(core->mac, size)) {
1683 return orig_size;
1684 }
1685
1686 net_rx_pkt_set_packet_type(core->rx_pkt,
1687 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1688
1689 if (!e1000e_receive_filter(core, filter_buf, size)) {
1690 trace_e1000e_rx_flt_dropped();
1691 return orig_size;
1692 }
1693
1694 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1695 e1000x_vlan_enabled(core->mac), core->vet);
1696
1697 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1698 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1699
1700 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
1701
1702 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1703 e1000x_fcs_len(core->mac);
1704
1705 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1706 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1707
1708 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1709
1710 retval = orig_size;
1711
1712 /* Perform small receive detection (RSRPD) */
1713 if (total_size < core->mac[RSRPD]) {
1714 n |= E1000_ICS_SRPD;
1715 }
1716
1717 /* Perform ACK receive detection */
1718 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1719 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1720 n |= E1000_ICS_ACK;
1721 }
1722
1723 /* Check if receive descriptor minimum threshold hit */
1724 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1725 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1726
1727 trace_e1000e_rx_written_to_guest(n);
1728 } else {
1729 n |= E1000_ICS_RXO;
1730 retval = 0;
1731
1732 trace_e1000e_rx_not_written_to_guest(n);
1733 }
1734
1735 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1736 trace_e1000e_rx_interrupt_set(n);
1737 e1000e_set_interrupt_cause(core, n);
1738 } else {
1739 trace_e1000e_rx_interrupt_delayed(n);
1740 }
1741
1742 return retval;
1743 }
1744
1745 static inline bool
1746 e1000e_have_autoneg(E1000ECore *core)
1747 {
1748 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN;
1749 }
1750
1751 static void e1000e_update_flowctl_status(E1000ECore *core)
1752 {
1753 if (e1000e_have_autoneg(core) &&
1754 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) {
1755 trace_e1000e_link_autoneg_flowctl(true);
1756 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1757 } else {
1758 trace_e1000e_link_autoneg_flowctl(false);
1759 }
1760 }
1761
1762 static inline void
1763 e1000e_link_down(E1000ECore *core)
1764 {
1765 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1766 e1000e_update_flowctl_status(core);
1767 }
1768
1769 static inline void
1770 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1771 {
1772 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
1773 core->phy[0][PHY_CTRL] = val & ~(0x3f |
1774 MII_CR_RESET |
1775 MII_CR_RESTART_AUTO_NEG);
1776
1777 if ((val & MII_CR_RESTART_AUTO_NEG) &&
1778 e1000e_have_autoneg(core)) {
1779 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1780 }
1781 }
1782
1783 static void
1784 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1785 {
1786 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1787
1788 if (val & BIT(10)) {
1789 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1790 }
1791 }
1792
1793 static void
1794 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1795 {
1796 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1797 }
1798
1799 void
1800 e1000e_core_set_link_status(E1000ECore *core)
1801 {
1802 NetClientState *nc = qemu_get_queue(core->owner_nic);
1803 uint32_t old_status = core->mac[STATUS];
1804
1805 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1806
1807 if (nc->link_down) {
1808 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1809 } else {
1810 if (e1000e_have_autoneg(core) &&
1811 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
1812 e1000x_restart_autoneg(core->mac, core->phy[0],
1813 core->autoneg_timer);
1814 } else {
1815 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1816 e1000e_start_recv(core);
1817 }
1818 }
1819
1820 if (core->mac[STATUS] != old_status) {
1821 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1822 }
1823 }
1824
1825 static void
1826 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1827 {
1828 trace_e1000e_core_ctrl_write(index, val);
1829
1830 /* RST is self clearing */
1831 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1832 core->mac[CTRL_DUP] = core->mac[CTRL];
1833
1834 trace_e1000e_link_set_params(
1835 !!(val & E1000_CTRL_ASDE),
1836 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1837 !!(val & E1000_CTRL_FRCSPD),
1838 !!(val & E1000_CTRL_FRCDPX),
1839 !!(val & E1000_CTRL_RFCE),
1840 !!(val & E1000_CTRL_TFCE));
1841
1842 if (val & E1000_CTRL_RST) {
1843 trace_e1000e_core_ctrl_sw_reset();
1844 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
1845 }
1846
1847 if (val & E1000_CTRL_PHY_RST) {
1848 trace_e1000e_core_ctrl_phy_reset();
1849 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1850 }
1851 }
1852
1853 static void
1854 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1855 {
1856 trace_e1000e_rx_set_rfctl(val);
1857
1858 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1859 trace_e1000e_wrn_iscsi_filtering_not_supported();
1860 }
1861
1862 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1863 trace_e1000e_wrn_nfsw_filtering_not_supported();
1864 }
1865
1866 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1867 trace_e1000e_wrn_nfsr_filtering_not_supported();
1868 }
1869
1870 core->mac[RFCTL] = val;
1871 }
1872
1873 static void
1874 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1875 {
1876 int i;
1877 core->rx_desc_buf_size = 0;
1878
1879 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1880 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1881 }
1882 }
1883
1884 static void
1885 e1000e_parse_rxbufsize(E1000ECore *core)
1886 {
1887 uint32_t rctl = core->mac[RCTL];
1888
1889 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1890
1891 if (rctl & E1000_RCTL_DTYP_MASK) {
1892 uint32_t bsize;
1893
1894 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1895 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1896
1897 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1898 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1899
1900 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1901 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1902
1903 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1904 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1905 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1906 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1907 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1908 } else {
1909 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1910 }
1911
1912 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1913 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1914
1915 e1000e_calc_per_desc_buf_size(core);
1916 }
1917
1918 static void
1919 e1000e_calc_rxdesclen(E1000ECore *core)
1920 {
1921 if (e1000e_rx_use_legacy_descriptor(core)) {
1922 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1923 } else {
1924 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1925 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1926 } else {
1927 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1928 }
1929 }
1930 trace_e1000e_rx_desc_len(core->rx_desc_len);
1931 }
1932
1933 static void
1934 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1935 {
1936 core->mac[RCTL] = val;
1937 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1938
1939 if (val & E1000_RCTL_EN) {
1940 e1000e_parse_rxbufsize(core);
1941 e1000e_calc_rxdesclen(core);
1942 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1943 E1000_RING_DESC_LEN_SHIFT;
1944
1945 e1000e_start_recv(core);
1946 }
1947 }
1948
1949 static
1950 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1951 (E1000ECore *, int, uint16_t) = {
1952 [0] = {
1953 [PHY_CTRL] = e1000e_set_phy_ctrl,
1954 [PHY_PAGE] = e1000e_set_phy_page,
1955 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1956 }
1957 };
1958
1959 static inline void
1960 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
1961 {
1962 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1963 core->mac[IMS] &= ~bits;
1964 }
1965
1966 static inline bool
1967 e1000e_postpone_interrupt(bool *interrupt_pending,
1968 E1000IntrDelayTimer *timer)
1969 {
1970 if (timer->running) {
1971 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1972
1973 *interrupt_pending = true;
1974 return true;
1975 }
1976
1977 if (timer->core->mac[timer->delay_reg] != 0) {
1978 e1000e_intrmgr_rearm_timer(timer);
1979 }
1980
1981 return false;
1982 }
1983
1984 static inline bool
1985 e1000e_itr_should_postpone(E1000ECore *core)
1986 {
1987 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr);
1988 }
1989
1990 static inline bool
1991 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
1992 {
1993 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx],
1994 &core->eitr[idx]);
1995 }
1996
1997 static void
1998 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
1999 {
2000 uint32_t effective_eiac;
2001
2002 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2003 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2004 if (vec < E1000E_MSIX_VEC_NUM) {
2005 if (!e1000e_eitr_should_postpone(core, vec)) {
2006 trace_e1000e_irq_msix_notify_vec(vec);
2007 msix_notify(core->owner, vec);
2008 }
2009 } else {
2010 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2011 }
2012 } else {
2013 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2014 }
2015
2016 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2017 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2018 core->mac[IAM] &= ~cause;
2019 }
2020
2021 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2022
2023 effective_eiac = core->mac[EIAC] & cause;
2024
2025 core->mac[ICR] &= ~effective_eiac;
2026 core->msi_causes_pending &= ~effective_eiac;
2027
2028 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2029 core->mac[IMS] &= ~effective_eiac;
2030 }
2031 }
2032
2033 static void
2034 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2035 {
2036 if (causes & E1000_ICR_RXQ0) {
2037 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2038 E1000_IVAR_RXQ0(core->mac[IVAR]));
2039 }
2040
2041 if (causes & E1000_ICR_RXQ1) {
2042 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2043 E1000_IVAR_RXQ1(core->mac[IVAR]));
2044 }
2045
2046 if (causes & E1000_ICR_TXQ0) {
2047 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2048 E1000_IVAR_TXQ0(core->mac[IVAR]));
2049 }
2050
2051 if (causes & E1000_ICR_TXQ1) {
2052 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2053 E1000_IVAR_TXQ1(core->mac[IVAR]));
2054 }
2055
2056 if (causes & E1000_ICR_OTHER) {
2057 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2058 E1000_IVAR_OTHER(core->mac[IVAR]));
2059 }
2060 }
2061
2062 static void
2063 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2064 {
2065 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2066 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2067 if (vec < E1000E_MSIX_VEC_NUM) {
2068 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2069 msix_clr_pending(core->owner, vec);
2070 } else {
2071 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2072 }
2073 } else {
2074 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2075 }
2076 }
2077
2078 static void
2079 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2080 {
2081 if (causes & E1000_ICR_RXQ0) {
2082 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2083 E1000_IVAR_RXQ0(core->mac[IVAR]));
2084 }
2085
2086 if (causes & E1000_ICR_RXQ1) {
2087 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2088 E1000_IVAR_RXQ1(core->mac[IVAR]));
2089 }
2090
2091 if (causes & E1000_ICR_TXQ0) {
2092 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2093 E1000_IVAR_TXQ0(core->mac[IVAR]));
2094 }
2095
2096 if (causes & E1000_ICR_TXQ1) {
2097 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2098 E1000_IVAR_TXQ1(core->mac[IVAR]));
2099 }
2100
2101 if (causes & E1000_ICR_OTHER) {
2102 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2103 E1000_IVAR_OTHER(core->mac[IVAR]));
2104 }
2105 }
2106
2107 static inline void
2108 e1000e_fix_icr_asserted(E1000ECore *core)
2109 {
2110 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2111 if (core->mac[ICR]) {
2112 core->mac[ICR] |= E1000_ICR_ASSERTED;
2113 }
2114
2115 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2116 }
2117
2118 static void
2119 e1000e_send_msi(E1000ECore *core, bool msix)
2120 {
2121 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2122
2123 core->msi_causes_pending &= causes;
2124 causes ^= core->msi_causes_pending;
2125 if (causes == 0) {
2126 return;
2127 }
2128 core->msi_causes_pending |= causes;
2129
2130 if (msix) {
2131 e1000e_msix_notify(core, causes);
2132 } else {
2133 if (!e1000e_itr_should_postpone(core)) {
2134 trace_e1000e_irq_msi_notify(causes);
2135 msi_notify(core->owner, 0);
2136 }
2137 }
2138 }
2139
2140 static void
2141 e1000e_update_interrupt_state(E1000ECore *core)
2142 {
2143 bool interrupts_pending;
2144 bool is_msix = msix_enabled(core->owner);
2145
2146 /* Set ICR[OTHER] for MSI-X */
2147 if (is_msix) {
2148 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2149 core->mac[ICR] |= E1000_ICR_OTHER;
2150 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2151 }
2152 }
2153
2154 e1000e_fix_icr_asserted(core);
2155
2156 /*
2157 * Make sure ICR and ICS registers have the same value.
2158 * The spec says that the ICS register is write-only. However in practice,
2159 * on real hardware ICS is readable, and for reads it has the same value as
2160 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2161 *
2162 * The VxWorks PRO/1000 driver uses this behaviour.
2163 */
2164 core->mac[ICS] = core->mac[ICR];
2165
2166 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2167 if (!interrupts_pending) {
2168 core->msi_causes_pending = 0;
2169 }
2170
2171 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2172 core->mac[ICR], core->mac[IMS]);
2173
2174 if (is_msix || msi_enabled(core->owner)) {
2175 if (interrupts_pending) {
2176 e1000e_send_msi(core, is_msix);
2177 }
2178 } else {
2179 if (interrupts_pending) {
2180 if (!e1000e_itr_should_postpone(core)) {
2181 e1000e_raise_legacy_irq(core);
2182 }
2183 } else {
2184 e1000e_lower_legacy_irq(core);
2185 }
2186 }
2187 }
2188
2189 static void
2190 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2191 {
2192 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2193
2194 val |= e1000e_intmgr_collect_delayed_causes(core);
2195 core->mac[ICR] |= val;
2196
2197 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2198
2199 e1000e_update_interrupt_state(core);
2200 }
2201
2202 static inline void
2203 e1000e_autoneg_timer(void *opaque)
2204 {
2205 E1000ECore *core = opaque;
2206 if (!qemu_get_queue(core->owner_nic)->link_down) {
2207 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2208 e1000e_start_recv(core);
2209
2210 e1000e_update_flowctl_status(core);
2211 /* signal link status change to the guest */
2212 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2213 }
2214 }
2215
2216 static inline uint16_t
2217 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2218 {
2219 uint16_t index = (addr & 0x1ffff) >> 2;
2220 return index + (mac_reg_access[index] & 0xfffe);
2221 }
2222
2223 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2224 [0] = {
2225 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,
2226 [PHY_STATUS] = PHY_ANYPAGE | PHY_R,
2227 [PHY_ID1] = PHY_ANYPAGE | PHY_R,
2228 [PHY_ID2] = PHY_ANYPAGE | PHY_R,
2229 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW,
2230 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R,
2231 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R,
2232 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW,
2233 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R,
2234 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW,
2235 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R,
2236 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R,
2237 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2238
2239 [PHY_COPPER_CTRL1] = PHY_RW,
2240 [PHY_COPPER_STAT1] = PHY_R,
2241 [PHY_COPPER_CTRL3] = PHY_RW,
2242 [PHY_RX_ERR_CNTR] = PHY_R,
2243 [PHY_OEM_BITS] = PHY_RW,
2244 [PHY_BIAS_1] = PHY_RW,
2245 [PHY_BIAS_2] = PHY_RW,
2246 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2247 [PHY_COPPER_STAT2] = PHY_R,
2248 [PHY_COPPER_CTRL2] = PHY_RW
2249 },
2250 [2] = {
2251 [PHY_MAC_CTRL1] = PHY_RW,
2252 [PHY_MAC_INT_ENABLE] = PHY_RW,
2253 [PHY_MAC_STAT] = PHY_R,
2254 [PHY_MAC_CTRL2] = PHY_RW
2255 },
2256 [3] = {
2257 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2258 [PHY_LED_03_POL_CTRL] = PHY_RW,
2259 [PHY_LED_TIMER_CTRL] = PHY_RW,
2260 [PHY_LED_45_CTRL] = PHY_RW
2261 },
2262 [5] = {
2263 [PHY_1000T_SKEW] = PHY_R,
2264 [PHY_1000T_SWAP] = PHY_R
2265 },
2266 [6] = {
2267 [PHY_CRC_COUNTERS] = PHY_R
2268 }
2269 };
2270
2271 static bool
2272 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2273 char cap, uint8_t *page)
2274 {
2275 *page =
2276 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2277 : core->phy[0][PHY_PAGE];
2278
2279 if (*page >= E1000E_PHY_PAGES) {
2280 return false;
2281 }
2282
2283 return e1000e_phy_regcap[*page][addr] & cap;
2284 }
2285
2286 static void
2287 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2288 uint32_t addr, uint16_t data)
2289 {
2290 assert(page < E1000E_PHY_PAGES);
2291 assert(addr < E1000E_PHY_PAGE_SIZE);
2292
2293 if (e1000e_phyreg_writeops[page][addr]) {
2294 e1000e_phyreg_writeops[page][addr](core, addr, data);
2295 } else {
2296 core->phy[page][addr] = data;
2297 }
2298 }
2299
2300 static void
2301 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2302 {
2303 uint32_t data = val & E1000_MDIC_DATA_MASK;
2304 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2305 uint8_t page;
2306
2307 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2308 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2309 } else if (val & E1000_MDIC_OP_READ) {
2310 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2311 trace_e1000e_core_mdic_read_unhandled(page, addr);
2312 val |= E1000_MDIC_ERROR;
2313 } else {
2314 val = (val ^ data) | core->phy[page][addr];
2315 trace_e1000e_core_mdic_read(page, addr, val);
2316 }
2317 } else if (val & E1000_MDIC_OP_WRITE) {
2318 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2319 trace_e1000e_core_mdic_write_unhandled(page, addr);
2320 val |= E1000_MDIC_ERROR;
2321 } else {
2322 trace_e1000e_core_mdic_write(page, addr, data);
2323 e1000e_phy_reg_write(core, page, addr, data);
2324 }
2325 }
2326 core->mac[MDIC] = val | E1000_MDIC_READY;
2327
2328 if (val & E1000_MDIC_INT_EN) {
2329 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2330 }
2331 }
2332
2333 static void
2334 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2335 {
2336 core->mac[index] = val & 0xffff;
2337 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2338 e1000e_start_recv(core);
2339 }
2340
2341 static void
2342 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2343 {
2344 if ((val & E1000_STATUS_PHYRA) == 0) {
2345 core->mac[index] &= ~E1000_STATUS_PHYRA;
2346 }
2347 }
2348
2349 static void
2350 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2351 {
2352 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2353 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2354
2355 /* Zero self-clearing bits */
2356 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2357 core->mac[CTRL_EXT] = val;
2358 }
2359
2360 static void
2361 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2362 {
2363 int i;
2364
2365 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2366
2367 if (!msix_enabled(core->owner)) {
2368 return;
2369 }
2370
2371 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2372 if (core->mac[PBACLR] & BIT(i)) {
2373 msix_clr_pending(core->owner, i);
2374 }
2375 }
2376 }
2377
2378 static void
2379 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2380 {
2381 core->mac[FCRTH] = val & 0xFFF8;
2382 }
2383
2384 static void
2385 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2386 {
2387 core->mac[FCRTL] = val & 0x8000FFF8;
2388 }
2389
2390 static inline void
2391 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
2392 {
2393 core->mac[index] = val & 0xffff;
2394 }
2395
2396 static void
2397 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
2398 {
2399 core->mac[index] = val & 0xfff;
2400 }
2401
2402 static void
2403 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2404 {
2405 core->mac[VET] = val & 0xffff;
2406 core->vet = le16_to_cpu(core->mac[VET]);
2407 trace_e1000e_vlan_vet(core->vet);
2408 }
2409
2410 static void
2411 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2412 {
2413 core->mac[index] = val & E1000_XDLEN_MASK;
2414 }
2415
2416 static void
2417 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2418 {
2419 core->mac[index] = val & E1000_XDBAL_MASK;
2420 }
2421
2422 static void
2423 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2424 {
2425 E1000E_TxRing txr;
2426 core->mac[index] = val;
2427
2428 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2429 e1000e_tx_ring_init(core, &txr, 0);
2430 e1000e_start_xmit(core, &txr);
2431 }
2432
2433 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2434 e1000e_tx_ring_init(core, &txr, 1);
2435 e1000e_start_xmit(core, &txr);
2436 }
2437 }
2438
2439 static void
2440 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2441 {
2442 E1000E_TxRing txr;
2443 int qidx = e1000e_mq_queue_idx(TDT, index);
2444 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2445
2446 core->mac[index] = val & 0xffff;
2447
2448 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2449 e1000e_tx_ring_init(core, &txr, qidx);
2450 e1000e_start_xmit(core, &txr);
2451 }
2452 }
2453
2454 static void
2455 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2456 {
2457 trace_e1000e_irq_write_ics(val);
2458 e1000e_set_interrupt_cause(core, val);
2459 }
2460
2461 static void
2462 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2463 {
2464 uint32_t icr = 0;
2465 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2466 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2467 trace_e1000e_irq_icr_process_iame();
2468 e1000e_clear_ims_bits(core, core->mac[IAM]);
2469 }
2470
2471 icr = core->mac[ICR] & ~val;
2472 /* Windows driver expects that the "receive overrun" bit and other
2473 * ones to be cleared when the "Other" bit (#24) is cleared.
2474 */
2475 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2476 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2477 core->mac[ICR] = icr;
2478 e1000e_update_interrupt_state(core);
2479 }
2480
2481 static void
2482 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2483 {
2484 trace_e1000e_irq_ims_clear_set_imc(val);
2485 e1000e_clear_ims_bits(core, val);
2486 e1000e_update_interrupt_state(core);
2487 }
2488
2489 static void
2490 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2491 {
2492 static const uint32_t ims_ext_mask =
2493 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2494 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2495 E1000_IMS_OTHER;
2496
2497 static const uint32_t ims_valid_mask =
2498 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2499 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2500 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2501 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2502 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2503 E1000_IMS_OTHER;
2504
2505 uint32_t valid_val = val & ims_valid_mask;
2506
2507 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2508 core->mac[IMS] |= valid_val;
2509
2510 if ((valid_val & ims_ext_mask) &&
2511 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2512 msix_enabled(core->owner)) {
2513 e1000e_msix_clear(core, valid_val);
2514 }
2515
2516 if ((valid_val == ims_valid_mask) &&
2517 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2518 trace_e1000e_irq_fire_all_timers(val);
2519 e1000e_intrmgr_fire_all_timers(core);
2520 }
2521
2522 e1000e_update_interrupt_state(core);
2523 }
2524
2525 static void
2526 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2527 {
2528 e1000e_set_16bit(core, index, val);
2529
2530 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2531 trace_e1000e_irq_rdtr_fpd_running();
2532 e1000e_intrmgr_fire_delayed_interrupts(core);
2533 } else {
2534 trace_e1000e_irq_rdtr_fpd_not_running();
2535 }
2536 }
2537
2538 static void
2539 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2540 {
2541 e1000e_set_16bit(core, index, val);
2542
2543 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2544 trace_e1000e_irq_tidv_fpd_running();
2545 e1000e_intrmgr_fire_delayed_interrupts(core);
2546 } else {
2547 trace_e1000e_irq_tidv_fpd_not_running();
2548 }
2549 }
2550
2551 static uint32_t
2552 e1000e_mac_readreg(E1000ECore *core, int index)
2553 {
2554 return core->mac[index];
2555 }
2556
2557 static uint32_t
2558 e1000e_mac_ics_read(E1000ECore *core, int index)
2559 {
2560 trace_e1000e_irq_read_ics(core->mac[ICS]);
2561 return core->mac[ICS];
2562 }
2563
2564 static uint32_t
2565 e1000e_mac_ims_read(E1000ECore *core, int index)
2566 {
2567 trace_e1000e_irq_read_ims(core->mac[IMS]);
2568 return core->mac[IMS];
2569 }
2570
2571 #define E1000E_LOW_BITS_READ_FUNC(num) \
2572 static uint32_t \
2573 e1000e_mac_low##num##_read(E1000ECore *core, int index) \
2574 { \
2575 return core->mac[index] & (BIT(num) - 1); \
2576 } \
2577
2578 #define E1000E_LOW_BITS_READ(num) \
2579 e1000e_mac_low##num##_read
2580
2581 E1000E_LOW_BITS_READ_FUNC(4);
2582 E1000E_LOW_BITS_READ_FUNC(6);
2583 E1000E_LOW_BITS_READ_FUNC(11);
2584 E1000E_LOW_BITS_READ_FUNC(13);
2585 E1000E_LOW_BITS_READ_FUNC(16);
2586
2587 static uint32_t
2588 e1000e_mac_swsm_read(E1000ECore *core, int index)
2589 {
2590 uint32_t val = core->mac[SWSM];
2591 core->mac[SWSM] = val | 1;
2592 return val;
2593 }
2594
2595 static uint32_t
2596 e1000e_mac_itr_read(E1000ECore *core, int index)
2597 {
2598 return core->itr_guest_value;
2599 }
2600
2601 static uint32_t
2602 e1000e_mac_eitr_read(E1000ECore *core, int index)
2603 {
2604 return core->eitr_guest_value[index - EITR];
2605 }
2606
2607 static uint32_t
2608 e1000e_mac_icr_read(E1000ECore *core, int index)
2609 {
2610 uint32_t ret = core->mac[ICR];
2611 trace_e1000e_irq_icr_read_entry(ret);
2612
2613 if (core->mac[IMS] == 0) {
2614 trace_e1000e_irq_icr_clear_zero_ims();
2615 core->mac[ICR] = 0;
2616 }
2617
2618 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2619 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2620 trace_e1000e_irq_icr_clear_iame();
2621 core->mac[ICR] = 0;
2622 trace_e1000e_irq_icr_process_iame();
2623 e1000e_clear_ims_bits(core, core->mac[IAM]);
2624 }
2625
2626 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2627 e1000e_update_interrupt_state(core);
2628 return ret;
2629 }
2630
2631 static uint32_t
2632 e1000e_mac_read_clr4(E1000ECore *core, int index)
2633 {
2634 uint32_t ret = core->mac[index];
2635
2636 core->mac[index] = 0;
2637 return ret;
2638 }
2639
2640 static uint32_t
2641 e1000e_mac_read_clr8(E1000ECore *core, int index)
2642 {
2643 uint32_t ret = core->mac[index];
2644
2645 core->mac[index] = 0;
2646 core->mac[index - 1] = 0;
2647 return ret;
2648 }
2649
2650 static uint32_t
2651 e1000e_get_ctrl(E1000ECore *core, int index)
2652 {
2653 uint32_t val = core->mac[CTRL];
2654
2655 trace_e1000e_link_read_params(
2656 !!(val & E1000_CTRL_ASDE),
2657 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2658 !!(val & E1000_CTRL_FRCSPD),
2659 !!(val & E1000_CTRL_FRCDPX),
2660 !!(val & E1000_CTRL_RFCE),
2661 !!(val & E1000_CTRL_TFCE));
2662
2663 return val;
2664 }
2665
2666 static uint32_t
2667 e1000e_get_status(E1000ECore *core, int index)
2668 {
2669 uint32_t res = core->mac[STATUS];
2670
2671 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2672 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2673 }
2674
2675 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2676 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2677 } else {
2678 res |= E1000_STATUS_FD;
2679 }
2680
2681 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2682 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2683 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2684 case E1000_CTRL_SPD_10:
2685 res |= E1000_STATUS_SPEED_10;
2686 break;
2687 case E1000_CTRL_SPD_100:
2688 res |= E1000_STATUS_SPEED_100;
2689 break;
2690 case E1000_CTRL_SPD_1000:
2691 default:
2692 res |= E1000_STATUS_SPEED_1000;
2693 break;
2694 }
2695 } else {
2696 res |= E1000_STATUS_SPEED_1000;
2697 }
2698
2699 trace_e1000e_link_status(
2700 !!(res & E1000_STATUS_LU),
2701 !!(res & E1000_STATUS_FD),
2702 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2703 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2704
2705 return res;
2706 }
2707
2708 static uint32_t
2709 e1000e_get_tarc(E1000ECore *core, int index)
2710 {
2711 return core->mac[index] & ((BIT(11) - 1) |
2712 BIT(27) |
2713 BIT(28) |
2714 BIT(29) |
2715 BIT(30));
2716 }
2717
2718 static void
2719 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2720 {
2721 core->mac[index] = val;
2722 }
2723
2724 static void
2725 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2726 {
2727 uint32_t macaddr[2];
2728
2729 core->mac[index] = val;
2730
2731 macaddr[0] = cpu_to_le32(core->mac[RA]);
2732 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2733 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2734 (uint8_t *) macaddr);
2735
2736 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2737 }
2738
2739 static void
2740 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2741 {
2742 static const uint32_t ro_bits = E1000_EECD_PRES |
2743 E1000_EECD_AUTO_RD |
2744 E1000_EECD_SIZE_EX_MASK;
2745
2746 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2747 }
2748
2749 static void
2750 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2751 {
2752 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2753 uint32_t flags = 0;
2754 uint32_t data = 0;
2755
2756 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2757 data = core->eeprom[addr];
2758 flags = E1000_EERW_DONE;
2759 }
2760
2761 core->mac[EERD] = flags |
2762 (addr << E1000_EERW_ADDR_SHIFT) |
2763 (data << E1000_EERW_DATA_SHIFT);
2764 }
2765
2766 static void
2767 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2768 {
2769 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2770 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2771 uint32_t flags = 0;
2772
2773 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2774 core->eeprom[addr] = data;
2775 flags = E1000_EERW_DONE;
2776 }
2777
2778 core->mac[EERD] = flags |
2779 (addr << E1000_EERW_ADDR_SHIFT) |
2780 (data << E1000_EERW_DATA_SHIFT);
2781 }
2782
2783 static void
2784 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2785 {
2786 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2787 }
2788
2789 static void
2790 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2791 {
2792 uint32_t interval = val & 0xffff;
2793
2794 trace_e1000e_irq_itr_set(val);
2795
2796 core->itr_guest_value = interval;
2797 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2798 }
2799
2800 static void
2801 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2802 {
2803 uint32_t interval = val & 0xffff;
2804 uint32_t eitr_num = index - EITR;
2805
2806 trace_e1000e_irq_eitr_set(eitr_num, val);
2807
2808 core->eitr_guest_value[eitr_num] = interval;
2809 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2810 }
2811
2812 static void
2813 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2814 {
2815 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2816 hw_error("e1000e: PSRCTL.BSIZE0 cannot be zero");
2817 }
2818
2819 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2820 hw_error("e1000e: PSRCTL.BSIZE1 cannot be zero");
2821 }
2822
2823 core->mac[PSRCTL] = val;
2824 }
2825
2826 static void
2827 e1000e_update_rx_offloads(E1000ECore *core)
2828 {
2829 int cso_state = e1000e_rx_l4_cso_enabled(core);
2830
2831 trace_e1000e_rx_set_cso(cso_state);
2832
2833 if (core->has_vnet) {
2834 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2835 cso_state, 0, 0, 0, 0);
2836 }
2837 }
2838
2839 static void
2840 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2841 {
2842 core->mac[RXCSUM] = val;
2843 e1000e_update_rx_offloads(core);
2844 }
2845
2846 static void
2847 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2848 {
2849 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2850 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2851 }
2852
2853 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2854 static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = {
2855 e1000e_getreg(PBA),
2856 e1000e_getreg(WUFC),
2857 e1000e_getreg(MANC),
2858 e1000e_getreg(TOTL),
2859 e1000e_getreg(RDT0),
2860 e1000e_getreg(RDBAH0),
2861 e1000e_getreg(TDBAL1),
2862 e1000e_getreg(RDLEN0),
2863 e1000e_getreg(RDH1),
2864 e1000e_getreg(LATECOL),
2865 e1000e_getreg(SEQEC),
2866 e1000e_getreg(XONTXC),
2867 e1000e_getreg(WUS),
2868 e1000e_getreg(GORCL),
2869 e1000e_getreg(MGTPRC),
2870 e1000e_getreg(EERD),
2871 e1000e_getreg(EIAC),
2872 e1000e_getreg(PSRCTL),
2873 e1000e_getreg(MANC2H),
2874 e1000e_getreg(RXCSUM),
2875 e1000e_getreg(GSCL_3),
2876 e1000e_getreg(GSCN_2),
2877 e1000e_getreg(RSRPD),
2878 e1000e_getreg(RDBAL1),
2879 e1000e_getreg(FCAH),
2880 e1000e_getreg(FCRTH),
2881 e1000e_getreg(FLOP),
2882 e1000e_getreg(FLASHT),
2883 e1000e_getreg(RXSTMPH),
2884 e1000e_getreg(TXSTMPL),
2885 e1000e_getreg(TIMADJL),
2886 e1000e_getreg(TXDCTL),
2887 e1000e_getreg(RDH0),
2888 e1000e_getreg(TDT1),
2889 e1000e_getreg(TNCRS),
2890 e1000e_getreg(RJC),
2891 e1000e_getreg(IAM),
2892 e1000e_getreg(GSCL_2),
2893 e1000e_getreg(RDBAH1),
2894 e1000e_getreg(FLSWDATA),
2895 e1000e_getreg(RXSATRH),
2896 e1000e_getreg(TIPG),
2897 e1000e_getreg(FLMNGCTL),
2898 e1000e_getreg(FLMNGCNT),
2899 e1000e_getreg(TSYNCTXCTL),
2900 e1000e_getreg(EXTCNF_SIZE),
2901 e1000e_getreg(EXTCNF_CTRL),
2902 e1000e_getreg(EEMNGDATA),
2903 e1000e_getreg(CTRL_EXT),
2904 e1000e_getreg(SYSTIMH),
2905 e1000e_getreg(EEMNGCTL),
2906 e1000e_getreg(FLMNGDATA),
2907 e1000e_getreg(TSYNCRXCTL),
2908 e1000e_getreg(TDH),
2909 e1000e_getreg(LEDCTL),
2910 e1000e_getreg(STATUS),
2911 e1000e_getreg(TCTL),
2912 e1000e_getreg(TDBAL),
2913 e1000e_getreg(TDLEN),
2914 e1000e_getreg(TDH1),
2915 e1000e_getreg(RADV),
2916 e1000e_getreg(ECOL),
2917 e1000e_getreg(DC),
2918 e1000e_getreg(RLEC),
2919 e1000e_getreg(XOFFTXC),
2920 e1000e_getreg(RFC),
2921 e1000e_getreg(RNBC),
2922 e1000e_getreg(MGTPTC),
2923 e1000e_getreg(TIMINCA),
2924 e1000e_getreg(RXCFGL),
2925 e1000e_getreg(MFUTP01),
2926 e1000e_getreg(FACTPS),
2927 e1000e_getreg(GSCL_1),
2928 e1000e_getreg(GSCN_0),
2929 e1000e_getreg(GCR2),
2930 e1000e_getreg(RDT1),
2931 e1000e_getreg(PBACLR),
2932 e1000e_getreg(FCTTV),
2933 e1000e_getreg(EEWR),
2934 e1000e_getreg(FLSWCTL),
2935 e1000e_getreg(RXDCTL1),
2936 e1000e_getreg(RXSATRL),
2937 e1000e_getreg(SYSTIML),
2938 e1000e_getreg(RXUDP),
2939 e1000e_getreg(TORL),
2940 e1000e_getreg(TDLEN1),
2941 e1000e_getreg(MCC),
2942 e1000e_getreg(WUC),
2943 e1000e_getreg(EECD),
2944 e1000e_getreg(MFUTP23),
2945 e1000e_getreg(RAID),
2946 e1000e_getreg(FCRTV),
2947 e1000e_getreg(TXDCTL1),
2948 e1000e_getreg(RCTL),
2949 e1000e_getreg(TDT),
2950 e1000e_getreg(MDIC),
2951 e1000e_getreg(FCRUC),
2952 e1000e_getreg(VET),
2953 e1000e_getreg(RDBAL0),
2954 e1000e_getreg(TDBAH1),
2955 e1000e_getreg(RDTR),
2956 e1000e_getreg(SCC),
2957 e1000e_getreg(COLC),
2958 e1000e_getreg(CEXTERR),
2959 e1000e_getreg(XOFFRXC),
2960 e1000e_getreg(IPAV),
2961 e1000e_getreg(GOTCL),
2962 e1000e_getreg(MGTPDC),
2963 e1000e_getreg(GCR),
2964 e1000e_getreg(IVAR),
2965 e1000e_getreg(POEMB),
2966 e1000e_getreg(MFVAL),
2967 e1000e_getreg(FUNCTAG),
2968 e1000e_getreg(GSCL_4),
2969 e1000e_getreg(GSCN_3),
2970 e1000e_getreg(MRQC),
2971 e1000e_getreg(RDLEN1),
2972 e1000e_getreg(FCT),
2973 e1000e_getreg(FLA),
2974 e1000e_getreg(FLOL),
2975 e1000e_getreg(RXDCTL),
2976 e1000e_getreg(RXSTMPL),
2977 e1000e_getreg(TXSTMPH),
2978 e1000e_getreg(TIMADJH),
2979 e1000e_getreg(FCRTL),
2980 e1000e_getreg(TDBAH),
2981 e1000e_getreg(TADV),
2982 e1000e_getreg(XONRXC),
2983 e1000e_getreg(TSCTFC),
2984 e1000e_getreg(RFCTL),
2985 e1000e_getreg(GSCN_1),
2986 e1000e_getreg(FCAL),
2987 e1000e_getreg(FLSWCNT),
2988
2989 [TOTH] = e1000e_mac_read_clr8,
2990 [GOTCH] = e1000e_mac_read_clr8,
2991 [PRC64] = e1000e_mac_read_clr4,
2992 [PRC255] = e1000e_mac_read_clr4,
2993 [PRC1023] = e1000e_mac_read_clr4,
2994 [PTC64] = e1000e_mac_read_clr4,
2995 [PTC255] = e1000e_mac_read_clr4,
2996 [PTC1023] = e1000e_mac_read_clr4,
2997 [GPRC] = e1000e_mac_read_clr4,
2998 [TPT] = e1000e_mac_read_clr4,
2999 [RUC] = e1000e_mac_read_clr4,
3000 [BPRC] = e1000e_mac_read_clr4,
3001 [MPTC] = e1000e_mac_read_clr4,
3002 [IAC] = e1000e_mac_read_clr4,
3003 [ICR] = e1000e_mac_icr_read,
3004 [RDFH] = E1000E_LOW_BITS_READ(13),
3005 [RDFHS] = E1000E_LOW_BITS_READ(13),
3006 [RDFPC] = E1000E_LOW_BITS_READ(13),
3007 [TDFH] = E1000E_LOW_BITS_READ(13),
3008 [TDFHS] = E1000E_LOW_BITS_READ(13),
3009 [STATUS] = e1000e_get_status,
3010 [TARC0] = e1000e_get_tarc,
3011 [PBS] = E1000E_LOW_BITS_READ(6),
3012 [ICS] = e1000e_mac_ics_read,
3013 [AIT] = E1000E_LOW_BITS_READ(16),
3014 [TORH] = e1000e_mac_read_clr8,
3015 [GORCH] = e1000e_mac_read_clr8,
3016 [PRC127] = e1000e_mac_read_clr4,
3017 [PRC511] = e1000e_mac_read_clr4,
3018 [PRC1522] = e1000e_mac_read_clr4,
3019 [PTC127] = e1000e_mac_read_clr4,
3020 [PTC511] = e1000e_mac_read_clr4,
3021 [PTC1522] = e1000e_mac_read_clr4,
3022 [GPTC] = e1000e_mac_read_clr4,
3023 [TPR] = e1000e_mac_read_clr4,
3024 [ROC] = e1000e_mac_read_clr4,
3025 [MPRC] = e1000e_mac_read_clr4,
3026 [BPTC] = e1000e_mac_read_clr4,
3027 [TSCTC] = e1000e_mac_read_clr4,
3028 [ITR] = e1000e_mac_itr_read,
3029 [RDFT] = E1000E_LOW_BITS_READ(13),
3030 [RDFTS] = E1000E_LOW_BITS_READ(13),
3031 [TDFPC] = E1000E_LOW_BITS_READ(13),
3032 [TDFT] = E1000E_LOW_BITS_READ(13),
3033 [TDFTS] = E1000E_LOW_BITS_READ(13),
3034 [CTRL] = e1000e_get_ctrl,
3035 [TARC1] = e1000e_get_tarc,
3036 [SWSM] = e1000e_mac_swsm_read,
3037 [IMS] = e1000e_mac_ims_read,
3038
3039 [CRCERRS ... MPC] = e1000e_mac_readreg,
3040 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3041 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3042 [RA ... RA + 31] = e1000e_mac_readreg,
3043 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3044 [MTA ... MTA + 127] = e1000e_mac_readreg,
3045 [VFTA ... VFTA + 127] = e1000e_mac_readreg,
3046 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
3047 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3048 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3049 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
3050 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3051 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3052 [RETA ... RETA + 31] = e1000e_mac_readreg,
3053 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3054 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3055 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3056 };
3057 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3058
3059 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3060 static void (*e1000e_macreg_writeops[])(E1000ECore *, int, uint32_t) = {
3061 e1000e_putreg(PBA),
3062 e1000e_putreg(SWSM),
3063 e1000e_putreg(WUFC),
3064 e1000e_putreg(RDBAH1),
3065 e1000e_putreg(TDBAH),
3066 e1000e_putreg(TXDCTL),
3067 e1000e_putreg(RDBAH0),
3068 e1000e_putreg(LEDCTL),
3069 e1000e_putreg(FCAL),
3070 e1000e_putreg(FCRUC),
3071 e1000e_putreg(AIT),
3072 e1000e_putreg(TDFH),
3073 e1000e_putreg(TDFT),
3074 e1000e_putreg(TDFHS),
3075 e1000e_putreg(TDFTS),
3076 e1000e_putreg(TDFPC),
3077 e1000e_putreg(WUC),
3078 e1000e_putreg(WUS),
3079 e1000e_putreg(RDFH),
3080 e1000e_putreg(RDFT),
3081 e1000e_putreg(RDFHS),
3082 e1000e_putreg(RDFTS),
3083 e1000e_putreg(RDFPC),
3084 e1000e_putreg(IPAV),
3085 e1000e_putreg(TDBAH1),
3086 e1000e_putreg(TIMINCA),
3087 e1000e_putreg(IAM),
3088 e1000e_putreg(EIAC),
3089 e1000e_putreg(IVAR),
3090 e1000e_putreg(TARC0),
3091 e1000e_putreg(TARC1),
3092 e1000e_putreg(FLSWDATA),
3093 e1000e_putreg(POEMB),
3094 e1000e_putreg(PBS),
3095 e1000e_putreg(MFUTP01),
3096 e1000e_putreg(MFUTP23),
3097 e1000e_putreg(MANC),
3098 e1000e_putreg(MANC2H),
3099 e1000e_putreg(MFVAL),
3100 e1000e_putreg(EXTCNF_CTRL),
3101 e1000e_putreg(FACTPS),
3102 e1000e_putreg(FUNCTAG),
3103 e1000e_putreg(GSCL_1),
3104 e1000e_putreg(GSCL_2),
3105 e1000e_putreg(GSCL_3),
3106 e1000e_putreg(GSCL_4),
3107 e1000e_putreg(GSCN_0),
3108 e1000e_putreg(GSCN_1),
3109 e1000e_putreg(GSCN_2),
3110 e1000e_putreg(GSCN_3),
3111 e1000e_putreg(GCR2),
3112 e1000e_putreg(MRQC),
3113 e1000e_putreg(FLOP),
3114 e1000e_putreg(FLOL),
3115 e1000e_putreg(FLSWCTL),
3116 e1000e_putreg(FLSWCNT),
3117 e1000e_putreg(FLA),
3118 e1000e_putreg(RXDCTL1),
3119 e1000e_putreg(TXDCTL1),
3120 e1000e_putreg(TIPG),
3121 e1000e_putreg(RXSTMPH),
3122 e1000e_putreg(RXSTMPL),
3123 e1000e_putreg(RXSATRL),
3124 e1000e_putreg(RXSATRH),
3125 e1000e_putreg(TXSTMPL),
3126 e1000e_putreg(TXSTMPH),
3127 e1000e_putreg(SYSTIML),
3128 e1000e_putreg(SYSTIMH),
3129 e1000e_putreg(TIMADJL),
3130 e1000e_putreg(TIMADJH),
3131 e1000e_putreg(RXUDP),
3132 e1000e_putreg(RXCFGL),
3133 e1000e_putreg(TSYNCRXCTL),
3134 e1000e_putreg(TSYNCTXCTL),
3135 e1000e_putreg(FLSWDATA),
3136 e1000e_putreg(EXTCNF_SIZE),
3137 e1000e_putreg(EEMNGCTL),
3138 e1000e_putreg(RA),
3139
3140 [TDH1] = e1000e_set_16bit,
3141 [TDT1] = e1000e_set_tdt,
3142 [TCTL] = e1000e_set_tctl,
3143 [TDT] = e1000e_set_tdt,
3144 [MDIC] = e1000e_set_mdic,
3145 [ICS] = e1000e_set_ics,
3146 [TDH] = e1000e_set_16bit,
3147 [RDH0] = e1000e_set_16bit,
3148 [RDT0] = e1000e_set_rdt,
3149 [IMC] = e1000e_set_imc,
3150 [IMS] = e1000e_set_ims,
3151 [ICR] = e1000e_set_icr,
3152 [EECD] = e1000e_set_eecd,
3153 [RCTL] = e1000e_set_rx_control,
3154 [CTRL] = e1000e_set_ctrl,
3155 [RDTR] = e1000e_set_rdtr,
3156 [RADV] = e1000e_set_16bit,
3157 [TADV] = e1000e_set_16bit,
3158 [ITR] = e1000e_set_itr,
3159 [EERD] = e1000e_set_eerd,
3160 [GCR] = e1000e_set_gcr,
3161 [PSRCTL] = e1000e_set_psrctl,
3162 [RXCSUM] = e1000e_set_rxcsum,
3163 [RAID] = e1000e_set_16bit,
3164 [RSRPD] = e1000e_set_12bit,
3165 [TIDV] = e1000e_set_tidv,
3166 [TDLEN1] = e1000e_set_dlen,
3167 [TDLEN] = e1000e_set_dlen,
3168 [RDLEN0] = e1000e_set_dlen,
3169 [RDLEN1] = e1000e_set_dlen,
3170 [TDBAL] = e1000e_set_dbal,
3171 [TDBAL1] = e1000e_set_dbal,
3172 [RDBAL0] = e1000e_set_dbal,
3173 [RDBAL1] = e1000e_set_dbal,
3174 [RDH1] = e1000e_set_16bit,
3175 [RDT1] = e1000e_set_rdt,
3176 [STATUS] = e1000e_set_status,
3177 [PBACLR] = e1000e_set_pbaclr,
3178 [CTRL_EXT] = e1000e_set_ctrlext,
3179 [FCAH] = e1000e_set_16bit,
3180 [FCT] = e1000e_set_16bit,
3181 [FCTTV] = e1000e_set_16bit,
3182 [FCRTV] = e1000e_set_16bit,
3183 [FCRTH] = e1000e_set_fcrth,
3184 [FCRTL] = e1000e_set_fcrtl,
3185 [VET] = e1000e_set_vet,
3186 [RXDCTL] = e1000e_set_rxdctl,
3187 [FLASHT] = e1000e_set_16bit,
3188 [EEWR] = e1000e_set_eewr,
3189 [CTRL_DUP] = e1000e_set_ctrl,
3190 [RFCTL] = e1000e_set_rfctl,
3191 [RA + 1] = e1000e_mac_setmacaddr,
3192
3193 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3194 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3195 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3196 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3197 [MTA ... MTA + 127] = e1000e_mac_writereg,
3198 [VFTA ... VFTA + 127] = e1000e_mac_writereg,
3199 [FFMT ... FFMT + 254] = e1000e_mac_writereg,
3200 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3201 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3202 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3203 [FFLT ... FFLT + 10] = e1000e_mac_writereg,
3204 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3205 [RETA ... RETA + 31] = e1000e_mac_writereg,
3206 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3207 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3208 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3209 };
3210 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3211
3212 enum { MAC_ACCESS_PARTIAL = 1 };
3213
3214 /* The array below combines alias offsets of the index values for the
3215 * MAC registers that have aliases, with the indication of not fully
3216 * implemented registers (lowest bit). This combination is possible
3217 * because all of the offsets are even. */
3218 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3219 /* Alias index offsets */
3220 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3221 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3222 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3223 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3224 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3225 [RA_A ... RA_A + 31] = 0x14f0,
3226 [VFTA_A ... VFTA_A + 127] = 0x1400,
3227 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3228 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3229 /* Access options */
3230 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3231 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3232 [RDFPC] = MAC_ACCESS_PARTIAL,
3233 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3234 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3235 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3236 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3237 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3238 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3239 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3240 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3241 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3242 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3243 };
3244
3245 void
3246 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3247 {
3248 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3249
3250 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3251 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3252 trace_e1000e_wrn_regs_write_trivial(index << 2);
3253 }
3254 trace_e1000e_core_write(index << 2, size, val);
3255 e1000e_macreg_writeops[index](core, index, val);
3256 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3257 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3258 } else {
3259 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3260 }
3261 }
3262
3263 uint64_t
3264 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3265 {
3266 uint64_t val;
3267 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3268
3269 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3270 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3271 trace_e1000e_wrn_regs_read_trivial(index << 2);
3272 }
3273 val = e1000e_macreg_readops[index](core, index);
3274 trace_e1000e_core_read(index << 2, size, val);
3275 return val;
3276 } else {
3277 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3278 }
3279 return 0;
3280 }
3281
3282 static inline void
3283 e1000e_autoneg_pause(E1000ECore *core)
3284 {
3285 timer_del(core->autoneg_timer);
3286 }
3287
3288 static void
3289 e1000e_autoneg_resume(E1000ECore *core)
3290 {
3291 if (e1000e_have_autoneg(core) &&
3292 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
3293 qemu_get_queue(core->owner_nic)->link_down = false;
3294 timer_mod(core->autoneg_timer,
3295 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3296 }
3297 }
3298
3299 static void
3300 e1000e_vm_state_change(void *opaque, int running, RunState state)
3301 {
3302 E1000ECore *core = opaque;
3303
3304 if (running) {
3305 trace_e1000e_vm_state_running();
3306 e1000e_intrmgr_resume(core);
3307 e1000e_autoneg_resume(core);
3308 } else {
3309 trace_e1000e_vm_state_stopped();
3310 e1000e_autoneg_pause(core);
3311 e1000e_intrmgr_pause(core);
3312 }
3313 }
3314
3315 void
3316 e1000e_core_pci_realize(E1000ECore *core,
3317 const uint16_t *eeprom_templ,
3318 uint32_t eeprom_size,
3319 const uint8_t *macaddr)
3320 {
3321 int i;
3322
3323 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3324 e1000e_autoneg_timer, core);
3325 e1000e_intrmgr_pci_realize(core);
3326
3327 core->vmstate =
3328 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3329
3330 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3331 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,
3332 E1000E_MAX_TX_FRAGS, core->has_vnet);
3333 }
3334
3335 net_rx_pkt_init(&core->rx_pkt, core->has_vnet);
3336
3337 e1000x_core_prepare_eeprom(core->eeprom,
3338 eeprom_templ,
3339 eeprom_size,
3340 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3341 macaddr);
3342 e1000e_update_rx_offloads(core);
3343 }
3344
3345 void
3346 e1000e_core_pci_uninit(E1000ECore *core)
3347 {
3348 int i;
3349
3350 timer_del(core->autoneg_timer);
3351 timer_free(core->autoneg_timer);
3352
3353 e1000e_intrmgr_pci_unint(core);
3354
3355 qemu_del_vm_change_state_handler(core->vmstate);
3356
3357 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3358 net_tx_pkt_reset(core->tx[i].tx_pkt);
3359 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3360 }
3361
3362 net_rx_pkt_uninit(core->rx_pkt);
3363 }
3364
3365 static const uint16_t
3366 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3367 [0] = {
3368 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
3369 MII_CR_FULL_DUPLEX |
3370 MII_CR_AUTO_NEG_EN,
3371
3372 [PHY_STATUS] = MII_SR_EXTENDED_CAPS |
3373 MII_SR_LINK_STATUS |
3374 MII_SR_AUTONEG_CAPS |
3375 MII_SR_PREAMBLE_SUPPRESS |
3376 MII_SR_EXTENDED_STATUS |
3377 MII_SR_10T_HD_CAPS |
3378 MII_SR_10T_FD_CAPS |
3379 MII_SR_100X_HD_CAPS |
3380 MII_SR_100X_FD_CAPS,
3381
3382 [PHY_ID1] = 0x141,
3383 [PHY_ID2] = E1000_PHY_ID2_82574x,
3384 [PHY_AUTONEG_ADV] = 0xde1,
3385 [PHY_LP_ABILITY] = 0x7e0,
3386 [PHY_AUTONEG_EXP] = BIT(2),
3387 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13),
3388 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11),
3389 [PHY_1000T_STATUS] = 0x3c00,
3390 [PHY_EXT_STATUS] = BIT(12) | BIT(13),
3391
3392 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3393 BIT(12) | BIT(13),
3394 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3395 },
3396 [2] = {
3397 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3398 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3399 },
3400 [3] = {
3401 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3402 }
3403 };
3404
3405 static const uint32_t e1000e_mac_reg_init[] = {
3406 [PBA] = 0x00140014,
3407 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3408 [EXTCNF_CTRL] = BIT(3),
3409 [EEMNGCTL] = BIT(31),
3410 [FLASHT] = 0x2,
3411 [FLSWCTL] = BIT(30) | BIT(31),
3412 [FLOL] = BIT(0),
3413 [RXDCTL] = BIT(16),
3414 [RXDCTL1] = BIT(16),
3415 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3416 [RXCFGL] = 0x88F7,
3417 [RXUDP] = 0x319,
3418 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3419 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3420 E1000_CTRL_ADVD3WUC,
3421 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3422 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3423 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3424 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3425 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3426 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3427 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3428 [EERD] = E1000_EERW_DONE,
3429 [EEWR] = E1000_EERW_DONE,
3430 [GCR] = E1000_L0S_ADJUST |
3431 E1000_L1_ENTRY_LATENCY_MSB |
3432 E1000_L1_ENTRY_LATENCY_LSB,
3433 [TDFH] = 0x600,
3434 [TDFT] = 0x600,
3435 [TDFHS] = 0x600,
3436 [TDFTS] = 0x600,
3437 [POEMB] = 0x30D,
3438 [PBS] = 0x028,
3439 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3440 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3441 [SWSM] = 1,
3442 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3443 [ITR] = E1000E_MIN_XITR,
3444 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3445 };
3446
3447 void
3448 e1000e_core_reset(E1000ECore *core)
3449 {
3450 int i;
3451
3452 timer_del(core->autoneg_timer);
3453
3454 e1000e_intrmgr_reset(core);
3455
3456 memset(core->phy, 0, sizeof core->phy);
3457 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3458 memset(core->mac, 0, sizeof core->mac);
3459 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);
3460
3461 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3462
3463 if (qemu_get_queue(core->owner_nic)->link_down) {
3464 e1000e_link_down(core);
3465 }
3466
3467 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3468
3469 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3470 net_tx_pkt_reset(core->tx[i].tx_pkt);
3471 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3472 core->tx[i].skip_cp = false;
3473 }
3474 }
3475
3476 void e1000e_core_pre_save(E1000ECore *core)
3477 {
3478 int i;
3479 NetClientState *nc = qemu_get_queue(core->owner_nic);
3480
3481 /*
3482 * If link is down and auto-negotiation is supported and ongoing,
3483 * complete auto-negotiation immediately. This allows us to look
3484 * at MII_SR_AUTONEG_COMPLETE to infer link status on load.
3485 */
3486 if (nc->link_down && e1000e_have_autoneg(core)) {
3487 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
3488 e1000e_update_flowctl_status(core);
3489 }
3490
3491 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3492 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3493 core->tx[i].skip_cp = true;
3494 }
3495 }
3496 }
3497
3498 int
3499 e1000e_core_post_load(E1000ECore *core)
3500 {
3501 NetClientState *nc = qemu_get_queue(core->owner_nic);
3502
3503 /* nc.link_down can't be migrated, so infer link_down according
3504 * to link status bit in core.mac[STATUS].
3505 */
3506 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3507
3508 return 0;
3509 }
AR7 emulation for QEMU