target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #ifndef CONFIG_USER_ONLY
  26
  27 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
  28               int mmu_idx, uintptr_t retaddr)
  29 {
  30     int ret;
  31
  32     ret = superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
  33     if (ret) {
  34         /* now we have a real cpu fault */
  35         if (retaddr) {
  36             cpu_restore_state(cs, retaddr);
  37         }
  38         cpu_loop_exit(cs);
  39     }
  40 }
  41
  42 #endif
  43
  44 #ifdef CONFIG_USER_ONLY
  45 void QEMU_NORETURN helper_ldtlb(CPUSH4State *env)
  46 #else
  47 void helper_ldtlb(CPUSH4State *env)
  48 #endif
  49 {
  50 #ifdef CONFIG_USER_ONLY
  51     SuperHCPU *cpu = sh_env_get_cpu(env);
  52
  53     /* XXXXX */
  54     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  55 #else
  56     cpu_load_tlb(env);
  57 #endif
  58 }
  59
  60 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  61                                                  uintptr_t retaddr)
  62 {
  63     CPUState *cs = CPU(sh_env_get_cpu(env));
  64
  65     cs->exception_index = index;
  66     if (retaddr) {
  67         cpu_restore_state(cs, retaddr);
  68     }
  69     cpu_loop_exit(cs);
  70 }
  71
  72 void QEMU_NORETURN helper_raise_illegal_instruction(CPUSH4State *env)
  73 {
  74     raise_exception(env, 0x180, 0);
  75 }
  76
  77 void QEMU_NORETURN helper_raise_slot_illegal_instruction(CPUSH4State *env)
  78 {
  79     raise_exception(env, 0x1a0, 0);
  80 }
  81
  82 void QEMU_NORETURN helper_raise_fpu_disable(CPUSH4State *env)
  83 {
  84     raise_exception(env, 0x800, 0);
  85 }
  86
  87 void QEMU_NORETURN helper_raise_slot_fpu_disable(CPUSH4State *env)
  88 {
  89     raise_exception(env, 0x820, 0);
  90 }
  91
  92 void QEMU_NORETURN helper_debug(CPUSH4State *env)
  93 {
  94     raise_exception(env, EXCP_DEBUG, 0);
  95 }
  96
  97 void QEMU_NORETURN helper_sleep(CPUSH4State *env)
  98 {
  99     CPUState *cs = CPU(sh_env_get_cpu(env));
 100
 101     cs->halted = 1;
 102     env->in_sleep = 1;
 103     raise_exception(env, EXCP_HLT, 0);
 104 }
 105
 106 void QEMU_NORETURN helper_trapa(CPUSH4State *env, uint32_t tra)
 107 {
 108     env->tra = tra << 2;
 109     raise_exception(env, 0x160, 0);
 110 }
 111
 112 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 113 {
 114     if (cpu_sh4_is_cached (env, address))
 115     {
 116         memory_content *r = g_new(memory_content, 1);
 117
 118         r->address = address;
 119         r->value = value;
 120         r->next = NULL;
 121
 122         *(env->movcal_backup_tail) = r;
 123         env->movcal_backup_tail = &(r->next);
 124     }
 125 }
 126
 127 void helper_discard_movcal_backup(CPUSH4State *env)
 128 {
 129     memory_content *current = env->movcal_backup;
 130
 131     while(current)
 132     {
 133         memory_content *next = current->next;
 134         g_free(current);
 135         env->movcal_backup = current = next;
 136         if (current == NULL)
 137             env->movcal_backup_tail = &(env->movcal_backup);
 138     }
 139 }
 140
 141 void helper_ocbi(CPUSH4State *env, uint32_t address)
 142 {
 143     memory_content **current = &(env->movcal_backup);
 144     while (*current)
 145     {
 146         uint32_t a = (*current)->address;
 147         if ((a & ~0x1F) == (address & ~0x1F))
 148         {
 149             memory_content *next = (*current)->next;
 150             cpu_stl_data(env, a, (*current)->value);
 151
 152             if (next == NULL)
 153             {
 154                 env->movcal_backup_tail = current;
 155             }
 156
 157             g_free(*current);
 158             *current = next;
 159             break;
 160         }
 161     }
 162 }
 163
 164 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 165 {
 166     int64_t res;
 167
 168     res = ((uint64_t) env->mach << 32) | env->macl;
 169     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 170     env->mach = (res >> 32) & 0xffffffff;
 171     env->macl = res & 0xffffffff;
 172     if (env->sr & (1u << SR_S)) {
 173         if (res < 0)
 174             env->mach |= 0xffff0000;
 175         else
 176             env->mach &= 0x00007fff;
 177     }
 178 }
 179
 180 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 181 {
 182     int64_t res;
 183
 184     res = ((uint64_t) env->mach << 32) | env->macl;
 185     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 186     env->mach = (res >> 32) & 0xffffffff;
 187     env->macl = res & 0xffffffff;
 188     if (env->sr & (1u << SR_S)) {
 189         if (res < -0x80000000) {
 190             env->mach = 1;
 191             env->macl = 0x80000000;
 192         } else if (res > 0x000000007fffffff) {
 193             env->mach = 1;
 194             env->macl = 0x7fffffff;
 195         }
 196     }
 197 }
 198
 199 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 200 {
 201     env->fpscr = val & FPSCR_MASK;
 202     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 203         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 204     } else {
 205         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 206     }
 207     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 208 }
 209
 210 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 211 {
 212     int xcpt, cause, enable;
 213
 214     xcpt = get_float_exception_flags(&env->fp_status);
 215
 216     /* Clear the flag entries */
 217     env->fpscr &= ~FPSCR_FLAG_MASK;
 218
 219     if (unlikely(xcpt)) {
 220         if (xcpt & float_flag_invalid) {
 221             env->fpscr |= FPSCR_FLAG_V;
 222         }
 223         if (xcpt & float_flag_divbyzero) {
 224             env->fpscr |= FPSCR_FLAG_Z;
 225         }
 226         if (xcpt & float_flag_overflow) {
 227             env->fpscr |= FPSCR_FLAG_O;
 228         }
 229         if (xcpt & float_flag_underflow) {
 230             env->fpscr |= FPSCR_FLAG_U;
 231         }
 232         if (xcpt & float_flag_inexact) {
 233             env->fpscr |= FPSCR_FLAG_I;
 234         }
 235
 236         /* Accumulate in cause entries */
 237         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 238                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 239
 240         /* Generate an exception if enabled */
 241         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 242         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 243         if (cause & enable) {
 244             raise_exception(env, 0x120, retaddr);
 245         }
 246     }
 247 }
 248
 249 float32 helper_fabs_FT(float32 t0)
 250 {
 251     return float32_abs(t0);
 252 }
 253
 254 float64 helper_fabs_DT(float64 t0)
 255 {
 256     return float64_abs(t0);
 257 }
 258
 259 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 260 {
 261     set_float_exception_flags(0, &env->fp_status);
 262     t0 = float32_add(t0, t1, &env->fp_status);
 263     update_fpscr(env, GETPC());
 264     return t0;
 265 }
 266
 267 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 268 {
 269     set_float_exception_flags(0, &env->fp_status);
 270     t0 = float64_add(t0, t1, &env->fp_status);
 271     update_fpscr(env, GETPC());
 272     return t0;
 273 }
 274
 275 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 276 {
 277     int relation;
 278
 279     set_float_exception_flags(0, &env->fp_status);
 280     relation = float32_compare(t0, t1, &env->fp_status);
 281     if (unlikely(relation == float_relation_unordered)) {
 282         update_fpscr(env, GETPC());
 283     } else {
 284         env->sr_t = (relation == float_relation_equal);
 285     }
 286 }
 287
 288 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 289 {
 290     int relation;
 291
 292     set_float_exception_flags(0, &env->fp_status);
 293     relation = float64_compare(t0, t1, &env->fp_status);
 294     if (unlikely(relation == float_relation_unordered)) {
 295         update_fpscr(env, GETPC());
 296     } else {
 297         env->sr_t = (relation == float_relation_equal);
 298     }
 299 }
 300
 301 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 302 {
 303     int relation;
 304
 305     set_float_exception_flags(0, &env->fp_status);
 306     relation = float32_compare(t0, t1, &env->fp_status);
 307     if (unlikely(relation == float_relation_unordered)) {
 308         update_fpscr(env, GETPC());
 309     } else {
 310         env->sr_t = (relation == float_relation_greater);
 311     }
 312 }
 313
 314 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 315 {
 316     int relation;
 317
 318     set_float_exception_flags(0, &env->fp_status);
 319     relation = float64_compare(t0, t1, &env->fp_status);
 320     if (unlikely(relation == float_relation_unordered)) {
 321         update_fpscr(env, GETPC());
 322     } else {
 323         env->sr_t = (relation == float_relation_greater);
 324     }
 325 }
 326
 327 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 328 {
 329     float64 ret;
 330     set_float_exception_flags(0, &env->fp_status);
 331     ret = float32_to_float64(t0, &env->fp_status);
 332     update_fpscr(env, GETPC());
 333     return ret;
 334 }
 335
 336 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 337 {
 338     float32 ret;
 339     set_float_exception_flags(0, &env->fp_status);
 340     ret = float64_to_float32(t0, &env->fp_status);
 341     update_fpscr(env, GETPC());
 342     return ret;
 343 }
 344
 345 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 346 {
 347     set_float_exception_flags(0, &env->fp_status);
 348     t0 = float32_div(t0, t1, &env->fp_status);
 349     update_fpscr(env, GETPC());
 350     return t0;
 351 }
 352
 353 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 354 {
 355     set_float_exception_flags(0, &env->fp_status);
 356     t0 = float64_div(t0, t1, &env->fp_status);
 357     update_fpscr(env, GETPC());
 358     return t0;
 359 }
 360
 361 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 362 {
 363     float32 ret;
 364     set_float_exception_flags(0, &env->fp_status);
 365     ret = int32_to_float32(t0, &env->fp_status);
 366     update_fpscr(env, GETPC());
 367     return ret;
 368 }
 369
 370 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 371 {
 372     float64 ret;
 373     set_float_exception_flags(0, &env->fp_status);
 374     ret = int32_to_float64(t0, &env->fp_status);
 375     update_fpscr(env, GETPC());
 376     return ret;
 377 }
 378
 379 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 380 {
 381     set_float_exception_flags(0, &env->fp_status);
 382     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 383     update_fpscr(env, GETPC());
 384     return t0;
 385 }
 386
 387 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 388 {
 389     set_float_exception_flags(0, &env->fp_status);
 390     t0 = float32_mul(t0, t1, &env->fp_status);
 391     update_fpscr(env, GETPC());
 392     return t0;
 393 }
 394
 395 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 396 {
 397     set_float_exception_flags(0, &env->fp_status);
 398     t0 = float64_mul(t0, t1, &env->fp_status);
 399     update_fpscr(env, GETPC());
 400     return t0;
 401 }
 402
 403 float32 helper_fneg_T(float32 t0)
 404 {
 405     return float32_chs(t0);
 406 }
 407
 408 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 409 {
 410     set_float_exception_flags(0, &env->fp_status);
 411     t0 = float32_sqrt(t0, &env->fp_status);
 412     update_fpscr(env, GETPC());
 413     return t0;
 414 }
 415
 416 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 417 {
 418     set_float_exception_flags(0, &env->fp_status);
 419     t0 = float64_sqrt(t0, &env->fp_status);
 420     update_fpscr(env, GETPC());
 421     return t0;
 422 }
 423
 424 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 425 {
 426     set_float_exception_flags(0, &env->fp_status);
 427     t0 = float32_sub(t0, t1, &env->fp_status);
 428     update_fpscr(env, GETPC());
 429     return t0;
 430 }
 431
 432 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 433 {
 434     set_float_exception_flags(0, &env->fp_status);
 435     t0 = float64_sub(t0, t1, &env->fp_status);
 436     update_fpscr(env, GETPC());
 437     return t0;
 438 }
 439
 440 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 441 {
 442     uint32_t ret;
 443     set_float_exception_flags(0, &env->fp_status);
 444     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 445     update_fpscr(env, GETPC());
 446     return ret;
 447 }
 448
 449 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 450 {
 451     uint32_t ret;
 452     set_float_exception_flags(0, &env->fp_status);
 453     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 454     update_fpscr(env, GETPC());
 455     return ret;
 456 }
 457
 458 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 459 {
 460     int bank, i;
 461     float32 r, p;
 462
 463     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 464     r = float32_zero;
 465     set_float_exception_flags(0, &env->fp_status);
 466
 467     for (i = 0 ; i < 4 ; i++) {
 468         p = float32_mul(env->fregs[bank + m + i],
 469                         env->fregs[bank + n + i],
 470                         &env->fp_status);
 471         r = float32_add(r, p, &env->fp_status);
 472     }
 473     update_fpscr(env, GETPC());
 474
 475     env->fregs[bank + n + 3] = r;
 476 }
 477
 478 void helper_ftrv(CPUSH4State *env, uint32_t n)
 479 {
 480     int bank_matrix, bank_vector;
 481     int i, j;
 482     float32 r[4];
 483     float32 p;
 484
 485     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 486     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 487     set_float_exception_flags(0, &env->fp_status);
 488     for (i = 0 ; i < 4 ; i++) {
 489         r[i] = float32_zero;
 490         for (j = 0 ; j < 4 ; j++) {
 491             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 492                             env->fregs[bank_vector + j],
 493                             &env->fp_status);
 494             r[i] = float32_add(r[i], p, &env->fp_status);
 495         }
 496     }
 497     update_fpscr(env, GETPC());
 498
 499     for (i = 0 ; i < 4 ; i++) {
 500         env->fregs[bank_vector + i] = r[i];
 501     }
 502 }