tcg: Add generic vector ops for constant shifts
[qemu/ar7.git] / tcg / tcg-op-gvec.h
blobb9f9eb7b848b8c7ab519f1c57942681672639494
1 /*
2 * Generic vector operation expansion
4 * Copyright (c) 2018 Linaro
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * "Generic" vectors. All operands are given as offsets from ENV,
22 * and therefore cannot also be allocated via tcg_global_mem_new_*.
23 * OPRSZ is the byte size of the vector upon which the operation is performed.
24 * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
26 * All sizes must be 8 or any multiple of 16.
27 * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
28 * Operands may completely, but not partially, overlap.
31 /* Expand a call to a gvec-style helper, with pointers to two vector
32 operands, and a descriptor (see tcg-gvec-desc.h). */
33 typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32);
34 void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
35 uint32_t oprsz, uint32_t maxsz, int32_t data,
36 gen_helper_gvec_2 *fn);
38 /* Similarly, passing an extra pointer (e.g. env or float_status). */
39 typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
40 void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
41 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
42 int32_t data, gen_helper_gvec_2_ptr *fn);
44 /* Similarly, with three vector operands. */
45 typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
46 void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
47 uint32_t oprsz, uint32_t maxsz, int32_t data,
48 gen_helper_gvec_3 *fn);
50 /* Similarly, with four vector operands. */
51 typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr,
52 TCGv_ptr, TCGv_i32);
53 void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
54 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
55 int32_t data, gen_helper_gvec_4 *fn);
57 /* Similarly, with five vector operands. */
58 typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
59 TCGv_ptr, TCGv_i32);
60 void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
61 uint32_t cofs, uint32_t xofs, uint32_t oprsz,
62 uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
64 typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
65 TCGv_ptr, TCGv_i32);
66 void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
67 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
68 int32_t data, gen_helper_gvec_3_ptr *fn);
70 typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
71 TCGv_ptr, TCGv_ptr, TCGv_i32);
72 void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
73 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
74 uint32_t maxsz, int32_t data,
75 gen_helper_gvec_4_ptr *fn);
77 /* Expand a gvec operation. Either inline or out-of-line depending on
78 the actual vector size and the operations supported by the host. */
79 typedef struct {
80 /* Expand inline as a 64-bit or 32-bit integer.
81 Only one of these will be non-NULL. */
82 void (*fni8)(TCGv_i64, TCGv_i64);
83 void (*fni4)(TCGv_i32, TCGv_i32);
84 /* Expand inline with a host vector type. */
85 void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
86 /* Expand out-of-line helper w/descriptor. */
87 gen_helper_gvec_2 *fno;
88 /* The opcode, if any, to which this corresponds. */
89 TCGOpcode opc;
90 /* The data argument to the out-of-line helper. */
91 int32_t data;
92 /* The vector element size, if applicable. */
93 uint8_t vece;
94 /* Prefer i64 to v64. */
95 bool prefer_i64;
96 } GVecGen2;
98 typedef struct {
99 /* Expand inline as a 64-bit or 32-bit integer.
100 Only one of these will be non-NULL. */
101 void (*fni8)(TCGv_i64, TCGv_i64, int64_t);
102 void (*fni4)(TCGv_i32, TCGv_i32, int32_t);
103 /* Expand inline with a host vector type. */
104 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t);
105 /* Expand out-of-line helper w/descriptor. */
106 gen_helper_gvec_2 *fno;
107 /* The opcode, if any, to which this corresponds. */
108 TCGOpcode opc;
109 /* The vector element size, if applicable. */
110 uint8_t vece;
111 /* Prefer i64 to v64. */
112 bool prefer_i64;
113 /* Load dest as a 3rd source operand. */
114 bool load_dest;
115 } GVecGen2i;
117 typedef struct {
118 /* Expand inline as a 64-bit or 32-bit integer.
119 Only one of these will be non-NULL. */
120 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
121 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
122 /* Expand inline with a host vector type. */
123 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
124 /* Expand out-of-line helper w/descriptor. */
125 gen_helper_gvec_3 *fno;
126 /* The opcode, if any, to which this corresponds. */
127 TCGOpcode opc;
128 /* The data argument to the out-of-line helper. */
129 int32_t data;
130 /* The vector element size, if applicable. */
131 uint8_t vece;
132 /* Prefer i64 to v64. */
133 bool prefer_i64;
134 /* Load dest as a 3rd source operand. */
135 bool load_dest;
136 } GVecGen3;
138 typedef struct {
139 /* Expand inline as a 64-bit or 32-bit integer.
140 Only one of these will be non-NULL. */
141 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
142 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
143 /* Expand inline with a host vector type. */
144 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
145 /* Expand out-of-line helper w/descriptor. */
146 gen_helper_gvec_4 *fno;
147 /* The opcode, if any, to which this corresponds. */
148 TCGOpcode opc;
149 /* The data argument to the out-of-line helper. */
150 int32_t data;
151 /* The vector element size, if applicable. */
152 uint8_t vece;
153 /* Prefer i64 to v64. */
154 bool prefer_i64;
155 } GVecGen4;
157 void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
158 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
159 void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
160 uint32_t maxsz, int64_t c, const GVecGen2i *);
161 void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
162 uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
163 void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
164 uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
166 /* Expand a specific vector operation. */
168 void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
169 uint32_t oprsz, uint32_t maxsz);
170 void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
171 uint32_t oprsz, uint32_t maxsz);
172 void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
173 uint32_t oprsz, uint32_t maxsz);
175 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
176 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
177 void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
178 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
180 void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
181 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
182 void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
183 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
184 void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
185 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
186 void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
187 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
188 void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
189 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
191 void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
192 uint32_t s, uint32_t m);
193 void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
194 uint32_t m, TCGv_i32);
195 void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
196 uint32_t m, TCGv_i64);
198 void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
199 void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
200 void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
201 void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
203 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
204 int64_t shift, uint32_t oprsz, uint32_t maxsz);
205 void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
206 int64_t shift, uint32_t oprsz, uint32_t maxsz);
207 void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
208 int64_t shift, uint32_t oprsz, uint32_t maxsz);
211 * 64-bit vector operations. Use these when the register has been allocated
212 * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
213 * OPRSZ = MAXSZ = 8.
216 void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a);
217 void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a);
218 void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a);
220 void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
221 void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
222 void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
224 void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
225 void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
226 void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
228 void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
229 void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
230 void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
231 void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
232 void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
233 void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);