4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
27 #include "hw/display/vga.h"
28 #include "hw/pci/pci.h"
31 #include "ui/pixel_ops.h"
32 #include "qemu/timer.h"
33 #include "hw/xen/xen.h"
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
39 /* 16 state changes per vertical frame @60 Hz */
40 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43 * Video Graphics Array (VGA)
45 * Chipset docs for original IBM VGA:
46 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 * http://www.osdever.net/FreeVGA/home.htm
51 * Standard VGA features and Bochs VBE extensions are implemented.
54 /* force some bits to zero */
55 const uint8_t sr_mask
[8] = {
66 const uint8_t gr_mask
[16] = {
85 #define cbswap_32(__x) \
87 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
88 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
89 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
90 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
92 #ifdef HOST_WORDS_BIGENDIAN
93 #define PAT(x) cbswap_32(x)
98 #ifdef HOST_WORDS_BIGENDIAN
104 #ifdef HOST_WORDS_BIGENDIAN
105 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
107 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110 static const uint32_t mask16
[16] = {
131 #ifdef HOST_WORDS_BIGENDIAN
134 #define PAT(x) cbswap_32(x)
137 static uint32_t expand4
[256];
138 static uint16_t expand2
[256];
139 static uint8_t expand4to8
[16];
141 static void vbe_update_vgaregs(VGACommonState
*s
);
143 static inline bool vbe_enabled(VGACommonState
*s
)
145 return s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
;
148 static inline uint8_t sr(VGACommonState
*s
, int idx
)
150 return vbe_enabled(s
) ? s
->sr_vbe
[idx
] : s
->sr
[idx
];
153 static void vga_update_memory_access(VGACommonState
*s
)
155 hwaddr base
, offset
, size
;
157 if (s
->legacy_address_space
== NULL
) {
161 if (s
->has_chain4_alias
) {
162 memory_region_del_subregion(s
->legacy_address_space
, &s
->chain4_alias
);
163 object_unparent(OBJECT(&s
->chain4_alias
));
164 s
->has_chain4_alias
= false;
165 s
->plane_updated
= 0xf;
167 if ((sr(s
, VGA_SEQ_PLANE_WRITE
) & VGA_SR02_ALL_PLANES
) ==
168 VGA_SR02_ALL_PLANES
&& sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
170 switch ((s
->gr
[VGA_GFX_MISC
] >> 2) & 3) {
178 offset
= s
->bank_offset
;
190 assert(offset
+ size
<= s
->vram_size
);
191 memory_region_init_alias(&s
->chain4_alias
, memory_region_owner(&s
->vram
),
192 "vga.chain4", &s
->vram
, offset
, size
);
193 memory_region_add_subregion_overlap(s
->legacy_address_space
, base
,
194 &s
->chain4_alias
, 2);
195 s
->has_chain4_alias
= true;
199 static void vga_dumb_update_retrace_info(VGACommonState
*s
)
204 static void vga_precise_update_retrace_info(VGACommonState
*s
)
207 int hretr_start_char
;
208 int hretr_skew_chars
;
212 int vretr_start_line
;
221 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
222 int64_t chars_per_sec
;
223 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
225 htotal_chars
= s
->cr
[VGA_CRTC_H_TOTAL
] + 5;
226 hretr_start_char
= s
->cr
[VGA_CRTC_H_SYNC_START
];
227 hretr_skew_chars
= (s
->cr
[VGA_CRTC_H_SYNC_END
] >> 5) & 3;
228 hretr_end_char
= s
->cr
[VGA_CRTC_H_SYNC_END
] & 0x1f;
230 vtotal_lines
= (s
->cr
[VGA_CRTC_V_TOTAL
] |
231 (((s
->cr
[VGA_CRTC_OVERFLOW
] & 1) |
232 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 4) & 2)) << 8)) + 2;
233 vretr_start_line
= s
->cr
[VGA_CRTC_V_SYNC_START
] |
234 ((((s
->cr
[VGA_CRTC_OVERFLOW
] >> 2) & 1) |
235 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 6) & 2)) << 8);
236 vretr_end_line
= s
->cr
[VGA_CRTC_V_SYNC_END
] & 0xf;
238 clocking_mode
= (sr(s
, VGA_SEQ_CLOCK_MODE
) >> 3) & 1;
239 clock_sel
= (s
->msr
>> 2) & 3;
240 dots
= (s
->msr
& 1) ? 8 : 9;
242 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
244 htotal_chars
<<= clocking_mode
;
246 r
->total_chars
= vtotal_lines
* htotal_chars
;
248 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ (r
->total_chars
* r
->freq
);
250 r
->ticks_per_char
= NANOSECONDS_PER_SECOND
/ chars_per_sec
;
253 r
->vstart
= vretr_start_line
;
254 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
256 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
257 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
258 r
->htotal
= htotal_chars
;
261 div2
= (s
->cr
[VGA_CRTC_MODE
] >> 2) & 1;
262 sldiv2
= (s
->cr
[VGA_CRTC_MODE
] >> 3) & 1;
272 "div2 = %d sldiv2 = %d\n"
273 "clocking_mode = %d\n"
274 "clock_sel = %d %d\n"
276 "ticks/char = %" PRId64
"\n"
278 (double) NANOSECONDS_PER_SECOND
/ (r
->ticks_per_char
* r
->total_chars
),
296 static uint8_t vga_precise_retrace(VGACommonState
*s
)
298 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
299 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
301 if (r
->total_chars
) {
302 int cur_line
, cur_line_char
, cur_char
;
305 cur_tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
307 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
308 cur_line
= cur_char
/ r
->htotal
;
310 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
311 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
313 cur_line_char
= cur_char
% r
->htotal
;
314 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
315 val
|= ST01_DISP_ENABLE
;
321 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
325 static uint8_t vga_dumb_retrace(VGACommonState
*s
)
327 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
330 int vga_ioport_invalid(VGACommonState
*s
, uint32_t addr
)
332 if (s
->msr
& VGA_MIS_COLOR
) {
334 return (addr
>= 0x3b0 && addr
<= 0x3bf);
337 return (addr
>= 0x3d0 && addr
<= 0x3df);
341 uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
343 VGACommonState
*s
= opaque
;
346 if (vga_ioport_invalid(s
, addr
)) {
351 if (s
->ar_flip_flop
== 0) {
358 index
= s
->ar_index
& 0x1f;
359 if (index
< VGA_ATT_C
) {
372 val
= s
->sr
[s
->sr_index
];
374 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
381 val
= s
->dac_write_index
;
384 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
385 if (++s
->dac_sub_index
== 3) {
386 s
->dac_sub_index
= 0;
400 val
= s
->gr
[s
->gr_index
];
402 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
411 val
= s
->cr
[s
->cr_index
];
413 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
418 /* just toggle to fool polling */
419 val
= s
->st01
= s
->retrace(s
);
427 trace_vga_std_read_io(addr
, val
);
431 void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
433 VGACommonState
*s
= opaque
;
436 /* check port range access depending on color/monochrome mode */
437 if (vga_ioport_invalid(s
, addr
)) {
440 trace_vga_std_write_io(addr
, val
);
444 if (s
->ar_flip_flop
== 0) {
448 index
= s
->ar_index
& 0x1f;
450 case VGA_ATC_PALETTE0
... VGA_ATC_PALETTEF
:
451 s
->ar
[index
] = val
& 0x3f;
454 s
->ar
[index
] = val
& ~0x10;
456 case VGA_ATC_OVERSCAN
:
459 case VGA_ATC_PLANE_ENABLE
:
460 s
->ar
[index
] = val
& ~0xc0;
463 s
->ar
[index
] = val
& ~0xf0;
465 case VGA_ATC_COLOR_PAGE
:
466 s
->ar
[index
] = val
& ~0xf0;
472 s
->ar_flip_flop
^= 1;
475 s
->msr
= val
& ~0x10;
476 s
->update_retrace_info(s
);
479 s
->sr_index
= val
& 7;
483 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
485 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
486 if (s
->sr_index
== VGA_SEQ_CLOCK_MODE
) {
487 s
->update_retrace_info(s
);
489 vga_update_memory_access(s
);
492 s
->dac_read_index
= val
;
493 s
->dac_sub_index
= 0;
497 s
->dac_write_index
= val
;
498 s
->dac_sub_index
= 0;
502 s
->dac_cache
[s
->dac_sub_index
] = val
;
503 if (++s
->dac_sub_index
== 3) {
504 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
505 s
->dac_sub_index
= 0;
506 s
->dac_write_index
++;
510 s
->gr_index
= val
& 0x0f;
514 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
516 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
517 vbe_update_vgaregs(s
);
518 vga_update_memory_access(s
);
527 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
529 /* handle CR0-7 protection */
530 if ((s
->cr
[VGA_CRTC_V_SYNC_END
] & VGA_CR11_LOCK_CR0_CR7
) &&
531 s
->cr_index
<= VGA_CRTC_OVERFLOW
) {
532 /* can always write bit 4 of CR7 */
533 if (s
->cr_index
== VGA_CRTC_OVERFLOW
) {
534 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x10) |
536 vbe_update_vgaregs(s
);
540 s
->cr
[s
->cr_index
] = val
;
541 vbe_update_vgaregs(s
);
543 switch(s
->cr_index
) {
544 case VGA_CRTC_H_TOTAL
:
545 case VGA_CRTC_H_SYNC_START
:
546 case VGA_CRTC_H_SYNC_END
:
547 case VGA_CRTC_V_TOTAL
:
548 case VGA_CRTC_OVERFLOW
:
549 case VGA_CRTC_V_SYNC_END
:
551 s
->update_retrace_info(s
);
563 * Sanity check vbe register writes.
565 * As we don't have a way to signal errors to the guest in the bochs
566 * dispi interface we'll go adjust the registers to the closest valid
569 static void vbe_fixup_regs(VGACommonState
*s
)
571 uint16_t *r
= s
->vbe_regs
;
572 uint32_t bits
, linelength
, maxy
, offset
;
574 if (!vbe_enabled(s
)) {
575 /* vbe is turned off -- nothing to do */
580 switch (r
[VBE_DISPI_INDEX_BPP
]) {
586 bits
= r
[VBE_DISPI_INDEX_BPP
];
592 bits
= r
[VBE_DISPI_INDEX_BPP
] = 8;
597 r
[VBE_DISPI_INDEX_XRES
] &= ~7u;
598 if (r
[VBE_DISPI_INDEX_XRES
] == 0) {
599 r
[VBE_DISPI_INDEX_XRES
] = 8;
601 if (r
[VBE_DISPI_INDEX_XRES
] > VBE_DISPI_MAX_XRES
) {
602 r
[VBE_DISPI_INDEX_XRES
] = VBE_DISPI_MAX_XRES
;
604 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] &= ~7u;
605 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] > VBE_DISPI_MAX_XRES
) {
606 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = VBE_DISPI_MAX_XRES
;
608 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] < r
[VBE_DISPI_INDEX_XRES
]) {
609 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = r
[VBE_DISPI_INDEX_XRES
];
613 linelength
= r
[VBE_DISPI_INDEX_VIRT_WIDTH
] * bits
/ 8;
614 maxy
= s
->vbe_size
/ linelength
;
615 if (r
[VBE_DISPI_INDEX_YRES
] == 0) {
616 r
[VBE_DISPI_INDEX_YRES
] = 1;
618 if (r
[VBE_DISPI_INDEX_YRES
] > VBE_DISPI_MAX_YRES
) {
619 r
[VBE_DISPI_INDEX_YRES
] = VBE_DISPI_MAX_YRES
;
621 if (r
[VBE_DISPI_INDEX_YRES
] > maxy
) {
622 r
[VBE_DISPI_INDEX_YRES
] = maxy
;
626 if (r
[VBE_DISPI_INDEX_X_OFFSET
] > VBE_DISPI_MAX_XRES
) {
627 r
[VBE_DISPI_INDEX_X_OFFSET
] = VBE_DISPI_MAX_XRES
;
629 if (r
[VBE_DISPI_INDEX_Y_OFFSET
] > VBE_DISPI_MAX_YRES
) {
630 r
[VBE_DISPI_INDEX_Y_OFFSET
] = VBE_DISPI_MAX_YRES
;
632 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
633 offset
+= r
[VBE_DISPI_INDEX_Y_OFFSET
] * linelength
;
634 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
635 r
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
636 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
637 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
638 r
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
643 /* update vga state */
644 r
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = maxy
;
645 s
->vbe_line_offset
= linelength
;
646 s
->vbe_start_addr
= offset
/ 4;
649 /* we initialize the VGA graphic mode */
650 static void vbe_update_vgaregs(VGACommonState
*s
)
652 int h
, shift_control
;
654 if (!vbe_enabled(s
)) {
655 /* vbe is turned off -- nothing to do */
659 /* graphic mode + memory map 1 */
660 s
->gr
[VGA_GFX_MISC
] = (s
->gr
[VGA_GFX_MISC
] & ~0x0c) | 0x04 |
661 VGA_GR06_GRAPHICS_MODE
;
662 s
->cr
[VGA_CRTC_MODE
] |= 3; /* no CGA modes */
663 s
->cr
[VGA_CRTC_OFFSET
] = s
->vbe_line_offset
>> 3;
665 s
->cr
[VGA_CRTC_H_DISP
] =
666 (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
667 /* height (only meaningful if < 1024) */
668 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
669 s
->cr
[VGA_CRTC_V_DISP_END
] = h
;
670 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x42) |
671 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
672 /* line compare to 1023 */
673 s
->cr
[VGA_CRTC_LINE_COMPARE
] = 0xff;
674 s
->cr
[VGA_CRTC_OVERFLOW
] |= 0x10;
675 s
->cr
[VGA_CRTC_MAX_SCAN
] |= 0x40;
677 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
679 s
->sr_vbe
[VGA_SEQ_CLOCK_MODE
] &= ~8; /* no double line */
682 /* set chain 4 mode */
683 s
->sr_vbe
[VGA_SEQ_MEMORY_MODE
] |= VGA_SR04_CHN_4M
;
684 /* activate all planes */
685 s
->sr_vbe
[VGA_SEQ_PLANE_WRITE
] |= VGA_SR02_ALL_PLANES
;
687 s
->gr
[VGA_GFX_MODE
] = (s
->gr
[VGA_GFX_MODE
] & ~0x60) |
688 (shift_control
<< 5);
689 s
->cr
[VGA_CRTC_MAX_SCAN
] &= ~0x9f; /* no double scan */
692 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
694 VGACommonState
*s
= opaque
;
698 uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
700 VGACommonState
*s
= opaque
;
703 if (s
->vbe_index
< VBE_DISPI_INDEX_NB
) {
704 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
705 switch(s
->vbe_index
) {
706 /* XXX: do not hardcode ? */
707 case VBE_DISPI_INDEX_XRES
:
708 val
= VBE_DISPI_MAX_XRES
;
710 case VBE_DISPI_INDEX_YRES
:
711 val
= VBE_DISPI_MAX_YRES
;
713 case VBE_DISPI_INDEX_BPP
:
714 val
= VBE_DISPI_MAX_BPP
;
717 val
= s
->vbe_regs
[s
->vbe_index
];
721 val
= s
->vbe_regs
[s
->vbe_index
];
723 } else if (s
->vbe_index
== VBE_DISPI_INDEX_VIDEO_MEMORY_64K
) {
724 val
= s
->vbe_size
/ (64 * 1024);
728 trace_vga_vbe_read(s
->vbe_index
, val
);
732 void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
734 VGACommonState
*s
= opaque
;
738 void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
740 VGACommonState
*s
= opaque
;
742 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
743 trace_vga_vbe_write(s
->vbe_index
, val
);
744 switch(s
->vbe_index
) {
745 case VBE_DISPI_INDEX_ID
:
746 if (val
== VBE_DISPI_ID0
||
747 val
== VBE_DISPI_ID1
||
748 val
== VBE_DISPI_ID2
||
749 val
== VBE_DISPI_ID3
||
750 val
== VBE_DISPI_ID4
) {
751 s
->vbe_regs
[s
->vbe_index
] = val
;
754 case VBE_DISPI_INDEX_XRES
:
755 case VBE_DISPI_INDEX_YRES
:
756 case VBE_DISPI_INDEX_BPP
:
757 case VBE_DISPI_INDEX_VIRT_WIDTH
:
758 case VBE_DISPI_INDEX_X_OFFSET
:
759 case VBE_DISPI_INDEX_Y_OFFSET
:
760 s
->vbe_regs
[s
->vbe_index
] = val
;
762 vbe_update_vgaregs(s
);
764 case VBE_DISPI_INDEX_BANK
:
765 val
&= s
->vbe_bank_mask
;
766 s
->vbe_regs
[s
->vbe_index
] = val
;
767 s
->bank_offset
= (val
<< 16);
768 vga_update_memory_access(s
);
770 case VBE_DISPI_INDEX_ENABLE
:
771 if ((val
& VBE_DISPI_ENABLED
) &&
772 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
774 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = 0;
775 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
776 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
777 s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] |= VBE_DISPI_ENABLED
;
779 vbe_update_vgaregs(s
);
781 /* clear the screen */
782 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
783 memset(s
->vram_ptr
, 0,
784 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
789 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
790 s
->vbe_regs
[s
->vbe_index
] = val
;
791 vga_update_memory_access(s
);
799 /* called for accesses between 0xa0000 and 0xc0000 */
800 uint32_t vga_mem_readb(VGACommonState
*s
, hwaddr addr
)
802 int memory_map_mode
, plane
;
805 /* convert to VGA memory offset */
806 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
808 switch(memory_map_mode
) {
814 addr
+= s
->bank_offset
;
829 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
830 /* chain 4 mode : simplest access */
831 assert(addr
< s
->vram_size
);
832 ret
= s
->vram_ptr
[addr
];
833 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
834 /* odd/even mode (aka text mode mapping) */
835 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
836 addr
= ((addr
& ~1) << 1) | plane
;
837 if (addr
>= s
->vram_size
) {
840 ret
= s
->vram_ptr
[addr
];
842 /* standard VGA latched access */
843 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
846 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
848 if (!(s
->gr
[VGA_GFX_MODE
] & 0x08)) {
850 plane
= s
->gr
[VGA_GFX_PLANE_READ
];
851 ret
= GET_PLANE(s
->latch
, plane
);
854 ret
= (s
->latch
^ mask16
[s
->gr
[VGA_GFX_COMPARE_VALUE
]]) &
855 mask16
[s
->gr
[VGA_GFX_COMPARE_MASK
]];
864 /* called for accesses between 0xa0000 and 0xc0000 */
865 void vga_mem_writeb(VGACommonState
*s
, hwaddr addr
, uint32_t val
)
867 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
868 uint32_t write_mask
, bit_mask
, set_mask
;
871 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
873 /* convert to VGA memory offset */
874 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
876 switch(memory_map_mode
) {
882 addr
+= s
->bank_offset
;
897 if (sr(s
, VGA_SEQ_MEMORY_MODE
) & VGA_SR04_CHN_4M
) {
898 /* chain 4 mode : simplest access */
901 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
902 assert(addr
< s
->vram_size
);
903 s
->vram_ptr
[addr
] = val
;
905 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
907 s
->plane_updated
|= mask
; /* only used to detect font change */
908 memory_region_set_dirty(&s
->vram
, addr
, 1);
910 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
911 /* odd/even mode (aka text mode mapping) */
912 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
914 if (sr(s
, VGA_SEQ_PLANE_WRITE
) & mask
) {
915 addr
= ((addr
& ~1) << 1) | plane
;
916 if (addr
>= s
->vram_size
) {
919 s
->vram_ptr
[addr
] = val
;
921 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
923 s
->plane_updated
|= mask
; /* only used to detect font change */
924 memory_region_set_dirty(&s
->vram
, addr
, 1);
927 /* standard VGA latched access */
928 write_mode
= s
->gr
[VGA_GFX_MODE
] & 3;
933 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
934 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
938 /* apply set/reset mask */
939 set_mask
= mask16
[s
->gr
[VGA_GFX_SR_ENABLE
]];
940 val
= (val
& ~set_mask
) |
941 (mask16
[s
->gr
[VGA_GFX_SR_VALUE
]] & set_mask
);
942 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
948 val
= mask16
[val
& 0x0f];
949 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
953 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
954 val
= (val
>> b
) | (val
<< (8 - b
));
956 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
] & val
;
957 val
= mask16
[s
->gr
[VGA_GFX_SR_VALUE
]];
961 /* apply logical operation */
962 func_select
= s
->gr
[VGA_GFX_DATA_ROTATE
] >> 3;
963 switch(func_select
) {
983 bit_mask
|= bit_mask
<< 8;
984 bit_mask
|= bit_mask
<< 16;
985 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
988 /* mask data according to sr[2] */
989 mask
= sr(s
, VGA_SEQ_PLANE_WRITE
);
990 s
->plane_updated
|= mask
; /* only used to detect font change */
991 write_mask
= mask16
[mask
];
992 if (addr
* sizeof(uint32_t) >= s
->vram_size
) {
995 ((uint32_t *)s
->vram_ptr
)[addr
] =
996 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
999 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
1000 addr
* 4, write_mask
, val
);
1002 memory_region_set_dirty(&s
->vram
, addr
<< 2, sizeof(uint32_t));
1006 typedef void vga_draw_line_func(VGACommonState
*s1
, uint8_t *d
,
1007 uint32_t srcaddr
, int width
);
1009 #include "vga-helpers.h"
1011 /* return true if the palette was modified */
1012 static int update_palette16(VGACommonState
*s
)
1015 uint32_t v
, col
, *palette
;
1018 palette
= s
->last_palette
;
1019 for(i
= 0; i
< 16; i
++) {
1021 if (s
->ar
[VGA_ATC_MODE
] & 0x80) {
1022 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xf) << 4) | (v
& 0xf);
1024 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xc) << 4) | (v
& 0x3f);
1027 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1028 c6_to_8(s
->palette
[v
+ 1]),
1029 c6_to_8(s
->palette
[v
+ 2]));
1030 if (col
!= palette
[i
]) {
1038 /* return true if the palette was modified */
1039 static int update_palette256(VGACommonState
*s
)
1042 uint32_t v
, col
, *palette
;
1045 palette
= s
->last_palette
;
1047 for(i
= 0; i
< 256; i
++) {
1049 col
= rgb_to_pixel32(s
->palette
[v
],
1053 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1054 c6_to_8(s
->palette
[v
+ 1]),
1055 c6_to_8(s
->palette
[v
+ 2]));
1057 if (col
!= palette
[i
]) {
1066 static void vga_get_offsets(VGACommonState
*s
,
1067 uint32_t *pline_offset
,
1068 uint32_t *pstart_addr
,
1069 uint32_t *pline_compare
)
1071 uint32_t start_addr
, line_offset
, line_compare
;
1073 if (vbe_enabled(s
)) {
1074 line_offset
= s
->vbe_line_offset
;
1075 start_addr
= s
->vbe_start_addr
;
1076 line_compare
= 65535;
1078 /* compute line_offset in bytes */
1079 line_offset
= s
->cr
[VGA_CRTC_OFFSET
];
1082 /* starting address */
1083 start_addr
= s
->cr
[VGA_CRTC_START_LO
] |
1084 (s
->cr
[VGA_CRTC_START_HI
] << 8);
1087 line_compare
= s
->cr
[VGA_CRTC_LINE_COMPARE
] |
1088 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x10) << 4) |
1089 ((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x40) << 3);
1091 *pline_offset
= line_offset
;
1092 *pstart_addr
= start_addr
;
1093 *pline_compare
= line_compare
;
1096 /* update start_addr and line_offset. Return TRUE if modified */
1097 static int update_basic_params(VGACommonState
*s
)
1100 uint32_t start_addr
, line_offset
, line_compare
;
1104 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1106 if (line_offset
!= s
->line_offset
||
1107 start_addr
!= s
->start_addr
||
1108 line_compare
!= s
->line_compare
) {
1109 s
->line_offset
= line_offset
;
1110 s
->start_addr
= start_addr
;
1111 s
->line_compare
= line_compare
;
1118 static const uint8_t cursor_glyph
[32 * 4] = {
1119 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 static void vga_get_text_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
,
1138 int *pcwidth
, int *pcheight
)
1140 int width
, cwidth
, height
, cheight
;
1142 /* total width & height */
1143 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1145 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1148 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1149 cwidth
= 16; /* NOTE: no 18 pixel wide */
1151 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1152 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1153 /* ugly hack for CGA 160x100x16 - explain me the logic */
1156 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1157 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1158 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1159 height
= (height
+ 1) / cheight
;
1165 *pcheight
= cheight
;
1176 static void vga_draw_text(VGACommonState
*s
, int full_update
)
1178 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1179 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1180 int cx_min
, cx_max
, linesize
, x_incr
, line
, line1
;
1181 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1182 uint8_t *d1
, *d
, *src
, *dest
, *cursor_ptr
;
1183 const uint8_t *font_ptr
, *font_base
[2];
1184 int dup9
, line_offset
;
1186 uint32_t *ch_attr_ptr
;
1187 int64_t now
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1189 /* compute font data address (in plane 2) */
1190 v
= sr(s
, VGA_SEQ_CHARACTER_MAP
);
1191 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1192 if (offset
!= s
->font_offsets
[0]) {
1193 s
->font_offsets
[0] = offset
;
1196 font_base
[0] = s
->vram_ptr
+ offset
;
1198 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1199 font_base
[1] = s
->vram_ptr
+ offset
;
1200 if (offset
!= s
->font_offsets
[1]) {
1201 s
->font_offsets
[1] = offset
;
1204 if (s
->plane_updated
& (1 << 2) || s
->has_chain4_alias
) {
1205 /* if the plane 2 was modified since the last display, it
1206 indicates the font may have been modified */
1207 s
->plane_updated
= 0;
1210 full_update
|= update_basic_params(s
);
1212 line_offset
= s
->line_offset
;
1214 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1215 if ((height
* width
) <= 1) {
1216 /* better than nothing: exit if transient size is too small */
1219 if ((height
* width
) > CH_ATTR_SIZE
) {
1220 /* better than nothing: exit if transient size is too big */
1224 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1225 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1226 s
->last_scr_width
= width
* cw
;
1227 s
->last_scr_height
= height
* cheight
;
1228 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1229 surface
= qemu_console_surface(s
->con
);
1230 dpy_text_resize(s
->con
, width
, height
);
1232 s
->last_width
= width
;
1233 s
->last_height
= height
;
1234 s
->last_ch
= cheight
;
1238 full_update
|= update_palette16(s
);
1239 palette
= s
->last_palette
;
1240 x_incr
= cw
* surface_bytes_per_pixel(surface
);
1243 s
->full_update_text
= 1;
1245 if (s
->full_update_gfx
) {
1246 s
->full_update_gfx
= 0;
1250 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1251 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1252 if (cursor_offset
!= s
->cursor_offset
||
1253 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1254 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
) {
1255 /* if the cursor position changed, we update the old and new
1257 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1258 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1259 if (cursor_offset
< CH_ATTR_SIZE
)
1260 s
->last_ch_attr
[cursor_offset
] = -1;
1261 s
->cursor_offset
= cursor_offset
;
1262 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1263 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1265 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1266 if (now
>= s
->cursor_blink_time
) {
1267 s
->cursor_blink_time
= now
+ VGA_TEXT_CURSOR_PERIOD_MS
/ 2;
1268 s
->cursor_visible_phase
= !s
->cursor_visible_phase
;
1271 dest
= surface_data(surface
);
1272 linesize
= surface_stride(surface
);
1273 ch_attr_ptr
= s
->last_ch_attr
;
1275 offset
= s
->start_addr
* 4;
1276 for(cy
= 0; cy
< height
; cy
++) {
1278 src
= s
->vram_ptr
+ offset
;
1281 for(cx
= 0; cx
< width
; cx
++) {
1282 if (src
+ sizeof(uint16_t) > s
->vram_ptr
+ s
->vram_size
) {
1285 ch_attr
= *(uint16_t *)src
;
1286 if (full_update
|| ch_attr
!= *ch_attr_ptr
|| src
== cursor_ptr
) {
1291 *ch_attr_ptr
= ch_attr
;
1292 #ifdef HOST_WORDS_BIGENDIAN
1294 cattr
= ch_attr
& 0xff;
1296 ch
= ch_attr
& 0xff;
1297 cattr
= ch_attr
>> 8;
1299 font_ptr
= font_base
[(cattr
>> 3) & 1];
1300 font_ptr
+= 32 * 4 * ch
;
1301 bgcol
= palette
[cattr
>> 4];
1302 fgcol
= palette
[cattr
& 0x0f];
1304 vga_draw_glyph16(d1
, linesize
,
1305 font_ptr
, cheight
, fgcol
, bgcol
);
1306 } else if (cw
!= 9) {
1307 vga_draw_glyph8(d1
, linesize
,
1308 font_ptr
, cheight
, fgcol
, bgcol
);
1311 if (ch
>= 0xb0 && ch
<= 0xdf &&
1312 (s
->ar
[VGA_ATC_MODE
] & 0x04)) {
1315 vga_draw_glyph9(d1
, linesize
,
1316 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1318 if (src
== cursor_ptr
&&
1319 !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20) &&
1320 s
->cursor_visible_phase
) {
1321 int line_start
, line_last
, h
;
1322 /* draw the cursor */
1323 line_start
= s
->cr
[VGA_CRTC_CURSOR_START
] & 0x1f;
1324 line_last
= s
->cr
[VGA_CRTC_CURSOR_END
] & 0x1f;
1325 /* XXX: check that */
1326 if (line_last
> cheight
- 1)
1327 line_last
= cheight
- 1;
1328 if (line_last
>= line_start
&& line_start
< cheight
) {
1329 h
= line_last
- line_start
+ 1;
1330 d
= d1
+ linesize
* line_start
;
1332 vga_draw_glyph16(d
, linesize
,
1333 cursor_glyph
, h
, fgcol
, bgcol
);
1334 } else if (cw
!= 9) {
1335 vga_draw_glyph8(d
, linesize
,
1336 cursor_glyph
, h
, fgcol
, bgcol
);
1338 vga_draw_glyph9(d
, linesize
,
1339 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1349 dpy_gfx_update(s
->con
, cx_min
* cw
, cy
* cheight
,
1350 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1352 dest
+= linesize
* cheight
;
1353 line1
= line
+ cheight
;
1354 offset
+= line_offset
;
1355 if (line
< s
->line_compare
&& line1
>= s
->line_compare
) {
1380 static vga_draw_line_func
* const vga_draw_line_table
[VGA_DRAW_LINE_NB
] = {
1397 static int vga_get_bpp(VGACommonState
*s
)
1401 if (vbe_enabled(s
)) {
1402 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1409 static void vga_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1413 if (vbe_enabled(s
)) {
1414 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1415 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1417 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1) * 8;
1418 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1419 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1420 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1421 height
= (height
+ 1);
1427 void vga_invalidate_scanlines(VGACommonState
*s
, int y1
, int y2
)
1430 if (y1
>= VGA_MAX_HEIGHT
)
1432 if (y2
>= VGA_MAX_HEIGHT
)
1433 y2
= VGA_MAX_HEIGHT
;
1434 for(y
= y1
; y
< y2
; y
++) {
1435 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1439 static bool vga_scanline_invalidated(VGACommonState
*s
, int y
)
1441 if (y
>= VGA_MAX_HEIGHT
) {
1444 return s
->invalidated_y_table
[y
>> 5] & (1 << (y
& 0x1f));
1447 void vga_sync_dirty_bitmap(VGACommonState
*s
)
1449 memory_region_sync_dirty_bitmap(&s
->vram
);
1452 void vga_dirty_log_start(VGACommonState
*s
)
1454 memory_region_set_log(&s
->vram
, true, DIRTY_MEMORY_VGA
);
1457 void vga_dirty_log_stop(VGACommonState
*s
)
1459 memory_region_set_log(&s
->vram
, false, DIRTY_MEMORY_VGA
);
1465 static void vga_draw_graphic(VGACommonState
*s
, int full_update
)
1467 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1468 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1469 int width
, height
, shift_control
, bwidth
, bits
;
1470 ram_addr_t page0
, page1
, region_start
, region_end
;
1471 DirtyBitmapSnapshot
*snap
= NULL
;
1472 int disp_width
, multi_scan
, multi_run
;
1474 uint32_t v
, addr1
, addr
;
1475 vga_draw_line_func
*vga_draw_line
= NULL
;
1476 bool share_surface
, force_shadow
= false;
1477 pixman_format_code_t format
;
1478 #ifdef HOST_WORDS_BIGENDIAN
1479 bool byteswap
= !s
->big_endian_fb
;
1481 bool byteswap
= s
->big_endian_fb
;
1484 full_update
|= update_basic_params(s
);
1486 s
->get_resolution(s
, &width
, &height
);
1489 region_start
= (s
->start_addr
* 4);
1490 region_end
= region_start
+ (ram_addr_t
)s
->line_offset
* height
;
1491 if (region_end
> s
->vbe_size
) {
1492 /* wraps around (can happen with cirrus vbe modes) */
1494 region_end
= s
->vbe_size
;
1495 force_shadow
= true;
1498 shift_control
= (s
->gr
[VGA_GFX_MODE
] >> 5) & 3;
1499 double_scan
= (s
->cr
[VGA_CRTC_MAX_SCAN
] >> 7);
1500 if (shift_control
!= 1) {
1501 multi_scan
= (((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1) << double_scan
)
1504 /* in CGA modes, multi_scan is ignored */
1505 /* XXX: is it correct ? */
1506 multi_scan
= double_scan
;
1508 multi_run
= multi_scan
;
1509 if (shift_control
!= s
->shift_control
||
1510 double_scan
!= s
->double_scan
) {
1512 s
->shift_control
= shift_control
;
1513 s
->double_scan
= double_scan
;
1516 if (shift_control
== 0) {
1517 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1520 } else if (shift_control
== 1) {
1521 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1526 depth
= s
->get_bpp(s
);
1529 * Check whether we can share the surface with the backend
1530 * or whether we need a shadow surface. We share native
1531 * endian surfaces for 15bpp and above and byteswapped
1532 * surfaces for 24bpp and above.
1534 format
= qemu_default_pixman_format(depth
, !byteswap
);
1536 share_surface
= dpy_gfx_check_format(s
->con
, format
)
1537 && !s
->force_shadow
&& !force_shadow
;
1539 share_surface
= false;
1541 if (s
->line_offset
!= s
->last_line_offset
||
1542 disp_width
!= s
->last_width
||
1543 height
!= s
->last_height
||
1544 s
->last_depth
!= depth
||
1545 s
->last_byteswap
!= byteswap
||
1546 share_surface
!= is_buffer_shared(surface
)) {
1547 if (share_surface
) {
1548 surface
= qemu_create_displaysurface_from(disp_width
,
1549 height
, format
, s
->line_offset
,
1550 s
->vram_ptr
+ (s
->start_addr
* 4));
1551 dpy_gfx_replace_surface(s
->con
, surface
);
1553 qemu_console_resize(s
->con
, disp_width
, height
);
1554 surface
= qemu_console_surface(s
->con
);
1556 s
->last_scr_width
= disp_width
;
1557 s
->last_scr_height
= height
;
1558 s
->last_width
= disp_width
;
1559 s
->last_height
= height
;
1560 s
->last_line_offset
= s
->line_offset
;
1561 s
->last_depth
= depth
;
1562 s
->last_byteswap
= byteswap
;
1564 } else if (is_buffer_shared(surface
) &&
1565 (full_update
|| surface_data(surface
) != s
->vram_ptr
1566 + (s
->start_addr
* 4))) {
1567 pixman_format_code_t format
=
1568 qemu_default_pixman_format(depth
, !byteswap
);
1569 surface
= qemu_create_displaysurface_from(disp_width
,
1570 height
, format
, s
->line_offset
,
1571 s
->vram_ptr
+ (s
->start_addr
* 4));
1572 dpy_gfx_replace_surface(s
->con
, surface
);
1575 if (shift_control
== 0) {
1576 full_update
|= update_palette16(s
);
1577 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1578 v
= VGA_DRAW_LINE4D2
;
1583 } else if (shift_control
== 1) {
1584 full_update
|= update_palette16(s
);
1585 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 8) {
1586 v
= VGA_DRAW_LINE2D2
;
1592 switch(s
->get_bpp(s
)) {
1595 full_update
|= update_palette256(s
);
1596 v
= VGA_DRAW_LINE8D2
;
1600 full_update
|= update_palette256(s
);
1605 v
= s
->big_endian_fb
? VGA_DRAW_LINE15_BE
: VGA_DRAW_LINE15_LE
;
1609 v
= s
->big_endian_fb
? VGA_DRAW_LINE16_BE
: VGA_DRAW_LINE16_LE
;
1613 v
= s
->big_endian_fb
? VGA_DRAW_LINE24_BE
: VGA_DRAW_LINE24_LE
;
1617 v
= s
->big_endian_fb
? VGA_DRAW_LINE32_BE
: VGA_DRAW_LINE32_LE
;
1622 vga_draw_line
= vga_draw_line_table
[v
];
1624 if (!is_buffer_shared(surface
) && s
->cursor_invalidate
) {
1625 s
->cursor_invalidate(s
);
1629 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1630 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[VGA_CRTC_MODE
],
1631 s
->line_compare
, sr(s
, VGA_SEQ_CLOCK_MODE
));
1633 addr1
= (s
->start_addr
* 4);
1634 bwidth
= DIV_ROUND_UP(width
* bits
, 8);
1636 d
= surface_data(surface
);
1637 linesize
= surface_stride(surface
);
1641 vga_sync_dirty_bitmap(s
);
1642 if (s
->line_compare
< height
) {
1643 /* split screen mode */
1646 snap
= memory_region_snapshot_and_clear_dirty(&s
->vram
, region_start
,
1647 region_end
- region_start
,
1651 for(y
= 0; y
< height
; y
++) {
1653 if (!(s
->cr
[VGA_CRTC_MODE
] & 1)) {
1655 /* CGA compatibility handling */
1656 shift
= 14 + ((s
->cr
[VGA_CRTC_MODE
] >> 6) & 1);
1657 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1659 if (!(s
->cr
[VGA_CRTC_MODE
] & 2)) {
1660 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1662 update
= full_update
;
1663 page0
= addr
& s
->vbe_size_mask
;
1664 page1
= (addr
+ bwidth
- 1) & s
->vbe_size_mask
;
1667 } else if (page1
< page0
) {
1668 /* scanline wraps from end of video memory to the start */
1669 assert(force_shadow
);
1670 update
= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1671 page0
, s
->vbe_size
- page0
);
1672 update
|= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1675 update
= memory_region_snapshot_get_dirty(&s
->vram
, snap
,
1676 page0
, page1
- page0
);
1678 /* explicit invalidation for the hardware cursor (cirrus only) */
1679 update
|= vga_scanline_invalidated(s
, y
);
1683 if (!(is_buffer_shared(surface
))) {
1684 vga_draw_line(s
, d
, addr
, width
);
1685 if (s
->cursor_draw_line
)
1686 s
->cursor_draw_line(s
, d
, y
);
1690 /* flush to display */
1691 dpy_gfx_update(s
->con
, 0, y_start
,
1692 disp_width
, y
- y_start
);
1697 mask
= (s
->cr
[VGA_CRTC_MODE
] & 3) ^ 3;
1698 if ((y1
& mask
) == mask
)
1699 addr1
+= s
->line_offset
;
1701 multi_run
= multi_scan
;
1705 /* line compare acts on the displayed lines */
1706 if (y
== s
->line_compare
)
1711 /* flush to display */
1712 dpy_gfx_update(s
->con
, 0, y_start
,
1713 disp_width
, y
- y_start
);
1716 memset(s
->invalidated_y_table
, 0, sizeof(s
->invalidated_y_table
));
1719 static void vga_draw_blank(VGACommonState
*s
, int full_update
)
1721 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1727 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1730 w
= s
->last_scr_width
* surface_bytes_per_pixel(surface
);
1731 d
= surface_data(surface
);
1732 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1734 d
+= surface_stride(surface
);
1736 dpy_gfx_update(s
->con
, 0, 0,
1737 s
->last_scr_width
, s
->last_scr_height
);
1740 #define GMODE_TEXT 0
1741 #define GMODE_GRAPH 1
1742 #define GMODE_BLANK 2
1744 static void vga_update_display(void *opaque
)
1746 VGACommonState
*s
= opaque
;
1747 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1748 int full_update
, graphic_mode
;
1750 qemu_flush_coalesced_mmio_buffer();
1752 if (surface_bits_per_pixel(surface
) == 0) {
1756 if (!(s
->ar_index
& 0x20)) {
1757 graphic_mode
= GMODE_BLANK
;
1759 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1761 if (graphic_mode
!= s
->graphic_mode
) {
1762 s
->graphic_mode
= graphic_mode
;
1763 s
->cursor_blink_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1766 switch(graphic_mode
) {
1768 vga_draw_text(s
, full_update
);
1771 vga_draw_graphic(s
, full_update
);
1775 vga_draw_blank(s
, full_update
);
1781 /* force a full display refresh */
1782 static void vga_invalidate_display(void *opaque
)
1784 VGACommonState
*s
= opaque
;
1787 s
->last_height
= -1;
1790 void vga_common_reset(VGACommonState
*s
)
1793 memset(s
->sr
, '\0', sizeof(s
->sr
));
1794 memset(s
->sr_vbe
, '\0', sizeof(s
->sr_vbe
));
1796 memset(s
->gr
, '\0', sizeof(s
->gr
));
1798 memset(s
->ar
, '\0', sizeof(s
->ar
));
1799 s
->ar_flip_flop
= 0;
1801 memset(s
->cr
, '\0', sizeof(s
->cr
));
1807 s
->dac_sub_index
= 0;
1808 s
->dac_read_index
= 0;
1809 s
->dac_write_index
= 0;
1810 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1812 memset(s
->palette
, '\0', sizeof(s
->palette
));
1815 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1816 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID5
;
1817 s
->vbe_start_addr
= 0;
1818 s
->vbe_line_offset
= 0;
1819 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1820 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1821 s
->graphic_mode
= -1; /* force full update */
1822 s
->shift_control
= 0;
1825 s
->line_compare
= 0;
1827 s
->plane_updated
= 0;
1832 s
->last_scr_width
= 0;
1833 s
->last_scr_height
= 0;
1834 s
->cursor_start
= 0;
1836 s
->cursor_offset
= 0;
1837 s
->big_endian_fb
= s
->default_endian_fb
;
1838 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1839 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1840 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1841 switch (vga_retrace_method
) {
1842 case VGA_RETRACE_DUMB
:
1844 case VGA_RETRACE_PRECISE
:
1845 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1848 vga_update_memory_access(s
);
1851 static void vga_reset(void *opaque
)
1853 VGACommonState
*s
= opaque
;
1854 vga_common_reset(s
);
1857 #define TEXTMODE_X(x) ((x) % width)
1858 #define TEXTMODE_Y(x) ((x) / width)
1859 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1860 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1861 /* relay text rendering to the display driver
1862 * instead of doing a full vga_update_display() */
1863 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1865 VGACommonState
*s
= opaque
;
1866 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1867 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1869 console_ch_t
*dst
, val
;
1870 char msg_buffer
[80];
1871 int full_update
= 0;
1873 qemu_flush_coalesced_mmio_buffer();
1875 if (!(s
->ar_index
& 0x20)) {
1876 graphic_mode
= GMODE_BLANK
;
1878 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1880 if (graphic_mode
!= s
->graphic_mode
) {
1881 s
->graphic_mode
= graphic_mode
;
1884 if (s
->last_width
== -1) {
1889 switch (graphic_mode
) {
1891 /* TODO: update palette */
1892 full_update
|= update_basic_params(s
);
1894 /* total width & height */
1895 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1897 if (!(sr(s
, VGA_SEQ_CLOCK_MODE
) & VGA_SR01_CHAR_CLK_8DOTS
)) {
1900 if (sr(s
, VGA_SEQ_CLOCK_MODE
) & 0x08) {
1901 cw
= 16; /* NOTE: no 18 pixel wide */
1903 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1904 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1905 /* ugly hack for CGA 160x100x16 - explain me the logic */
1908 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1909 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1910 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1911 height
= (height
+ 1) / cheight
;
1914 size
= (height
* width
);
1915 if (size
> CH_ATTR_SIZE
) {
1919 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
1924 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1925 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
1926 s
->last_scr_width
= width
* cw
;
1927 s
->last_scr_height
= height
* cheight
;
1928 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1929 dpy_text_resize(s
->con
, width
, height
);
1931 s
->last_width
= width
;
1932 s
->last_height
= height
;
1933 s
->last_ch
= cheight
;
1939 s
->full_update_gfx
= 1;
1941 if (s
->full_update_text
) {
1942 s
->full_update_text
= 0;
1946 /* Update "hardware" cursor */
1947 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1948 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1949 if (cursor_offset
!= s
->cursor_offset
||
1950 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1951 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
|| full_update
) {
1952 cursor_visible
= !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20);
1953 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
1954 dpy_text_cursor(s
->con
,
1955 TEXTMODE_X(cursor_offset
),
1956 TEXTMODE_Y(cursor_offset
));
1958 dpy_text_cursor(s
->con
, -1, -1);
1959 s
->cursor_offset
= cursor_offset
;
1960 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1961 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1964 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
1968 for (i
= 0; i
< size
; src
++, dst
++, i
++)
1969 console_write_ch(dst
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1971 dpy_text_update(s
->con
, 0, 0, width
, height
);
1975 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
1976 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1984 for (; i
< size
; src
++, dst
++, i
++) {
1985 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1992 if (c_min
<= c_max
) {
1993 i
= TEXTMODE_Y(c_min
);
1994 dpy_text_update(s
->con
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
2003 s
->get_resolution(s
, &width
, &height
);
2004 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
2012 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
2016 /* Display a message */
2018 s
->last_height
= height
= 3;
2019 dpy_text_cursor(s
->con
, -1, -1);
2020 dpy_text_resize(s
->con
, s
->last_width
, height
);
2022 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
2023 console_write_ch(dst
++, ' ');
2025 size
= strlen(msg_buffer
);
2026 width
= (s
->last_width
- size
) / 2;
2027 dst
= chardata
+ s
->last_width
+ width
;
2028 for (i
= 0; i
< size
; i
++)
2029 console_write_ch(dst
++, ATTR2CHTYPE(msg_buffer
[i
], QEMU_COLOR_BLUE
,
2030 QEMU_COLOR_BLACK
, 1));
2032 dpy_text_update(s
->con
, 0, 0, s
->last_width
, height
);
2035 static uint64_t vga_mem_read(void *opaque
, hwaddr addr
,
2038 VGACommonState
*s
= opaque
;
2040 return vga_mem_readb(s
, addr
);
2043 static void vga_mem_write(void *opaque
, hwaddr addr
,
2044 uint64_t data
, unsigned size
)
2046 VGACommonState
*s
= opaque
;
2048 vga_mem_writeb(s
, addr
, data
);
2051 const MemoryRegionOps vga_mem_ops
= {
2052 .read
= vga_mem_read
,
2053 .write
= vga_mem_write
,
2054 .endianness
= DEVICE_LITTLE_ENDIAN
,
2056 .min_access_size
= 1,
2057 .max_access_size
= 1,
2061 static int vga_common_post_load(void *opaque
, int version_id
)
2063 VGACommonState
*s
= opaque
;
2066 s
->graphic_mode
= -1;
2067 vbe_update_vgaregs(s
);
2068 vga_update_memory_access(s
);
2072 static bool vga_endian_state_needed(void *opaque
)
2074 VGACommonState
*s
= opaque
;
2077 * Only send the endian state if it's different from the
2078 * default one, thus ensuring backward compatibility for
2079 * migration of the common case
2081 return s
->default_endian_fb
!= s
->big_endian_fb
;
2084 static const VMStateDescription vmstate_vga_endian
= {
2085 .name
= "vga.endian",
2087 .minimum_version_id
= 1,
2088 .needed
= vga_endian_state_needed
,
2089 .fields
= (VMStateField
[]) {
2090 VMSTATE_BOOL(big_endian_fb
, VGACommonState
),
2091 VMSTATE_END_OF_LIST()
2095 const VMStateDescription vmstate_vga_common
= {
2098 .minimum_version_id
= 2,
2099 .post_load
= vga_common_post_load
,
2100 .fields
= (VMStateField
[]) {
2101 VMSTATE_UINT32(latch
, VGACommonState
),
2102 VMSTATE_UINT8(sr_index
, VGACommonState
),
2103 VMSTATE_PARTIAL_BUFFER(sr
, VGACommonState
, 8),
2104 VMSTATE_UINT8(gr_index
, VGACommonState
),
2105 VMSTATE_PARTIAL_BUFFER(gr
, VGACommonState
, 16),
2106 VMSTATE_UINT8(ar_index
, VGACommonState
),
2107 VMSTATE_BUFFER(ar
, VGACommonState
),
2108 VMSTATE_INT32(ar_flip_flop
, VGACommonState
),
2109 VMSTATE_UINT8(cr_index
, VGACommonState
),
2110 VMSTATE_BUFFER(cr
, VGACommonState
),
2111 VMSTATE_UINT8(msr
, VGACommonState
),
2112 VMSTATE_UINT8(fcr
, VGACommonState
),
2113 VMSTATE_UINT8(st00
, VGACommonState
),
2114 VMSTATE_UINT8(st01
, VGACommonState
),
2116 VMSTATE_UINT8(dac_state
, VGACommonState
),
2117 VMSTATE_UINT8(dac_sub_index
, VGACommonState
),
2118 VMSTATE_UINT8(dac_read_index
, VGACommonState
),
2119 VMSTATE_UINT8(dac_write_index
, VGACommonState
),
2120 VMSTATE_BUFFER(dac_cache
, VGACommonState
),
2121 VMSTATE_BUFFER(palette
, VGACommonState
),
2123 VMSTATE_INT32(bank_offset
, VGACommonState
),
2124 VMSTATE_UINT8_EQUAL(is_vbe_vmstate
, VGACommonState
, NULL
),
2125 VMSTATE_UINT16(vbe_index
, VGACommonState
),
2126 VMSTATE_UINT16_ARRAY(vbe_regs
, VGACommonState
, VBE_DISPI_INDEX_NB
),
2127 VMSTATE_UINT32(vbe_start_addr
, VGACommonState
),
2128 VMSTATE_UINT32(vbe_line_offset
, VGACommonState
),
2129 VMSTATE_UINT32(vbe_bank_mask
, VGACommonState
),
2130 VMSTATE_END_OF_LIST()
2132 .subsections
= (const VMStateDescription
*[]) {
2133 &vmstate_vga_endian
,
2138 static const GraphicHwOps vga_ops
= {
2139 .invalidate
= vga_invalidate_display
,
2140 .gfx_update
= vga_update_display
,
2141 .text_update
= vga_update_text
,
2144 static inline uint32_t uint_clamp(uint32_t val
, uint32_t vmin
, uint32_t vmax
)
2155 void vga_common_init(VGACommonState
*s
, Object
*obj
, bool global_vmstate
)
2159 for(i
= 0;i
< 256; i
++) {
2161 for(j
= 0; j
< 8; j
++) {
2162 v
|= ((i
>> j
) & 1) << (j
* 4);
2167 for(j
= 0; j
< 4; j
++) {
2168 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2172 for(i
= 0; i
< 16; i
++) {
2174 for(j
= 0; j
< 4; j
++) {
2177 v
|= b
<< (2 * j
+ 1);
2182 s
->vram_size_mb
= uint_clamp(s
->vram_size_mb
, 1, 512);
2183 s
->vram_size_mb
= pow2ceil(s
->vram_size_mb
);
2184 s
->vram_size
= s
->vram_size_mb
<< 20;
2187 s
->vbe_size
= s
->vram_size
;
2189 s
->vbe_size_mask
= s
->vbe_size
- 1;
2191 s
->is_vbe_vmstate
= 1;
2192 memory_region_init_ram_nomigrate(&s
->vram
, obj
, "vga.vram", s
->vram_size
,
2194 vmstate_register_ram(&s
->vram
, global_vmstate
? NULL
: DEVICE(obj
));
2195 xen_register_framebuffer(&s
->vram
);
2196 s
->vram_ptr
= memory_region_get_ram_ptr(&s
->vram
);
2197 s
->get_bpp
= vga_get_bpp
;
2198 s
->get_offsets
= vga_get_offsets
;
2199 s
->get_resolution
= vga_get_resolution
;
2200 s
->hw_ops
= &vga_ops
;
2201 switch (vga_retrace_method
) {
2202 case VGA_RETRACE_DUMB
:
2203 s
->retrace
= vga_dumb_retrace
;
2204 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2207 case VGA_RETRACE_PRECISE
:
2208 s
->retrace
= vga_precise_retrace
;
2209 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2214 * Set default fb endian based on target, could probably be turned
2215 * into a device attribute set by the machine/platform to remove
2216 * all target endian dependencies from this file.
2218 #ifdef TARGET_WORDS_BIGENDIAN
2219 s
->default_endian_fb
= true;
2221 s
->default_endian_fb
= false;
2223 vga_dirty_log_start(s
);
2226 static const MemoryRegionPortio vga_portio_list
[] = {
2227 { 0x04, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3b4 */
2228 { 0x0a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3ba */
2229 { 0x10, 16, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3c0 */
2230 { 0x24, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3d4 */
2231 { 0x2a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3da */
2232 PORTIO_END_OF_LIST(),
2235 static const MemoryRegionPortio vbe_portio_list
[] = {
2236 { 0, 1, 2, .read
= vbe_ioport_read_index
, .write
= vbe_ioport_write_index
},
2238 { 1, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2240 { 2, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2241 PORTIO_END_OF_LIST(),
2244 /* Used by both ISA and PCI */
2245 MemoryRegion
*vga_init_io(VGACommonState
*s
, Object
*obj
,
2246 const MemoryRegionPortio
**vga_ports
,
2247 const MemoryRegionPortio
**vbe_ports
)
2249 MemoryRegion
*vga_mem
;
2251 *vga_ports
= vga_portio_list
;
2252 *vbe_ports
= vbe_portio_list
;
2254 vga_mem
= g_malloc(sizeof(*vga_mem
));
2255 memory_region_init_io(vga_mem
, obj
, &vga_mem_ops
, s
,
2256 "vga-lowmem", 0x20000);
2257 memory_region_set_flush_coalesced(vga_mem
);
2262 void vga_init(VGACommonState
*s
, Object
*obj
, MemoryRegion
*address_space
,
2263 MemoryRegion
*address_space_io
, bool init_vga_ports
)
2265 MemoryRegion
*vga_io_memory
;
2266 const MemoryRegionPortio
*vga_ports
, *vbe_ports
;
2268 qemu_register_reset(vga_reset
, s
);
2272 s
->legacy_address_space
= address_space
;
2274 vga_io_memory
= vga_init_io(s
, obj
, &vga_ports
, &vbe_ports
);
2275 memory_region_add_subregion_overlap(address_space
,
2279 memory_region_set_coalescing(vga_io_memory
);
2280 if (init_vga_ports
) {
2281 portio_list_init(&s
->vga_port_list
, obj
, vga_ports
, s
, "vga");
2282 portio_list_set_flush_coalesced(&s
->vga_port_list
);
2283 portio_list_add(&s
->vga_port_list
, address_space_io
, 0x3b0);
2286 portio_list_init(&s
->vbe_port_list
, obj
, vbe_ports
, s
, "vbe");
2287 portio_list_add(&s
->vbe_port_list
, address_space_io
, 0x1ce);
2291 void vga_init_vbe(VGACommonState
*s
, Object
*obj
, MemoryRegion
*system_memory
)
2293 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2294 * so use an alias to avoid double-mapping the same region.
2296 memory_region_init_alias(&s
->vram_vbe
, obj
, "vram.vbe",
2297 &s
->vram
, 0, memory_region_size(&s
->vram
));
2298 /* XXX: use optimized standard vga accesses */
2299 memory_region_add_subregion(system_memory
,
2300 VBE_DISPI_LFB_PHYSICAL_ADDRESS
,