2 * Samsung exynos4210 Display Controller (FIMD)
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "hw/sysbus.h"
28 #include "ui/console.h"
29 #include "ui/pixel_ops.h"
30 #include "qemu/bswap.h"
32 /* Debug messages configuration */
33 #define EXYNOS4210_FIMD_DEBUG 0
34 #define EXYNOS4210_FIMD_MODE_TRACE 0
36 #if EXYNOS4210_FIMD_DEBUG == 0
37 #define DPRINT_L1(fmt, args...) do { } while (0)
38 #define DPRINT_L2(fmt, args...) do { } while (0)
39 #define DPRINT_ERROR(fmt, args...) do { } while (0)
40 #elif EXYNOS4210_FIMD_DEBUG == 1
41 #define DPRINT_L1(fmt, args...) \
42 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
43 #define DPRINT_L2(fmt, args...) do { } while (0)
44 #define DPRINT_ERROR(fmt, args...) \
45 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
47 #define DPRINT_L1(fmt, args...) \
48 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
49 #define DPRINT_L2(fmt, args...) \
50 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
51 #define DPRINT_ERROR(fmt, args...) \
52 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
55 #if EXYNOS4210_FIMD_MODE_TRACE == 0
56 #define DPRINT_TRACE(fmt, args...) do { } while (0)
58 #define DPRINT_TRACE(fmt, args...) \
59 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
62 #define NUM_OF_WINDOWS 5
63 #define FIMD_REGS_SIZE 0x4114
65 /* Video main control registers */
66 #define FIMD_VIDCON0 0x0000
67 #define FIMD_VIDCON1 0x0004
68 #define FIMD_VIDCON2 0x0008
69 #define FIMD_VIDCON3 0x000C
70 #define FIMD_VIDCON0_ENVID_F (1 << 0)
71 #define FIMD_VIDCON0_ENVID (1 << 1)
72 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
73 #define FIMD_VIDCON1_ROMASK 0x07FFE000
75 /* Video time control registers */
76 #define FIMD_VIDTCON_START 0x10
77 #define FIMD_VIDTCON_END 0x1C
78 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF
79 #define FIMD_VIDTCON2_HOR_SHIFT 0
80 #define FIMD_VIDTCON2_VER_SHIFT 11
82 /* Window control registers */
83 #define FIMD_WINCON_START 0x0020
84 #define FIMD_WINCON_END 0x0030
85 #define FIMD_WINCON_ROMASK 0x82200000
86 #define FIMD_WINCON_ENWIN (1 << 0)
87 #define FIMD_WINCON_BLD_PIX (1 << 6)
88 #define FIMD_WINCON_ALPHA_MUL (1 << 7)
89 #define FIMD_WINCON_ALPHA_SEL (1 << 1)
90 #define FIMD_WINCON_SWAP 0x078000
91 #define FIMD_WINCON_SWAP_SHIFT 15
92 #define FIMD_WINCON_SWAP_WORD 0x1
93 #define FIMD_WINCON_SWAP_HWORD 0x2
94 #define FIMD_WINCON_SWAP_BYTE 0x4
95 #define FIMD_WINCON_SWAP_BITS 0x8
96 #define FIMD_WINCON_BUFSTAT_L (1 << 21)
97 #define FIMD_WINCON_BUFSTAT_H (1 << 31)
98 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31))
99 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
100 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
101 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31))
102 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30))
103 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
104 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
105 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
106 #define FIMD_WINCON_BUFMODE (1 << 14)
107 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
108 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7)
109 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
110 #define WIN_BPP_MODE_WITH_ALPHA(w) \
111 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
113 /* Shadow control register */
114 #define FIMD_SHADOWCON 0x0034
115 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
116 /* Channel mapping control register */
117 #define FIMD_WINCHMAP 0x003C
119 /* Window position control registers */
120 #define FIMD_VIDOSD_START 0x0040
121 #define FIMD_VIDOSD_END 0x0088
122 #define FIMD_VIDOSD_COORD_MASK 0x07FF
123 #define FIMD_VIDOSD_HOR_SHIFT 11
124 #define FIMD_VIDOSD_VER_SHIFT 0
125 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
126 #define FIMD_VIDOSD_AEN0_SHIFT 12
127 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
129 /* Frame buffer address registers */
130 #define FIMD_VIDWADD0_START 0x00A0
131 #define FIMD_VIDWADD0_END 0x00C4
132 #define FIMD_VIDWADD0_END 0x00C4
133 #define FIMD_VIDWADD1_START 0x00D0
134 #define FIMD_VIDWADD1_END 0x00F4
135 #define FIMD_VIDWADD2_START 0x0100
136 #define FIMD_VIDWADD2_END 0x0110
137 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
138 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF
139 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
140 #define FIMD_VIDW0ADD0_B2 0x20A0
141 #define FIMD_VIDW4ADD0_B2 0x20C0
143 /* Video interrupt control registers */
144 #define FIMD_VIDINTCON0 0x130
145 #define FIMD_VIDINTCON1 0x134
147 /* Window color key registers */
148 #define FIMD_WKEYCON_START 0x140
149 #define FIMD_WKEYCON_END 0x15C
150 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
151 #define FIMD_WKEYCON0_CTL_SHIFT 24
152 #define FIMD_WKEYCON0_DIRCON (1 << 24)
153 #define FIMD_WKEYCON0_KEYEN (1 << 25)
154 #define FIMD_WKEYCON0_KEYBLEN (1 << 26)
155 /* Window color key alpha control register */
156 #define FIMD_WKEYALPHA_START 0x160
157 #define FIMD_WKEYALPHA_END 0x16C
159 /* Dithering control register */
160 #define FIMD_DITHMODE 0x170
162 /* Window alpha control registers */
163 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
164 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
165 #define FIMD_VIDWALPHA_START 0x21C
166 #define FIMD_VIDWALPHA_END 0x240
168 /* Window color map registers */
169 #define FIMD_WINMAP_START 0x180
170 #define FIMD_WINMAP_END 0x190
171 #define FIMD_WINMAP_EN (1 << 24)
172 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
174 /* Window palette control registers */
175 #define FIMD_WPALCON_HIGH 0x019C
176 #define FIMD_WPALCON_LOW 0x01A0
177 #define FIMD_WPALCON_UPDATEEN (1 << 9)
178 #define FIMD_WPAL_W0PAL_L 0x07
179 #define FIMD_WPAL_W0PAL_L_SHT 0
180 #define FIMD_WPAL_W1PAL_L 0x07
181 #define FIMD_WPAL_W1PAL_L_SHT 3
182 #define FIMD_WPAL_W2PAL_L 0x01
183 #define FIMD_WPAL_W2PAL_L_SHT 6
184 #define FIMD_WPAL_W2PAL_H 0x06
185 #define FIMD_WPAL_W2PAL_H_SHT 8
186 #define FIMD_WPAL_W3PAL_L 0x01
187 #define FIMD_WPAL_W3PAL_L_SHT 7
188 #define FIMD_WPAL_W3PAL_H 0x06
189 #define FIMD_WPAL_W3PAL_H_SHT 12
190 #define FIMD_WPAL_W4PAL_L 0x01
191 #define FIMD_WPAL_W4PAL_L_SHT 8
192 #define FIMD_WPAL_W4PAL_H 0x06
193 #define FIMD_WPAL_W4PAL_H_SHT 16
195 /* Trigger control registers */
196 #define FIMD_TRIGCON 0x01A4
197 #define FIMD_TRIGCON_ROMASK 0x00000004
199 /* LCD I80 Interface Control */
200 #define FIMD_I80IFCON_START 0x01B0
201 #define FIMD_I80IFCON_END 0x01BC
202 /* Color gain control register */
203 #define FIMD_COLORGAINCON 0x01C0
204 /* LCD i80 Interface Command Control */
205 #define FIMD_LDI_CMDCON0 0x01D0
206 #define FIMD_LDI_CMDCON1 0x01D4
207 /* I80 System Interface Manual Command Control */
208 #define FIMD_SIFCCON0 0x01E0
209 #define FIMD_SIFCCON2 0x01E8
211 /* Hue Control Registers */
212 #define FIMD_HUECOEFCR_START 0x01EC
213 #define FIMD_HUECOEFCR_END 0x01F4
214 #define FIMD_HUECOEFCB_START 0x01FC
215 #define FIMD_HUECOEFCB_END 0x0208
216 #define FIMD_HUEOFFSET 0x020C
218 /* Video interrupt control registers */
219 #define FIMD_VIDINT_INTFIFOPEND (1 << 0)
220 #define FIMD_VIDINT_INTFRMPEND (1 << 1)
221 #define FIMD_VIDINT_INTI80PEND (1 << 2)
222 #define FIMD_VIDINT_INTEN (1 << 0)
223 #define FIMD_VIDINT_INTFIFOEN (1 << 1)
224 #define FIMD_VIDINT_INTFRMEN (1 << 12)
225 #define FIMD_VIDINT_I80IFDONE (1 << 17)
227 /* Window blend equation control registers */
228 #define FIMD_BLENDEQ_START 0x0244
229 #define FIMD_BLENDEQ_END 0x0250
230 #define FIMD_BLENDCON 0x0260
231 #define FIMD_ALPHA_8BIT (1 << 0)
232 #define FIMD_BLENDEQ_COEF_MASK 0xF
234 /* Window RTQOS Control Registers */
235 #define FIMD_WRTQOSCON_START 0x0264
236 #define FIMD_WRTQOSCON_END 0x0274
238 /* LCD I80 Interface Command */
239 #define FIMD_I80IFCMD_START 0x0280
240 #define FIMD_I80IFCMD_END 0x02AC
242 /* Shadow windows control registers */
243 #define FIMD_SHD_ADD0_START 0x40A0
244 #define FIMD_SHD_ADD0_END 0x40C0
245 #define FIMD_SHD_ADD1_START 0x40D0
246 #define FIMD_SHD_ADD1_END 0x40F0
247 #define FIMD_SHD_ADD2_START 0x4100
248 #define FIMD_SHD_ADD2_END 0x4110
251 #define FIMD_PAL_MEM_START 0x2400
252 #define FIMD_PAL_MEM_END 0x37FC
253 /* Palette memory aliases for windows 0 and 1 */
254 #define FIMD_PALMEM_AL_START 0x0400
255 #define FIMD_PALMEM_AL_END 0x0BFC
259 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
264 typedef void pixel_to_rgb_func(uint32_t pixel
, rgba
*p
);
265 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow
;
267 struct Exynos4210fimdWindow
{
268 uint32_t wincon
; /* Window control register */
269 uint32_t buf_start
[3]; /* Start address for video frame buffer */
270 uint32_t buf_end
[3]; /* End address for video frame buffer */
271 uint32_t keycon
[2]; /* Window color key registers */
272 uint32_t keyalpha
; /* Color key alpha control register */
273 uint32_t winmap
; /* Window color map register */
274 uint32_t blendeq
; /* Window blending equation control register */
275 uint32_t rtqoscon
; /* Window RTQOS Control Registers */
276 uint32_t palette
[256]; /* Palette RAM */
277 uint32_t shadow_buf_start
; /* Start address of shadow frame buffer */
278 uint32_t shadow_buf_end
; /* End address of shadow frame buffer */
279 uint32_t shadow_buf_size
; /* Virtual shadow screen width */
281 pixel_to_rgb_func
*pixel_to_rgb
;
282 void (*draw_line
)(Exynos4210fimdWindow
*w
, uint8_t *src
, uint8_t *dst
,
284 uint32_t (*get_alpha
)(Exynos4210fimdWindow
*w
, uint32_t pix_a
);
285 uint16_t lefttop_x
, lefttop_y
; /* VIDOSD0 register */
286 uint16_t rightbot_x
, rightbot_y
; /* VIDOSD1 register */
287 uint32_t osdsize
; /* VIDOSD2&3 register */
288 uint32_t alpha_val
[2]; /* VIDOSD2&3, VIDWALPHA registers */
289 uint16_t virtpage_width
; /* VIDWADD2 register */
290 uint16_t virtpage_offsize
; /* VIDWADD2 register */
291 MemoryRegionSection mem_section
; /* RAM fragment containing framebuffer */
292 uint8_t *host_fb_addr
; /* Host pointer to window's framebuffer */
293 hwaddr fb_len
; /* Framebuffer length */
296 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
297 #define EXYNOS4210_FIMD(obj) \
298 OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)
301 SysBusDevice parent_obj
;
304 QemuConsole
*console
;
307 uint32_t vidcon
[4]; /* Video main control registers 0-3 */
308 uint32_t vidtcon
[4]; /* Video time control registers 0-3 */
309 uint32_t shadowcon
; /* Window shadow control register */
310 uint32_t winchmap
; /* Channel mapping control register */
311 uint32_t vidintcon
[2]; /* Video interrupt control registers */
312 uint32_t dithmode
; /* Dithering control register */
313 uint32_t wpalcon
[2]; /* Window palette control registers */
314 uint32_t trigcon
; /* Trigger control register */
315 uint32_t i80ifcon
[4]; /* I80 interface control registers */
316 uint32_t colorgaincon
; /* Color gain control register */
317 uint32_t ldi_cmdcon
[2]; /* LCD I80 interface command control */
318 uint32_t sifccon
[3]; /* I80 System Interface Manual Command Control */
319 uint32_t huecoef_cr
[4]; /* Hue control registers */
320 uint32_t huecoef_cb
[4]; /* Hue control registers */
321 uint32_t hueoffset
; /* Hue offset control register */
322 uint32_t blendcon
; /* Blending control register */
323 uint32_t i80ifcmd
[12]; /* LCD I80 Interface Command */
325 Exynos4210fimdWindow window
[5]; /* Window-specific registers */
326 uint8_t *ifb
; /* Internal frame buffer */
327 bool invalidate
; /* Image needs to be redrawn */
328 bool enabled
; /* Display controller is enabled */
329 } Exynos4210fimdState
;
331 /* Perform byte/halfword/word swap of data according to WINCON */
332 static inline void fimd_swap_data(unsigned int swap_ctl
, uint64_t *data
)
338 if (swap_ctl
& FIMD_WINCON_SWAP_BITS
) {
340 for (i
= 0; i
< 64; i
++) {
341 if (x
& (1ULL << (63 - i
))) {
348 if (swap_ctl
& FIMD_WINCON_SWAP_BYTE
) {
352 if (swap_ctl
& FIMD_WINCON_SWAP_HWORD
) {
353 x
= ((x
& 0x000000000000FFFFULL
) << 48) |
354 ((x
& 0x00000000FFFF0000ULL
) << 16) |
355 ((x
& 0x0000FFFF00000000ULL
) >> 16) |
356 ((x
& 0xFFFF000000000000ULL
) >> 48);
359 if (swap_ctl
& FIMD_WINCON_SWAP_WORD
) {
360 x
= ((x
& 0x00000000FFFFFFFFULL
) << 32) |
361 ((x
& 0xFFFFFFFF00000000ULL
) >> 32);
367 /* Conversion routines of Pixel data from frame buffer area to internal RGBA
368 * pixel representation.
369 * Every color component internally represented as 8-bit value. If original
370 * data has less than 8 bit for component, data is extended to 8 bit. For
371 * example, if blue component has only two possible values 0 and 1 it will be
372 * extended to 0 and 0xFF */
374 /* One bit for alpha representation */
375 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
376 static void N(uint32_t pixel, rgba *p) \
378 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
379 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
381 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
382 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
384 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
385 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
387 p->a = (pixel & 0x1); \
390 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb
, 4, 4, 4)
391 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb
, 5, 5, 5)
392 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb
, 6, 6, 6)
393 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb
, 6, 6, 5)
394 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb
, 8, 8, 8)
395 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb
, 8, 8, 7)
397 /* Alpha component is always zero */
398 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
399 static void N(uint32_t pixel, rgba *p) \
401 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
402 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
404 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
405 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
407 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
408 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
412 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb
, 5, 6, 5)
413 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb
, 5, 5, 5)
414 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb
, 6, 6, 6)
415 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb
, 8, 8, 8)
417 /* Alpha component has some meaningful value */
418 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
419 static void N(uint32_t pixel, rgba *p) \
421 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
422 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
424 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
425 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
427 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
428 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
430 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
431 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
432 p->a = p->a | (p->a << 8) | (p->a << 16); \
435 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb
, 4, 4, 4, 4)
436 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb
, 8, 8, 8, 8)
438 /* Lookup table to extent 2-bit color component to 8 bit */
439 static const uint8_t pixel_lutable_2b
[4] = {
440 0x0, 0x55, 0xAA, 0xFF
442 /* Lookup table to extent 3-bit color component to 8 bit */
443 static const uint8_t pixel_lutable_3b
[8] = {
444 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
446 /* Special case for a232 bpp mode */
447 static void pixel_a232_to_rgb(uint32_t pixel
, rgba
*p
)
449 p
->b
= pixel_lutable_2b
[(pixel
& 0x3)];
451 p
->g
= pixel_lutable_3b
[(pixel
& 0x7)];
453 p
->r
= pixel_lutable_2b
[(pixel
& 0x3)];
455 p
->a
= (pixel
& 0x1);
458 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
459 * for all three color components */
460 static void pixel_1555_to_rgb(uint32_t pixel
, rgba
*p
)
462 uint8_t comm
= (pixel
>> 15) & 1;
463 p
->b
= ((((pixel
& 0x1F) << 1) | comm
) << 2) | ((pixel
>> 3) & 0x3);
465 p
->g
= ((((pixel
& 0x1F) << 1) | comm
) << 2) | ((pixel
>> 3) & 0x3);
467 p
->r
= ((((pixel
& 0x1F) << 1) | comm
) << 2) | ((pixel
>> 3) & 0x3);
471 /* Put/get pixel to/from internal LCD Controller framebuffer */
473 static int put_pixel_ifb(const rgba p
, uint8_t *d
)
475 *(uint8_t *)d
++ = p
.r
;
476 *(uint8_t *)d
++ = p
.g
;
477 *(uint8_t *)d
++ = p
.b
;
478 *(uint32_t *)d
= p
.a
;
482 static int get_pixel_ifb(const uint8_t *s
, rgba
*p
)
484 p
->r
= *(uint8_t *)s
++;
485 p
->g
= *(uint8_t *)s
++;
486 p
->b
= *(uint8_t *)s
++;
487 p
->a
= (*(uint32_t *)s
) & 0x00FFFFFF;
491 static pixel_to_rgb_func
*palette_data_format
[8] = {
492 [0] = pixel_565_to_rgb
,
493 [1] = pixel_a555_to_rgb
,
494 [2] = pixel_666_to_rgb
,
495 [3] = pixel_a665_to_rgb
,
496 [4] = pixel_a666_to_rgb
,
497 [5] = pixel_888_to_rgb
,
498 [6] = pixel_a888_to_rgb
,
499 [7] = pixel_8888_to_rgb
502 /* Returns Index in palette data formats table for given window number WINDOW */
504 exynos4210_fimd_palette_format(Exynos4210fimdState
*s
, int window
)
510 ret
= (s
->wpalcon
[1] >> FIMD_WPAL_W0PAL_L_SHT
) & FIMD_WPAL_W0PAL_L
;
516 ret
= (s
->wpalcon
[1] >> FIMD_WPAL_W1PAL_L_SHT
) & FIMD_WPAL_W1PAL_L
;
522 ret
= ((s
->wpalcon
[0] >> FIMD_WPAL_W2PAL_H_SHT
) & FIMD_WPAL_W2PAL_H
) |
523 ((s
->wpalcon
[1] >> FIMD_WPAL_W2PAL_L_SHT
) & FIMD_WPAL_W2PAL_L
);
526 ret
= ((s
->wpalcon
[0] >> FIMD_WPAL_W3PAL_H_SHT
) & FIMD_WPAL_W3PAL_H
) |
527 ((s
->wpalcon
[1] >> FIMD_WPAL_W3PAL_L_SHT
) & FIMD_WPAL_W3PAL_L
);
530 ret
= ((s
->wpalcon
[0] >> FIMD_WPAL_W4PAL_H_SHT
) & FIMD_WPAL_W4PAL_H
) |
531 ((s
->wpalcon
[1] >> FIMD_WPAL_W4PAL_L_SHT
) & FIMD_WPAL_W4PAL_L
);
534 hw_error("exynos4210.fimd: incorrect window number %d\n", window
);
541 #define FIMD_1_MINUS_COLOR(x) \
542 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
543 (0xFF0000 - ((x) & 0xFF0000)))
544 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
545 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
547 /* Multiply three lower bytes of two 32-bit words with each other.
548 * Each byte with values 0-255 is considered as a number with possible values
549 * in a range [0 - 1] */
550 static inline uint32_t fimd_mult_each_byte(uint32_t a
, uint32_t b
)
555 ret
= ((tmp
= (((a
& 0xFF) * (b
& 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp
;
556 ret
|= ((tmp
= ((((a
>> 8) & 0xFF) * ((b
>> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
558 ret
|= ((tmp
= ((((a
>> 16) & 0xFF) * ((b
>> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
559 0xFF0000 : tmp
<< 16;
563 /* For each corresponding bytes of two 32-bit words: (a*b + c*d)
564 * Byte values 0-255 are mapped to a range [0 .. 1] */
565 static inline uint32_t
566 fimd_mult_and_sum_each_byte(uint32_t a
, uint32_t b
, uint32_t c
, uint32_t d
)
571 ret
= ((tmp
= (((a
& 0xFF) * (b
& 0xFF) + (c
& 0xFF) * (d
& 0xFF)) / 0xFF))
572 > 0xFF) ? 0xFF : tmp
;
573 ret
|= ((tmp
= ((((a
>> 8) & 0xFF) * ((b
>> 8) & 0xFF) + ((c
>> 8) & 0xFF) *
574 ((d
>> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp
<< 8;
575 ret
|= ((tmp
= ((((a
>> 16) & 0xFF) * ((b
>> 16) & 0xFF) +
576 ((c
>> 16) & 0xFF) * ((d
>> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
577 0xFF0000 : tmp
<< 16;
581 /* These routines cover all possible sources of window's transparent factor
582 * used in blending equation. Choice of routine is affected by WPALCON
583 * registers, BLENDCON register and window's WINCON register */
585 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
591 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
593 return EXTEND_LOWER_HALFBYTE(pix_a
);
597 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
599 return EXTEND_UPPER_HALFBYTE(pix_a
);
602 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
604 return fimd_mult_each_byte(pix_a
, w
->alpha_val
[0]);
607 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
609 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a
),
610 EXTEND_UPPER_HALFBYTE(w
->alpha_val
[0]));
613 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
615 return w
->alpha_val
[pix_a
];
618 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
620 return EXTEND_UPPER_HALFBYTE(w
->alpha_val
[pix_a
]);
623 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
625 return w
->alpha_val
[(w
->wincon
& FIMD_WINCON_ALPHA_SEL
) ? 1 : 0];
628 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow
*w
, uint32_t pix_a
)
630 return EXTEND_UPPER_HALFBYTE(w
->alpha_val
[(w
->wincon
&
631 FIMD_WINCON_ALPHA_SEL
) ? 1 : 0]);
634 /* Updates currently active alpha value get function for specified window */
635 static void fimd_update_get_alpha(Exynos4210fimdState
*s
, int win
)
637 Exynos4210fimdWindow
*w
= &s
->window
[win
];
638 const bool alpha_is_8bit
= s
->blendcon
& FIMD_ALPHA_8BIT
;
640 if (w
->wincon
& FIMD_WINCON_BLD_PIX
) {
641 if ((w
->wincon
& FIMD_WINCON_ALPHA_SEL
) && WIN_BPP_MODE_WITH_ALPHA(w
)) {
642 /* In this case, alpha component contains meaningful value */
643 if (w
->wincon
& FIMD_WINCON_ALPHA_MUL
) {
644 w
->get_alpha
= alpha_is_8bit
?
645 fimd_get_alpha_mult
: fimd_get_alpha_mult_ext
;
647 w
->get_alpha
= alpha_is_8bit
?
648 fimd_get_alpha_pix
: fimd_get_alpha_pix_extlow
;
651 if (IS_PALETTIZED_MODE(w
) &&
652 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s
, win
))) {
653 /* Alpha component has 8-bit numeric value */
654 w
->get_alpha
= alpha_is_8bit
?
655 fimd_get_alpha_pix
: fimd_get_alpha_pix_exthigh
;
657 /* Alpha has only two possible values (AEN) */
658 w
->get_alpha
= alpha_is_8bit
?
659 fimd_get_alpha_aen
: fimd_get_alpha_aen_ext
;
663 w
->get_alpha
= alpha_is_8bit
? fimd_get_alpha_sel
:
664 fimd_get_alpha_sel_ext
;
668 /* Blends current window's (w) pixel (foreground pixel *ret) with background
669 * window (w_blend) pixel p_bg according to formula:
670 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
671 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
674 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow
*w
, rgba p_bg
, rgba
*ret
)
677 uint32_t bg_color
= ((p_bg
.r
& 0xFF) << 16) | ((p_bg
.g
& 0xFF) << 8) |
679 uint32_t fg_color
= ((p_fg
.r
& 0xFF) << 16) | ((p_fg
.g
& 0xFF) << 8) |
681 uint32_t alpha_fg
= p_fg
.a
;
683 /* It is possible that blending equation parameters a and b do not
684 * depend on window BLENEQ register. Account for this with first_coef */
685 enum { A_COEF
= 0, B_COEF
= 1, P_COEF
= 2, Q_COEF
= 3, COEF_NUM
= 4};
686 uint32_t first_coef
= A_COEF
;
687 uint32_t blend_param
[COEF_NUM
];
689 if (w
->keycon
[0] & FIMD_WKEYCON0_KEYEN
) {
690 uint32_t colorkey
= (w
->keycon
[1] &
691 ~(w
->keycon
[0] & FIMD_WKEYCON0_COMPKEY
)) & FIMD_WKEYCON0_COMPKEY
;
693 if ((w
->keycon
[0] & FIMD_WKEYCON0_DIRCON
) &&
694 (bg_color
& ~(w
->keycon
[0] & FIMD_WKEYCON0_COMPKEY
)) == colorkey
) {
695 /* Foreground pixel is displayed */
696 if (w
->keycon
[0] & FIMD_WKEYCON0_KEYBLEN
) {
697 alpha_fg
= w
->keyalpha
;
698 blend_param
[A_COEF
] = alpha_fg
;
699 blend_param
[B_COEF
] = FIMD_1_MINUS_COLOR(alpha_fg
);
702 blend_param
[A_COEF
] = 0xFFFFFF;
703 blend_param
[B_COEF
] = 0x0;
706 } else if ((w
->keycon
[0] & FIMD_WKEYCON0_DIRCON
) == 0 &&
707 (fg_color
& ~(w
->keycon
[0] & FIMD_WKEYCON0_COMPKEY
)) == colorkey
) {
708 /* Background pixel is displayed */
709 if (w
->keycon
[0] & FIMD_WKEYCON0_KEYBLEN
) {
710 alpha_fg
= w
->keyalpha
;
711 blend_param
[A_COEF
] = alpha_fg
;
712 blend_param
[B_COEF
] = FIMD_1_MINUS_COLOR(alpha_fg
);
715 blend_param
[A_COEF
] = 0x0;
716 blend_param
[B_COEF
] = 0xFFFFFF;
722 for (i
= first_coef
; i
< COEF_NUM
; i
++) {
723 switch ((w
->blendeq
>> i
* 6) & FIMD_BLENDEQ_COEF_MASK
) {
728 blend_param
[i
] = 0xFFFFFF;
731 blend_param
[i
] = alpha_fg
;
734 blend_param
[i
] = FIMD_1_MINUS_COLOR(alpha_fg
);
737 blend_param
[i
] = p_bg
.a
;
740 blend_param
[i
] = FIMD_1_MINUS_COLOR(p_bg
.a
);
743 blend_param
[i
] = w
->alpha_val
[0];
746 blend_param
[i
] = fg_color
;
749 blend_param
[i
] = FIMD_1_MINUS_COLOR(fg_color
);
752 blend_param
[i
] = bg_color
;
755 blend_param
[i
] = FIMD_1_MINUS_COLOR(bg_color
);
758 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
763 fg_color
= fimd_mult_and_sum_each_byte(bg_color
, blend_param
[B_COEF
],
764 fg_color
, blend_param
[A_COEF
]);
765 ret
->b
= fg_color
& 0xFF;
767 ret
->g
= fg_color
& 0xFF;
769 ret
->r
= fg_color
& 0xFF;
770 ret
->a
= fimd_mult_and_sum_each_byte(alpha_fg
, blend_param
[P_COEF
],
771 p_bg
.a
, blend_param
[Q_COEF
]);
774 /* These routines read data from video frame buffer in system RAM, convert
775 * this data to display controller internal representation, if necessary,
776 * perform pixel blending with data, currently presented in internal buffer.
777 * Result is stored in display controller internal frame buffer. */
779 /* Draw line with index in palette table in RAM frame buffer data */
780 #define DEF_DRAW_LINE_PALETTE(N) \
781 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
782 uint8_t *dst, bool blend) \
784 int width = w->rightbot_x - w->lefttop_x + 1; \
785 uint8_t *ifb = dst; \
786 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
791 memcpy(&data, src, sizeof(data)); \
793 fimd_swap_data(swap, &data); \
794 for (i = (64 / (N) - 1); i >= 0; i--) { \
795 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
796 ((1ULL << (N)) - 1)], &p); \
797 p.a = w->get_alpha(w, p.a); \
799 ifb += get_pixel_ifb(ifb, &p_old); \
800 exynos4210_fimd_blend_pixel(w, p_old, &p); \
802 dst += put_pixel_ifb(p, dst); \
804 width -= (64 / (N)); \
805 } while (width > 0); \
808 /* Draw line with direct color value in RAM frame buffer data */
809 #define DEF_DRAW_LINE_NOPALETTE(N) \
810 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
811 uint8_t *dst, bool blend) \
813 int width = w->rightbot_x - w->lefttop_x + 1; \
814 uint8_t *ifb = dst; \
815 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
820 memcpy(&data, src, sizeof(data)); \
822 fimd_swap_data(swap, &data); \
823 for (i = (64 / (N) - 1); i >= 0; i--) { \
824 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
825 p.a = w->get_alpha(w, p.a); \
827 ifb += get_pixel_ifb(ifb, &p_old); \
828 exynos4210_fimd_blend_pixel(w, p_old, &p); \
830 dst += put_pixel_ifb(p, dst); \
832 width -= (64 / (N)); \
833 } while (width > 0); \
836 DEF_DRAW_LINE_PALETTE(1)
837 DEF_DRAW_LINE_PALETTE(2)
838 DEF_DRAW_LINE_PALETTE(4)
839 DEF_DRAW_LINE_PALETTE(8)
840 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */
841 DEF_DRAW_LINE_NOPALETTE(16)
842 DEF_DRAW_LINE_NOPALETTE(32)
844 /* Special draw line routine for window color map case */
845 static void draw_line_mapcolor(Exynos4210fimdWindow
*w
, uint8_t *src
,
846 uint8_t *dst
, bool blend
)
850 int width
= w
->rightbot_x
- w
->lefttop_x
+ 1;
851 uint32_t map_color
= w
->winmap
& FIMD_WINMAP_COLOR_MASK
;
854 pixel_888_to_rgb(map_color
, &p
);
855 p
.a
= w
->get_alpha(w
, p
.a
);
857 ifb
+= get_pixel_ifb(ifb
, &p_old
);
858 exynos4210_fimd_blend_pixel(w
, p_old
, &p
);
860 dst
+= put_pixel_ifb(p
, dst
);
864 /* Write RGB to QEMU's GraphicConsole framebuffer */
866 static int put_to_qemufb_pixel8(const rgba p
, uint8_t *d
)
868 uint32_t pixel
= rgb_to_pixel8(p
.r
, p
.g
, p
.b
);
869 *(uint8_t *)d
= pixel
;
873 static int put_to_qemufb_pixel15(const rgba p
, uint8_t *d
)
875 uint32_t pixel
= rgb_to_pixel15(p
.r
, p
.g
, p
.b
);
876 *(uint16_t *)d
= pixel
;
880 static int put_to_qemufb_pixel16(const rgba p
, uint8_t *d
)
882 uint32_t pixel
= rgb_to_pixel16(p
.r
, p
.g
, p
.b
);
883 *(uint16_t *)d
= pixel
;
887 static int put_to_qemufb_pixel24(const rgba p
, uint8_t *d
)
889 uint32_t pixel
= rgb_to_pixel24(p
.r
, p
.g
, p
.b
);
890 *(uint8_t *)d
++ = (pixel
>> 0) & 0xFF;
891 *(uint8_t *)d
++ = (pixel
>> 8) & 0xFF;
892 *(uint8_t *)d
++ = (pixel
>> 16) & 0xFF;
896 static int put_to_qemufb_pixel32(const rgba p
, uint8_t *d
)
898 uint32_t pixel
= rgb_to_pixel24(p
.r
, p
.g
, p
.b
);
899 *(uint32_t *)d
= pixel
;
903 /* Routine to copy pixel from internal buffer to QEMU buffer */
904 static int (*put_pixel_toqemu
)(const rgba p
, uint8_t *pixel
);
905 static inline void fimd_update_putpix_qemu(int bpp
)
909 put_pixel_toqemu
= put_to_qemufb_pixel8
;
912 put_pixel_toqemu
= put_to_qemufb_pixel15
;
915 put_pixel_toqemu
= put_to_qemufb_pixel16
;
918 put_pixel_toqemu
= put_to_qemufb_pixel24
;
921 put_pixel_toqemu
= put_to_qemufb_pixel32
;
924 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp
);
929 /* Routine to copy a line from internal frame buffer to QEMU display */
930 static void fimd_copy_line_toqemu(int width
, uint8_t *src
, uint8_t *dst
)
935 src
+= get_pixel_ifb(src
, &p
);
936 dst
+= put_pixel_toqemu(p
, dst
);
940 /* Parse BPPMODE_F = WINCON1[5:2] bits */
941 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState
*s
, int win
)
943 Exynos4210fimdWindow
*w
= &s
->window
[win
];
945 if (w
->winmap
& FIMD_WINMAP_EN
) {
946 w
->draw_line
= draw_line_mapcolor
;
950 switch (WIN_BPP_MODE(w
)) {
952 w
->draw_line
= draw_line_palette_1
;
954 palette_data_format
[exynos4210_fimd_palette_format(s
, win
)];
957 w
->draw_line
= draw_line_palette_2
;
959 palette_data_format
[exynos4210_fimd_palette_format(s
, win
)];
962 w
->draw_line
= draw_line_palette_4
;
964 palette_data_format
[exynos4210_fimd_palette_format(s
, win
)];
967 w
->draw_line
= draw_line_palette_8
;
969 palette_data_format
[exynos4210_fimd_palette_format(s
, win
)];
972 w
->draw_line
= draw_line_8
;
973 w
->pixel_to_rgb
= pixel_a232_to_rgb
;
976 w
->draw_line
= draw_line_16
;
977 w
->pixel_to_rgb
= pixel_565_to_rgb
;
980 w
->draw_line
= draw_line_16
;
981 w
->pixel_to_rgb
= pixel_a555_to_rgb
;
984 w
->draw_line
= draw_line_16
;
985 w
->pixel_to_rgb
= pixel_1555_to_rgb
;
988 w
->draw_line
= draw_line_32
;
989 w
->pixel_to_rgb
= pixel_666_to_rgb
;
992 w
->draw_line
= draw_line_32
;
993 w
->pixel_to_rgb
= pixel_a665_to_rgb
;
996 w
->draw_line
= draw_line_32
;
997 w
->pixel_to_rgb
= pixel_a666_to_rgb
;
1000 w
->draw_line
= draw_line_32
;
1001 w
->pixel_to_rgb
= pixel_888_to_rgb
;
1004 w
->draw_line
= draw_line_32
;
1005 w
->pixel_to_rgb
= pixel_a887_to_rgb
;
1008 w
->draw_line
= draw_line_32
;
1009 if ((w
->wincon
& FIMD_WINCON_BLD_PIX
) && (w
->wincon
&
1010 FIMD_WINCON_ALPHA_SEL
)) {
1011 w
->pixel_to_rgb
= pixel_8888_to_rgb
;
1013 w
->pixel_to_rgb
= pixel_a888_to_rgb
;
1017 w
->draw_line
= draw_line_16
;
1018 if ((w
->wincon
& FIMD_WINCON_BLD_PIX
) && (w
->wincon
&
1019 FIMD_WINCON_ALPHA_SEL
)) {
1020 w
->pixel_to_rgb
= pixel_4444_to_rgb
;
1022 w
->pixel_to_rgb
= pixel_a444_to_rgb
;
1026 w
->draw_line
= draw_line_16
;
1027 w
->pixel_to_rgb
= pixel_555_to_rgb
;
1032 #if EXYNOS4210_FIMD_MODE_TRACE > 0
1033 static const char *exynos4210_fimd_get_bppmode(int mode_code
)
1035 switch (mode_code
) {
1043 return "8 bpp (palettized)";
1045 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1047 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1049 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1051 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1053 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1055 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1057 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1059 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1061 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1063 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1065 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1067 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1069 return "Non-existing bpp mode";
1073 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState
*s
,
1074 int win_num
, uint32_t val
)
1076 Exynos4210fimdWindow
*w
= &s
->window
[win_num
];
1078 if (w
->winmap
& FIMD_WINMAP_EN
) {
1079 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1080 win_num
, w
->winmap
& 0xFFFFFF);
1084 if ((val
!= 0xFFFFFFFF) && ((w
->wincon
>> 2) & 0xF) == ((val
>> 2) & 0xF)) {
1087 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num
,
1088 exynos4210_fimd_get_bppmode((val
>> 2) & 0xF));
1091 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState
*s
,
1092 int win_num
, uint32_t val
)
1098 static inline int fimd_get_buffer_id(Exynos4210fimdWindow
*w
)
1100 switch (w
->wincon
& FIMD_WINCON_BUFSTATUS
) {
1101 case FIMD_WINCON_BUF0_STAT
:
1103 case FIMD_WINCON_BUF1_STAT
:
1105 case FIMD_WINCON_BUF2_STAT
:
1108 DPRINT_ERROR("Non-existent buffer index\n");
1113 static void exynos4210_fimd_invalidate(void *opaque
)
1115 Exynos4210fimdState
*s
= (Exynos4210fimdState
*)opaque
;
1116 s
->invalidate
= true;
1119 /* Updates specified window's MemorySection based on values of WINCON,
1120 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1121 static void fimd_update_memory_section(Exynos4210fimdState
*s
, unsigned win
)
1123 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
1124 Exynos4210fimdWindow
*w
= &s
->window
[win
];
1125 hwaddr fb_start_addr
, fb_mapped_len
;
1127 if (!s
->enabled
|| !(w
->wincon
& FIMD_WINCON_ENWIN
) ||
1128 FIMD_WINDOW_PROTECTED(s
->shadowcon
, win
)) {
1132 if (w
->host_fb_addr
) {
1133 cpu_physical_memory_unmap(w
->host_fb_addr
, w
->fb_len
, 0, 0);
1134 w
->host_fb_addr
= NULL
;
1138 fb_start_addr
= w
->buf_start
[fimd_get_buffer_id(w
)];
1139 /* Total number of bytes of virtual screen used by current window */
1140 w
->fb_len
= fb_mapped_len
= (w
->virtpage_width
+ w
->virtpage_offsize
) *
1141 (w
->rightbot_y
- w
->lefttop_y
+ 1);
1143 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1144 * does not support hot-unplug.
1146 if (w
->mem_section
.mr
) {
1147 memory_region_set_log(w
->mem_section
.mr
, false, DIRTY_MEMORY_VGA
);
1148 memory_region_unref(w
->mem_section
.mr
);
1151 w
->mem_section
= memory_region_find(sysbus_address_space(sbd
),
1152 fb_start_addr
, w
->fb_len
);
1153 assert(w
->mem_section
.mr
);
1154 assert(w
->mem_section
.offset_within_address_space
== fb_start_addr
);
1155 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
1156 win
, fb_start_addr
, w
->fb_len
);
1158 if (int128_get64(w
->mem_section
.size
) != w
->fb_len
||
1159 !memory_region_is_ram(w
->mem_section
.mr
)) {
1160 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win
);
1164 w
->host_fb_addr
= cpu_physical_memory_map(fb_start_addr
, &fb_mapped_len
, 0);
1165 if (!w
->host_fb_addr
) {
1166 DPRINT_ERROR("Failed to map window %u framebuffer\n", win
);
1170 if (fb_mapped_len
!= w
->fb_len
) {
1171 DPRINT_ERROR("Window %u mapped framebuffer length is less then "
1173 cpu_physical_memory_unmap(w
->host_fb_addr
, fb_mapped_len
, 0, 0);
1176 memory_region_set_log(w
->mem_section
.mr
, true, DIRTY_MEMORY_VGA
);
1177 exynos4210_fimd_invalidate(s
);
1181 memory_region_unref(w
->mem_section
.mr
);
1182 w
->mem_section
.mr
= NULL
;
1183 w
->mem_section
.size
= int128_zero();
1184 w
->host_fb_addr
= NULL
;
1188 static void exynos4210_fimd_enable(Exynos4210fimdState
*s
, bool enabled
)
1190 if (enabled
&& !s
->enabled
) {
1193 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1194 fimd_update_memory_section(s
, w
);
1197 s
->enabled
= enabled
;
1198 DPRINT_TRACE("display controller %s\n", enabled
? "enabled" : "disabled");
1201 static inline uint32_t unpack_upper_4(uint32_t x
)
1203 return ((x
& 0xF00) << 12) | ((x
& 0xF0) << 8) | ((x
& 0xF) << 4);
1206 static inline uint32_t pack_upper_4(uint32_t x
)
1208 return (((x
& 0xF00000) >> 12) | ((x
& 0xF000) >> 8) |
1209 ((x
& 0xF0) >> 4)) & 0xFFF;
1212 static void exynos4210_fimd_update_irq(Exynos4210fimdState
*s
)
1214 if (!(s
->vidintcon
[0] & FIMD_VIDINT_INTEN
)) {
1215 qemu_irq_lower(s
->irq
[0]);
1216 qemu_irq_lower(s
->irq
[1]);
1217 qemu_irq_lower(s
->irq
[2]);
1220 if ((s
->vidintcon
[0] & FIMD_VIDINT_INTFIFOEN
) &&
1221 (s
->vidintcon
[1] & FIMD_VIDINT_INTFIFOPEND
)) {
1222 qemu_irq_raise(s
->irq
[0]);
1224 qemu_irq_lower(s
->irq
[0]);
1226 if ((s
->vidintcon
[0] & FIMD_VIDINT_INTFRMEN
) &&
1227 (s
->vidintcon
[1] & FIMD_VIDINT_INTFRMPEND
)) {
1228 qemu_irq_raise(s
->irq
[1]);
1230 qemu_irq_lower(s
->irq
[1]);
1232 if ((s
->vidintcon
[0] & FIMD_VIDINT_I80IFDONE
) &&
1233 (s
->vidintcon
[1] & FIMD_VIDINT_INTI80PEND
)) {
1234 qemu_irq_raise(s
->irq
[2]);
1236 qemu_irq_lower(s
->irq
[2]);
1240 static void exynos4210_update_resolution(Exynos4210fimdState
*s
)
1242 DisplaySurface
*surface
= qemu_console_surface(s
->console
);
1244 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1245 uint32_t width
= ((s
->vidtcon
[2] >> FIMD_VIDTCON2_HOR_SHIFT
) &
1246 FIMD_VIDTCON2_SIZE_MASK
) + 1;
1247 uint32_t height
= ((s
->vidtcon
[2] >> FIMD_VIDTCON2_VER_SHIFT
) &
1248 FIMD_VIDTCON2_SIZE_MASK
) + 1;
1250 if (s
->ifb
== NULL
|| surface_width(surface
) != width
||
1251 surface_height(surface
) != height
) {
1252 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
1253 surface_width(surface
), surface_height(surface
), width
, height
);
1254 qemu_console_resize(s
->console
, width
, height
);
1255 s
->ifb
= g_realloc(s
->ifb
, width
* height
* RGBA_SIZE
+ 1);
1256 memset(s
->ifb
, 0, width
* height
* RGBA_SIZE
+ 1);
1257 exynos4210_fimd_invalidate(s
);
1261 static void exynos4210_fimd_update(void *opaque
)
1263 Exynos4210fimdState
*s
= (Exynos4210fimdState
*)opaque
;
1264 DisplaySurface
*surface
;
1265 Exynos4210fimdWindow
*w
;
1266 DirtyBitmapSnapshot
*snap
;
1268 hwaddr fb_line_addr
, inc_size
;
1270 int first_line
= -1, last_line
= -1, scrn_width
;
1272 uint8_t *host_fb_addr
;
1273 bool is_dirty
= false;
1274 const int global_width
= (s
->vidtcon
[2] & FIMD_VIDTCON2_SIZE_MASK
) + 1;
1275 const int global_height
= ((s
->vidtcon
[2] >> FIMD_VIDTCON2_VER_SHIFT
) &
1276 FIMD_VIDTCON2_SIZE_MASK
) + 1;
1278 if (!s
|| !s
->console
|| !s
->enabled
||
1279 surface_bits_per_pixel(qemu_console_surface(s
->console
)) == 0) {
1282 exynos4210_update_resolution(s
);
1283 surface
= qemu_console_surface(s
->console
);
1285 for (i
= 0; i
< NUM_OF_WINDOWS
; i
++) {
1287 if ((w
->wincon
& FIMD_WINCON_ENWIN
) && w
->host_fb_addr
) {
1288 scrn_height
= w
->rightbot_y
- w
->lefttop_y
+ 1;
1289 scrn_width
= w
->virtpage_width
;
1290 /* Total width of virtual screen page in bytes */
1291 inc_size
= scrn_width
+ w
->virtpage_offsize
;
1292 memory_region_sync_dirty_bitmap(w
->mem_section
.mr
);
1293 host_fb_addr
= w
->host_fb_addr
;
1294 fb_line_addr
= w
->mem_section
.offset_within_region
;
1295 snap
= memory_region_snapshot_and_clear_dirty(w
->mem_section
.mr
,
1296 fb_line_addr
, inc_size
* scrn_height
, DIRTY_MEMORY_VGA
);
1298 for (line
= 0; line
< scrn_height
; line
++) {
1299 is_dirty
= memory_region_snapshot_get_dirty(w
->mem_section
.mr
,
1300 snap
, fb_line_addr
, scrn_width
);
1302 if (s
->invalidate
|| is_dirty
) {
1303 if (first_line
== -1) {
1307 w
->draw_line(w
, host_fb_addr
, s
->ifb
+
1308 w
->lefttop_x
* RGBA_SIZE
+ (w
->lefttop_y
+ line
) *
1309 global_width
* RGBA_SIZE
, blend
);
1311 host_fb_addr
+= inc_size
;
1312 fb_line_addr
+= inc_size
;
1320 /* Copy resulting image to QEMU_CONSOLE. */
1321 if (first_line
>= 0) {
1325 bpp
= surface_bits_per_pixel(surface
);
1326 fimd_update_putpix_qemu(bpp
);
1327 bpp
= (bpp
+ 1) >> 3;
1328 d
= surface_data(surface
);
1329 for (line
= first_line
; line
<= last_line
; line
++) {
1330 fimd_copy_line_toqemu(global_width
, s
->ifb
+ global_width
* line
*
1331 RGBA_SIZE
, d
+ global_width
* line
* bpp
);
1333 dpy_gfx_update(s
->console
, 0, 0, global_width
, global_height
);
1335 s
->invalidate
= false;
1336 s
->vidintcon
[1] |= FIMD_VIDINT_INTFRMPEND
;
1337 if ((s
->vidcon
[0] & FIMD_VIDCON0_ENVID_F
) == 0) {
1338 exynos4210_fimd_enable(s
, false);
1340 exynos4210_fimd_update_irq(s
);
1343 static void exynos4210_fimd_reset(DeviceState
*d
)
1345 Exynos4210fimdState
*s
= EXYNOS4210_FIMD(d
);
1348 DPRINT_TRACE("Display controller reset\n");
1349 /* Set all display controller registers to 0 */
1350 memset(&s
->vidcon
, 0, (uint8_t *)&s
->window
- (uint8_t *)&s
->vidcon
);
1351 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1352 memset(&s
->window
[w
], 0, sizeof(Exynos4210fimdWindow
));
1353 s
->window
[w
].blendeq
= 0xC2;
1354 exynos4210_fimd_update_win_bppmode(s
, w
);
1355 exynos4210_fimd_trace_bppmode(s
, w
, 0xFFFFFFFF);
1356 fimd_update_get_alpha(s
, w
);
1362 exynos4210_fimd_invalidate(s
);
1363 exynos4210_fimd_enable(s
, false);
1364 /* Some registers have non-zero initial values */
1365 s
->winchmap
= 0x7D517D51;
1366 s
->colorgaincon
= 0x10040100;
1367 s
->huecoef_cr
[0] = s
->huecoef_cr
[3] = 0x01000100;
1368 s
->huecoef_cb
[0] = s
->huecoef_cb
[3] = 0x01000100;
1369 s
->hueoffset
= 0x01800080;
1372 static void exynos4210_fimd_write(void *opaque
, hwaddr offset
,
1373 uint64_t val
, unsigned size
)
1375 Exynos4210fimdState
*s
= (Exynos4210fimdState
*)opaque
;
1379 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset
,
1380 (long long unsigned int)val
, (long long unsigned int)val
);
1384 if ((val
& FIMD_VIDCON0_ENVID_MASK
) == FIMD_VIDCON0_ENVID_MASK
) {
1385 exynos4210_fimd_enable(s
, true);
1387 if ((val
& FIMD_VIDCON0_ENVID
) == 0) {
1388 exynos4210_fimd_enable(s
, false);
1394 /* Leave read-only bits as is */
1395 val
= (val
& (~FIMD_VIDCON1_ROMASK
)) |
1396 (s
->vidcon
[1] & FIMD_VIDCON1_ROMASK
);
1399 case FIMD_VIDCON2
... FIMD_VIDCON3
:
1400 s
->vidcon
[(offset
) >> 2] = val
;
1402 case FIMD_VIDTCON_START
... FIMD_VIDTCON_END
:
1403 s
->vidtcon
[(offset
- FIMD_VIDTCON_START
) >> 2] = val
;
1405 case FIMD_WINCON_START
... FIMD_WINCON_END
:
1406 w
= (offset
- FIMD_WINCON_START
) >> 2;
1407 /* Window's current buffer ID */
1408 i
= fimd_get_buffer_id(&s
->window
[w
]);
1409 old_value
= s
->window
[w
].wincon
;
1410 val
= (val
& ~FIMD_WINCON_ROMASK
) |
1411 (s
->window
[w
].wincon
& FIMD_WINCON_ROMASK
);
1413 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1414 val
&= ~FIMD_WINCON_ALPHA_MUL
;
1416 exynos4210_fimd_trace_bppmode(s
, w
, val
);
1417 switch (val
& FIMD_WINCON_BUFSELECT
) {
1418 case FIMD_WINCON_BUF0_SEL
:
1419 val
&= ~FIMD_WINCON_BUFSTATUS
;
1421 case FIMD_WINCON_BUF1_SEL
:
1422 val
= (val
& ~FIMD_WINCON_BUFSTAT_H
) | FIMD_WINCON_BUFSTAT_L
;
1424 case FIMD_WINCON_BUF2_SEL
:
1425 if (val
& FIMD_WINCON_BUFMODE
) {
1426 val
= (val
& ~FIMD_WINCON_BUFSTAT_L
) | FIMD_WINCON_BUFSTAT_H
;
1432 s
->window
[w
].wincon
= val
;
1433 exynos4210_fimd_update_win_bppmode(s
, w
);
1434 fimd_update_get_alpha(s
, w
);
1435 if ((i
!= fimd_get_buffer_id(&s
->window
[w
])) ||
1436 (!(old_value
& FIMD_WINCON_ENWIN
) && (s
->window
[w
].wincon
&
1437 FIMD_WINCON_ENWIN
))) {
1438 fimd_update_memory_section(s
, w
);
1441 case FIMD_SHADOWCON
:
1442 old_value
= s
->shadowcon
;
1444 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1445 if (FIMD_WINDOW_PROTECTED(old_value
, w
) &&
1446 !FIMD_WINDOW_PROTECTED(s
->shadowcon
, w
)) {
1447 fimd_update_memory_section(s
, w
);
1454 case FIMD_VIDOSD_START
... FIMD_VIDOSD_END
:
1455 w
= (offset
- FIMD_VIDOSD_START
) >> 4;
1456 i
= ((offset
- FIMD_VIDOSD_START
) & 0xF) >> 2;
1459 old_value
= s
->window
[w
].lefttop_y
;
1460 s
->window
[w
].lefttop_x
= (val
>> FIMD_VIDOSD_HOR_SHIFT
) &
1461 FIMD_VIDOSD_COORD_MASK
;
1462 s
->window
[w
].lefttop_y
= (val
>> FIMD_VIDOSD_VER_SHIFT
) &
1463 FIMD_VIDOSD_COORD_MASK
;
1464 if (s
->window
[w
].lefttop_y
!= old_value
) {
1465 fimd_update_memory_section(s
, w
);
1469 old_value
= s
->window
[w
].rightbot_y
;
1470 s
->window
[w
].rightbot_x
= (val
>> FIMD_VIDOSD_HOR_SHIFT
) &
1471 FIMD_VIDOSD_COORD_MASK
;
1472 s
->window
[w
].rightbot_y
= (val
>> FIMD_VIDOSD_VER_SHIFT
) &
1473 FIMD_VIDOSD_COORD_MASK
;
1474 if (s
->window
[w
].rightbot_y
!= old_value
) {
1475 fimd_update_memory_section(s
, w
);
1480 s
->window
[w
].osdsize
= val
;
1482 s
->window
[w
].alpha_val
[0] =
1483 unpack_upper_4((val
& FIMD_VIDOSD_ALPHA_AEN0
) >>
1484 FIMD_VIDOSD_AEN0_SHIFT
) |
1485 (s
->window
[w
].alpha_val
[0] & FIMD_VIDALPHA_ALPHA_LOWER
);
1486 s
->window
[w
].alpha_val
[1] =
1487 unpack_upper_4(val
& FIMD_VIDOSD_ALPHA_AEN1
) |
1488 (s
->window
[w
].alpha_val
[1] & FIMD_VIDALPHA_ALPHA_LOWER
);
1492 if (w
!= 1 && w
!= 2) {
1493 DPRINT_ERROR("Bad write offset 0x%08x\n", offset
);
1496 s
->window
[w
].osdsize
= val
;
1500 case FIMD_VIDWADD0_START
... FIMD_VIDWADD0_END
:
1501 w
= (offset
- FIMD_VIDWADD0_START
) >> 3;
1502 i
= ((offset
- FIMD_VIDWADD0_START
) >> 2) & 1;
1503 if (i
== fimd_get_buffer_id(&s
->window
[w
]) &&
1504 s
->window
[w
].buf_start
[i
] != val
) {
1505 s
->window
[w
].buf_start
[i
] = val
;
1506 fimd_update_memory_section(s
, w
);
1509 s
->window
[w
].buf_start
[i
] = val
;
1511 case FIMD_VIDWADD1_START
... FIMD_VIDWADD1_END
:
1512 w
= (offset
- FIMD_VIDWADD1_START
) >> 3;
1513 i
= ((offset
- FIMD_VIDWADD1_START
) >> 2) & 1;
1514 s
->window
[w
].buf_end
[i
] = val
;
1516 case FIMD_VIDWADD2_START
... FIMD_VIDWADD2_END
:
1517 w
= (offset
- FIMD_VIDWADD2_START
) >> 2;
1518 if (((val
& FIMD_VIDWADD2_PAGEWIDTH
) != s
->window
[w
].virtpage_width
) ||
1519 (((val
>> FIMD_VIDWADD2_OFFSIZE_SHIFT
) & FIMD_VIDWADD2_OFFSIZE
) !=
1520 s
->window
[w
].virtpage_offsize
)) {
1521 s
->window
[w
].virtpage_width
= val
& FIMD_VIDWADD2_PAGEWIDTH
;
1522 s
->window
[w
].virtpage_offsize
=
1523 (val
>> FIMD_VIDWADD2_OFFSIZE_SHIFT
) & FIMD_VIDWADD2_OFFSIZE
;
1524 fimd_update_memory_section(s
, w
);
1527 case FIMD_VIDINTCON0
:
1528 s
->vidintcon
[0] = val
;
1530 case FIMD_VIDINTCON1
:
1531 s
->vidintcon
[1] &= ~(val
& 7);
1532 exynos4210_fimd_update_irq(s
);
1534 case FIMD_WKEYCON_START
... FIMD_WKEYCON_END
:
1535 w
= ((offset
- FIMD_WKEYCON_START
) >> 3) + 1;
1536 i
= ((offset
- FIMD_WKEYCON_START
) >> 2) & 1;
1537 s
->window
[w
].keycon
[i
] = val
;
1539 case FIMD_WKEYALPHA_START
... FIMD_WKEYALPHA_END
:
1540 w
= ((offset
- FIMD_WKEYALPHA_START
) >> 2) + 1;
1541 s
->window
[w
].keyalpha
= val
;
1546 case FIMD_WINMAP_START
... FIMD_WINMAP_END
:
1547 w
= (offset
- FIMD_WINMAP_START
) >> 2;
1548 old_value
= s
->window
[w
].winmap
;
1549 s
->window
[w
].winmap
= val
;
1550 if ((val
& FIMD_WINMAP_EN
) ^ (old_value
& FIMD_WINMAP_EN
)) {
1551 exynos4210_fimd_invalidate(s
);
1552 exynos4210_fimd_update_win_bppmode(s
, w
);
1553 exynos4210_fimd_trace_bppmode(s
, w
, 0xFFFFFFFF);
1554 exynos4210_fimd_update(s
);
1557 case FIMD_WPALCON_HIGH
... FIMD_WPALCON_LOW
:
1558 i
= (offset
- FIMD_WPALCON_HIGH
) >> 2;
1559 s
->wpalcon
[i
] = val
;
1560 if (s
->wpalcon
[1] & FIMD_WPALCON_UPDATEEN
) {
1561 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1562 exynos4210_fimd_update_win_bppmode(s
, w
);
1563 fimd_update_get_alpha(s
, w
);
1568 val
= (val
& ~FIMD_TRIGCON_ROMASK
) | (s
->trigcon
& FIMD_TRIGCON_ROMASK
);
1571 case FIMD_I80IFCON_START
... FIMD_I80IFCON_END
:
1572 s
->i80ifcon
[(offset
- FIMD_I80IFCON_START
) >> 2] = val
;
1574 case FIMD_COLORGAINCON
:
1575 s
->colorgaincon
= val
;
1577 case FIMD_LDI_CMDCON0
... FIMD_LDI_CMDCON1
:
1578 s
->ldi_cmdcon
[(offset
- FIMD_LDI_CMDCON0
) >> 2] = val
;
1580 case FIMD_SIFCCON0
... FIMD_SIFCCON2
:
1581 i
= (offset
- FIMD_SIFCCON0
) >> 2;
1583 s
->sifccon
[i
] = val
;
1586 case FIMD_HUECOEFCR_START
... FIMD_HUECOEFCR_END
:
1587 i
= (offset
- FIMD_HUECOEFCR_START
) >> 2;
1588 s
->huecoef_cr
[i
] = val
;
1590 case FIMD_HUECOEFCB_START
... FIMD_HUECOEFCB_END
:
1591 i
= (offset
- FIMD_HUECOEFCB_START
) >> 2;
1592 s
->huecoef_cb
[i
] = val
;
1594 case FIMD_HUEOFFSET
:
1597 case FIMD_VIDWALPHA_START
... FIMD_VIDWALPHA_END
:
1598 w
= ((offset
- FIMD_VIDWALPHA_START
) >> 3);
1599 i
= ((offset
- FIMD_VIDWALPHA_START
) >> 2) & 1;
1601 s
->window
[w
].alpha_val
[i
] = val
;
1603 s
->window
[w
].alpha_val
[i
] = (val
& FIMD_VIDALPHA_ALPHA_LOWER
) |
1604 (s
->window
[w
].alpha_val
[i
] & FIMD_VIDALPHA_ALPHA_UPPER
);
1607 case FIMD_BLENDEQ_START
... FIMD_BLENDEQ_END
:
1608 s
->window
[(offset
- FIMD_BLENDEQ_START
) >> 2].blendeq
= val
;
1611 old_value
= s
->blendcon
;
1613 if ((s
->blendcon
& FIMD_ALPHA_8BIT
) != (old_value
& FIMD_ALPHA_8BIT
)) {
1614 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1615 fimd_update_get_alpha(s
, w
);
1619 case FIMD_WRTQOSCON_START
... FIMD_WRTQOSCON_END
:
1620 s
->window
[(offset
- FIMD_WRTQOSCON_START
) >> 2].rtqoscon
= val
;
1622 case FIMD_I80IFCMD_START
... FIMD_I80IFCMD_END
:
1623 s
->i80ifcmd
[(offset
- FIMD_I80IFCMD_START
) >> 2] = val
;
1625 case FIMD_VIDW0ADD0_B2
... FIMD_VIDW4ADD0_B2
:
1626 if (offset
& 0x0004) {
1627 DPRINT_ERROR("bad write offset 0x%08x\n", offset
);
1630 w
= (offset
- FIMD_VIDW0ADD0_B2
) >> 3;
1631 if (fimd_get_buffer_id(&s
->window
[w
]) == 2 &&
1632 s
->window
[w
].buf_start
[2] != val
) {
1633 s
->window
[w
].buf_start
[2] = val
;
1634 fimd_update_memory_section(s
, w
);
1637 s
->window
[w
].buf_start
[2] = val
;
1639 case FIMD_SHD_ADD0_START
... FIMD_SHD_ADD0_END
:
1640 if (offset
& 0x0004) {
1641 DPRINT_ERROR("bad write offset 0x%08x\n", offset
);
1644 s
->window
[(offset
- FIMD_SHD_ADD0_START
) >> 3].shadow_buf_start
= val
;
1646 case FIMD_SHD_ADD1_START
... FIMD_SHD_ADD1_END
:
1647 if (offset
& 0x0004) {
1648 DPRINT_ERROR("bad write offset 0x%08x\n", offset
);
1651 s
->window
[(offset
- FIMD_SHD_ADD1_START
) >> 3].shadow_buf_end
= val
;
1653 case FIMD_SHD_ADD2_START
... FIMD_SHD_ADD2_END
:
1654 s
->window
[(offset
- FIMD_SHD_ADD2_START
) >> 2].shadow_buf_size
= val
;
1656 case FIMD_PAL_MEM_START
... FIMD_PAL_MEM_END
:
1657 w
= (offset
- FIMD_PAL_MEM_START
) >> 10;
1658 i
= ((offset
- FIMD_PAL_MEM_START
) >> 2) & 0xFF;
1659 s
->window
[w
].palette
[i
] = val
;
1661 case FIMD_PALMEM_AL_START
... FIMD_PALMEM_AL_END
:
1662 /* Palette memory aliases for windows 0 and 1 */
1663 w
= (offset
- FIMD_PALMEM_AL_START
) >> 10;
1664 i
= ((offset
- FIMD_PALMEM_AL_START
) >> 2) & 0xFF;
1665 s
->window
[w
].palette
[i
] = val
;
1668 DPRINT_ERROR("bad write offset 0x%08x\n", offset
);
1673 static uint64_t exynos4210_fimd_read(void *opaque
, hwaddr offset
,
1676 Exynos4210fimdState
*s
= (Exynos4210fimdState
*)opaque
;
1680 DPRINT_L2("read offset 0x%08x\n", offset
);
1683 case FIMD_VIDCON0
... FIMD_VIDCON3
:
1684 return s
->vidcon
[(offset
- FIMD_VIDCON0
) >> 2];
1685 case FIMD_VIDTCON_START
... FIMD_VIDTCON_END
:
1686 return s
->vidtcon
[(offset
- FIMD_VIDTCON_START
) >> 2];
1687 case FIMD_WINCON_START
... FIMD_WINCON_END
:
1688 return s
->window
[(offset
- FIMD_WINCON_START
) >> 2].wincon
;
1689 case FIMD_SHADOWCON
:
1690 return s
->shadowcon
;
1693 case FIMD_VIDOSD_START
... FIMD_VIDOSD_END
:
1694 w
= (offset
- FIMD_VIDOSD_START
) >> 4;
1695 i
= ((offset
- FIMD_VIDOSD_START
) & 0xF) >> 2;
1698 ret
= ((s
->window
[w
].lefttop_x
& FIMD_VIDOSD_COORD_MASK
) <<
1699 FIMD_VIDOSD_HOR_SHIFT
) |
1700 (s
->window
[w
].lefttop_y
& FIMD_VIDOSD_COORD_MASK
);
1703 ret
= ((s
->window
[w
].rightbot_x
& FIMD_VIDOSD_COORD_MASK
) <<
1704 FIMD_VIDOSD_HOR_SHIFT
) |
1705 (s
->window
[w
].rightbot_y
& FIMD_VIDOSD_COORD_MASK
);
1709 ret
= s
->window
[w
].osdsize
;
1711 ret
= (pack_upper_4(s
->window
[w
].alpha_val
[0]) <<
1712 FIMD_VIDOSD_AEN0_SHIFT
) |
1713 pack_upper_4(s
->window
[w
].alpha_val
[1]);
1717 if (w
!= 1 && w
!= 2) {
1718 DPRINT_ERROR("bad read offset 0x%08x\n", offset
);
1721 ret
= s
->window
[w
].osdsize
;
1725 case FIMD_VIDWADD0_START
... FIMD_VIDWADD0_END
:
1726 w
= (offset
- FIMD_VIDWADD0_START
) >> 3;
1727 i
= ((offset
- FIMD_VIDWADD0_START
) >> 2) & 1;
1728 return s
->window
[w
].buf_start
[i
];
1729 case FIMD_VIDWADD1_START
... FIMD_VIDWADD1_END
:
1730 w
= (offset
- FIMD_VIDWADD1_START
) >> 3;
1731 i
= ((offset
- FIMD_VIDWADD1_START
) >> 2) & 1;
1732 return s
->window
[w
].buf_end
[i
];
1733 case FIMD_VIDWADD2_START
... FIMD_VIDWADD2_END
:
1734 w
= (offset
- FIMD_VIDWADD2_START
) >> 2;
1735 return s
->window
[w
].virtpage_width
| (s
->window
[w
].virtpage_offsize
<<
1736 FIMD_VIDWADD2_OFFSIZE_SHIFT
);
1737 case FIMD_VIDINTCON0
... FIMD_VIDINTCON1
:
1738 return s
->vidintcon
[(offset
- FIMD_VIDINTCON0
) >> 2];
1739 case FIMD_WKEYCON_START
... FIMD_WKEYCON_END
:
1740 w
= ((offset
- FIMD_WKEYCON_START
) >> 3) + 1;
1741 i
= ((offset
- FIMD_WKEYCON_START
) >> 2) & 1;
1742 return s
->window
[w
].keycon
[i
];
1743 case FIMD_WKEYALPHA_START
... FIMD_WKEYALPHA_END
:
1744 w
= ((offset
- FIMD_WKEYALPHA_START
) >> 2) + 1;
1745 return s
->window
[w
].keyalpha
;
1748 case FIMD_WINMAP_START
... FIMD_WINMAP_END
:
1749 return s
->window
[(offset
- FIMD_WINMAP_START
) >> 2].winmap
;
1750 case FIMD_WPALCON_HIGH
... FIMD_WPALCON_LOW
:
1751 return s
->wpalcon
[(offset
- FIMD_WPALCON_HIGH
) >> 2];
1754 case FIMD_I80IFCON_START
... FIMD_I80IFCON_END
:
1755 return s
->i80ifcon
[(offset
- FIMD_I80IFCON_START
) >> 2];
1756 case FIMD_COLORGAINCON
:
1757 return s
->colorgaincon
;
1758 case FIMD_LDI_CMDCON0
... FIMD_LDI_CMDCON1
:
1759 return s
->ldi_cmdcon
[(offset
- FIMD_LDI_CMDCON0
) >> 2];
1760 case FIMD_SIFCCON0
... FIMD_SIFCCON2
:
1761 i
= (offset
- FIMD_SIFCCON0
) >> 2;
1762 return s
->sifccon
[i
];
1763 case FIMD_HUECOEFCR_START
... FIMD_HUECOEFCR_END
:
1764 i
= (offset
- FIMD_HUECOEFCR_START
) >> 2;
1765 return s
->huecoef_cr
[i
];
1766 case FIMD_HUECOEFCB_START
... FIMD_HUECOEFCB_END
:
1767 i
= (offset
- FIMD_HUECOEFCB_START
) >> 2;
1768 return s
->huecoef_cb
[i
];
1769 case FIMD_HUEOFFSET
:
1770 return s
->hueoffset
;
1771 case FIMD_VIDWALPHA_START
... FIMD_VIDWALPHA_END
:
1772 w
= ((offset
- FIMD_VIDWALPHA_START
) >> 3);
1773 i
= ((offset
- FIMD_VIDWALPHA_START
) >> 2) & 1;
1774 return s
->window
[w
].alpha_val
[i
] &
1775 (w
== 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER
);
1776 case FIMD_BLENDEQ_START
... FIMD_BLENDEQ_END
:
1777 return s
->window
[(offset
- FIMD_BLENDEQ_START
) >> 2].blendeq
;
1780 case FIMD_WRTQOSCON_START
... FIMD_WRTQOSCON_END
:
1781 return s
->window
[(offset
- FIMD_WRTQOSCON_START
) >> 2].rtqoscon
;
1782 case FIMD_I80IFCMD_START
... FIMD_I80IFCMD_END
:
1783 return s
->i80ifcmd
[(offset
- FIMD_I80IFCMD_START
) >> 2];
1784 case FIMD_VIDW0ADD0_B2
... FIMD_VIDW4ADD0_B2
:
1785 if (offset
& 0x0004) {
1788 return s
->window
[(offset
- FIMD_VIDW0ADD0_B2
) >> 3].buf_start
[2];
1789 case FIMD_SHD_ADD0_START
... FIMD_SHD_ADD0_END
:
1790 if (offset
& 0x0004) {
1793 return s
->window
[(offset
- FIMD_SHD_ADD0_START
) >> 3].shadow_buf_start
;
1794 case FIMD_SHD_ADD1_START
... FIMD_SHD_ADD1_END
:
1795 if (offset
& 0x0004) {
1798 return s
->window
[(offset
- FIMD_SHD_ADD1_START
) >> 3].shadow_buf_end
;
1799 case FIMD_SHD_ADD2_START
... FIMD_SHD_ADD2_END
:
1800 return s
->window
[(offset
- FIMD_SHD_ADD2_START
) >> 2].shadow_buf_size
;
1801 case FIMD_PAL_MEM_START
... FIMD_PAL_MEM_END
:
1802 w
= (offset
- FIMD_PAL_MEM_START
) >> 10;
1803 i
= ((offset
- FIMD_PAL_MEM_START
) >> 2) & 0xFF;
1804 return s
->window
[w
].palette
[i
];
1805 case FIMD_PALMEM_AL_START
... FIMD_PALMEM_AL_END
:
1806 /* Palette aliases for win 0,1 */
1807 w
= (offset
- FIMD_PALMEM_AL_START
) >> 10;
1808 i
= ((offset
- FIMD_PALMEM_AL_START
) >> 2) & 0xFF;
1809 return s
->window
[w
].palette
[i
];
1812 DPRINT_ERROR("bad read offset 0x%08x\n", offset
);
1816 static const MemoryRegionOps exynos4210_fimd_mmio_ops
= {
1817 .read
= exynos4210_fimd_read
,
1818 .write
= exynos4210_fimd_write
,
1820 .min_access_size
= 4,
1821 .max_access_size
= 4,
1824 .endianness
= DEVICE_NATIVE_ENDIAN
,
1827 static int exynos4210_fimd_load(void *opaque
, int version_id
)
1829 Exynos4210fimdState
*s
= (Exynos4210fimdState
*)opaque
;
1832 if (version_id
!= 1) {
1836 for (w
= 0; w
< NUM_OF_WINDOWS
; w
++) {
1837 exynos4210_fimd_update_win_bppmode(s
, w
);
1838 fimd_update_get_alpha(s
, w
);
1839 fimd_update_memory_section(s
, w
);
1842 /* Redraw the whole screen */
1843 exynos4210_update_resolution(s
);
1844 exynos4210_fimd_invalidate(s
);
1845 exynos4210_fimd_enable(s
, (s
->vidcon
[0] & FIMD_VIDCON0_ENVID_MASK
) ==
1846 FIMD_VIDCON0_ENVID_MASK
);
1850 static const VMStateDescription exynos4210_fimd_window_vmstate
= {
1851 .name
= "exynos4210.fimd_window",
1853 .minimum_version_id
= 1,
1854 .fields
= (VMStateField
[]) {
1855 VMSTATE_UINT32(wincon
, Exynos4210fimdWindow
),
1856 VMSTATE_UINT32_ARRAY(buf_start
, Exynos4210fimdWindow
, 3),
1857 VMSTATE_UINT32_ARRAY(buf_end
, Exynos4210fimdWindow
, 3),
1858 VMSTATE_UINT32_ARRAY(keycon
, Exynos4210fimdWindow
, 2),
1859 VMSTATE_UINT32(keyalpha
, Exynos4210fimdWindow
),
1860 VMSTATE_UINT32(winmap
, Exynos4210fimdWindow
),
1861 VMSTATE_UINT32(blendeq
, Exynos4210fimdWindow
),
1862 VMSTATE_UINT32(rtqoscon
, Exynos4210fimdWindow
),
1863 VMSTATE_UINT32_ARRAY(palette
, Exynos4210fimdWindow
, 256),
1864 VMSTATE_UINT32(shadow_buf_start
, Exynos4210fimdWindow
),
1865 VMSTATE_UINT32(shadow_buf_end
, Exynos4210fimdWindow
),
1866 VMSTATE_UINT32(shadow_buf_size
, Exynos4210fimdWindow
),
1867 VMSTATE_UINT16(lefttop_x
, Exynos4210fimdWindow
),
1868 VMSTATE_UINT16(lefttop_y
, Exynos4210fimdWindow
),
1869 VMSTATE_UINT16(rightbot_x
, Exynos4210fimdWindow
),
1870 VMSTATE_UINT16(rightbot_y
, Exynos4210fimdWindow
),
1871 VMSTATE_UINT32(osdsize
, Exynos4210fimdWindow
),
1872 VMSTATE_UINT32_ARRAY(alpha_val
, Exynos4210fimdWindow
, 2),
1873 VMSTATE_UINT16(virtpage_width
, Exynos4210fimdWindow
),
1874 VMSTATE_UINT16(virtpage_offsize
, Exynos4210fimdWindow
),
1875 VMSTATE_END_OF_LIST()
1879 static const VMStateDescription exynos4210_fimd_vmstate
= {
1880 .name
= "exynos4210.fimd",
1882 .minimum_version_id
= 1,
1883 .post_load
= exynos4210_fimd_load
,
1884 .fields
= (VMStateField
[]) {
1885 VMSTATE_UINT32_ARRAY(vidcon
, Exynos4210fimdState
, 4),
1886 VMSTATE_UINT32_ARRAY(vidtcon
, Exynos4210fimdState
, 4),
1887 VMSTATE_UINT32(shadowcon
, Exynos4210fimdState
),
1888 VMSTATE_UINT32(winchmap
, Exynos4210fimdState
),
1889 VMSTATE_UINT32_ARRAY(vidintcon
, Exynos4210fimdState
, 2),
1890 VMSTATE_UINT32(dithmode
, Exynos4210fimdState
),
1891 VMSTATE_UINT32_ARRAY(wpalcon
, Exynos4210fimdState
, 2),
1892 VMSTATE_UINT32(trigcon
, Exynos4210fimdState
),
1893 VMSTATE_UINT32_ARRAY(i80ifcon
, Exynos4210fimdState
, 4),
1894 VMSTATE_UINT32(colorgaincon
, Exynos4210fimdState
),
1895 VMSTATE_UINT32_ARRAY(ldi_cmdcon
, Exynos4210fimdState
, 2),
1896 VMSTATE_UINT32_ARRAY(sifccon
, Exynos4210fimdState
, 3),
1897 VMSTATE_UINT32_ARRAY(huecoef_cr
, Exynos4210fimdState
, 4),
1898 VMSTATE_UINT32_ARRAY(huecoef_cb
, Exynos4210fimdState
, 4),
1899 VMSTATE_UINT32(hueoffset
, Exynos4210fimdState
),
1900 VMSTATE_UINT32_ARRAY(i80ifcmd
, Exynos4210fimdState
, 12),
1901 VMSTATE_UINT32(blendcon
, Exynos4210fimdState
),
1902 VMSTATE_STRUCT_ARRAY(window
, Exynos4210fimdState
, 5, 1,
1903 exynos4210_fimd_window_vmstate
, Exynos4210fimdWindow
),
1904 VMSTATE_END_OF_LIST()
1908 static const GraphicHwOps exynos4210_fimd_ops
= {
1909 .invalidate
= exynos4210_fimd_invalidate
,
1910 .gfx_update
= exynos4210_fimd_update
,
1913 static void exynos4210_fimd_init(Object
*obj
)
1915 Exynos4210fimdState
*s
= EXYNOS4210_FIMD(obj
);
1916 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1920 sysbus_init_irq(dev
, &s
->irq
[0]);
1921 sysbus_init_irq(dev
, &s
->irq
[1]);
1922 sysbus_init_irq(dev
, &s
->irq
[2]);
1924 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_fimd_mmio_ops
, s
,
1925 "exynos4210.fimd", FIMD_REGS_SIZE
);
1926 sysbus_init_mmio(dev
, &s
->iomem
);
1929 static void exynos4210_fimd_realize(DeviceState
*dev
, Error
**errp
)
1931 Exynos4210fimdState
*s
= EXYNOS4210_FIMD(dev
);
1933 s
->console
= graphic_console_init(dev
, 0, &exynos4210_fimd_ops
, s
);
1936 static void exynos4210_fimd_class_init(ObjectClass
*klass
, void *data
)
1938 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1940 dc
->vmsd
= &exynos4210_fimd_vmstate
;
1941 dc
->reset
= exynos4210_fimd_reset
;
1942 dc
->realize
= exynos4210_fimd_realize
;
1945 static const TypeInfo exynos4210_fimd_info
= {
1946 .name
= TYPE_EXYNOS4210_FIMD
,
1947 .parent
= TYPE_SYS_BUS_DEVICE
,
1948 .instance_size
= sizeof(Exynos4210fimdState
),
1949 .instance_init
= exynos4210_fimd_init
,
1950 .class_init
= exynos4210_fimd_class_init
,
1953 static void exynos4210_fimd_register_types(void)
1955 type_register_static(&exynos4210_fimd_info
);
1958 type_init(exynos4210_fimd_register_types
)