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parallels: Switch to byte-based calls
[qemu/ar7.git] / hw / sparc / sun4m.c
blobb984d2da0e3e3e1645d44ab12f1da481b96a5d94
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m_iommu.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/isa/isa.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "trace.h"
48 #include "qemu/cutils.h"
49
50 /*
51 * Sun4m architecture was used in the following machines:
52 *
53 * SPARCserver 6xxMP/xx
54 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
55 * SPARCclassic X (4/10)
56 * SPARCstation LX/ZX (4/30)
57 * SPARCstation Voyager
58 * SPARCstation 10/xx, SPARCserver 10/xx
59 * SPARCstation 5, SPARCserver 5
60 * SPARCstation 20/xx, SPARCserver 20
61 * SPARCstation 4
62 *
63 * See for example: http://www.sunhelp.org/faq/sunref1.html
64 */
65
66 #define KERNEL_LOAD_ADDR 0x00004000
67 #define CMDLINE_ADDR 0x007ff000
68 #define INITRD_LOAD_ADDR 0x00800000
69 #define PROM_SIZE_MAX (1024 * 1024)
70 #define PROM_VADDR 0xffd00000
71 #define PROM_FILENAME "openbios-sparc32"
72 #define CFG_ADDR 0xd00000510ULL
73 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
74 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
75 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
76
77 #define MAX_CPUS 16
78 #define MAX_PILS 16
79 #define MAX_VSIMMS 4
80
81 #define ESCC_CLOCK 4915200
82
83 struct sun4m_hwdef {
84 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
85 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
86 hwaddr serial_base, fd_base;
87 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
88 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
89 hwaddr bpp_base, dbri_base, sx_base;
90 struct {
91 hwaddr reg_base, vram_base;
92 } vsimm[MAX_VSIMMS];
93 hwaddr ecc_base;
94 uint64_t max_mem;
95 uint32_t ecc_version;
96 uint32_t iommu_version;
97 uint16_t machine_id;
98 uint8_t nvram_machine_id;
99 };
100
101 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
102 Error **errp)
103 {
104 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
105 }
106
107 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
108 const char *cmdline, const char *boot_devices,
109 ram_addr_t RAM_size, uint32_t kernel_size,
110 int width, int height, int depth,
111 int nvram_machine_id, const char *arch)
112 {
113 unsigned int i;
114 int sysp_end;
115 uint8_t image[0x1ff0];
116 NvramClass *k = NVRAM_GET_CLASS(nvram);
117
118 memset(image, '\0', sizeof(image));
119
120 /* OpenBIOS nvram variables partition */
121 sysp_end = chrp_nvram_create_system_partition(image, 0);
122
123 /* Free space partition */
124 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
125
126 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
127 nvram_machine_id);
128
129 for (i = 0; i < sizeof(image); i++) {
130 (k->write)(nvram, i, image[i]);
131 }
132 }
133
134 void cpu_check_irqs(CPUSPARCState *env)
135 {
136 CPUState *cs;
137
138 /* We should be holding the BQL before we mess with IRQs */
139 g_assert(qemu_mutex_iothread_locked());
140
141 if (env->pil_in && (env->interrupt_index == 0 ||
142 (env->interrupt_index & ~15) == TT_EXTINT)) {
143 unsigned int i;
144
145 for (i = 15; i > 0; i--) {
146 if (env->pil_in & (1 << i)) {
147 int old_interrupt = env->interrupt_index;
148
149 env->interrupt_index = TT_EXTINT | i;
150 if (old_interrupt != env->interrupt_index) {
151 cs = CPU(sparc_env_get_cpu(env));
152 trace_sun4m_cpu_interrupt(i);
153 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
154 }
155 break;
156 }
157 }
158 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
159 cs = CPU(sparc_env_get_cpu(env));
160 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
161 env->interrupt_index = 0;
162 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
163 }
164 }
165
166 static void cpu_kick_irq(SPARCCPU *cpu)
167 {
168 CPUSPARCState *env = &cpu->env;
169 CPUState *cs = CPU(cpu);
170
171 cs->halted = 0;
172 cpu_check_irqs(env);
173 qemu_cpu_kick(cs);
174 }
175
176 static void cpu_set_irq(void *opaque, int irq, int level)
177 {
178 SPARCCPU *cpu = opaque;
179 CPUSPARCState *env = &cpu->env;
180
181 if (level) {
182 trace_sun4m_cpu_set_irq_raise(irq);
183 env->pil_in |= 1 << irq;
184 cpu_kick_irq(cpu);
185 } else {
186 trace_sun4m_cpu_set_irq_lower(irq);
187 env->pil_in &= ~(1 << irq);
188 cpu_check_irqs(env);
189 }
190 }
191
192 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
193 {
194 }
195
196 static void main_cpu_reset(void *opaque)
197 {
198 SPARCCPU *cpu = opaque;
199 CPUState *cs = CPU(cpu);
200
201 cpu_reset(cs);
202 cs->halted = 0;
203 }
204
205 static void secondary_cpu_reset(void *opaque)
206 {
207 SPARCCPU *cpu = opaque;
208 CPUState *cs = CPU(cpu);
209
210 cpu_reset(cs);
211 cs->halted = 1;
212 }
213
214 static void cpu_halt_signal(void *opaque, int irq, int level)
215 {
216 if (level && current_cpu) {
217 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
218 }
219 }
220
221 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
222 {
223 return addr - 0xf0000000ULL;
224 }
225
226 static unsigned long sun4m_load_kernel(const char *kernel_filename,
227 const char *initrd_filename,
228 ram_addr_t RAM_size)
229 {
230 int linux_boot;
231 unsigned int i;
232 long initrd_size, kernel_size;
233 uint8_t *ptr;
234
235 linux_boot = (kernel_filename != NULL);
236
237 kernel_size = 0;
238 if (linux_boot) {
239 int bswap_needed;
240
241 #ifdef BSWAP_NEEDED
242 bswap_needed = 1;
243 #else
244 bswap_needed = 0;
245 #endif
246 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
247 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
248 if (kernel_size < 0)
249 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
250 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
251 TARGET_PAGE_SIZE);
252 if (kernel_size < 0)
253 kernel_size = load_image_targphys(kernel_filename,
254 KERNEL_LOAD_ADDR,
255 RAM_size - KERNEL_LOAD_ADDR);
256 if (kernel_size < 0) {
257 error_report("could not load kernel '%s'", kernel_filename);
258 exit(1);
259 }
260
261 /* load initrd */
262 initrd_size = 0;
263 if (initrd_filename) {
264 initrd_size = load_image_targphys(initrd_filename,
265 INITRD_LOAD_ADDR,
266 RAM_size - INITRD_LOAD_ADDR);
267 if (initrd_size < 0) {
268 error_report("could not load initial ram disk '%s'",
269 initrd_filename);
270 exit(1);
271 }
272 }
273 if (initrd_size > 0) {
274 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
275 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
276 if (ldl_p(ptr) == 0x48647253) { // HdrS
277 stl_p(ptr + 16, INITRD_LOAD_ADDR);
278 stl_p(ptr + 20, initrd_size);
279 break;
280 }
281 }
282 }
283 }
284 return kernel_size;
285 }
286
287 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
288 {
289 DeviceState *dev;
290 SysBusDevice *s;
291
292 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
293 qdev_prop_set_uint32(dev, "version", version);
294 qdev_init_nofail(dev);
295 s = SYS_BUS_DEVICE(dev);
296 sysbus_connect_irq(s, 0, irq);
297 sysbus_mmio_map(s, 0, addr);
298
299 return s;
300 }
301
302 static void *sparc32_dma_init(hwaddr dma_base,
303 hwaddr esp_base, qemu_irq espdma_irq,
304 hwaddr le_base, qemu_irq ledma_irq)
305 {
306 DeviceState *dma;
307 ESPDMADeviceState *espdma;
308 LEDMADeviceState *ledma;
309 SysBusESPState *esp;
310 SysBusPCNetState *lance;
311
312 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
313 qdev_init_nofail(dma);
314 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
315
316 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
317 OBJECT(dma), "espdma"));
318 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
319
320 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
321 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
322 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
323
324 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
325 OBJECT(dma), "ledma"));
326 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
327
328 lance = SYSBUS_PCNET(object_resolve_path_component(
329 OBJECT(ledma), "lance"));
330 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
331
332 return dma;
333 }
334
335 static DeviceState *slavio_intctl_init(hwaddr addr,
336 hwaddr addrg,
337 qemu_irq **parent_irq)
338 {
339 DeviceState *dev;
340 SysBusDevice *s;
341 unsigned int i, j;
342
343 dev = qdev_create(NULL, "slavio_intctl");
344 qdev_init_nofail(dev);
345
346 s = SYS_BUS_DEVICE(dev);
347
348 for (i = 0; i < MAX_CPUS; i++) {
349 for (j = 0; j < MAX_PILS; j++) {
350 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
351 }
352 }
353 sysbus_mmio_map(s, 0, addrg);
354 for (i = 0; i < MAX_CPUS; i++) {
355 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
356 }
357
358 return dev;
359 }
360
361 #define SYS_TIMER_OFFSET 0x10000ULL
362 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
363
364 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
365 qemu_irq *cpu_irqs, unsigned int num_cpus)
366 {
367 DeviceState *dev;
368 SysBusDevice *s;
369 unsigned int i;
370
371 dev = qdev_create(NULL, "slavio_timer");
372 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
373 qdev_init_nofail(dev);
374 s = SYS_BUS_DEVICE(dev);
375 sysbus_connect_irq(s, 0, master_irq);
376 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
377
378 for (i = 0; i < MAX_CPUS; i++) {
379 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
380 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
381 }
382 }
383
384 static qemu_irq slavio_system_powerdown;
385
386 static void slavio_powerdown_req(Notifier *n, void *opaque)
387 {
388 qemu_irq_raise(slavio_system_powerdown);
389 }
390
391 static Notifier slavio_system_powerdown_notifier = {
392 .notify = slavio_powerdown_req
393 };
394
395 #define MISC_LEDS 0x01600000
396 #define MISC_CFG 0x01800000
397 #define MISC_DIAG 0x01a00000
398 #define MISC_MDM 0x01b00000
399 #define MISC_SYS 0x01f00000
400
401 static void slavio_misc_init(hwaddr base,
402 hwaddr aux1_base,
403 hwaddr aux2_base, qemu_irq irq,
404 qemu_irq fdc_tc)
405 {
406 DeviceState *dev;
407 SysBusDevice *s;
408
409 dev = qdev_create(NULL, "slavio_misc");
410 qdev_init_nofail(dev);
411 s = SYS_BUS_DEVICE(dev);
412 if (base) {
413 /* 8 bit registers */
414 /* Slavio control */
415 sysbus_mmio_map(s, 0, base + MISC_CFG);
416 /* Diagnostics */
417 sysbus_mmio_map(s, 1, base + MISC_DIAG);
418 /* Modem control */
419 sysbus_mmio_map(s, 2, base + MISC_MDM);
420 /* 16 bit registers */
421 /* ss600mp diag LEDs */
422 sysbus_mmio_map(s, 3, base + MISC_LEDS);
423 /* 32 bit registers */
424 /* System control */
425 sysbus_mmio_map(s, 4, base + MISC_SYS);
426 }
427 if (aux1_base) {
428 /* AUX 1 (Misc System Functions) */
429 sysbus_mmio_map(s, 5, aux1_base);
430 }
431 if (aux2_base) {
432 /* AUX 2 (Software Powerdown Control) */
433 sysbus_mmio_map(s, 6, aux2_base);
434 }
435 sysbus_connect_irq(s, 0, irq);
436 sysbus_connect_irq(s, 1, fdc_tc);
437 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
438 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
439 }
440
441 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
442 {
443 DeviceState *dev;
444 SysBusDevice *s;
445
446 dev = qdev_create(NULL, "eccmemctl");
447 qdev_prop_set_uint32(dev, "version", version);
448 qdev_init_nofail(dev);
449 s = SYS_BUS_DEVICE(dev);
450 sysbus_connect_irq(s, 0, irq);
451 sysbus_mmio_map(s, 0, base);
452 if (version == 0) { // SS-600MP only
453 sysbus_mmio_map(s, 1, base + 0x1000);
454 }
455 }
456
457 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
458 {
459 DeviceState *dev;
460 SysBusDevice *s;
461
462 dev = qdev_create(NULL, "apc");
463 qdev_init_nofail(dev);
464 s = SYS_BUS_DEVICE(dev);
465 /* Power management (APC) XXX: not a Slavio device */
466 sysbus_mmio_map(s, 0, power_base);
467 sysbus_connect_irq(s, 0, cpu_halt);
468 }
469
470 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
471 int height, int depth)
472 {
473 DeviceState *dev;
474 SysBusDevice *s;
475
476 dev = qdev_create(NULL, "SUNW,tcx");
477 qdev_prop_set_uint32(dev, "vram_size", vram_size);
478 qdev_prop_set_uint16(dev, "width", width);
479 qdev_prop_set_uint16(dev, "height", height);
480 qdev_prop_set_uint16(dev, "depth", depth);
481 qdev_init_nofail(dev);
482 s = SYS_BUS_DEVICE(dev);
483
484 /* 10/ROM : FCode ROM */
485 sysbus_mmio_map(s, 0, addr);
486 /* 2/STIP : Stipple */
487 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
488 /* 3/BLIT : Blitter */
489 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
490 /* 5/RSTIP : Raw Stipple */
491 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
492 /* 6/RBLIT : Raw Blitter */
493 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
494 /* 7/TEC : Transform Engine */
495 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
496 /* 8/CMAP : DAC */
497 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
498 /* 9/THC : */
499 if (depth == 8) {
500 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
501 } else {
502 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
503 }
504 /* 11/DHC : */
505 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
506 /* 12/ALT : */
507 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
508 /* 0/DFB8 : 8-bit plane */
509 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
510 /* 1/DFB24 : 24bit plane */
511 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
512 /* 4/RDFB32: Raw framebuffer. Control plane */
513 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
514 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
515 if (depth == 8) {
516 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
517 }
518
519 sysbus_connect_irq(s, 0, irq);
520 }
521
522 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
523 int height, int depth)
524 {
525 DeviceState *dev;
526 SysBusDevice *s;
527
528 dev = qdev_create(NULL, "cgthree");
529 qdev_prop_set_uint32(dev, "vram-size", vram_size);
530 qdev_prop_set_uint16(dev, "width", width);
531 qdev_prop_set_uint16(dev, "height", height);
532 qdev_prop_set_uint16(dev, "depth", depth);
533 qdev_init_nofail(dev);
534 s = SYS_BUS_DEVICE(dev);
535
536 /* FCode ROM */
537 sysbus_mmio_map(s, 0, addr);
538 /* DAC */
539 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
540 /* 8-bit plane */
541 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
542
543 sysbus_connect_irq(s, 0, irq);
544 }
545
546 /* NCR89C100/MACIO Internal ID register */
547
548 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
549
550 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
551
552 static void idreg_init(hwaddr addr)
553 {
554 DeviceState *dev;
555 SysBusDevice *s;
556
557 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
558 qdev_init_nofail(dev);
559 s = SYS_BUS_DEVICE(dev);
560
561 sysbus_mmio_map(s, 0, addr);
562 cpu_physical_memory_write_rom(&address_space_memory,
563 addr, idreg_data, sizeof(idreg_data));
564 }
565
566 #define MACIO_ID_REGISTER(obj) \
567 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
568
569 typedef struct IDRegState {
570 SysBusDevice parent_obj;
571
572 MemoryRegion mem;
573 } IDRegState;
574
575 static void idreg_realize(DeviceState *ds, Error **errp)
576 {
577 IDRegState *s = MACIO_ID_REGISTER(ds);
578 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
579 Error *local_err = NULL;
580
581 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
582 sizeof(idreg_data), &local_err);
583 if (local_err) {
584 error_propagate(errp, local_err);
585 return;
586 }
587
588 vmstate_register_ram_global(&s->mem);
589 memory_region_set_readonly(&s->mem, true);
590 sysbus_init_mmio(dev, &s->mem);
591 }
592
593 static void idreg_class_init(ObjectClass *oc, void *data)
594 {
595 DeviceClass *dc = DEVICE_CLASS(oc);
596
597 dc->realize = idreg_realize;
598 }
599
600 static const TypeInfo idreg_info = {
601 .name = TYPE_MACIO_ID_REGISTER,
602 .parent = TYPE_SYS_BUS_DEVICE,
603 .instance_size = sizeof(IDRegState),
604 .class_init = idreg_class_init,
605 };
606
607 #define TYPE_TCX_AFX "tcx_afx"
608 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
609
610 typedef struct AFXState {
611 SysBusDevice parent_obj;
612
613 MemoryRegion mem;
614 } AFXState;
615
616 /* SS-5 TCX AFX register */
617 static void afx_init(hwaddr addr)
618 {
619 DeviceState *dev;
620 SysBusDevice *s;
621
622 dev = qdev_create(NULL, TYPE_TCX_AFX);
623 qdev_init_nofail(dev);
624 s = SYS_BUS_DEVICE(dev);
625
626 sysbus_mmio_map(s, 0, addr);
627 }
628
629 static void afx_realize(DeviceState *ds, Error **errp)
630 {
631 AFXState *s = TCX_AFX(ds);
632 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
633 Error *local_err = NULL;
634
635 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
636 &local_err);
637 if (local_err) {
638 error_propagate(errp, local_err);
639 return;
640 }
641
642 vmstate_register_ram_global(&s->mem);
643 sysbus_init_mmio(dev, &s->mem);
644 }
645
646 static void afx_class_init(ObjectClass *oc, void *data)
647 {
648 DeviceClass *dc = DEVICE_CLASS(oc);
649
650 dc->realize = afx_realize;
651 }
652
653 static const TypeInfo afx_info = {
654 .name = TYPE_TCX_AFX,
655 .parent = TYPE_SYS_BUS_DEVICE,
656 .instance_size = sizeof(AFXState),
657 .class_init = afx_class_init,
658 };
659
660 #define TYPE_OPENPROM "openprom"
661 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
662
663 typedef struct PROMState {
664 SysBusDevice parent_obj;
665
666 MemoryRegion prom;
667 } PROMState;
668
669 /* Boot PROM (OpenBIOS) */
670 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
671 {
672 hwaddr *base_addr = (hwaddr *)opaque;
673 return addr + *base_addr - PROM_VADDR;
674 }
675
676 static void prom_init(hwaddr addr, const char *bios_name)
677 {
678 DeviceState *dev;
679 SysBusDevice *s;
680 char *filename;
681 int ret;
682
683 dev = qdev_create(NULL, TYPE_OPENPROM);
684 qdev_init_nofail(dev);
685 s = SYS_BUS_DEVICE(dev);
686
687 sysbus_mmio_map(s, 0, addr);
688
689 /* load boot prom */
690 if (bios_name == NULL) {
691 bios_name = PROM_FILENAME;
692 }
693 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
694 if (filename) {
695 ret = load_elf(filename, translate_prom_address, &addr, NULL,
696 NULL, NULL, 1, EM_SPARC, 0, 0);
697 if (ret < 0 || ret > PROM_SIZE_MAX) {
698 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
699 }
700 g_free(filename);
701 } else {
702 ret = -1;
703 }
704 if (ret < 0 || ret > PROM_SIZE_MAX) {
705 error_report("could not load prom '%s'", bios_name);
706 exit(1);
707 }
708 }
709
710 static void prom_realize(DeviceState *ds, Error **errp)
711 {
712 PROMState *s = OPENPROM(ds);
713 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
714 Error *local_err = NULL;
715
716 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
717 PROM_SIZE_MAX, &local_err);
718 if (local_err) {
719 error_propagate(errp, local_err);
720 return;
721 }
722
723 vmstate_register_ram_global(&s->prom);
724 memory_region_set_readonly(&s->prom, true);
725 sysbus_init_mmio(dev, &s->prom);
726 }
727
728 static Property prom_properties[] = {
729 {/* end of property list */},
730 };
731
732 static void prom_class_init(ObjectClass *klass, void *data)
733 {
734 DeviceClass *dc = DEVICE_CLASS(klass);
735
736 dc->props = prom_properties;
737 dc->realize = prom_realize;
738 }
739
740 static const TypeInfo prom_info = {
741 .name = TYPE_OPENPROM,
742 .parent = TYPE_SYS_BUS_DEVICE,
743 .instance_size = sizeof(PROMState),
744 .class_init = prom_class_init,
745 };
746
747 #define TYPE_SUN4M_MEMORY "memory"
748 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
749
750 typedef struct RamDevice {
751 SysBusDevice parent_obj;
752
753 MemoryRegion ram;
754 uint64_t size;
755 } RamDevice;
756
757 /* System RAM */
758 static void ram_realize(DeviceState *dev, Error **errp)
759 {
760 RamDevice *d = SUN4M_RAM(dev);
761 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
762
763 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
764 d->size);
765 sysbus_init_mmio(sbd, &d->ram);
766 }
767
768 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
769 uint64_t max_mem)
770 {
771 DeviceState *dev;
772 SysBusDevice *s;
773 RamDevice *d;
774
775 /* allocate RAM */
776 if ((uint64_t)RAM_size > max_mem) {
777 error_report("Too much memory for this machine: %d, maximum %d",
778 (unsigned int)(RAM_size / (1024 * 1024)),
779 (unsigned int)(max_mem / (1024 * 1024)));
780 exit(1);
781 }
782 dev = qdev_create(NULL, "memory");
783 s = SYS_BUS_DEVICE(dev);
784
785 d = SUN4M_RAM(dev);
786 d->size = RAM_size;
787 qdev_init_nofail(dev);
788
789 sysbus_mmio_map(s, 0, addr);
790 }
791
792 static Property ram_properties[] = {
793 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
794 DEFINE_PROP_END_OF_LIST(),
795 };
796
797 static void ram_class_init(ObjectClass *klass, void *data)
798 {
799 DeviceClass *dc = DEVICE_CLASS(klass);
800
801 dc->realize = ram_realize;
802 dc->props = ram_properties;
803 }
804
805 static const TypeInfo ram_info = {
806 .name = TYPE_SUN4M_MEMORY,
807 .parent = TYPE_SYS_BUS_DEVICE,
808 .instance_size = sizeof(RamDevice),
809 .class_init = ram_class_init,
810 };
811
812 static void cpu_devinit(const char *cpu_type, unsigned int id,
813 uint64_t prom_addr, qemu_irq **cpu_irqs)
814 {
815 CPUState *cs;
816 SPARCCPU *cpu;
817 CPUSPARCState *env;
818
819 cpu = SPARC_CPU(cpu_create(cpu_type));
820 env = &cpu->env;
821
822 cpu_sparc_set_id(env, id);
823 if (id == 0) {
824 qemu_register_reset(main_cpu_reset, cpu);
825 } else {
826 qemu_register_reset(secondary_cpu_reset, cpu);
827 cs = CPU(cpu);
828 cs->halted = 1;
829 }
830 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
831 env->prom_addr = prom_addr;
832 }
833
834 static void dummy_fdc_tc(void *opaque, int irq, int level)
835 {
836 }
837
838 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
839 MachineState *machine)
840 {
841 DeviceState *slavio_intctl;
842 unsigned int i;
843 void *nvram;
844 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
845 qemu_irq fdc_tc;
846 unsigned long kernel_size;
847 DriveInfo *fd[MAX_FD];
848 FWCfgState *fw_cfg;
849 unsigned int num_vsimms;
850 DeviceState *dev;
851 SysBusDevice *s;
852
853 /* init CPUs */
854 for(i = 0; i < smp_cpus; i++) {
855 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
856 }
857
858 for (i = smp_cpus; i < MAX_CPUS; i++)
859 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
860
861
862 /* set up devices */
863 ram_init(0, machine->ram_size, hwdef->max_mem);
864 /* models without ECC don't trap when missing ram is accessed */
865 if (!hwdef->ecc_base) {
866 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
867 }
868
869 prom_init(hwdef->slavio_base, bios_name);
870
871 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
872 hwdef->intctl_base + 0x10000ULL,
873 cpu_irqs);
874
875 for (i = 0; i < 32; i++) {
876 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
877 }
878 for (i = 0; i < MAX_CPUS; i++) {
879 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
880 }
881
882 if (hwdef->idreg_base) {
883 idreg_init(hwdef->idreg_base);
884 }
885
886 if (hwdef->afx_base) {
887 afx_init(hwdef->afx_base);
888 }
889
890 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
891
892 if (hwdef->iommu_pad_base) {
893 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894 Software shouldn't use aliased addresses, neither should it crash
895 when does. Using empty_slot instead of aliasing can help with
896 debugging such accesses */
897 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
898 }
899
900 sparc32_dma_init(hwdef->dma_base,
901 hwdef->esp_base, slavio_irq[18],
902 hwdef->le_base, slavio_irq[16]);
903
904 if (graphic_depth != 8 && graphic_depth != 24) {
905 error_report("Unsupported depth: %d", graphic_depth);
906 exit (1);
907 }
908 num_vsimms = 0;
909 if (num_vsimms == 0) {
910 if (vga_interface_type == VGA_CG3) {
911 if (graphic_depth != 8) {
912 error_report("Unsupported depth: %d", graphic_depth);
913 exit(1);
914 }
915
916 if (!(graphic_width == 1024 && graphic_height == 768) &&
917 !(graphic_width == 1152 && graphic_height == 900)) {
918 error_report("Unsupported resolution: %d x %d", graphic_width,
919 graphic_height);
920 exit(1);
921 }
922
923 /* sbus irq 5 */
924 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
925 graphic_width, graphic_height, graphic_depth);
926 } else {
927 /* If no display specified, default to TCX */
928 if (graphic_depth != 8 && graphic_depth != 24) {
929 error_report("Unsupported depth: %d", graphic_depth);
930 exit(1);
931 }
932
933 if (!(graphic_width == 1024 && graphic_height == 768)) {
934 error_report("Unsupported resolution: %d x %d",
935 graphic_width, graphic_height);
936 exit(1);
937 }
938
939 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
940 graphic_width, graphic_height, graphic_depth);
941 }
942 }
943
944 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
945 /* vsimm registers probed by OBP */
946 if (hwdef->vsimm[i].reg_base) {
947 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
948 }
949 }
950
951 if (hwdef->sx_base) {
952 empty_slot_init(hwdef->sx_base, 0x2000);
953 }
954
955 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
956
957 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
958
959 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
960 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
961 dev = qdev_create(NULL, TYPE_ESCC);
962 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
963 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
964 qdev_prop_set_uint32(dev, "it_shift", 1);
965 qdev_prop_set_chr(dev, "chrB", NULL);
966 qdev_prop_set_chr(dev, "chrA", NULL);
967 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
968 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
969 qdev_init_nofail(dev);
970 s = SYS_BUS_DEVICE(dev);
971 sysbus_connect_irq(s, 0, slavio_irq[14]);
972 sysbus_connect_irq(s, 1, slavio_irq[14]);
973 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
974
975 dev = qdev_create(NULL, TYPE_ESCC);
976 qdev_prop_set_uint32(dev, "disabled", 0);
977 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
978 qdev_prop_set_uint32(dev, "it_shift", 1);
979 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
980 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
981 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
982 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
983 qdev_init_nofail(dev);
984
985 s = SYS_BUS_DEVICE(dev);
986 sysbus_connect_irq(s, 0, slavio_irq[15]);
987 sysbus_connect_irq(s, 1, slavio_irq[15]);
988 sysbus_mmio_map(s, 0, hwdef->serial_base);
989
990 if (hwdef->apc_base) {
991 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
992 }
993
994 if (hwdef->fd_base) {
995 /* there is zero or one floppy drive */
996 memset(fd, 0, sizeof(fd));
997 fd[0] = drive_get(IF_FLOPPY, 0, 0);
998 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
999 &fdc_tc);
1000 } else {
1001 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1002 }
1003
1004 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1005 slavio_irq[30], fdc_tc);
1006
1007 if (hwdef->cs_base) {
1008 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1009 slavio_irq[5]);
1010 }
1011
1012 if (hwdef->dbri_base) {
1013 /* ISDN chip with attached CS4215 audio codec */
1014 /* prom space */
1015 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1016 /* reg space */
1017 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1018 }
1019
1020 if (hwdef->bpp_base) {
1021 /* parallel port */
1022 empty_slot_init(hwdef->bpp_base, 0x20);
1023 }
1024
1025 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1026 machine->initrd_filename,
1027 machine->ram_size);
1028
1029 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1030 machine->boot_order, machine->ram_size, kernel_size,
1031 graphic_width, graphic_height, graphic_depth,
1032 hwdef->nvram_machine_id, "Sun4m");
1033
1034 if (hwdef->ecc_base)
1035 ecc_init(hwdef->ecc_base, slavio_irq[28],
1036 hwdef->ecc_version);
1037
1038 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1039 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1040 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1041 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1042 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1043 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1044 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1045 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1047 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1048 if (machine->kernel_cmdline) {
1049 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1050 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1051 machine->kernel_cmdline);
1052 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1053 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1054 strlen(machine->kernel_cmdline) + 1);
1055 } else {
1056 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1057 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1058 }
1059 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1060 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1061 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1062 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1063 }
1064
1065 enum {
1066 ss5_id = 32,
1067 vger_id,
1068 lx_id,
1069 ss4_id,
1070 scls_id,
1071 sbook_id,
1072 ss10_id = 64,
1073 ss20_id,
1074 ss600mp_id,
1075 };
1076
1077 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1078 /* SS-5 */
1079 {
1080 .iommu_base = 0x10000000,
1081 .iommu_pad_base = 0x10004000,
1082 .iommu_pad_len = 0x0fffb000,
1083 .tcx_base = 0x50000000,
1084 .cs_base = 0x6c000000,
1085 .slavio_base = 0x70000000,
1086 .ms_kb_base = 0x71000000,
1087 .serial_base = 0x71100000,
1088 .nvram_base = 0x71200000,
1089 .fd_base = 0x71400000,
1090 .counter_base = 0x71d00000,
1091 .intctl_base = 0x71e00000,
1092 .idreg_base = 0x78000000,
1093 .dma_base = 0x78400000,
1094 .esp_base = 0x78800000,
1095 .le_base = 0x78c00000,
1096 .apc_base = 0x6a000000,
1097 .afx_base = 0x6e000000,
1098 .aux1_base = 0x71900000,
1099 .aux2_base = 0x71910000,
1100 .nvram_machine_id = 0x80,
1101 .machine_id = ss5_id,
1102 .iommu_version = 0x05000000,
1103 .max_mem = 0x10000000,
1104 },
1105 /* SS-10 */
1106 {
1107 .iommu_base = 0xfe0000000ULL,
1108 .tcx_base = 0xe20000000ULL,
1109 .slavio_base = 0xff0000000ULL,
1110 .ms_kb_base = 0xff1000000ULL,
1111 .serial_base = 0xff1100000ULL,
1112 .nvram_base = 0xff1200000ULL,
1113 .fd_base = 0xff1700000ULL,
1114 .counter_base = 0xff1300000ULL,
1115 .intctl_base = 0xff1400000ULL,
1116 .idreg_base = 0xef0000000ULL,
1117 .dma_base = 0xef0400000ULL,
1118 .esp_base = 0xef0800000ULL,
1119 .le_base = 0xef0c00000ULL,
1120 .apc_base = 0xefa000000ULL, // XXX should not exist
1121 .aux1_base = 0xff1800000ULL,
1122 .aux2_base = 0xff1a01000ULL,
1123 .ecc_base = 0xf00000000ULL,
1124 .ecc_version = 0x10000000, // version 0, implementation 1
1125 .nvram_machine_id = 0x72,
1126 .machine_id = ss10_id,
1127 .iommu_version = 0x03000000,
1128 .max_mem = 0xf00000000ULL,
1129 },
1130 /* SS-600MP */
1131 {
1132 .iommu_base = 0xfe0000000ULL,
1133 .tcx_base = 0xe20000000ULL,
1134 .slavio_base = 0xff0000000ULL,
1135 .ms_kb_base = 0xff1000000ULL,
1136 .serial_base = 0xff1100000ULL,
1137 .nvram_base = 0xff1200000ULL,
1138 .counter_base = 0xff1300000ULL,
1139 .intctl_base = 0xff1400000ULL,
1140 .dma_base = 0xef0081000ULL,
1141 .esp_base = 0xef0080000ULL,
1142 .le_base = 0xef0060000ULL,
1143 .apc_base = 0xefa000000ULL, // XXX should not exist
1144 .aux1_base = 0xff1800000ULL,
1145 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1146 .ecc_base = 0xf00000000ULL,
1147 .ecc_version = 0x00000000, // version 0, implementation 0
1148 .nvram_machine_id = 0x71,
1149 .machine_id = ss600mp_id,
1150 .iommu_version = 0x01000000,
1151 .max_mem = 0xf00000000ULL,
1152 },
1153 /* SS-20 */
1154 {
1155 .iommu_base = 0xfe0000000ULL,
1156 .tcx_base = 0xe20000000ULL,
1157 .slavio_base = 0xff0000000ULL,
1158 .ms_kb_base = 0xff1000000ULL,
1159 .serial_base = 0xff1100000ULL,
1160 .nvram_base = 0xff1200000ULL,
1161 .fd_base = 0xff1700000ULL,
1162 .counter_base = 0xff1300000ULL,
1163 .intctl_base = 0xff1400000ULL,
1164 .idreg_base = 0xef0000000ULL,
1165 .dma_base = 0xef0400000ULL,
1166 .esp_base = 0xef0800000ULL,
1167 .le_base = 0xef0c00000ULL,
1168 .bpp_base = 0xef4800000ULL,
1169 .apc_base = 0xefa000000ULL, // XXX should not exist
1170 .aux1_base = 0xff1800000ULL,
1171 .aux2_base = 0xff1a01000ULL,
1172 .dbri_base = 0xee0000000ULL,
1173 .sx_base = 0xf80000000ULL,
1174 .vsimm = {
1175 {
1176 .reg_base = 0x9c000000ULL,
1177 .vram_base = 0xfc000000ULL
1178 }, {
1179 .reg_base = 0x90000000ULL,
1180 .vram_base = 0xf0000000ULL
1181 }, {
1182 .reg_base = 0x94000000ULL
1183 }, {
1184 .reg_base = 0x98000000ULL
1185 }
1186 },
1187 .ecc_base = 0xf00000000ULL,
1188 .ecc_version = 0x20000000, // version 0, implementation 2
1189 .nvram_machine_id = 0x72,
1190 .machine_id = ss20_id,
1191 .iommu_version = 0x13000000,
1192 .max_mem = 0xf00000000ULL,
1193 },
1194 /* Voyager */
1195 {
1196 .iommu_base = 0x10000000,
1197 .tcx_base = 0x50000000,
1198 .slavio_base = 0x70000000,
1199 .ms_kb_base = 0x71000000,
1200 .serial_base = 0x71100000,
1201 .nvram_base = 0x71200000,
1202 .fd_base = 0x71400000,
1203 .counter_base = 0x71d00000,
1204 .intctl_base = 0x71e00000,
1205 .idreg_base = 0x78000000,
1206 .dma_base = 0x78400000,
1207 .esp_base = 0x78800000,
1208 .le_base = 0x78c00000,
1209 .apc_base = 0x71300000, // pmc
1210 .aux1_base = 0x71900000,
1211 .aux2_base = 0x71910000,
1212 .nvram_machine_id = 0x80,
1213 .machine_id = vger_id,
1214 .iommu_version = 0x05000000,
1215 .max_mem = 0x10000000,
1216 },
1217 /* LX */
1218 {
1219 .iommu_base = 0x10000000,
1220 .iommu_pad_base = 0x10004000,
1221 .iommu_pad_len = 0x0fffb000,
1222 .tcx_base = 0x50000000,
1223 .slavio_base = 0x70000000,
1224 .ms_kb_base = 0x71000000,
1225 .serial_base = 0x71100000,
1226 .nvram_base = 0x71200000,
1227 .fd_base = 0x71400000,
1228 .counter_base = 0x71d00000,
1229 .intctl_base = 0x71e00000,
1230 .idreg_base = 0x78000000,
1231 .dma_base = 0x78400000,
1232 .esp_base = 0x78800000,
1233 .le_base = 0x78c00000,
1234 .aux1_base = 0x71900000,
1235 .aux2_base = 0x71910000,
1236 .nvram_machine_id = 0x80,
1237 .machine_id = lx_id,
1238 .iommu_version = 0x04000000,
1239 .max_mem = 0x10000000,
1240 },
1241 /* SS-4 */
1242 {
1243 .iommu_base = 0x10000000,
1244 .tcx_base = 0x50000000,
1245 .cs_base = 0x6c000000,
1246 .slavio_base = 0x70000000,
1247 .ms_kb_base = 0x71000000,
1248 .serial_base = 0x71100000,
1249 .nvram_base = 0x71200000,
1250 .fd_base = 0x71400000,
1251 .counter_base = 0x71d00000,
1252 .intctl_base = 0x71e00000,
1253 .idreg_base = 0x78000000,
1254 .dma_base = 0x78400000,
1255 .esp_base = 0x78800000,
1256 .le_base = 0x78c00000,
1257 .apc_base = 0x6a000000,
1258 .aux1_base = 0x71900000,
1259 .aux2_base = 0x71910000,
1260 .nvram_machine_id = 0x80,
1261 .machine_id = ss4_id,
1262 .iommu_version = 0x05000000,
1263 .max_mem = 0x10000000,
1264 },
1265 /* SPARCClassic */
1266 {
1267 .iommu_base = 0x10000000,
1268 .tcx_base = 0x50000000,
1269 .slavio_base = 0x70000000,
1270 .ms_kb_base = 0x71000000,
1271 .serial_base = 0x71100000,
1272 .nvram_base = 0x71200000,
1273 .fd_base = 0x71400000,
1274 .counter_base = 0x71d00000,
1275 .intctl_base = 0x71e00000,
1276 .idreg_base = 0x78000000,
1277 .dma_base = 0x78400000,
1278 .esp_base = 0x78800000,
1279 .le_base = 0x78c00000,
1280 .apc_base = 0x6a000000,
1281 .aux1_base = 0x71900000,
1282 .aux2_base = 0x71910000,
1283 .nvram_machine_id = 0x80,
1284 .machine_id = scls_id,
1285 .iommu_version = 0x05000000,
1286 .max_mem = 0x10000000,
1287 },
1288 /* SPARCbook */
1289 {
1290 .iommu_base = 0x10000000,
1291 .tcx_base = 0x50000000, // XXX
1292 .slavio_base = 0x70000000,
1293 .ms_kb_base = 0x71000000,
1294 .serial_base = 0x71100000,
1295 .nvram_base = 0x71200000,
1296 .fd_base = 0x71400000,
1297 .counter_base = 0x71d00000,
1298 .intctl_base = 0x71e00000,
1299 .idreg_base = 0x78000000,
1300 .dma_base = 0x78400000,
1301 .esp_base = 0x78800000,
1302 .le_base = 0x78c00000,
1303 .apc_base = 0x6a000000,
1304 .aux1_base = 0x71900000,
1305 .aux2_base = 0x71910000,
1306 .nvram_machine_id = 0x80,
1307 .machine_id = sbook_id,
1308 .iommu_version = 0x05000000,
1309 .max_mem = 0x10000000,
1310 },
1311 };
1312
1313 /* SPARCstation 5 hardware initialisation */
1314 static void ss5_init(MachineState *machine)
1315 {
1316 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1317 }
1318
1319 /* SPARCstation 10 hardware initialisation */
1320 static void ss10_init(MachineState *machine)
1321 {
1322 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1323 }
1324
1325 /* SPARCserver 600MP hardware initialisation */
1326 static void ss600mp_init(MachineState *machine)
1327 {
1328 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1329 }
1330
1331 /* SPARCstation 20 hardware initialisation */
1332 static void ss20_init(MachineState *machine)
1333 {
1334 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1335 }
1336
1337 /* SPARCstation Voyager hardware initialisation */
1338 static void vger_init(MachineState *machine)
1339 {
1340 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1341 }
1342
1343 /* SPARCstation LX hardware initialisation */
1344 static void ss_lx_init(MachineState *machine)
1345 {
1346 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1347 }
1348
1349 /* SPARCstation 4 hardware initialisation */
1350 static void ss4_init(MachineState *machine)
1351 {
1352 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1353 }
1354
1355 /* SPARCClassic hardware initialisation */
1356 static void scls_init(MachineState *machine)
1357 {
1358 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1359 }
1360
1361 /* SPARCbook hardware initialisation */
1362 static void sbook_init(MachineState *machine)
1363 {
1364 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1365 }
1366
1367 static void ss5_class_init(ObjectClass *oc, void *data)
1368 {
1369 MachineClass *mc = MACHINE_CLASS(oc);
1370
1371 mc->desc = "Sun4m platform, SPARCstation 5";
1372 mc->init = ss5_init;
1373 mc->block_default_type = IF_SCSI;
1374 mc->is_default = 1;
1375 mc->default_boot_order = "c";
1376 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1377 }
1378
1379 static const TypeInfo ss5_type = {
1380 .name = MACHINE_TYPE_NAME("SS-5"),
1381 .parent = TYPE_MACHINE,
1382 .class_init = ss5_class_init,
1383 };
1384
1385 static void ss10_class_init(ObjectClass *oc, void *data)
1386 {
1387 MachineClass *mc = MACHINE_CLASS(oc);
1388
1389 mc->desc = "Sun4m platform, SPARCstation 10";
1390 mc->init = ss10_init;
1391 mc->block_default_type = IF_SCSI;
1392 mc->max_cpus = 4;
1393 mc->default_boot_order = "c";
1394 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1395 }
1396
1397 static const TypeInfo ss10_type = {
1398 .name = MACHINE_TYPE_NAME("SS-10"),
1399 .parent = TYPE_MACHINE,
1400 .class_init = ss10_class_init,
1401 };
1402
1403 static void ss600mp_class_init(ObjectClass *oc, void *data)
1404 {
1405 MachineClass *mc = MACHINE_CLASS(oc);
1406
1407 mc->desc = "Sun4m platform, SPARCserver 600MP";
1408 mc->init = ss600mp_init;
1409 mc->block_default_type = IF_SCSI;
1410 mc->max_cpus = 4;
1411 mc->default_boot_order = "c";
1412 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1413 }
1414
1415 static const TypeInfo ss600mp_type = {
1416 .name = MACHINE_TYPE_NAME("SS-600MP"),
1417 .parent = TYPE_MACHINE,
1418 .class_init = ss600mp_class_init,
1419 };
1420
1421 static void ss20_class_init(ObjectClass *oc, void *data)
1422 {
1423 MachineClass *mc = MACHINE_CLASS(oc);
1424
1425 mc->desc = "Sun4m platform, SPARCstation 20";
1426 mc->init = ss20_init;
1427 mc->block_default_type = IF_SCSI;
1428 mc->max_cpus = 4;
1429 mc->default_boot_order = "c";
1430 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1431 }
1432
1433 static const TypeInfo ss20_type = {
1434 .name = MACHINE_TYPE_NAME("SS-20"),
1435 .parent = TYPE_MACHINE,
1436 .class_init = ss20_class_init,
1437 };
1438
1439 static void voyager_class_init(ObjectClass *oc, void *data)
1440 {
1441 MachineClass *mc = MACHINE_CLASS(oc);
1442
1443 mc->desc = "Sun4m platform, SPARCstation Voyager";
1444 mc->init = vger_init;
1445 mc->block_default_type = IF_SCSI;
1446 mc->default_boot_order = "c";
1447 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1448 }
1449
1450 static const TypeInfo voyager_type = {
1451 .name = MACHINE_TYPE_NAME("Voyager"),
1452 .parent = TYPE_MACHINE,
1453 .class_init = voyager_class_init,
1454 };
1455
1456 static void ss_lx_class_init(ObjectClass *oc, void *data)
1457 {
1458 MachineClass *mc = MACHINE_CLASS(oc);
1459
1460 mc->desc = "Sun4m platform, SPARCstation LX";
1461 mc->init = ss_lx_init;
1462 mc->block_default_type = IF_SCSI;
1463 mc->default_boot_order = "c";
1464 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1465 }
1466
1467 static const TypeInfo ss_lx_type = {
1468 .name = MACHINE_TYPE_NAME("LX"),
1469 .parent = TYPE_MACHINE,
1470 .class_init = ss_lx_class_init,
1471 };
1472
1473 static void ss4_class_init(ObjectClass *oc, void *data)
1474 {
1475 MachineClass *mc = MACHINE_CLASS(oc);
1476
1477 mc->desc = "Sun4m platform, SPARCstation 4";
1478 mc->init = ss4_init;
1479 mc->block_default_type = IF_SCSI;
1480 mc->default_boot_order = "c";
1481 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1482 }
1483
1484 static const TypeInfo ss4_type = {
1485 .name = MACHINE_TYPE_NAME("SS-4"),
1486 .parent = TYPE_MACHINE,
1487 .class_init = ss4_class_init,
1488 };
1489
1490 static void scls_class_init(ObjectClass *oc, void *data)
1491 {
1492 MachineClass *mc = MACHINE_CLASS(oc);
1493
1494 mc->desc = "Sun4m platform, SPARCClassic";
1495 mc->init = scls_init;
1496 mc->block_default_type = IF_SCSI;
1497 mc->default_boot_order = "c";
1498 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1499 }
1500
1501 static const TypeInfo scls_type = {
1502 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1503 .parent = TYPE_MACHINE,
1504 .class_init = scls_class_init,
1505 };
1506
1507 static void sbook_class_init(ObjectClass *oc, void *data)
1508 {
1509 MachineClass *mc = MACHINE_CLASS(oc);
1510
1511 mc->desc = "Sun4m platform, SPARCbook";
1512 mc->init = sbook_init;
1513 mc->block_default_type = IF_SCSI;
1514 mc->default_boot_order = "c";
1515 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1516 }
1517
1518 static const TypeInfo sbook_type = {
1519 .name = MACHINE_TYPE_NAME("SPARCbook"),
1520 .parent = TYPE_MACHINE,
1521 .class_init = sbook_class_init,
1522 };
1523
1524 static void sun4m_register_types(void)
1525 {
1526 type_register_static(&idreg_info);
1527 type_register_static(&afx_info);
1528 type_register_static(&prom_info);
1529 type_register_static(&ram_info);
1530
1531 type_register_static(&ss5_type);
1532 type_register_static(&ss10_type);
1533 type_register_static(&ss600mp_type);
1534 type_register_static(&ss20_type);
1535 type_register_static(&voyager_type);
1536 type_register_static(&ss_lx_type);
1537 type_register_static(&ss4_type);
1538 type_register_static(&scls_type);
1539 type_register_static(&sbook_type);
1540 }
1541
1542 type_init(sun4m_register_types)
AR7 emulation for QEMU