ppc/pnv: check size before data buffer access
[qemu/ar7.git] / hw / hppa / pci.c
blob766420254e147496dc92c88d14c01f6c0a57df74
1 /*
2 * QEMU HP-PARISC PCI support functions.
4 */
6 #include "qemu/osdep.h"
7 #include "qemu-common.h"
8 #include "hppa_sys.h"
9 #include "qemu/log.h"
10 #include "sysemu/sysemu.h"
11 #include "trace.h"
14 /* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
16 static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
18 return 0;
21 static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
25 const MemoryRegionOps hppa_pci_ignore_ops = {
26 .read = ignore_read,
27 .write = ignore_write,
28 .endianness = DEVICE_BIG_ENDIAN,
29 .valid = {
30 .min_access_size = 1,
31 .max_access_size = 8,
33 .impl = {
34 .min_access_size = 1,
35 .max_access_size = 8,
40 /* PCI config space reads/writes, to byte-word addressable memory. */
41 static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
42 unsigned size)
44 PCIBus *b = opaque;
45 return pci_data_read(b, addr, size);
48 static void bw_conf1_write(void *opaque, hwaddr addr,
49 uint64_t val, unsigned size)
51 PCIBus *b = opaque;
52 pci_data_write(b, addr, val, size);
55 const MemoryRegionOps hppa_pci_conf1_ops = {
56 .read = bw_conf1_read,
57 .write = bw_conf1_write,
58 .endianness = DEVICE_BIG_ENDIAN,
59 .impl = {
60 .min_access_size = 1,
61 .max_access_size = 4,
65 /* PCI/EISA Interrupt Acknowledge Cycle. */
67 static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
69 return pic_read_irq(isa_pic);
72 static void special_write(void *opaque, hwaddr addr,
73 uint64_t val, unsigned size)
75 trace_hppa_pci_iack_write();
78 const MemoryRegionOps hppa_pci_iack_ops = {
79 .read = iack_read,
80 .write = special_write,
81 .endianness = DEVICE_BIG_ENDIAN,
82 .valid = {
83 .min_access_size = 4,
84 .max_access_size = 4,
86 .impl = {
87 .min_access_size = 4,
88 .max_access_size = 4,