cputlb.c

   1 /*
   2  *  Common CPU TLB handling
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "config.h"
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/memory.h"
  24 #include "exec/address-spaces.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #include "exec/cputlb.h"
  28
  29 #include "exec/memory-internal.h"
  30 #include "exec/ram_addr.h"
  31 #include "tcg/tcg.h"
  32
  33 //#define DEBUG_TLB
  34 //#define DEBUG_TLB_CHECK
  35
  36 /* statistics */
  37 int tlb_flush_count;
  38
  39 /* NOTE:
  40  * If flush_global is true (the usual case), flush all tlb entries.
  41  * If flush_global is false, flush (at least) all tlb entries not
  42  * marked global.
  43  *
  44  * Since QEMU doesn't currently implement a global/not-global flag
  45  * for tlb entries, at the moment tlb_flush() will also flush all
  46  * tlb entries in the flush_global == false case. This is OK because
  47  * CPU architectures generally permit an implementation to drop
  48  * entries from the TLB at any time, so flushing more entries than
  49  * required is only an efficiency issue, not a correctness issue.
  50  */
  51 void tlb_flush(CPUState *cpu, int flush_global)
  52 {
  53     CPUArchState *env = cpu->env_ptr;
  54
  55 #if defined(DEBUG_TLB)
  56     printf("tlb_flush:\n");
  57 #endif
  58     /* must reset current TB so that interrupts cannot modify the
  59        links while we are modifying them */
  60     cpu->current_tb = NULL;
  61
  62     memset(env->tlb_table, -1, sizeof(env->tlb_table));
  63     memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
  64
  65     env->tlb_flush_addr = -1;
  66     env->tlb_flush_mask = 0;
  67     tlb_flush_count++;
  68 }
  69
  70 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
  71 {
  72     if (addr == (tlb_entry->addr_read &
  73                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  74         addr == (tlb_entry->addr_write &
  75                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
  76         addr == (tlb_entry->addr_code &
  77                  (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  78         memset(tlb_entry, -1, sizeof(*tlb_entry));
  79     }
  80 }
  81
  82 void tlb_flush_page(CPUState *cpu, target_ulong addr)
  83 {
  84     CPUArchState *env = cpu->env_ptr;
  85     int i;
  86     int mmu_idx;
  87
  88 #if defined(DEBUG_TLB)
  89     printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
  90 #endif
  91     /* Check if we need to flush due to large pages.  */
  92     if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
  93 #if defined(DEBUG_TLB)
  94         printf("tlb_flush_page: forced full flush ("
  95                TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
  96                env->tlb_flush_addr, env->tlb_flush_mask);
  97 #endif
  98         tlb_flush(cpu, 1);
  99         return;
 100     }
 101     /* must reset current TB so that interrupts cannot modify the
 102        links while we are modifying them */
 103     cpu->current_tb = NULL;
 104
 105     addr &= TARGET_PAGE_MASK;
 106     i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 107     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 108         tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
 109     }
 110
 111     tb_flush_jmp_cache(cpu, addr);
 112 }
 113
 114 /* update the TLBs so that writes to code in the virtual page 'addr'
 115    can be detected */
 116 void tlb_protect_code(ram_addr_t ram_addr)
 117 {
 118     cpu_physical_memory_reset_dirty(ram_addr, TARGET_PAGE_SIZE,
 119                                     DIRTY_MEMORY_CODE);
 120 }
 121
 122 /* update the TLB so that writes in physical page 'phys_addr' are no longer
 123    tested for self modifying code */
 124 void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
 125                              target_ulong vaddr)
 126 {
 127     cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
 128 }
 129
 130 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
 131 {
 132     return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
 133 }
 134
 135 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
 136                            uintptr_t length)
 137 {
 138     uintptr_t addr;
 139
 140     if (tlb_is_dirty_ram(tlb_entry)) {
 141         addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
 142         if ((addr - start) < length) {
 143             tlb_entry->addr_write |= TLB_NOTDIRTY;
 144         }
 145     }
 146 }
 147
 148 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
 149 {
 150     ram_addr_t ram_addr;
 151
 152     if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
 153         fprintf(stderr, "Bad ram pointer %p\n", ptr);
 154         abort();
 155     }
 156     return ram_addr;
 157 }
 158
 159 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
 160 {
 161     CPUState *cpu;
 162     CPUArchState *env;
 163
 164     CPU_FOREACH(cpu) {
 165         int mmu_idx;
 166
 167         env = cpu->env_ptr;
 168         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 169             unsigned int i;
 170
 171             for (i = 0; i < CPU_TLB_SIZE; i++) {
 172                 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
 173                                       start1, length);
 174             }
 175         }
 176     }
 177 }
 178
 179 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
 180 {
 181     if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
 182         tlb_entry->addr_write = vaddr;
 183     }
 184 }
 185
 186 /* update the TLB corresponding to virtual page vaddr
 187    so that it is no longer dirty */
 188 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
 189 {
 190     int i;
 191     int mmu_idx;
 192
 193     vaddr &= TARGET_PAGE_MASK;
 194     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 195     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 196         tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
 197     }
 198 }
 199
 200 /* Our TLB does not support large pages, so remember the area covered by
 201    large pages and trigger a full TLB flush if these are invalidated.  */
 202 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
 203                                target_ulong size)
 204 {
 205     target_ulong mask = ~(size - 1);
 206
 207     if (env->tlb_flush_addr == (target_ulong)-1) {
 208         env->tlb_flush_addr = vaddr & mask;
 209         env->tlb_flush_mask = mask;
 210         return;
 211     }
 212     /* Extend the existing region to include the new page.
 213        This is a compromise between unnecessary flushes and the cost
 214        of maintaining a full variable size TLB.  */
 215     mask &= env->tlb_flush_mask;
 216     while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
 217         mask <<= 1;
 218     }
 219     env->tlb_flush_addr &= mask;
 220     env->tlb_flush_mask = mask;
 221 }
 222
 223 /* Add a new TLB entry. At most one entry for a given virtual address
 224    is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
 225    supplied size is only used by tlb_flush_page.  */
 226 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 227                   hwaddr paddr, int prot,
 228                   int mmu_idx, target_ulong size)
 229 {
 230     CPUArchState *env = cpu->env_ptr;
 231     MemoryRegionSection *section;
 232     unsigned int index;
 233     target_ulong address;
 234     target_ulong code_address;
 235     uintptr_t addend;
 236     CPUTLBEntry *te;
 237     hwaddr iotlb, xlat, sz;
 238
 239     assert(size >= TARGET_PAGE_SIZE);
 240     if (size != TARGET_PAGE_SIZE) {
 241         tlb_add_large_page(env, vaddr, size);
 242     }
 243
 244     sz = size;
 245     section = address_space_translate_for_iotlb(cpu->as, paddr,
 246                                                 &xlat, &sz);
 247     assert(sz >= TARGET_PAGE_SIZE);
 248
 249 #if defined(DEBUG_TLB)
 250     printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
 251            " prot=%x idx=%d\n",
 252            vaddr, paddr, prot, mmu_idx);
 253 #endif
 254
 255     address = vaddr;
 256     if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
 257         /* IO memory case */
 258         address |= TLB_MMIO;
 259         addend = 0;
 260     } else {
 261         /* TLB_MMIO for rom/romd handled below */
 262         addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
 263     }
 264
 265     code_address = address;
 266     iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
 267                                             prot, &address);
 268
 269     index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 270     env->iotlb[mmu_idx][index] = iotlb - vaddr;
 271     te = &env->tlb_table[mmu_idx][index];
 272     te->addend = addend - vaddr;
 273     if (prot & PAGE_READ) {
 274         te->addr_read = address;
 275     } else {
 276         te->addr_read = -1;
 277     }
 278
 279     if (prot & PAGE_EXEC) {
 280         te->addr_code = code_address;
 281     } else {
 282         te->addr_code = -1;
 283     }
 284     if (prot & PAGE_WRITE) {
 285         if ((memory_region_is_ram(section->mr) && section->readonly)
 286             || memory_region_is_romd(section->mr)) {
 287             /* Write access calls the I/O callback.  */
 288             te->addr_write = address | TLB_MMIO;
 289         } else if (memory_region_is_ram(section->mr)
 290                    && cpu_physical_memory_is_clean(section->mr->ram_addr
 291                                                    + xlat)) {
 292             te->addr_write = address | TLB_NOTDIRTY;
 293         } else {
 294             te->addr_write = address;
 295         }
 296     } else {
 297         te->addr_write = -1;
 298     }
 299 }
 300
 301 /* NOTE: this function can trigger an exception */
 302 /* NOTE2: the returned address is not exactly the physical address: it
 303  * is actually a ram_addr_t (in system mode; the user mode emulation
 304  * version of this function returns a guest virtual address).
 305  */
 306 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 307 {
 308     int mmu_idx, page_index, pd;
 309     void *p;
 310     MemoryRegion *mr;
 311     CPUState *cpu = ENV_GET_CPU(env1);
 312
 313     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 314     mmu_idx = cpu_mmu_index(env1);
 315     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 316                  (addr & TARGET_PAGE_MASK))) {
 317         cpu_ldub_code(env1, addr);
 318     }
 319     pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
 320     mr = iotlb_to_region(cpu->as, pd);
 321     if (memory_region_is_unassigned(mr)) {
 322         CPUClass *cc = CPU_GET_CLASS(cpu);
 323
 324         if (cc->do_unassigned_access) {
 325             cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
 326         } else {
 327             cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
 328                       TARGET_FMT_lx "\n", addr);
 329         }
 330     }
 331     p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
 332     return qemu_ram_addr_from_host_nofail(p);
 333 }
 334
 335 #define MMUSUFFIX _mmu
 336
 337 #define SHIFT 0
 338 #include "softmmu_template.h"
 339
 340 #define SHIFT 1
 341 #include "softmmu_template.h"
 342
 343 #define SHIFT 2
 344 #include "softmmu_template.h"
 345
 346 #define SHIFT 3
 347 #include "softmmu_template.h"
 348 #undef MMUSUFFIX
 349
 350 #define MMUSUFFIX _cmmu
 351 #undef GETPC_ADJ
 352 #define GETPC_ADJ 0
 353 #undef GETRA
 354 #define GETRA() ((uintptr_t)0)
 355 #define SOFTMMU_CODE_ACCESS
 356
 357 #define SHIFT 0
 358 #include "softmmu_template.h"
 359
 360 #define SHIFT 1
 361 #include "softmmu_template.h"
 362
 363 #define SHIFT 2
 364 #include "softmmu_template.h"
 365
 366 #define SHIFT 3
 367 #include "softmmu_template.h"