2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/i386/pc.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/isa/isa.h"
30 #include "hw/sysbus.h"
31 #include "qemu/range.h"
32 #include "hw/xen/xen.h"
33 #include "hw/pci-host/pam.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/i386/ioapic.h"
36 #include "qapi/visitor.h"
39 * I440FX chipset data sheet.
40 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
44 #define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
47 typedef struct I440FXState
{
48 PCIHostState parent_obj
;
50 uint64_t pci_hole64_size
;
51 uint32_t short_root_bus
;
54 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
55 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
56 #define XEN_PIIX_NUM_PIRQS 128ULL
57 #define PIIX_PIRQC 0x60
60 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
61 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
63 #define RCR_IOPORT 0xcf9
65 typedef struct PIIX3State
{
69 * bitmap to track pic levels.
70 * The pic level is the logical OR of all the PCI irqs mapped to it
71 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
73 * PIRQ is mapped to PIC pins, we track it by
74 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
75 * pic_irq * PIIX_NUM_PIRQS + pirq
77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
78 #error "unable to encode pic state in 64bit in pic_levels."
84 /* This member isn't used. Just for save/load compatibility */
85 int32_t pci_irq_levels_vmstate
[PIIX_NUM_PIRQS
];
87 /* Reset Control Register contents */
90 /* IO memory region for Reset Control Register (RCR_IOPORT) */
94 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
95 #define PIIX3_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
98 #define TYPE_I440FX_PCI_DEVICE "i440FX"
99 #define I440FX_PCI_DEVICE(obj) \
100 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
102 struct PCII440FXState
{
104 PCIDevice parent_obj
;
107 MemoryRegion
*system_memory
;
108 MemoryRegion
*pci_address_space
;
109 MemoryRegion
*ram_memory
;
110 PAMMemoryRegion pam_regions
[13];
111 MemoryRegion smram_region
;
112 MemoryRegion smram
, low_smram
;
116 #define I440FX_PAM 0x59
117 #define I440FX_PAM_SIZE 7
118 #define I440FX_SMRAM 0x72
120 static void piix3_set_irq(void *opaque
, int pirq
, int level
);
121 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pci_intx
);
122 static void piix3_write_config_xen(PCIDevice
*dev
,
123 uint32_t address
, uint32_t val
, int len
);
125 /* return the global irq number corresponding to a given device irq
126 pin. We could also use the bus number to have a more precise
128 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int pci_intx
)
131 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
132 return (pci_intx
+ slot_addend
) & 3;
135 static void i440fx_update_memory_mappings(PCII440FXState
*d
)
138 PCIDevice
*pd
= PCI_DEVICE(d
);
140 memory_region_transaction_begin();
141 for (i
= 0; i
< 13; i
++) {
142 pam_update(&d
->pam_regions
[i
], i
,
143 pd
->config
[I440FX_PAM
+ ((i
+ 1) / 2)]);
145 memory_region_set_enabled(&d
->smram_region
,
146 !(pd
->config
[I440FX_SMRAM
] & SMRAM_D_OPEN
));
147 memory_region_set_enabled(&d
->smram
,
148 pd
->config
[I440FX_SMRAM
] & SMRAM_G_SMRAME
);
149 memory_region_transaction_commit();
153 static void i440fx_write_config(PCIDevice
*dev
,
154 uint32_t address
, uint32_t val
, int len
)
156 PCII440FXState
*d
= I440FX_PCI_DEVICE(dev
);
158 /* XXX: implement SMRAM.D_LOCK */
159 pci_default_write_config(dev
, address
, val
, len
);
160 if (ranges_overlap(address
, len
, I440FX_PAM
, I440FX_PAM_SIZE
) ||
161 range_covers_byte(address
, len
, I440FX_SMRAM
)) {
162 i440fx_update_memory_mappings(d
);
166 static int i440fx_load_old(QEMUFile
* f
, void *opaque
, int version_id
)
168 PCII440FXState
*d
= opaque
;
169 PCIDevice
*pd
= PCI_DEVICE(d
);
173 ret
= pci_device_load(pd
, f
);
176 i440fx_update_memory_mappings(d
);
177 qemu_get_8s(f
, &smm_enabled
);
179 if (version_id
== 2) {
180 for (i
= 0; i
< PIIX_NUM_PIRQS
; i
++) {
181 qemu_get_be32(f
); /* dummy load for compatibility */
188 static int i440fx_post_load(void *opaque
, int version_id
)
190 PCII440FXState
*d
= opaque
;
192 i440fx_update_memory_mappings(d
);
196 static const VMStateDescription vmstate_i440fx
= {
199 .minimum_version_id
= 3,
200 .minimum_version_id_old
= 1,
201 .load_state_old
= i440fx_load_old
,
202 .post_load
= i440fx_post_load
,
203 .fields
= (VMStateField
[]) {
204 VMSTATE_PCI_DEVICE(parent_obj
, PCII440FXState
),
205 /* Used to be smm_enabled, which was basically always zero because
206 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
209 VMSTATE_END_OF_LIST()
213 static void i440fx_pcihost_get_pci_hole_start(Object
*obj
, Visitor
*v
,
214 void *opaque
, const char *name
,
217 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
218 uint32_t value
= s
->pci_info
.w32
.begin
;
220 visit_type_uint32(v
, &value
, name
, errp
);
223 static void i440fx_pcihost_get_pci_hole_end(Object
*obj
, Visitor
*v
,
224 void *opaque
, const char *name
,
227 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
228 uint32_t value
= s
->pci_info
.w32
.end
;
230 visit_type_uint32(v
, &value
, name
, errp
);
233 static void i440fx_pcihost_get_pci_hole64_start(Object
*obj
, Visitor
*v
,
234 void *opaque
, const char *name
,
237 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
240 pci_bus_get_w64_range(h
->bus
, &w64
);
242 visit_type_uint64(v
, &w64
.begin
, name
, errp
);
245 static void i440fx_pcihost_get_pci_hole64_end(Object
*obj
, Visitor
*v
,
246 void *opaque
, const char *name
,
249 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
252 pci_bus_get_w64_range(h
->bus
, &w64
);
254 visit_type_uint64(v
, &w64
.end
, name
, errp
);
257 static void i440fx_pcihost_initfn(Object
*obj
)
259 PCIHostState
*s
= PCI_HOST_BRIDGE(obj
);
260 I440FXState
*d
= I440FX_PCI_HOST_BRIDGE(obj
);
262 memory_region_init_io(&s
->conf_mem
, obj
, &pci_host_conf_le_ops
, s
,
264 memory_region_init_io(&s
->data_mem
, obj
, &pci_host_data_le_ops
, s
,
267 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_START
, "int",
268 i440fx_pcihost_get_pci_hole_start
,
269 NULL
, NULL
, NULL
, NULL
);
271 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_END
, "int",
272 i440fx_pcihost_get_pci_hole_end
,
273 NULL
, NULL
, NULL
, NULL
);
275 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_START
, "int",
276 i440fx_pcihost_get_pci_hole64_start
,
277 NULL
, NULL
, NULL
, NULL
);
279 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_END
, "int",
280 i440fx_pcihost_get_pci_hole64_end
,
281 NULL
, NULL
, NULL
, NULL
);
283 d
->pci_info
.w32
.end
= IO_APIC_DEFAULT_ADDRESS
;
286 static void i440fx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
288 PCIHostState
*s
= PCI_HOST_BRIDGE(dev
);
289 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
291 sysbus_add_io(sbd
, 0xcf8, &s
->conf_mem
);
292 sysbus_init_ioports(sbd
, 0xcf8, 4);
294 sysbus_add_io(sbd
, 0xcfc, &s
->data_mem
);
295 sysbus_init_ioports(sbd
, 0xcfc, 4);
298 static void i440fx_realize(PCIDevice
*dev
, Error
**errp
)
300 dev
->config
[I440FX_SMRAM
] = 0x02;
303 PCIBus
*i440fx_init(PCII440FXState
**pi440fx_state
,
305 ISABus
**isa_bus
, qemu_irq
*pic
,
306 MemoryRegion
*address_space_mem
,
307 MemoryRegion
*address_space_io
,
309 ram_addr_t below_4g_mem_size
,
310 ram_addr_t above_4g_mem_size
,
311 MemoryRegion
*pci_address_space
,
312 MemoryRegion
*ram_memory
)
323 dev
= qdev_create(NULL
, TYPE_I440FX_PCI_HOST_BRIDGE
);
324 s
= PCI_HOST_BRIDGE(dev
);
325 b
= pci_bus_new(dev
, NULL
, pci_address_space
,
326 address_space_io
, 0, TYPE_PCI_BUS
);
328 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev
), NULL
);
329 qdev_init_nofail(dev
);
331 d
= pci_create_simple(b
, 0, TYPE_I440FX_PCI_DEVICE
);
332 *pi440fx_state
= I440FX_PCI_DEVICE(d
);
334 f
->system_memory
= address_space_mem
;
335 f
->pci_address_space
= pci_address_space
;
336 f
->ram_memory
= ram_memory
;
338 i440fx
= I440FX_PCI_HOST_BRIDGE(dev
);
339 i440fx
->pci_info
.w32
.begin
= below_4g_mem_size
;
341 /* setup pci memory mapping */
342 pc_pci_as_mapping_init(OBJECT(f
), f
->system_memory
,
343 f
->pci_address_space
);
345 /* if *disabled* show SMRAM to all CPUs */
346 memory_region_init_alias(&f
->smram_region
, OBJECT(d
), "smram-region",
347 f
->pci_address_space
, 0xa0000, 0x20000);
348 memory_region_add_subregion_overlap(f
->system_memory
, 0xa0000,
349 &f
->smram_region
, 1);
350 memory_region_set_enabled(&f
->smram_region
, true);
352 /* smram, as seen by SMM CPUs */
353 memory_region_init(&f
->smram
, OBJECT(d
), "smram", 1ull << 32);
354 memory_region_set_enabled(&f
->smram
, true);
355 memory_region_init_alias(&f
->low_smram
, OBJECT(d
), "smram-low",
356 f
->ram_memory
, 0xa0000, 0x20000);
357 memory_region_set_enabled(&f
->low_smram
, true);
358 memory_region_add_subregion(&f
->smram
, 0xa0000, &f
->low_smram
);
359 object_property_add_const_link(qdev_get_machine(), "smram",
360 OBJECT(&f
->smram
), &error_abort
);
362 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
363 &f
->pam_regions
[0], PAM_BIOS_BASE
, PAM_BIOS_SIZE
);
364 for (i
= 0; i
< 12; ++i
) {
365 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
366 &f
->pam_regions
[i
+1], PAM_EXPAN_BASE
+ i
* PAM_EXPAN_SIZE
,
370 /* Xen supports additional interrupt routes from the PCI devices to
371 * the IOAPIC: the four pins of each PCI device on the bus are also
372 * connected to the IOAPIC directly.
373 * These additional routes can be discovered through ACPI. */
375 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
376 -1, true, "PIIX3-xen");
377 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
378 pci_bus_irqs(b
, xen_piix3_set_irq
, xen_pci_slot_get_pirq
,
379 piix3
, XEN_PIIX_NUM_PIRQS
);
381 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
383 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
384 pci_bus_irqs(b
, piix3_set_irq
, pci_slot_get_pirq
, piix3
,
386 pci_bus_set_route_irq_fn(b
, piix3_route_intx_pin_to_irq
);
389 *isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(piix3
), "isa.0"));
391 *piix3_devfn
= piix3
->dev
.devfn
;
393 ram_size
= ram_size
/ 8 / 1024 / 1024;
394 if (ram_size
> 255) {
397 d
->config
[0x57] = ram_size
;
399 i440fx_update_memory_mappings(f
);
404 PCIBus
*find_i440fx(void)
406 PCIHostState
*s
= OBJECT_CHECK(PCIHostState
,
407 object_resolve_path("/machine/i440fx", NULL
),
408 TYPE_PCI_HOST_BRIDGE
);
409 return s
? s
->bus
: NULL
;
412 /* PIIX3 PCI to ISA bridge */
413 static void piix3_set_irq_pic(PIIX3State
*piix3
, int pic_irq
)
415 qemu_set_irq(piix3
->pic
[pic_irq
],
416 !!(piix3
->pic_levels
&
417 (((1ULL << PIIX_NUM_PIRQS
) - 1) <<
418 (pic_irq
* PIIX_NUM_PIRQS
))));
421 static void piix3_set_irq_level_internal(PIIX3State
*piix3
, int pirq
, int level
)
426 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
427 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
431 mask
= 1ULL << ((pic_irq
* PIIX_NUM_PIRQS
) + pirq
);
432 piix3
->pic_levels
&= ~mask
;
433 piix3
->pic_levels
|= mask
* !!level
;
436 static void piix3_set_irq_level(PIIX3State
*piix3
, int pirq
, int level
)
440 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
441 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
445 piix3_set_irq_level_internal(piix3
, pirq
, level
);
447 piix3_set_irq_pic(piix3
, pic_irq
);
450 static void piix3_set_irq(void *opaque
, int pirq
, int level
)
452 PIIX3State
*piix3
= opaque
;
453 piix3_set_irq_level(piix3
, pirq
, level
);
456 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pin
)
458 PIIX3State
*piix3
= opaque
;
459 int irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pin
];
462 if (irq
< PIIX_NUM_PIC_IRQS
) {
463 route
.mode
= PCI_INTX_ENABLED
;
466 route
.mode
= PCI_INTX_DISABLED
;
472 /* irq routing is changed. so rebuild bitmap */
473 static void piix3_update_irq_levels(PIIX3State
*piix3
)
477 piix3
->pic_levels
= 0;
478 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
479 piix3_set_irq_level(piix3
, pirq
,
480 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
484 static void piix3_write_config(PCIDevice
*dev
,
485 uint32_t address
, uint32_t val
, int len
)
487 pci_default_write_config(dev
, address
, val
, len
);
488 if (ranges_overlap(address
, len
, PIIX_PIRQC
, 4)) {
489 PIIX3State
*piix3
= PIIX3_PCI_DEVICE(dev
);
492 pci_bus_fire_intx_routing_notifier(piix3
->dev
.bus
);
493 piix3_update_irq_levels(piix3
);
494 for (pic_irq
= 0; pic_irq
< PIIX_NUM_PIC_IRQS
; pic_irq
++) {
495 piix3_set_irq_pic(piix3
, pic_irq
);
500 static void piix3_write_config_xen(PCIDevice
*dev
,
501 uint32_t address
, uint32_t val
, int len
)
503 xen_piix_pci_write_config_client(address
, val
, len
);
504 piix3_write_config(dev
, address
, val
, len
);
507 static void piix3_reset(void *opaque
)
509 PIIX3State
*d
= opaque
;
510 uint8_t *pci_conf
= d
->dev
.config
;
512 pci_conf
[0x04] = 0x07; /* master, memory and I/O */
513 pci_conf
[0x05] = 0x00;
514 pci_conf
[0x06] = 0x00;
515 pci_conf
[0x07] = 0x02; /* PCI_status_devsel_medium */
516 pci_conf
[0x4c] = 0x4d;
517 pci_conf
[0x4e] = 0x03;
518 pci_conf
[0x4f] = 0x00;
519 pci_conf
[0x60] = 0x80;
520 pci_conf
[0x61] = 0x80;
521 pci_conf
[0x62] = 0x80;
522 pci_conf
[0x63] = 0x80;
523 pci_conf
[0x69] = 0x02;
524 pci_conf
[0x70] = 0x80;
525 pci_conf
[0x76] = 0x0c;
526 pci_conf
[0x77] = 0x0c;
527 pci_conf
[0x78] = 0x02;
528 pci_conf
[0x79] = 0x00;
529 pci_conf
[0x80] = 0x00;
530 pci_conf
[0x82] = 0x00;
531 pci_conf
[0xa0] = 0x08;
532 pci_conf
[0xa2] = 0x00;
533 pci_conf
[0xa3] = 0x00;
534 pci_conf
[0xa4] = 0x00;
535 pci_conf
[0xa5] = 0x00;
536 pci_conf
[0xa6] = 0x00;
537 pci_conf
[0xa7] = 0x00;
538 pci_conf
[0xa8] = 0x0f;
539 pci_conf
[0xaa] = 0x00;
540 pci_conf
[0xab] = 0x00;
541 pci_conf
[0xac] = 0x00;
542 pci_conf
[0xae] = 0x00;
548 static int piix3_post_load(void *opaque
, int version_id
)
550 PIIX3State
*piix3
= opaque
;
553 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
554 * might bring the system to a different state than the saved one;
555 * for example, the interrupt could be masked but the i8259 would
556 * not know that yet and would trigger an interrupt in the CPU.
558 * Here, we update irq levels without raising the interrupt.
559 * Interrupt state will be deserialized separately through the i8259.
561 piix3
->pic_levels
= 0;
562 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
563 piix3_set_irq_level_internal(piix3
, pirq
,
564 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
569 static void piix3_pre_save(void *opaque
)
572 PIIX3State
*piix3
= opaque
;
574 for (i
= 0; i
< ARRAY_SIZE(piix3
->pci_irq_levels_vmstate
); i
++) {
575 piix3
->pci_irq_levels_vmstate
[i
] =
576 pci_bus_get_irq_level(piix3
->dev
.bus
, i
);
580 static bool piix3_rcr_needed(void *opaque
)
582 PIIX3State
*piix3
= opaque
;
584 return (piix3
->rcr
!= 0);
587 static const VMStateDescription vmstate_piix3_rcr
= {
590 .minimum_version_id
= 1,
591 .needed
= piix3_rcr_needed
,
592 .fields
= (VMStateField
[]) {
593 VMSTATE_UINT8(rcr
, PIIX3State
),
594 VMSTATE_END_OF_LIST()
598 static const VMStateDescription vmstate_piix3
= {
601 .minimum_version_id
= 2,
602 .post_load
= piix3_post_load
,
603 .pre_save
= piix3_pre_save
,
604 .fields
= (VMStateField
[]) {
605 VMSTATE_PCI_DEVICE(dev
, PIIX3State
),
606 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate
, PIIX3State
,
608 VMSTATE_END_OF_LIST()
610 .subsections
= (const VMStateDescription
*[]) {
617 static void rcr_write(void *opaque
, hwaddr addr
, uint64_t val
, unsigned len
)
619 PIIX3State
*d
= opaque
;
622 qemu_system_reset_request();
625 d
->rcr
= val
& 2; /* keep System Reset type only */
628 static uint64_t rcr_read(void *opaque
, hwaddr addr
, unsigned len
)
630 PIIX3State
*d
= opaque
;
635 static const MemoryRegionOps rcr_ops
= {
638 .endianness
= DEVICE_LITTLE_ENDIAN
641 static void piix3_realize(PCIDevice
*dev
, Error
**errp
)
643 PIIX3State
*d
= PIIX3_PCI_DEVICE(dev
);
645 isa_bus_new(DEVICE(d
), get_system_memory(),
646 pci_address_space_io(dev
));
648 memory_region_init_io(&d
->rcr_mem
, OBJECT(dev
), &rcr_ops
, d
,
649 "piix3-reset-control", 1);
650 memory_region_add_subregion_overlap(pci_address_space_io(dev
), RCR_IOPORT
,
653 qemu_register_reset(piix3_reset
, d
);
656 static void pci_piix3_class_init(ObjectClass
*klass
, void *data
)
658 DeviceClass
*dc
= DEVICE_CLASS(klass
);
659 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
661 dc
->desc
= "ISA bridge";
662 dc
->vmsd
= &vmstate_piix3
;
663 dc
->hotpluggable
= false;
664 k
->realize
= piix3_realize
;
665 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
666 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
667 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
668 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
670 * Reason: part of PIIX3 southbridge, needs to be wired up by
671 * pc_piix.c's pc_init1()
673 dc
->cannot_instantiate_with_device_add_yet
= true;
676 static const TypeInfo piix3_pci_type_info
= {
677 .name
= TYPE_PIIX3_PCI_DEVICE
,
678 .parent
= TYPE_PCI_DEVICE
,
679 .instance_size
= sizeof(PIIX3State
),
681 .class_init
= pci_piix3_class_init
,
684 static void piix3_class_init(ObjectClass
*klass
, void *data
)
686 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
688 k
->config_write
= piix3_write_config
;
691 static const TypeInfo piix3_info
= {
693 .parent
= TYPE_PIIX3_PCI_DEVICE
,
694 .class_init
= piix3_class_init
,
697 static void piix3_xen_class_init(ObjectClass
*klass
, void *data
)
699 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
701 k
->config_write
= piix3_write_config_xen
;
704 static const TypeInfo piix3_xen_info
= {
706 .parent
= TYPE_PIIX3_PCI_DEVICE
,
707 .class_init
= piix3_xen_class_init
,
710 static void i440fx_class_init(ObjectClass
*klass
, void *data
)
712 DeviceClass
*dc
= DEVICE_CLASS(klass
);
713 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
715 k
->realize
= i440fx_realize
;
716 k
->config_write
= i440fx_write_config
;
717 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
718 k
->device_id
= PCI_DEVICE_ID_INTEL_82441
;
720 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
721 dc
->desc
= "Host bridge";
722 dc
->vmsd
= &vmstate_i440fx
;
724 * PCI-facing part of the host bridge, not usable without the
725 * host-facing part, which can't be device_add'ed, yet.
727 dc
->cannot_instantiate_with_device_add_yet
= true;
728 dc
->hotpluggable
= false;
731 static const TypeInfo i440fx_info
= {
732 .name
= TYPE_I440FX_PCI_DEVICE
,
733 .parent
= TYPE_PCI_DEVICE
,
734 .instance_size
= sizeof(PCII440FXState
),
735 .class_init
= i440fx_class_init
,
738 static const char *i440fx_pcihost_root_bus_path(PCIHostState
*host_bridge
,
741 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(host_bridge
);
743 /* For backwards compat with old device paths */
744 if (s
->short_root_bus
) {
750 static Property i440fx_props
[] = {
751 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE
, I440FXState
,
752 pci_hole64_size
, DEFAULT_PCI_HOLE64_SIZE
),
753 DEFINE_PROP_UINT32("short_root_bus", I440FXState
, short_root_bus
, 0),
754 DEFINE_PROP_END_OF_LIST(),
757 static void i440fx_pcihost_class_init(ObjectClass
*klass
, void *data
)
759 DeviceClass
*dc
= DEVICE_CLASS(klass
);
760 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
762 hc
->root_bus_path
= i440fx_pcihost_root_bus_path
;
763 dc
->realize
= i440fx_pcihost_realize
;
765 dc
->props
= i440fx_props
;
768 static const TypeInfo i440fx_pcihost_info
= {
769 .name
= TYPE_I440FX_PCI_HOST_BRIDGE
,
770 .parent
= TYPE_PCI_HOST_BRIDGE
,
771 .instance_size
= sizeof(I440FXState
),
772 .instance_init
= i440fx_pcihost_initfn
,
773 .class_init
= i440fx_pcihost_class_init
,
776 static void i440fx_register_types(void)
778 type_register_static(&i440fx_info
);
779 type_register_static(&piix3_pci_type_info
);
780 type_register_static(&piix3_info
);
781 type_register_static(&piix3_xen_info
);
782 type_register_static(&i440fx_pcihost_info
);
785 type_init(i440fx_register_types
)