4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
40 #else /* !CONFIG_USER_ONLY */
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
69 #include "qemu/mmap-alloc.h"
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
82 static MemoryRegion
*system_memory
;
83 static MemoryRegion
*system_io
;
85 AddressSpace address_space_io
;
86 AddressSpace address_space_memory
;
88 MemoryRegion io_mem_rom
, io_mem_notdirty
;
89 static MemoryRegion io_mem_unassigned
;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 /* UFFDIO_ZEROPAGE is available on this RAMBlock to atomically
103 * zero the page and wake waiting processes.
104 * (Set during postcopy)
106 #define RAM_UF_ZEROPAGE (1 << 3)
108 /* RAM can be migrated */
109 #define RAM_MIGRATABLE (1 << 4)
112 #ifdef TARGET_PAGE_BITS_VARY
113 int target_page_bits
;
114 bool target_page_bits_decided
;
117 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
118 /* current CPU in the current thread. It is only valid inside
120 __thread CPUState
*current_cpu
;
121 /* 0 = Do not count executed instructions.
122 1 = Precise instruction counting.
123 2 = Adaptive rate instruction counting. */
126 uintptr_t qemu_host_page_size
;
127 intptr_t qemu_host_page_mask
;
129 bool set_preferred_target_page_bits(int bits
)
131 /* The target page size is the lowest common denominator for all
132 * the CPUs in the system, so we can only make it smaller, never
133 * larger. And we can't make it smaller once we've committed to
136 #ifdef TARGET_PAGE_BITS_VARY
137 assert(bits
>= TARGET_PAGE_BITS_MIN
);
138 if (target_page_bits
== 0 || target_page_bits
> bits
) {
139 if (target_page_bits_decided
) {
142 target_page_bits
= bits
;
148 #if !defined(CONFIG_USER_ONLY)
150 static void finalize_target_page_bits(void)
152 #ifdef TARGET_PAGE_BITS_VARY
153 if (target_page_bits
== 0) {
154 target_page_bits
= TARGET_PAGE_BITS_MIN
;
156 target_page_bits_decided
= true;
160 typedef struct PhysPageEntry PhysPageEntry
;
162 struct PhysPageEntry
{
163 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
165 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
169 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
171 /* Size of the L2 (and L3, etc) page tables. */
172 #define ADDR_SPACE_BITS 64
175 #define P_L2_SIZE (1 << P_L2_BITS)
177 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
179 typedef PhysPageEntry Node
[P_L2_SIZE
];
181 typedef struct PhysPageMap
{
184 unsigned sections_nb
;
185 unsigned sections_nb_alloc
;
187 unsigned nodes_nb_alloc
;
189 MemoryRegionSection
*sections
;
192 struct AddressSpaceDispatch
{
193 MemoryRegionSection
*mru_section
;
194 /* This is a multi-level map on the physical address space.
195 * The bottom level has pointers to MemoryRegionSections.
197 PhysPageEntry phys_map
;
201 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
202 typedef struct subpage_t
{
206 uint16_t sub_section
[];
209 #define PHYS_SECTION_UNASSIGNED 0
210 #define PHYS_SECTION_NOTDIRTY 1
211 #define PHYS_SECTION_ROM 2
212 #define PHYS_SECTION_WATCH 3
214 static void io_mem_init(void);
215 static void memory_map_init(void);
216 static void tcg_commit(MemoryListener
*listener
);
218 static MemoryRegion io_mem_watch
;
221 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
222 * @cpu: the CPU whose AddressSpace this is
223 * @as: the AddressSpace itself
224 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
225 * @tcg_as_listener: listener for tracking changes to the AddressSpace
227 struct CPUAddressSpace
{
230 struct AddressSpaceDispatch
*memory_dispatch
;
231 MemoryListener tcg_as_listener
;
234 struct DirtyBitmapSnapshot
{
237 unsigned long dirty
[];
242 #if !defined(CONFIG_USER_ONLY)
244 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
246 static unsigned alloc_hint
= 16;
247 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
248 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
249 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
250 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
251 alloc_hint
= map
->nodes_nb_alloc
;
255 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
262 ret
= map
->nodes_nb
++;
264 assert(ret
!= PHYS_MAP_NODE_NIL
);
265 assert(ret
!= map
->nodes_nb_alloc
);
267 e
.skip
= leaf
? 0 : 1;
268 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
269 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
270 memcpy(&p
[i
], &e
, sizeof(e
));
275 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
276 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
280 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
282 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
283 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
285 p
= map
->nodes
[lp
->ptr
];
286 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
288 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
289 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
295 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
301 static void phys_page_set(AddressSpaceDispatch
*d
,
302 hwaddr index
, hwaddr nb
,
305 /* Wildly overreserve - it doesn't matter much. */
306 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
308 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
311 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
312 * and update our entry so we can skip it and go directly to the destination.
314 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
316 unsigned valid_ptr
= P_L2_SIZE
;
321 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
326 for (i
= 0; i
< P_L2_SIZE
; i
++) {
327 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
334 phys_page_compact(&p
[i
], nodes
);
338 /* We can only compress if there's only one child. */
343 assert(valid_ptr
< P_L2_SIZE
);
345 /* Don't compress if it won't fit in the # of bits we have. */
346 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
350 lp
->ptr
= p
[valid_ptr
].ptr
;
351 if (!p
[valid_ptr
].skip
) {
352 /* If our only child is a leaf, make this a leaf. */
353 /* By design, we should have made this node a leaf to begin with so we
354 * should never reach here.
355 * But since it's so simple to handle this, let's do it just in case we
360 lp
->skip
+= p
[valid_ptr
].skip
;
364 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
366 if (d
->phys_map
.skip
) {
367 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
371 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
374 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
375 * the section must cover the entire address space.
377 return int128_gethi(section
->size
) ||
378 range_covers_byte(section
->offset_within_address_space
,
379 int128_getlo(section
->size
), addr
);
382 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
384 PhysPageEntry lp
= d
->phys_map
, *p
;
385 Node
*nodes
= d
->map
.nodes
;
386 MemoryRegionSection
*sections
= d
->map
.sections
;
387 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
390 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
391 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
392 return §ions
[PHYS_SECTION_UNASSIGNED
];
395 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
398 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
399 return §ions
[lp
.ptr
];
401 return §ions
[PHYS_SECTION_UNASSIGNED
];
405 bool memory_region_is_unassigned(MemoryRegion
*mr
)
407 return mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !mr
->rom_device
408 && mr
!= &io_mem_watch
;
411 /* Called from RCU critical section */
412 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
414 bool resolve_subpage
)
416 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
419 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
420 !section_covers_addr(section
, addr
)) {
421 section
= phys_page_find(d
, addr
);
422 atomic_set(&d
->mru_section
, section
);
424 if (resolve_subpage
&& section
->mr
->subpage
) {
425 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
426 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
431 /* Called from RCU critical section */
432 static MemoryRegionSection
*
433 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
434 hwaddr
*plen
, bool resolve_subpage
)
436 MemoryRegionSection
*section
;
440 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
441 /* Compute offset within MemoryRegionSection */
442 addr
-= section
->offset_within_address_space
;
444 /* Compute offset within MemoryRegion */
445 *xlat
= addr
+ section
->offset_within_region
;
449 /* MMIO registers can be expected to perform full-width accesses based only
450 * on their address, without considering adjacent registers that could
451 * decode to completely different MemoryRegions. When such registers
452 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
453 * regions overlap wildly. For this reason we cannot clamp the accesses
456 * If the length is small (as is the case for address_space_ldl/stl),
457 * everything works fine. If the incoming length is large, however,
458 * the caller really has to do the clamping through memory_access_size.
460 if (memory_region_is_ram(mr
)) {
461 diff
= int128_sub(section
->size
, int128_make64(addr
));
462 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
468 * address_space_translate_iommu - translate an address through an IOMMU
469 * memory region and then through the target address space.
471 * @iommu_mr: the IOMMU memory region that we start the translation from
472 * @addr: the address to be translated through the MMU
473 * @xlat: the translated address offset within the destination memory region.
474 * It cannot be %NULL.
475 * @plen_out: valid read/write length of the translated address. It
477 * @page_mask_out: page mask for the translated address. This
478 * should only be meaningful for IOMMU translated
479 * addresses, since there may be huge pages that this bit
480 * would tell. It can be %NULL if we don't care about it.
481 * @is_write: whether the translation operation is for write
482 * @is_mmio: whether this can be MMIO, set true if it can
483 * @target_as: the address space targeted by the IOMMU
484 * @attrs: transaction attributes
486 * This function is called from RCU critical section. It is the common
487 * part of flatview_do_translate and address_space_translate_cached.
489 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
492 hwaddr
*page_mask_out
,
495 AddressSpace
**target_as
,
498 MemoryRegionSection
*section
;
499 hwaddr page_mask
= (hwaddr
)-1;
503 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
507 if (imrc
->attrs_to_index
) {
508 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
511 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
512 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
514 if (!(iotlb
.perm
& (1 << is_write
))) {
518 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
519 | (addr
& iotlb
.addr_mask
));
520 page_mask
&= iotlb
.addr_mask
;
521 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
522 *target_as
= iotlb
.target_as
;
524 section
= address_space_translate_internal(
525 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
528 iommu_mr
= memory_region_get_iommu(section
->mr
);
529 } while (unlikely(iommu_mr
));
532 *page_mask_out
= page_mask
;
537 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
541 * flatview_do_translate - translate an address in FlatView
543 * @fv: the flat view that we want to translate on
544 * @addr: the address to be translated in above address space
545 * @xlat: the translated address offset within memory region. It
547 * @plen_out: valid read/write length of the translated address. It
548 * can be @NULL when we don't care about it.
549 * @page_mask_out: page mask for the translated address. This
550 * should only be meaningful for IOMMU translated
551 * addresses, since there may be huge pages that this bit
552 * would tell. It can be @NULL if we don't care about it.
553 * @is_write: whether the translation operation is for write
554 * @is_mmio: whether this can be MMIO, set true if it can
555 * @target_as: the address space targeted by the IOMMU
556 * @attrs: memory transaction attributes
558 * This function is called from RCU critical section
560 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
564 hwaddr
*page_mask_out
,
567 AddressSpace
**target_as
,
570 MemoryRegionSection
*section
;
571 IOMMUMemoryRegion
*iommu_mr
;
572 hwaddr plen
= (hwaddr
)(-1);
578 section
= address_space_translate_internal(
579 flatview_to_dispatch(fv
), addr
, xlat
,
582 iommu_mr
= memory_region_get_iommu(section
->mr
);
583 if (unlikely(iommu_mr
)) {
584 return address_space_translate_iommu(iommu_mr
, xlat
,
585 plen_out
, page_mask_out
,
590 /* Not behind an IOMMU, use default page size. */
591 *page_mask_out
= ~TARGET_PAGE_MASK
;
597 /* Called from RCU critical section */
598 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
599 bool is_write
, MemTxAttrs attrs
)
601 MemoryRegionSection section
;
602 hwaddr xlat
, page_mask
;
605 * This can never be MMIO, and we don't really care about plen,
608 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
609 NULL
, &page_mask
, is_write
, false, &as
,
612 /* Illegal translation */
613 if (section
.mr
== &io_mem_unassigned
) {
617 /* Convert memory region offset into address space offset */
618 xlat
+= section
.offset_within_address_space
-
619 section
.offset_within_region
;
621 return (IOMMUTLBEntry
) {
623 .iova
= addr
& ~page_mask
,
624 .translated_addr
= xlat
& ~page_mask
,
625 .addr_mask
= page_mask
,
626 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
631 return (IOMMUTLBEntry
) {0};
634 /* Called from RCU critical section */
635 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
636 hwaddr
*plen
, bool is_write
,
640 MemoryRegionSection section
;
641 AddressSpace
*as
= NULL
;
643 /* This can be MMIO, so setup MMIO bit. */
644 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
645 is_write
, true, &as
, attrs
);
648 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
649 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
650 *plen
= MIN(page
, *plen
);
656 typedef struct TCGIOMMUNotifier
{
664 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
666 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
668 if (!notifier
->active
) {
671 tlb_flush(notifier
->cpu
);
672 notifier
->active
= false;
673 /* We leave the notifier struct on the list to avoid reallocating it later.
674 * Generally the number of IOMMUs a CPU deals with will be small.
675 * In any case we can't unregister the iommu notifier from a notify
680 static void tcg_register_iommu_notifier(CPUState
*cpu
,
681 IOMMUMemoryRegion
*iommu_mr
,
684 /* Make sure this CPU has an IOMMU notifier registered for this
685 * IOMMU/IOMMU index combination, so that we can flush its TLB
686 * when the IOMMU tells us the mappings we've cached have changed.
688 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
689 TCGIOMMUNotifier
*notifier
;
692 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
693 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
694 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
698 if (i
== cpu
->iommu_notifiers
->len
) {
699 /* Not found, add a new entry at the end of the array */
700 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
701 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
704 notifier
->iommu_idx
= iommu_idx
;
706 /* Rather than trying to register interest in the specific part
707 * of the iommu's address space that we've accessed and then
708 * expand it later as subsequent accesses touch more of it, we
709 * just register interest in the whole thing, on the assumption
710 * that iommu reconfiguration will be rare.
712 iommu_notifier_init(¬ifier
->n
,
713 tcg_iommu_unmap_notify
,
714 IOMMU_NOTIFIER_UNMAP
,
718 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
721 if (!notifier
->active
) {
722 notifier
->active
= true;
726 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
728 /* Destroy the CPU's notifier list */
730 TCGIOMMUNotifier
*notifier
;
732 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
733 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
734 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
736 g_array_free(cpu
->iommu_notifiers
, true);
739 /* Called from RCU critical section */
740 MemoryRegionSection
*
741 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
742 hwaddr
*xlat
, hwaddr
*plen
,
743 MemTxAttrs attrs
, int *prot
)
745 MemoryRegionSection
*section
;
746 IOMMUMemoryRegion
*iommu_mr
;
747 IOMMUMemoryRegionClass
*imrc
;
750 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
753 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
755 iommu_mr
= memory_region_get_iommu(section
->mr
);
760 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
762 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
763 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
764 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
765 * doesn't short-cut its translation table walk.
767 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
768 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
769 | (addr
& iotlb
.addr_mask
));
770 /* Update the caller's prot bits to remove permissions the IOMMU
771 * is giving us a failure response for. If we get down to no
772 * permissions left at all we can give up now.
774 if (!(iotlb
.perm
& IOMMU_RO
)) {
775 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
777 if (!(iotlb
.perm
& IOMMU_WO
)) {
778 *prot
&= ~PAGE_WRITE
;
785 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
788 assert(!memory_region_is_iommu(section
->mr
));
793 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
797 #if !defined(CONFIG_USER_ONLY)
799 static int cpu_common_post_load(void *opaque
, int version_id
)
801 CPUState
*cpu
= opaque
;
803 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
804 version_id is increased. */
805 cpu
->interrupt_request
&= ~0x01;
808 /* loadvm has just updated the content of RAM, bypassing the
809 * usual mechanisms that ensure we flush TBs for writes to
810 * memory we've translated code from. So we must flush all TBs,
811 * which will now be stale.
818 static int cpu_common_pre_load(void *opaque
)
820 CPUState
*cpu
= opaque
;
822 cpu
->exception_index
= -1;
827 static bool cpu_common_exception_index_needed(void *opaque
)
829 CPUState
*cpu
= opaque
;
831 return tcg_enabled() && cpu
->exception_index
!= -1;
834 static const VMStateDescription vmstate_cpu_common_exception_index
= {
835 .name
= "cpu_common/exception_index",
837 .minimum_version_id
= 1,
838 .needed
= cpu_common_exception_index_needed
,
839 .fields
= (VMStateField
[]) {
840 VMSTATE_INT32(exception_index
, CPUState
),
841 VMSTATE_END_OF_LIST()
845 static bool cpu_common_crash_occurred_needed(void *opaque
)
847 CPUState
*cpu
= opaque
;
849 return cpu
->crash_occurred
;
852 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
853 .name
= "cpu_common/crash_occurred",
855 .minimum_version_id
= 1,
856 .needed
= cpu_common_crash_occurred_needed
,
857 .fields
= (VMStateField
[]) {
858 VMSTATE_BOOL(crash_occurred
, CPUState
),
859 VMSTATE_END_OF_LIST()
863 const VMStateDescription vmstate_cpu_common
= {
864 .name
= "cpu_common",
866 .minimum_version_id
= 1,
867 .pre_load
= cpu_common_pre_load
,
868 .post_load
= cpu_common_post_load
,
869 .fields
= (VMStateField
[]) {
870 VMSTATE_UINT32(halted
, CPUState
),
871 VMSTATE_UINT32(interrupt_request
, CPUState
),
872 VMSTATE_END_OF_LIST()
874 .subsections
= (const VMStateDescription
*[]) {
875 &vmstate_cpu_common_exception_index
,
876 &vmstate_cpu_common_crash_occurred
,
883 CPUState
*qemu_get_cpu(int index
)
888 if (cpu
->cpu_index
== index
) {
896 #if !defined(CONFIG_USER_ONLY)
897 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
898 const char *prefix
, MemoryRegion
*mr
)
900 CPUAddressSpace
*newas
;
901 AddressSpace
*as
= g_new0(AddressSpace
, 1);
905 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
906 address_space_init(as
, mr
, as_name
);
909 /* Target code should have set num_ases before calling us */
910 assert(asidx
< cpu
->num_ases
);
913 /* address space 0 gets the convenience alias */
917 /* KVM cannot currently support multiple address spaces. */
918 assert(asidx
== 0 || !kvm_enabled());
920 if (!cpu
->cpu_ases
) {
921 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
924 newas
= &cpu
->cpu_ases
[asidx
];
928 newas
->tcg_as_listener
.commit
= tcg_commit
;
929 memory_listener_register(&newas
->tcg_as_listener
, as
);
933 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
935 /* Return the AddressSpace corresponding to the specified index */
936 return cpu
->cpu_ases
[asidx
].as
;
940 void cpu_exec_unrealizefn(CPUState
*cpu
)
942 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
944 cpu_list_remove(cpu
);
946 if (cc
->vmsd
!= NULL
) {
947 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
949 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
950 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
952 #ifndef CONFIG_USER_ONLY
953 tcg_iommu_free_notifier_list(cpu
);
957 Property cpu_common_props
[] = {
958 #ifndef CONFIG_USER_ONLY
959 /* Create a memory property for softmmu CPU object,
960 * so users can wire up its memory. (This can't go in qom/cpu.c
961 * because that file is compiled only once for both user-mode
962 * and system builds.) The default if no link is set up is to use
963 * the system address space.
965 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
968 DEFINE_PROP_END_OF_LIST(),
971 void cpu_exec_initfn(CPUState
*cpu
)
973 #ifdef TARGET_WORDS_BIGENDIAN
974 cpu
->bigendian
= true;
976 cpu
->bigendian
= false;
981 #ifndef CONFIG_USER_ONLY
982 cpu
->thread_id
= qemu_get_thread_id();
983 cpu
->memory
= system_memory
;
984 object_ref(OBJECT(cpu
->memory
));
988 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
990 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
991 static bool tcg_target_initialized
;
995 if (tcg_enabled() && !tcg_target_initialized
) {
996 tcg_target_initialized
= true;
997 cc
->tcg_initialize();
1000 #ifndef CONFIG_USER_ONLY
1001 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
1002 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
1004 if (cc
->vmsd
!= NULL
) {
1005 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
1008 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
));
1012 const char *parse_cpu_model(const char *cpu_model
)
1016 gchar
**model_pieces
;
1017 const char *cpu_type
;
1019 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1021 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1023 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1024 g_strfreev(model_pieces
);
1028 cpu_type
= object_class_get_name(oc
);
1030 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1031 g_strfreev(model_pieces
);
1035 #if defined(CONFIG_USER_ONLY)
1036 void tb_invalidate_phys_addr(target_ulong addr
)
1039 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1043 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1045 tb_invalidate_phys_addr(pc
);
1048 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1050 ram_addr_t ram_addr
;
1054 if (!tcg_enabled()) {
1059 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1060 if (!(memory_region_is_ram(mr
)
1061 || memory_region_is_romd(mr
))) {
1065 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1066 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1070 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1073 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1074 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1076 /* Locks grabbed by tb_invalidate_phys_addr */
1077 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1078 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1083 #if defined(CONFIG_USER_ONLY)
1084 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1089 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1095 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1099 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1100 int flags
, CPUWatchpoint
**watchpoint
)
1105 /* Add a watchpoint. */
1106 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1107 int flags
, CPUWatchpoint
**watchpoint
)
1111 /* forbid ranges which are empty or run off the end of the address space */
1112 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1113 error_report("tried to set invalid watchpoint at %"
1114 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1117 wp
= g_malloc(sizeof(*wp
));
1123 /* keep all GDB-injected watchpoints in front */
1124 if (flags
& BP_GDB
) {
1125 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1127 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1130 tlb_flush_page(cpu
, addr
);
1137 /* Remove a specific watchpoint. */
1138 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1143 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1144 if (addr
== wp
->vaddr
&& len
== wp
->len
1145 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1146 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1153 /* Remove a specific watchpoint by reference. */
1154 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1156 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1158 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1163 /* Remove all matching watchpoints. */
1164 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1166 CPUWatchpoint
*wp
, *next
;
1168 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1169 if (wp
->flags
& mask
) {
1170 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1175 /* Return true if this watchpoint address matches the specified
1176 * access (ie the address range covered by the watchpoint overlaps
1177 * partially or completely with the address range covered by the
1180 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1184 /* We know the lengths are non-zero, but a little caution is
1185 * required to avoid errors in the case where the range ends
1186 * exactly at the top of the address space and so addr + len
1187 * wraps round to zero.
1189 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1190 vaddr addrend
= addr
+ len
- 1;
1192 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1197 /* Add a breakpoint. */
1198 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1199 CPUBreakpoint
**breakpoint
)
1203 bp
= g_malloc(sizeof(*bp
));
1208 /* keep all GDB-injected breakpoints in front */
1209 if (flags
& BP_GDB
) {
1210 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1212 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1215 breakpoint_invalidate(cpu
, pc
);
1223 /* Remove a specific breakpoint. */
1224 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1228 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1229 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1230 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1237 /* Remove a specific breakpoint by reference. */
1238 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1240 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1242 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1247 /* Remove all matching breakpoints. */
1248 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1250 CPUBreakpoint
*bp
, *next
;
1252 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1253 if (bp
->flags
& mask
) {
1254 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1259 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1260 CPU loop after each instruction */
1261 void cpu_single_step(CPUState
*cpu
, int enabled
)
1263 if (cpu
->singlestep_enabled
!= enabled
) {
1264 cpu
->singlestep_enabled
= enabled
;
1265 if (kvm_enabled()) {
1266 kvm_update_guest_debug(cpu
, 0);
1268 /* must flush all the translated code to avoid inconsistencies */
1269 /* XXX: only flush what is necessary */
1275 void QEMU_NORETURN
cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1282 fprintf(stderr
, "qemu: fatal: ");
1283 vfprintf(stderr
, fmt
, ap
);
1284 fprintf(stderr
, "\n");
1285 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1286 if (qemu_log_separate()) {
1288 qemu_log("qemu: fatal: ");
1289 qemu_log_vprintf(fmt
, ap2
);
1291 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1299 #if defined(CONFIG_USER_ONLY)
1301 struct sigaction act
;
1302 sigfillset(&act
.sa_mask
);
1303 act
.sa_handler
= SIG_DFL
;
1305 sigaction(SIGABRT
, &act
, NULL
);
1311 #if !defined(CONFIG_USER_ONLY)
1312 /* Called from RCU critical section */
1313 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1317 block
= atomic_rcu_read(&ram_list
.mru_block
);
1318 if (block
&& addr
- block
->offset
< block
->max_length
) {
1321 RAMBLOCK_FOREACH(block
) {
1322 if (addr
- block
->offset
< block
->max_length
) {
1327 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1331 /* It is safe to write mru_block outside the iothread lock. This
1336 * xxx removed from list
1340 * call_rcu(reclaim_ramblock, xxx);
1343 * atomic_rcu_set is not needed here. The block was already published
1344 * when it was placed into the list. Here we're just making an extra
1345 * copy of the pointer.
1347 ram_list
.mru_block
= block
;
1351 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1358 assert(tcg_enabled());
1359 end
= TARGET_PAGE_ALIGN(start
+ length
);
1360 start
&= TARGET_PAGE_MASK
;
1363 block
= qemu_get_ram_block(start
);
1364 assert(block
== qemu_get_ram_block(end
- 1));
1365 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1367 tlb_reset_dirty(cpu
, start1
, length
);
1372 /* Note: start and end must be within the same ram block. */
1373 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1377 DirtyMemoryBlocks
*blocks
;
1378 unsigned long end
, page
;
1385 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1386 page
= start
>> TARGET_PAGE_BITS
;
1390 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1392 while (page
< end
) {
1393 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1394 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1395 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1397 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1404 if (dirty
&& tcg_enabled()) {
1405 tlb_reset_dirty_range_all(start
, length
);
1411 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1412 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1414 DirtyMemoryBlocks
*blocks
;
1415 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1416 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1417 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1418 DirtyBitmapSnapshot
*snap
;
1419 unsigned long page
, end
, dest
;
1421 snap
= g_malloc0(sizeof(*snap
) +
1422 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1423 snap
->start
= first
;
1426 page
= first
>> TARGET_PAGE_BITS
;
1427 end
= last
>> TARGET_PAGE_BITS
;
1432 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1434 while (page
< end
) {
1435 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1436 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1437 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1439 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1440 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1441 offset
>>= BITS_PER_LEVEL
;
1443 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1444 blocks
->blocks
[idx
] + offset
,
1447 dest
+= num
>> BITS_PER_LEVEL
;
1452 if (tcg_enabled()) {
1453 tlb_reset_dirty_range_all(start
, length
);
1459 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1463 unsigned long page
, end
;
1465 assert(start
>= snap
->start
);
1466 assert(start
+ length
<= snap
->end
);
1468 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1469 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1471 while (page
< end
) {
1472 if (test_bit(page
, snap
->dirty
)) {
1480 /* Called from RCU critical section */
1481 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1482 MemoryRegionSection
*section
,
1484 hwaddr paddr
, hwaddr xlat
,
1486 target_ulong
*address
)
1491 if (memory_region_is_ram(section
->mr
)) {
1493 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1494 if (!section
->readonly
) {
1495 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1497 iotlb
|= PHYS_SECTION_ROM
;
1500 AddressSpaceDispatch
*d
;
1502 d
= flatview_to_dispatch(section
->fv
);
1503 iotlb
= section
- d
->map
.sections
;
1507 /* Make accesses to pages with watchpoints go via the
1508 watchpoint trap routines. */
1509 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1510 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1511 /* Avoid trapping reads of pages with a write breakpoint. */
1512 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1513 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1514 *address
|= TLB_MMIO
;
1522 #endif /* defined(CONFIG_USER_ONLY) */
1524 #if !defined(CONFIG_USER_ONLY)
1526 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1528 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1530 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1531 qemu_anon_ram_alloc
;
1534 * Set a custom physical guest memory alloator.
1535 * Accelerators with unusual needs may need this. Hopefully, we can
1536 * get rid of it eventually.
1538 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1540 phys_mem_alloc
= alloc
;
1543 static uint16_t phys_section_add(PhysPageMap
*map
,
1544 MemoryRegionSection
*section
)
1546 /* The physical section number is ORed with a page-aligned
1547 * pointer to produce the iotlb entries. Thus it should
1548 * never overflow into the page-aligned value.
1550 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1552 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1553 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1554 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1555 map
->sections_nb_alloc
);
1557 map
->sections
[map
->sections_nb
] = *section
;
1558 memory_region_ref(section
->mr
);
1559 return map
->sections_nb
++;
1562 static void phys_section_destroy(MemoryRegion
*mr
)
1564 bool have_sub_page
= mr
->subpage
;
1566 memory_region_unref(mr
);
1568 if (have_sub_page
) {
1569 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1570 object_unref(OBJECT(&subpage
->iomem
));
1575 static void phys_sections_free(PhysPageMap
*map
)
1577 while (map
->sections_nb
> 0) {
1578 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1579 phys_section_destroy(section
->mr
);
1581 g_free(map
->sections
);
1585 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1587 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1589 hwaddr base
= section
->offset_within_address_space
1591 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1592 MemoryRegionSection subsection
= {
1593 .offset_within_address_space
= base
,
1594 .size
= int128_make64(TARGET_PAGE_SIZE
),
1598 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1600 if (!(existing
->mr
->subpage
)) {
1601 subpage
= subpage_init(fv
, base
);
1603 subsection
.mr
= &subpage
->iomem
;
1604 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1605 phys_section_add(&d
->map
, &subsection
));
1607 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1609 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1610 end
= start
+ int128_get64(section
->size
) - 1;
1611 subpage_register(subpage
, start
, end
,
1612 phys_section_add(&d
->map
, section
));
1616 static void register_multipage(FlatView
*fv
,
1617 MemoryRegionSection
*section
)
1619 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1620 hwaddr start_addr
= section
->offset_within_address_space
;
1621 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1622 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1626 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1629 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1631 MemoryRegionSection now
= *section
, remain
= *section
;
1632 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1634 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1635 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1636 - now
.offset_within_address_space
;
1638 now
.size
= int128_min(int128_make64(left
), now
.size
);
1639 register_subpage(fv
, &now
);
1641 now
.size
= int128_zero();
1643 while (int128_ne(remain
.size
, now
.size
)) {
1644 remain
.size
= int128_sub(remain
.size
, now
.size
);
1645 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1646 remain
.offset_within_region
+= int128_get64(now
.size
);
1648 if (int128_lt(remain
.size
, page_size
)) {
1649 register_subpage(fv
, &now
);
1650 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1651 now
.size
= page_size
;
1652 register_subpage(fv
, &now
);
1654 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1655 register_multipage(fv
, &now
);
1660 void qemu_flush_coalesced_mmio_buffer(void)
1663 kvm_flush_coalesced_mmio_buffer();
1666 void qemu_mutex_lock_ramlist(void)
1668 qemu_mutex_lock(&ram_list
.mutex
);
1671 void qemu_mutex_unlock_ramlist(void)
1673 qemu_mutex_unlock(&ram_list
.mutex
);
1676 void ram_block_dump(Monitor
*mon
)
1682 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1683 "Block Name", "PSize", "Offset", "Used", "Total");
1684 RAMBLOCK_FOREACH(block
) {
1685 psize
= size_to_str(block
->page_size
);
1686 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1687 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1688 (uint64_t)block
->offset
,
1689 (uint64_t)block
->used_length
,
1690 (uint64_t)block
->max_length
);
1698 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1699 * may or may not name the same files / on the same filesystem now as
1700 * when we actually open and map them. Iterate over the file
1701 * descriptors instead, and use qemu_fd_getpagesize().
1703 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1705 long *hpsize_min
= opaque
;
1707 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1708 long hpsize
= host_memory_backend_pagesize(MEMORY_BACKEND(obj
));
1710 if (hpsize
< *hpsize_min
) {
1711 *hpsize_min
= hpsize
;
1718 long qemu_getrampagesize(void)
1720 long hpsize
= LONG_MAX
;
1721 long mainrampagesize
;
1722 Object
*memdev_root
;
1724 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1726 /* it's possible we have memory-backend objects with
1727 * hugepage-backed RAM. these may get mapped into system
1728 * address space via -numa parameters or memory hotplug
1729 * hooks. we want to take these into account, but we
1730 * also want to make sure these supported hugepage
1731 * sizes are applicable across the entire range of memory
1732 * we may boot from, so we take the min across all
1733 * backends, and assume normal pages in cases where a
1734 * backend isn't backed by hugepages.
1736 memdev_root
= object_resolve_path("/objects", NULL
);
1738 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1740 if (hpsize
== LONG_MAX
) {
1741 /* No additional memory regions found ==> Report main RAM page size */
1742 return mainrampagesize
;
1745 /* If NUMA is disabled or the NUMA nodes are not backed with a
1746 * memory-backend, then there is at least one node using "normal" RAM,
1747 * so if its page size is smaller we have got to report that size instead.
1749 if (hpsize
> mainrampagesize
&&
1750 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1753 error_report("Huge page support disabled (n/a for main memory).");
1756 return mainrampagesize
;
1762 long qemu_getrampagesize(void)
1764 return getpagesize();
1769 static int64_t get_file_size(int fd
)
1771 int64_t size
= lseek(fd
, 0, SEEK_END
);
1778 static int file_ram_open(const char *path
,
1779 const char *region_name
,
1784 char *sanitized_name
;
1790 fd
= open(path
, O_RDWR
);
1792 /* @path names an existing file, use it */
1795 if (errno
== ENOENT
) {
1796 /* @path names a file that doesn't exist, create it */
1797 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1802 } else if (errno
== EISDIR
) {
1803 /* @path names a directory, create a file there */
1804 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1805 sanitized_name
= g_strdup(region_name
);
1806 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1812 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1814 g_free(sanitized_name
);
1816 fd
= mkstemp(filename
);
1824 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1825 error_setg_errno(errp
, errno
,
1826 "can't open backing store %s for guest RAM",
1831 * Try again on EINTR and EEXIST. The latter happens when
1832 * something else creates the file between our two open().
1839 static void *file_ram_alloc(RAMBlock
*block
,
1847 block
->page_size
= qemu_fd_getpagesize(fd
);
1848 if (block
->mr
->align
% block
->page_size
) {
1849 error_setg(errp
, "alignment 0x%" PRIx64
1850 " must be multiples of page size 0x%zx",
1851 block
->mr
->align
, block
->page_size
);
1853 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1854 error_setg(errp
, "alignment 0x%" PRIx64
1855 " must be a power of two", block
->mr
->align
);
1858 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1859 #if defined(__s390x__)
1860 if (kvm_enabled()) {
1861 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1865 if (memory
< block
->page_size
) {
1866 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1867 "or larger than page size 0x%zx",
1868 memory
, block
->page_size
);
1872 memory
= ROUND_UP(memory
, block
->page_size
);
1875 * ftruncate is not supported by hugetlbfs in older
1876 * hosts, so don't bother bailing out on errors.
1877 * If anything goes wrong with it under other filesystems,
1880 * Do not truncate the non-empty backend file to avoid corrupting
1881 * the existing data in the file. Disabling shrinking is not
1882 * enough. For example, the current vNVDIMM implementation stores
1883 * the guest NVDIMM labels at the end of the backend file. If the
1884 * backend file is later extended, QEMU will not be able to find
1885 * those labels. Therefore, extending the non-empty backend file
1886 * is disabled as well.
1888 if (truncate
&& ftruncate(fd
, memory
)) {
1889 perror("ftruncate");
1892 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1893 block
->flags
& RAM_SHARED
);
1894 if (area
== MAP_FAILED
) {
1895 error_setg_errno(errp
, errno
,
1896 "unable to map backing store for guest RAM");
1901 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1902 if (errp
&& *errp
) {
1903 qemu_ram_munmap(area
, memory
);
1913 /* Allocate space within the ram_addr_t space that governs the
1915 * Called with the ramlist lock held.
1917 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1919 RAMBlock
*block
, *next_block
;
1920 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1922 assert(size
!= 0); /* it would hand out same offset multiple times */
1924 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1928 RAMBLOCK_FOREACH(block
) {
1929 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1931 /* Align blocks to start on a 'long' in the bitmap
1932 * which makes the bitmap sync'ing take the fast path.
1934 candidate
= block
->offset
+ block
->max_length
;
1935 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1937 /* Search for the closest following block
1940 RAMBLOCK_FOREACH(next_block
) {
1941 if (next_block
->offset
>= candidate
) {
1942 next
= MIN(next
, next_block
->offset
);
1946 /* If it fits remember our place and remember the size
1947 * of gap, but keep going so that we might find a smaller
1948 * gap to fill so avoiding fragmentation.
1950 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1952 mingap
= next
- candidate
;
1955 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1958 if (offset
== RAM_ADDR_MAX
) {
1959 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1964 trace_find_ram_offset(size
, offset
);
1969 static unsigned long last_ram_page(void)
1972 ram_addr_t last
= 0;
1975 RAMBLOCK_FOREACH(block
) {
1976 last
= MAX(last
, block
->offset
+ block
->max_length
);
1979 return last
>> TARGET_PAGE_BITS
;
1982 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1986 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1987 if (!machine_dump_guest_core(current_machine
)) {
1988 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1990 perror("qemu_madvise");
1991 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1992 "but dump_guest_core=off specified\n");
1997 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2002 bool qemu_ram_is_shared(RAMBlock
*rb
)
2004 return rb
->flags
& RAM_SHARED
;
2007 /* Note: Only set at the start of postcopy */
2008 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2010 return rb
->flags
& RAM_UF_ZEROPAGE
;
2013 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2015 rb
->flags
|= RAM_UF_ZEROPAGE
;
2018 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2020 return rb
->flags
& RAM_MIGRATABLE
;
2023 void qemu_ram_set_migratable(RAMBlock
*rb
)
2025 rb
->flags
|= RAM_MIGRATABLE
;
2028 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2030 rb
->flags
&= ~RAM_MIGRATABLE
;
2033 /* Called with iothread lock held. */
2034 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2039 assert(!new_block
->idstr
[0]);
2042 char *id
= qdev_get_dev_path(dev
);
2044 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2048 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2051 RAMBLOCK_FOREACH(block
) {
2052 if (block
!= new_block
&&
2053 !strcmp(block
->idstr
, new_block
->idstr
)) {
2054 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2062 /* Called with iothread lock held. */
2063 void qemu_ram_unset_idstr(RAMBlock
*block
)
2065 /* FIXME: arch_init.c assumes that this is not called throughout
2066 * migration. Ignore the problem since hot-unplug during migration
2067 * does not work anyway.
2070 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2074 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2076 return rb
->page_size
;
2079 /* Returns the largest size of page in use */
2080 size_t qemu_ram_pagesize_largest(void)
2085 RAMBLOCK_FOREACH(block
) {
2086 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2092 static int memory_try_enable_merging(void *addr
, size_t len
)
2094 if (!machine_mem_merge(current_machine
)) {
2095 /* disabled by the user */
2099 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2102 /* Only legal before guest might have detected the memory size: e.g. on
2103 * incoming migration, or right after reset.
2105 * As memory core doesn't know how is memory accessed, it is up to
2106 * resize callback to update device state and/or add assertions to detect
2107 * misuse, if necessary.
2109 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2113 newsize
= HOST_PAGE_ALIGN(newsize
);
2115 if (block
->used_length
== newsize
) {
2119 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2120 error_setg_errno(errp
, EINVAL
,
2121 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2122 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2123 newsize
, block
->used_length
);
2127 if (block
->max_length
< newsize
) {
2128 error_setg_errno(errp
, EINVAL
,
2129 "Length too large: %s: 0x" RAM_ADDR_FMT
2130 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2131 newsize
, block
->max_length
);
2135 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2136 block
->used_length
= newsize
;
2137 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2139 memory_region_set_size(block
->mr
, newsize
);
2140 if (block
->resized
) {
2141 block
->resized(block
->idstr
, newsize
, block
->host
);
2146 /* Called with ram_list.mutex held */
2147 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2148 ram_addr_t new_ram_size
)
2150 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2151 DIRTY_MEMORY_BLOCK_SIZE
);
2152 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2153 DIRTY_MEMORY_BLOCK_SIZE
);
2156 /* Only need to extend if block count increased */
2157 if (new_num_blocks
<= old_num_blocks
) {
2161 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2162 DirtyMemoryBlocks
*old_blocks
;
2163 DirtyMemoryBlocks
*new_blocks
;
2166 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2167 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2168 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2170 if (old_num_blocks
) {
2171 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2172 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2175 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2176 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2179 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2182 g_free_rcu(old_blocks
, rcu
);
2187 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2190 RAMBlock
*last_block
= NULL
;
2191 ram_addr_t old_ram_size
, new_ram_size
;
2194 old_ram_size
= last_ram_page();
2196 qemu_mutex_lock_ramlist();
2197 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2199 if (!new_block
->host
) {
2200 if (xen_enabled()) {
2201 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2202 new_block
->mr
, &err
);
2204 error_propagate(errp
, err
);
2205 qemu_mutex_unlock_ramlist();
2209 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2210 &new_block
->mr
->align
, shared
);
2211 if (!new_block
->host
) {
2212 error_setg_errno(errp
, errno
,
2213 "cannot set up guest memory '%s'",
2214 memory_region_name(new_block
->mr
));
2215 qemu_mutex_unlock_ramlist();
2218 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2222 new_ram_size
= MAX(old_ram_size
,
2223 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2224 if (new_ram_size
> old_ram_size
) {
2225 dirty_memory_extend(old_ram_size
, new_ram_size
);
2227 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2228 * QLIST (which has an RCU-friendly variant) does not have insertion at
2229 * tail, so save the last element in last_block.
2231 RAMBLOCK_FOREACH(block
) {
2233 if (block
->max_length
< new_block
->max_length
) {
2238 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2239 } else if (last_block
) {
2240 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2241 } else { /* list is empty */
2242 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2244 ram_list
.mru_block
= NULL
;
2246 /* Write list before version */
2249 qemu_mutex_unlock_ramlist();
2251 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2252 new_block
->used_length
,
2255 if (new_block
->host
) {
2256 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2257 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2258 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2259 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2260 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2265 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2269 RAMBlock
*new_block
;
2270 Error
*local_err
= NULL
;
2273 if (xen_enabled()) {
2274 error_setg(errp
, "-mem-path not supported with Xen");
2278 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2280 "host lacks kvm mmu notifiers, -mem-path unsupported");
2284 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2286 * file_ram_alloc() needs to allocate just like
2287 * phys_mem_alloc, but we haven't bothered to provide
2291 "-mem-path not supported with this accelerator");
2295 size
= HOST_PAGE_ALIGN(size
);
2296 file_size
= get_file_size(fd
);
2297 if (file_size
> 0 && file_size
< size
) {
2298 error_setg(errp
, "backing store %s size 0x%" PRIx64
2299 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2300 mem_path
, file_size
, size
);
2304 new_block
= g_malloc0(sizeof(*new_block
));
2306 new_block
->used_length
= size
;
2307 new_block
->max_length
= size
;
2308 new_block
->flags
= share
? RAM_SHARED
: 0;
2309 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2310 if (!new_block
->host
) {
2315 ram_block_add(new_block
, &local_err
, share
);
2318 error_propagate(errp
, local_err
);
2326 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2327 bool share
, const char *mem_path
,
2334 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2339 block
= qemu_ram_alloc_from_fd(size
, mr
, share
, fd
, errp
);
2353 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2354 void (*resized
)(const char*,
2357 void *host
, bool resizeable
, bool share
,
2358 MemoryRegion
*mr
, Error
**errp
)
2360 RAMBlock
*new_block
;
2361 Error
*local_err
= NULL
;
2363 size
= HOST_PAGE_ALIGN(size
);
2364 max_size
= HOST_PAGE_ALIGN(max_size
);
2365 new_block
= g_malloc0(sizeof(*new_block
));
2367 new_block
->resized
= resized
;
2368 new_block
->used_length
= size
;
2369 new_block
->max_length
= max_size
;
2370 assert(max_size
>= size
);
2372 new_block
->page_size
= getpagesize();
2373 new_block
->host
= host
;
2375 new_block
->flags
|= RAM_PREALLOC
;
2378 new_block
->flags
|= RAM_RESIZEABLE
;
2380 ram_block_add(new_block
, &local_err
, share
);
2383 error_propagate(errp
, local_err
);
2389 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2390 MemoryRegion
*mr
, Error
**errp
)
2392 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2396 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2397 MemoryRegion
*mr
, Error
**errp
)
2399 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2403 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2404 void (*resized
)(const char*,
2407 MemoryRegion
*mr
, Error
**errp
)
2409 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2413 static void reclaim_ramblock(RAMBlock
*block
)
2415 if (block
->flags
& RAM_PREALLOC
) {
2417 } else if (xen_enabled()) {
2418 xen_invalidate_map_cache_entry(block
->host
);
2420 } else if (block
->fd
>= 0) {
2421 qemu_ram_munmap(block
->host
, block
->max_length
);
2425 qemu_anon_ram_free(block
->host
, block
->max_length
);
2430 void qemu_ram_free(RAMBlock
*block
)
2437 ram_block_notify_remove(block
->host
, block
->max_length
);
2440 qemu_mutex_lock_ramlist();
2441 QLIST_REMOVE_RCU(block
, next
);
2442 ram_list
.mru_block
= NULL
;
2443 /* Write list before version */
2446 call_rcu(block
, reclaim_ramblock
, rcu
);
2447 qemu_mutex_unlock_ramlist();
2451 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2458 RAMBLOCK_FOREACH(block
) {
2459 offset
= addr
- block
->offset
;
2460 if (offset
< block
->max_length
) {
2461 vaddr
= ramblock_ptr(block
, offset
);
2462 if (block
->flags
& RAM_PREALLOC
) {
2464 } else if (xen_enabled()) {
2468 if (block
->fd
>= 0) {
2469 flags
|= (block
->flags
& RAM_SHARED
?
2470 MAP_SHARED
: MAP_PRIVATE
);
2471 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2472 flags
, block
->fd
, offset
);
2475 * Remap needs to match alloc. Accelerators that
2476 * set phys_mem_alloc never remap. If they did,
2477 * we'd need a remap hook here.
2479 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2481 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2482 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2485 if (area
!= vaddr
) {
2486 error_report("Could not remap addr: "
2487 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2491 memory_try_enable_merging(vaddr
, length
);
2492 qemu_ram_setup_dump(vaddr
, length
);
2497 #endif /* !_WIN32 */
2499 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2500 * This should not be used for general purpose DMA. Use address_space_map
2501 * or address_space_rw instead. For local memory (e.g. video ram) that the
2502 * device owns, use memory_region_get_ram_ptr.
2504 * Called within RCU critical section.
2506 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2508 RAMBlock
*block
= ram_block
;
2510 if (block
== NULL
) {
2511 block
= qemu_get_ram_block(addr
);
2512 addr
-= block
->offset
;
2515 if (xen_enabled() && block
->host
== NULL
) {
2516 /* We need to check if the requested address is in the RAM
2517 * because we don't want to map the entire memory in QEMU.
2518 * In that case just map until the end of the page.
2520 if (block
->offset
== 0) {
2521 return xen_map_cache(addr
, 0, 0, false);
2524 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2526 return ramblock_ptr(block
, addr
);
2529 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2530 * but takes a size argument.
2532 * Called within RCU critical section.
2534 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2535 hwaddr
*size
, bool lock
)
2537 RAMBlock
*block
= ram_block
;
2542 if (block
== NULL
) {
2543 block
= qemu_get_ram_block(addr
);
2544 addr
-= block
->offset
;
2546 *size
= MIN(*size
, block
->max_length
- addr
);
2548 if (xen_enabled() && block
->host
== NULL
) {
2549 /* We need to check if the requested address is in the RAM
2550 * because we don't want to map the entire memory in QEMU.
2551 * In that case just map the requested area.
2553 if (block
->offset
== 0) {
2554 return xen_map_cache(addr
, *size
, lock
, lock
);
2557 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2560 return ramblock_ptr(block
, addr
);
2563 /* Return the offset of a hostpointer within a ramblock */
2564 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2566 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2567 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2568 assert(res
< rb
->max_length
);
2574 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2577 * ptr: Host pointer to look up
2578 * round_offset: If true round the result offset down to a page boundary
2579 * *ram_addr: set to result ram_addr
2580 * *offset: set to result offset within the RAMBlock
2582 * Returns: RAMBlock (or NULL if not found)
2584 * By the time this function returns, the returned pointer is not protected
2585 * by RCU anymore. If the caller is not within an RCU critical section and
2586 * does not hold the iothread lock, it must have other means of protecting the
2587 * pointer, such as a reference to the region that includes the incoming
2590 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2594 uint8_t *host
= ptr
;
2596 if (xen_enabled()) {
2597 ram_addr_t ram_addr
;
2599 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2600 block
= qemu_get_ram_block(ram_addr
);
2602 *offset
= ram_addr
- block
->offset
;
2609 block
= atomic_rcu_read(&ram_list
.mru_block
);
2610 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2614 RAMBLOCK_FOREACH(block
) {
2615 /* This case append when the block is not mapped. */
2616 if (block
->host
== NULL
) {
2619 if (host
- block
->host
< block
->max_length
) {
2628 *offset
= (host
- block
->host
);
2630 *offset
&= TARGET_PAGE_MASK
;
2637 * Finds the named RAMBlock
2639 * name: The name of RAMBlock to find
2641 * Returns: RAMBlock (or NULL if not found)
2643 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2647 RAMBLOCK_FOREACH(block
) {
2648 if (!strcmp(name
, block
->idstr
)) {
2656 /* Some of the softmmu routines need to translate from a host pointer
2657 (typically a TLB entry) back to a ram offset. */
2658 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2663 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2665 return RAM_ADDR_INVALID
;
2668 return block
->offset
+ offset
;
2671 /* Called within RCU critical section. */
2672 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2675 ram_addr_t ram_addr
,
2679 ndi
->ram_addr
= ram_addr
;
2680 ndi
->mem_vaddr
= mem_vaddr
;
2684 assert(tcg_enabled());
2685 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2686 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2687 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2691 /* Called within RCU critical section. */
2692 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2695 assert(tcg_enabled());
2696 page_collection_unlock(ndi
->pages
);
2700 /* Set both VGA and migration bits for simplicity and to remove
2701 * the notdirty callback faster.
2703 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2704 DIRTY_CLIENTS_NOCODE
);
2705 /* we remove the notdirty callback only if the code has been
2707 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2708 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2712 /* Called within RCU critical section. */
2713 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2714 uint64_t val
, unsigned size
)
2718 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2721 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2722 memory_notdirty_write_complete(&ndi
);
2725 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2726 unsigned size
, bool is_write
,
2732 static const MemoryRegionOps notdirty_mem_ops
= {
2733 .write
= notdirty_mem_write
,
2734 .valid
.accepts
= notdirty_mem_accepts
,
2735 .endianness
= DEVICE_NATIVE_ENDIAN
,
2737 .min_access_size
= 1,
2738 .max_access_size
= 8,
2742 .min_access_size
= 1,
2743 .max_access_size
= 8,
2748 /* Generate a debug exception if a watchpoint has been hit. */
2749 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2751 CPUState
*cpu
= current_cpu
;
2752 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2756 assert(tcg_enabled());
2757 if (cpu
->watchpoint_hit
) {
2758 /* We re-entered the check after replacing the TB. Now raise
2759 * the debug interrupt so that is will trigger after the
2760 * current instruction. */
2761 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2764 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2765 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2766 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2767 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2768 && (wp
->flags
& flags
)) {
2769 if (flags
== BP_MEM_READ
) {
2770 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2772 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2774 wp
->hitaddr
= vaddr
;
2775 wp
->hitattrs
= attrs
;
2776 if (!cpu
->watchpoint_hit
) {
2777 if (wp
->flags
& BP_CPU
&&
2778 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2779 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2782 cpu
->watchpoint_hit
= wp
;
2785 tb_check_watchpoint(cpu
);
2786 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2787 cpu
->exception_index
= EXCP_DEBUG
;
2791 /* Force execution of one insn next time. */
2792 cpu
->cflags_next_tb
= 1 | curr_cflags();
2794 cpu_loop_exit_noexc(cpu
);
2798 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2803 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2804 so these check for a hit then pass through to the normal out-of-line
2806 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2807 unsigned size
, MemTxAttrs attrs
)
2811 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2812 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2814 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2817 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2820 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2823 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2826 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2834 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2835 uint64_t val
, unsigned size
,
2839 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2840 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2842 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2845 address_space_stb(as
, addr
, val
, attrs
, &res
);
2848 address_space_stw(as
, addr
, val
, attrs
, &res
);
2851 address_space_stl(as
, addr
, val
, attrs
, &res
);
2854 address_space_stq(as
, addr
, val
, attrs
, &res
);
2861 static const MemoryRegionOps watch_mem_ops
= {
2862 .read_with_attrs
= watch_mem_read
,
2863 .write_with_attrs
= watch_mem_write
,
2864 .endianness
= DEVICE_NATIVE_ENDIAN
,
2866 .min_access_size
= 1,
2867 .max_access_size
= 8,
2871 .min_access_size
= 1,
2872 .max_access_size
= 8,
2877 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2878 MemTxAttrs attrs
, uint8_t *buf
, int len
);
2879 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2880 const uint8_t *buf
, int len
);
2881 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2882 bool is_write
, MemTxAttrs attrs
);
2884 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2885 unsigned len
, MemTxAttrs attrs
)
2887 subpage_t
*subpage
= opaque
;
2891 #if defined(DEBUG_SUBPAGE)
2892 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2893 subpage
, len
, addr
);
2895 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2899 *data
= ldn_p(buf
, len
);
2903 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2904 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2906 subpage_t
*subpage
= opaque
;
2909 #if defined(DEBUG_SUBPAGE)
2910 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2911 " value %"PRIx64
"\n",
2912 __func__
, subpage
, len
, addr
, value
);
2914 stn_p(buf
, len
, value
);
2915 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2918 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2919 unsigned len
, bool is_write
,
2922 subpage_t
*subpage
= opaque
;
2923 #if defined(DEBUG_SUBPAGE)
2924 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2925 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2928 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2929 len
, is_write
, attrs
);
2932 static const MemoryRegionOps subpage_ops
= {
2933 .read_with_attrs
= subpage_read
,
2934 .write_with_attrs
= subpage_write
,
2935 .impl
.min_access_size
= 1,
2936 .impl
.max_access_size
= 8,
2937 .valid
.min_access_size
= 1,
2938 .valid
.max_access_size
= 8,
2939 .valid
.accepts
= subpage_accepts
,
2940 .endianness
= DEVICE_NATIVE_ENDIAN
,
2943 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2948 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2950 idx
= SUBPAGE_IDX(start
);
2951 eidx
= SUBPAGE_IDX(end
);
2952 #if defined(DEBUG_SUBPAGE)
2953 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2954 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2956 for (; idx
<= eidx
; idx
++) {
2957 mmio
->sub_section
[idx
] = section
;
2963 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2967 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2970 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2971 NULL
, TARGET_PAGE_SIZE
);
2972 mmio
->iomem
.subpage
= true;
2973 #if defined(DEBUG_SUBPAGE)
2974 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2975 mmio
, base
, TARGET_PAGE_SIZE
);
2977 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2982 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2985 MemoryRegionSection section
= {
2988 .offset_within_address_space
= 0,
2989 .offset_within_region
= 0,
2990 .size
= int128_2_64(),
2993 return phys_section_add(map
, §ion
);
2996 static void readonly_mem_write(void *opaque
, hwaddr addr
,
2997 uint64_t val
, unsigned size
)
2999 /* Ignore any write to ROM. */
3002 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3003 unsigned size
, bool is_write
,
3009 /* This will only be used for writes, because reads are special cased
3010 * to directly access the underlying host ram.
3012 static const MemoryRegionOps readonly_mem_ops
= {
3013 .write
= readonly_mem_write
,
3014 .valid
.accepts
= readonly_mem_accepts
,
3015 .endianness
= DEVICE_NATIVE_ENDIAN
,
3017 .min_access_size
= 1,
3018 .max_access_size
= 8,
3022 .min_access_size
= 1,
3023 .max_access_size
= 8,
3028 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3029 hwaddr index
, MemTxAttrs attrs
)
3031 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3032 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3033 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3034 MemoryRegionSection
*sections
= d
->map
.sections
;
3036 return §ions
[index
& ~TARGET_PAGE_MASK
];
3039 static void io_mem_init(void)
3041 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3042 NULL
, NULL
, UINT64_MAX
);
3043 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3046 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3047 * which can be called without the iothread mutex.
3049 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3051 memory_region_clear_global_locking(&io_mem_notdirty
);
3053 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3057 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3059 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3062 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3063 assert(n
== PHYS_SECTION_UNASSIGNED
);
3064 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3065 assert(n
== PHYS_SECTION_NOTDIRTY
);
3066 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3067 assert(n
== PHYS_SECTION_ROM
);
3068 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3069 assert(n
== PHYS_SECTION_WATCH
);
3071 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3076 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3078 phys_sections_free(&d
->map
);
3082 static void tcg_commit(MemoryListener
*listener
)
3084 CPUAddressSpace
*cpuas
;
3085 AddressSpaceDispatch
*d
;
3087 assert(tcg_enabled());
3088 /* since each CPU stores ram addresses in its TLB cache, we must
3089 reset the modified entries */
3090 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3091 cpu_reloading_memory_map();
3092 /* The CPU and TLB are protected by the iothread lock.
3093 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3094 * may have split the RCU critical section.
3096 d
= address_space_to_dispatch(cpuas
->as
);
3097 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3098 tlb_flush(cpuas
->cpu
);
3101 static void memory_map_init(void)
3103 system_memory
= g_malloc(sizeof(*system_memory
));
3105 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3106 address_space_init(&address_space_memory
, system_memory
, "memory");
3108 system_io
= g_malloc(sizeof(*system_io
));
3109 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3111 address_space_init(&address_space_io
, system_io
, "I/O");
3114 MemoryRegion
*get_system_memory(void)
3116 return system_memory
;
3119 MemoryRegion
*get_system_io(void)
3124 #endif /* !defined(CONFIG_USER_ONLY) */
3126 /* physical memory access (slow version, mainly for debug) */
3127 #if defined(CONFIG_USER_ONLY)
3128 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3129 uint8_t *buf
, int len
, int is_write
)
3136 page
= addr
& TARGET_PAGE_MASK
;
3137 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3140 flags
= page_get_flags(page
);
3141 if (!(flags
& PAGE_VALID
))
3144 if (!(flags
& PAGE_WRITE
))
3146 /* XXX: this code should not depend on lock_user */
3147 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3150 unlock_user(p
, addr
, l
);
3152 if (!(flags
& PAGE_READ
))
3154 /* XXX: this code should not depend on lock_user */
3155 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3158 unlock_user(p
, addr
, 0);
3169 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3172 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3173 addr
+= memory_region_get_ram_addr(mr
);
3175 /* No early return if dirty_log_mask is or becomes 0, because
3176 * cpu_physical_memory_set_dirty_range will still call
3177 * xen_modified_memory.
3179 if (dirty_log_mask
) {
3181 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3183 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3184 assert(tcg_enabled());
3185 tb_invalidate_phys_range(addr
, addr
+ length
);
3186 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3188 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3191 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3193 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3195 /* Regions are assumed to support 1-4 byte accesses unless
3196 otherwise specified. */
3197 if (access_size_max
== 0) {
3198 access_size_max
= 4;
3201 /* Bound the maximum access by the alignment of the address. */
3202 if (!mr
->ops
->impl
.unaligned
) {
3203 unsigned align_size_max
= addr
& -addr
;
3204 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3205 access_size_max
= align_size_max
;
3209 /* Don't attempt accesses larger than the maximum. */
3210 if (l
> access_size_max
) {
3211 l
= access_size_max
;
3218 static bool prepare_mmio_access(MemoryRegion
*mr
)
3220 bool unlocked
= !qemu_mutex_iothread_locked();
3221 bool release_lock
= false;
3223 if (unlocked
&& mr
->global_locking
) {
3224 qemu_mutex_lock_iothread();
3226 release_lock
= true;
3228 if (mr
->flush_coalesced_mmio
) {
3230 qemu_mutex_lock_iothread();
3232 qemu_flush_coalesced_mmio_buffer();
3234 qemu_mutex_unlock_iothread();
3238 return release_lock
;
3241 /* Called within RCU critical section. */
3242 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3245 int len
, hwaddr addr1
,
3246 hwaddr l
, MemoryRegion
*mr
)
3250 MemTxResult result
= MEMTX_OK
;
3251 bool release_lock
= false;
3254 if (!memory_access_is_direct(mr
, true)) {
3255 release_lock
|= prepare_mmio_access(mr
);
3256 l
= memory_access_size(mr
, l
, addr1
);
3257 /* XXX: could force current_cpu to NULL to avoid
3259 val
= ldn_p(buf
, l
);
3260 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3263 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3264 memcpy(ptr
, buf
, l
);
3265 invalidate_and_set_dirty(mr
, addr1
, l
);
3269 qemu_mutex_unlock_iothread();
3270 release_lock
= false;
3282 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3288 /* Called from RCU critical section. */
3289 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3290 const uint8_t *buf
, int len
)
3295 MemTxResult result
= MEMTX_OK
;
3298 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3299 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3305 /* Called within RCU critical section. */
3306 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3307 MemTxAttrs attrs
, uint8_t *buf
,
3308 int len
, hwaddr addr1
, hwaddr l
,
3313 MemTxResult result
= MEMTX_OK
;
3314 bool release_lock
= false;
3317 if (!memory_access_is_direct(mr
, false)) {
3319 release_lock
|= prepare_mmio_access(mr
);
3320 l
= memory_access_size(mr
, l
, addr1
);
3321 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3325 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3326 memcpy(buf
, ptr
, l
);
3330 qemu_mutex_unlock_iothread();
3331 release_lock
= false;
3343 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3349 /* Called from RCU critical section. */
3350 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3351 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3358 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3359 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3363 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3364 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3366 MemTxResult result
= MEMTX_OK
;
3371 fv
= address_space_to_flatview(as
);
3372 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3379 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3381 const uint8_t *buf
, int len
)
3383 MemTxResult result
= MEMTX_OK
;
3388 fv
= address_space_to_flatview(as
);
3389 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3396 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3397 uint8_t *buf
, int len
, bool is_write
)
3400 return address_space_write(as
, addr
, attrs
, buf
, len
);
3402 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3406 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3407 int len
, int is_write
)
3409 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3410 buf
, len
, is_write
);
3413 enum write_rom_type
{
3418 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3419 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3429 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true,
3430 MEMTXATTRS_UNSPECIFIED
);
3432 if (!(memory_region_is_ram(mr
) ||
3433 memory_region_is_romd(mr
))) {
3434 l
= memory_access_size(mr
, l
, addr1
);
3437 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3440 memcpy(ptr
, buf
, l
);
3441 invalidate_and_set_dirty(mr
, addr1
, l
);
3444 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3455 /* used for ROM loading : can write in RAM and ROM */
3456 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3457 const uint8_t *buf
, int len
)
3459 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3462 void cpu_flush_icache_range(hwaddr start
, int len
)
3465 * This function should do the same thing as an icache flush that was
3466 * triggered from within the guest. For TCG we are always cache coherent,
3467 * so there is no need to flush anything. For KVM / Xen we need to flush
3468 * the host's instruction cache at least.
3470 if (tcg_enabled()) {
3474 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3475 start
, NULL
, len
, FLUSH_CACHE
);
3486 static BounceBuffer bounce
;
3488 typedef struct MapClient
{
3490 QLIST_ENTRY(MapClient
) link
;
3493 QemuMutex map_client_list_lock
;
3494 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3495 = QLIST_HEAD_INITIALIZER(map_client_list
);
3497 static void cpu_unregister_map_client_do(MapClient
*client
)
3499 QLIST_REMOVE(client
, link
);
3503 static void cpu_notify_map_clients_locked(void)
3507 while (!QLIST_EMPTY(&map_client_list
)) {
3508 client
= QLIST_FIRST(&map_client_list
);
3509 qemu_bh_schedule(client
->bh
);
3510 cpu_unregister_map_client_do(client
);
3514 void cpu_register_map_client(QEMUBH
*bh
)
3516 MapClient
*client
= g_malloc(sizeof(*client
));
3518 qemu_mutex_lock(&map_client_list_lock
);
3520 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3521 if (!atomic_read(&bounce
.in_use
)) {
3522 cpu_notify_map_clients_locked();
3524 qemu_mutex_unlock(&map_client_list_lock
);
3527 void cpu_exec_init_all(void)
3529 qemu_mutex_init(&ram_list
.mutex
);
3530 /* The data structures we set up here depend on knowing the page size,
3531 * so no more changes can be made after this point.
3532 * In an ideal world, nothing we did before we had finished the
3533 * machine setup would care about the target page size, and we could
3534 * do this much later, rather than requiring board models to state
3535 * up front what their requirements are.
3537 finalize_target_page_bits();
3540 qemu_mutex_init(&map_client_list_lock
);
3543 void cpu_unregister_map_client(QEMUBH
*bh
)
3547 qemu_mutex_lock(&map_client_list_lock
);
3548 QLIST_FOREACH(client
, &map_client_list
, link
) {
3549 if (client
->bh
== bh
) {
3550 cpu_unregister_map_client_do(client
);
3554 qemu_mutex_unlock(&map_client_list_lock
);
3557 static void cpu_notify_map_clients(void)
3559 qemu_mutex_lock(&map_client_list_lock
);
3560 cpu_notify_map_clients_locked();
3561 qemu_mutex_unlock(&map_client_list_lock
);
3564 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3565 bool is_write
, MemTxAttrs attrs
)
3572 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3573 if (!memory_access_is_direct(mr
, is_write
)) {
3574 l
= memory_access_size(mr
, l
, addr
);
3575 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3586 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3587 int len
, bool is_write
,
3594 fv
= address_space_to_flatview(as
);
3595 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3601 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3603 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3604 bool is_write
, MemTxAttrs attrs
)
3608 MemoryRegion
*this_mr
;
3614 if (target_len
== 0) {
3619 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3620 &len
, is_write
, attrs
);
3621 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3627 /* Map a physical memory region into a host virtual address.
3628 * May map a subset of the requested range, given by and returned in *plen.
3629 * May return NULL if resources needed to perform the mapping are exhausted.
3630 * Use only for reads OR writes - not for read-modify-write operations.
3631 * Use cpu_register_map_client() to know when retrying the map operation is
3632 * likely to succeed.
3634 void *address_space_map(AddressSpace
*as
,
3652 fv
= address_space_to_flatview(as
);
3653 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3655 if (!memory_access_is_direct(mr
, is_write
)) {
3656 if (atomic_xchg(&bounce
.in_use
, true)) {
3660 /* Avoid unbounded allocations */
3661 l
= MIN(l
, TARGET_PAGE_SIZE
);
3662 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3666 memory_region_ref(mr
);
3669 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3675 return bounce
.buffer
;
3679 memory_region_ref(mr
);
3680 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3681 l
, is_write
, attrs
);
3682 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3688 /* Unmaps a memory region previously mapped by address_space_map().
3689 * Will also mark the memory as dirty if is_write == 1. access_len gives
3690 * the amount of memory that was actually read or written by the caller.
3692 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3693 int is_write
, hwaddr access_len
)
3695 if (buffer
!= bounce
.buffer
) {
3699 mr
= memory_region_from_host(buffer
, &addr1
);
3702 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3704 if (xen_enabled()) {
3705 xen_invalidate_map_cache_entry(buffer
);
3707 memory_region_unref(mr
);
3711 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3712 bounce
.buffer
, access_len
);
3714 qemu_vfree(bounce
.buffer
);
3715 bounce
.buffer
= NULL
;
3716 memory_region_unref(bounce
.mr
);
3717 atomic_mb_set(&bounce
.in_use
, false);
3718 cpu_notify_map_clients();
3721 void *cpu_physical_memory_map(hwaddr addr
,
3725 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3726 MEMTXATTRS_UNSPECIFIED
);
3729 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3730 int is_write
, hwaddr access_len
)
3732 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3735 #define ARG1_DECL AddressSpace *as
3738 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3739 #define RCU_READ_LOCK(...) rcu_read_lock()
3740 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3741 #include "memory_ldst.inc.c"
3743 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3749 AddressSpaceDispatch
*d
;
3756 cache
->fv
= address_space_get_flatview(as
);
3757 d
= flatview_to_dispatch(cache
->fv
);
3758 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3761 memory_region_ref(mr
);
3762 if (memory_access_is_direct(mr
, is_write
)) {
3763 /* We don't care about the memory attributes here as we're only
3764 * doing this if we found actual RAM, which behaves the same
3765 * regardless of attributes; so UNSPECIFIED is fine.
3767 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3768 cache
->xlat
, l
, is_write
,
3769 MEMTXATTRS_UNSPECIFIED
);
3770 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3776 cache
->is_write
= is_write
;
3780 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3784 assert(cache
->is_write
);
3785 if (likely(cache
->ptr
)) {
3786 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3790 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3792 if (!cache
->mrs
.mr
) {
3796 if (xen_enabled()) {
3797 xen_invalidate_map_cache_entry(cache
->ptr
);
3799 memory_region_unref(cache
->mrs
.mr
);
3800 flatview_unref(cache
->fv
);
3801 cache
->mrs
.mr
= NULL
;
3805 /* Called from RCU critical section. This function has the same
3806 * semantics as address_space_translate, but it only works on a
3807 * predefined range of a MemoryRegion that was mapped with
3808 * address_space_cache_init.
3810 static inline MemoryRegion
*address_space_translate_cached(
3811 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3812 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3814 MemoryRegionSection section
;
3816 IOMMUMemoryRegion
*iommu_mr
;
3817 AddressSpace
*target_as
;
3819 assert(!cache
->ptr
);
3820 *xlat
= addr
+ cache
->xlat
;
3823 iommu_mr
= memory_region_get_iommu(mr
);
3829 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3830 NULL
, is_write
, true,
3835 /* Called from RCU critical section. address_space_read_cached uses this
3836 * out of line function when the target is an MMIO or IOMMU region.
3839 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3846 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3847 MEMTXATTRS_UNSPECIFIED
);
3848 flatview_read_continue(cache
->fv
,
3849 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3853 /* Called from RCU critical section. address_space_write_cached uses this
3854 * out of line function when the target is an MMIO or IOMMU region.
3857 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3858 const void *buf
, int len
)
3864 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3865 MEMTXATTRS_UNSPECIFIED
);
3866 flatview_write_continue(cache
->fv
,
3867 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3871 #define ARG1_DECL MemoryRegionCache *cache
3873 #define SUFFIX _cached_slow
3874 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3875 #define RCU_READ_LOCK() ((void)0)
3876 #define RCU_READ_UNLOCK() ((void)0)
3877 #include "memory_ldst.inc.c"
3879 /* virtual memory access for debug (includes writing to ROM) */
3880 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3881 uint8_t *buf
, int len
, int is_write
)
3887 cpu_synchronize_state(cpu
);
3892 page
= addr
& TARGET_PAGE_MASK
;
3893 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3894 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3895 /* if no physical page mapped, return an error */
3896 if (phys_addr
== -1)
3898 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3901 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3903 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3906 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3907 MEMTXATTRS_UNSPECIFIED
,
3918 * Allows code that needs to deal with migration bitmaps etc to still be built
3919 * target independent.
3921 size_t qemu_target_page_size(void)
3923 return TARGET_PAGE_SIZE
;
3926 int qemu_target_page_bits(void)
3928 return TARGET_PAGE_BITS
;
3931 int qemu_target_page_bits_min(void)
3933 return TARGET_PAGE_BITS_MIN
;
3938 * A helper function for the _utterly broken_ virtio device model to find out if
3939 * it's running on a big endian machine. Don't do this at home kids!
3941 bool target_words_bigendian(void);
3942 bool target_words_bigendian(void)
3944 #if defined(TARGET_WORDS_BIGENDIAN)
3951 #ifndef CONFIG_USER_ONLY
3952 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3959 mr
= address_space_translate(&address_space_memory
,
3960 phys_addr
, &phys_addr
, &l
, false,
3961 MEMTXATTRS_UNSPECIFIED
);
3963 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3968 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3974 RAMBLOCK_FOREACH(block
) {
3975 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3976 block
->used_length
, opaque
);
3985 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func
, void *opaque
)
3991 RAMBLOCK_FOREACH(block
) {
3992 if (!qemu_ram_is_migratable(block
)) {
3995 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3996 block
->used_length
, opaque
);
4006 * Unmap pages of memory from start to start+length such that
4007 * they a) read as 0, b) Trigger whatever fault mechanism
4008 * the OS provides for postcopy.
4009 * The pages must be unmapped by the end of the function.
4010 * Returns: 0 on success, none-0 on failure
4013 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4017 uint8_t *host_startaddr
= rb
->host
+ start
;
4019 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4020 error_report("ram_block_discard_range: Unaligned start address: %p",
4025 if ((start
+ length
) <= rb
->used_length
) {
4026 bool need_madvise
, need_fallocate
;
4027 uint8_t *host_endaddr
= host_startaddr
+ length
;
4028 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4029 error_report("ram_block_discard_range: Unaligned end address: %p",
4034 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4036 /* The logic here is messy;
4037 * madvise DONTNEED fails for hugepages
4038 * fallocate works on hugepages and shmem
4040 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4041 need_fallocate
= rb
->fd
!= -1;
4042 if (need_fallocate
) {
4043 /* For a file, this causes the area of the file to be zero'd
4044 * if read, and for hugetlbfs also causes it to be unmapped
4045 * so a userfault will trigger.
4047 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4048 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4052 error_report("ram_block_discard_range: Failed to fallocate "
4053 "%s:%" PRIx64
" +%zx (%d)",
4054 rb
->idstr
, start
, length
, ret
);
4059 error_report("ram_block_discard_range: fallocate not available/file"
4060 "%s:%" PRIx64
" +%zx (%d)",
4061 rb
->idstr
, start
, length
, ret
);
4066 /* For normal RAM this causes it to be unmapped,
4067 * for shared memory it causes the local mapping to disappear
4068 * and to fall back on the file contents (which we just
4069 * fallocate'd away).
4071 #if defined(CONFIG_MADVISE)
4072 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4075 error_report("ram_block_discard_range: Failed to discard range "
4076 "%s:%" PRIx64
" +%zx (%d)",
4077 rb
->idstr
, start
, length
, ret
);
4082 error_report("ram_block_discard_range: MADVISE not available"
4083 "%s:%" PRIx64
" +%zx (%d)",
4084 rb
->idstr
, start
, length
, ret
);
4088 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4089 need_madvise
, need_fallocate
, ret
);
4091 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4092 "/%zx/" RAM_ADDR_FMT
")",
4093 rb
->idstr
, start
, length
, rb
->used_length
);
4102 void page_size_init(void)
4104 /* NOTE: we can always suppose that qemu_host_page_size >=
4106 if (qemu_host_page_size
== 0) {
4107 qemu_host_page_size
= qemu_real_host_page_size
;
4109 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4110 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4112 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4115 #if !defined(CONFIG_USER_ONLY)
4117 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
4118 int start
, int end
, int skip
, int ptr
)
4120 if (start
== end
- 1) {
4121 mon(f
, "\t%3d ", start
);
4123 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
4125 mon(f
, " skip=%d ", skip
);
4126 if (ptr
== PHYS_MAP_NODE_NIL
) {
4129 mon(f
, " ptr=#%d", ptr
);
4131 mon(f
, " ptr=[%d]", ptr
);
4136 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4137 int128_sub((size), int128_one())) : 0)
4139 void mtree_print_dispatch(fprintf_function mon
, void *f
,
4140 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4144 mon(f
, " Dispatch\n");
4145 mon(f
, " Physical sections\n");
4147 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4148 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4149 const char *names
[] = { " [unassigned]", " [not dirty]",
4150 " [ROM]", " [watch]" };
4152 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
4154 s
->offset_within_address_space
,
4155 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4156 s
->mr
->name
? s
->mr
->name
: "(noname)",
4157 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4158 s
->mr
== root
? " [ROOT]" : "",
4159 s
== d
->mru_section
? " [MRU]" : "",
4160 s
->mr
->is_iommu
? " [iommu]" : "");
4163 mon(f
, " alias=%s", s
->mr
->alias
->name
?
4164 s
->mr
->alias
->name
: "noname");
4169 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4170 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4171 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4174 Node
*n
= d
->map
.nodes
+ i
;
4176 mon(f
, " [%d]\n", i
);
4178 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4179 PhysPageEntry
*pe
= *n
+ j
;
4181 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4185 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
4191 if (jprev
!= ARRAY_SIZE(*n
)) {
4192 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);