4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
109 switch (s
->mmu_idx
) {
110 case ARMMMUIdx_S12NSE1
:
111 return ARMMMUIdx_S12NSE0
;
112 case ARMMMUIdx_S1SE1
:
113 return ARMMMUIdx_S1SE0
;
115 g_assert_not_reached();
121 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
122 fprintf_function cpu_fprintf
, int flags
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
125 CPUARMState
*env
= &cpu
->env
;
126 uint32_t psr
= pstate_read(env
);
128 int el
= arm_current_el(env
);
129 const char *ns_status
;
131 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
132 env
->pc
, env
->xregs
[31]);
133 for (i
= 0; i
< 31; i
++) {
134 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
136 cpu_fprintf(f
, "\n");
142 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
143 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
148 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
150 psr
& PSTATE_N
? 'N' : '-',
151 psr
& PSTATE_Z
? 'Z' : '-',
152 psr
& PSTATE_C
? 'C' : '-',
153 psr
& PSTATE_V
? 'V' : '-',
156 psr
& PSTATE_SP
? 'h' : 't');
158 if (flags
& CPU_DUMP_FPU
) {
160 for (i
= 0; i
< numvfpregs
; i
+= 2) {
161 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
162 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
163 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
165 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
166 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
167 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
170 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
171 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
175 void gen_a64_set_pc_im(uint64_t val
)
177 tcg_gen_movi_i64(cpu_pc
, val
);
180 /* Load the PC from a generic TCG variable.
182 * If address tagging is enabled via the TCR TBI bits, then loading
183 * an address into the PC will clear out any tag in the it:
184 * + for EL2 and EL3 there is only one TBI bit, and if it is set
185 * then the address is zero-extended, clearing bits [63:56]
186 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
187 * and TBI1 controls addressses with bit 55 == 1.
188 * If the appropriate TBI bit is set for the address then
189 * the address is sign-extended from bit 55 into bits [63:56]
191 * We can avoid doing this for relative-branches, because the
192 * PC + offset can never overflow into the tag bits (assuming
193 * that virtual addresses are less than 56 bits wide, as they
194 * are currently), but we must handle it for branch-to-register.
196 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
199 if (s
->current_el
<= 1) {
200 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
201 * examine bit 55 of address, can just generate code.
202 * If mixed, then test via generated code
204 if (s
->tbi0
&& s
->tbi1
) {
205 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
206 /* Both bits set, sign extension from bit 55 into [63:56] will
209 tcg_gen_shli_i64(tmp_reg
, src
, 8);
210 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
211 tcg_temp_free_i64(tmp_reg
);
212 } else if (!s
->tbi0
&& !s
->tbi1
) {
213 /* Neither bit set, just load it as-is */
214 tcg_gen_mov_i64(cpu_pc
, src
);
216 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
217 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
218 TCGv_i64 tcg_zero
= tcg_const_i64(0);
220 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
223 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
224 tcg_gen_andi_i64(tcg_tmpval
, src
,
225 0x00FFFFFFFFFFFFFFull
);
226 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
229 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
230 tcg_gen_ori_i64(tcg_tmpval
, src
,
231 0xFF00000000000000ull
);
232 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 tcg_temp_free_i64(tcg_zero
);
236 tcg_temp_free_i64(tcg_bit55
);
237 tcg_temp_free_i64(tcg_tmpval
);
239 } else { /* EL > 1 */
241 /* Force tag byte to all zero */
242 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
244 /* Load unmodified address */
245 tcg_gen_mov_i64(cpu_pc
, src
);
250 typedef struct DisasCompare64
{
255 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
259 arm_test_cc(&c32
, cc
);
261 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
262 * properly. The NE/EQ comparisons are also fine with this choice. */
263 c64
->cond
= c32
.cond
;
264 c64
->value
= tcg_temp_new_i64();
265 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
270 static void a64_free_cc(DisasCompare64
*c64
)
272 tcg_temp_free_i64(c64
->value
);
275 static void gen_exception_internal(int excp
)
277 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
279 assert(excp_is_internal(excp
));
280 gen_helper_exception_internal(cpu_env
, tcg_excp
);
281 tcg_temp_free_i32(tcg_excp
);
284 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
286 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
287 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
288 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
290 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
292 tcg_temp_free_i32(tcg_el
);
293 tcg_temp_free_i32(tcg_syn
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
299 gen_a64_set_pc_im(s
->pc
- offset
);
300 gen_exception_internal(excp
);
301 s
->is_jmp
= DISAS_EXC
;
304 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
305 uint32_t syndrome
, uint32_t target_el
)
307 gen_a64_set_pc_im(s
->pc
- offset
);
308 gen_exception(excp
, syndrome
, target_el
);
309 s
->is_jmp
= DISAS_EXC
;
312 static void gen_ss_advance(DisasContext
*s
)
314 /* If the singlestep state is Active-not-pending, advance to
319 gen_helper_clear_pstate_ss(cpu_env
);
323 static void gen_step_complete_exception(DisasContext
*s
)
325 /* We just completed step of an insn. Move from Active-not-pending
326 * to Active-pending, and then also take the swstep exception.
327 * This corresponds to making the (IMPDEF) choice to prioritize
328 * swstep exceptions over asynchronous exceptions taken to an exception
329 * level where debug is disabled. This choice has the advantage that
330 * we do not need to maintain internal state corresponding to the
331 * ISV/EX syndrome bits between completion of the step and generation
332 * of the exception, and our syndrome information is always correct.
335 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
336 default_exception_el(s
));
337 s
->is_jmp
= DISAS_EXC
;
340 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
342 /* No direct tb linking with singlestep (either QEMU's or the ARM
343 * debug architecture kind) or deterministic io
345 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
349 #ifndef CONFIG_USER_ONLY
350 /* Only link tbs from inside the same guest page */
351 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
359 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
361 TranslationBlock
*tb
;
364 if (use_goto_tb(s
, n
, dest
)) {
366 gen_a64_set_pc_im(dest
);
367 tcg_gen_exit_tb((intptr_t)tb
+ n
);
368 s
->is_jmp
= DISAS_TB_JUMP
;
370 gen_a64_set_pc_im(dest
);
372 gen_step_complete_exception(s
);
373 } else if (s
->singlestep_enabled
) {
374 gen_exception_internal(EXCP_DEBUG
);
377 s
->is_jmp
= DISAS_TB_JUMP
;
382 static void unallocated_encoding(DisasContext
*s
)
384 /* Unallocated and reserved encodings are uncategorized */
385 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
386 default_exception_el(s
));
389 #define unsupported_encoding(s, insn) \
391 qemu_log_mask(LOG_UNIMP, \
392 "%s:%d: unsupported instruction encoding 0x%08x " \
393 "at pc=%016" PRIx64 "\n", \
394 __FILE__, __LINE__, insn, s->pc - 4); \
395 unallocated_encoding(s); \
398 static void init_tmp_a64_array(DisasContext
*s
)
400 #ifdef CONFIG_DEBUG_TCG
402 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
403 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
406 s
->tmp_a64_count
= 0;
409 static void free_tmp_a64(DisasContext
*s
)
412 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
413 tcg_temp_free_i64(s
->tmp_a64
[i
]);
415 init_tmp_a64_array(s
);
418 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
420 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
421 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
424 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
426 TCGv_i64 t
= new_tmp_a64(s
);
427 tcg_gen_movi_i64(t
, 0);
432 * Register access functions
434 * These functions are used for directly accessing a register in where
435 * changes to the final register value are likely to be made. If you
436 * need to use a register for temporary calculation (e.g. index type
437 * operations) use the read_* form.
439 * B1.2.1 Register mappings
441 * In instruction register encoding 31 can refer to ZR (zero register) or
442 * the SP (stack pointer) depending on context. In QEMU's case we map SP
443 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
444 * This is the point of the _sp forms.
446 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
449 return new_tmp_a64_zero(s
);
455 /* register access for when 31 == SP */
456 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
461 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
462 * representing the register contents. This TCGv is an auto-freed
463 * temporary so it need not be explicitly freed, and may be modified.
465 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
467 TCGv_i64 v
= new_tmp_a64(s
);
470 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
472 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
475 tcg_gen_movi_i64(v
, 0);
480 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
482 TCGv_i64 v
= new_tmp_a64(s
);
484 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
486 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
491 /* We should have at some point before trying to access an FP register
492 * done the necessary access check, so assert that
493 * (a) we did the check and
494 * (b) we didn't then just plough ahead anyway if it failed.
495 * Print the instruction pattern in the abort message so we can figure
496 * out what we need to fix if a user encounters this problem in the wild.
498 static inline void assert_fp_access_checked(DisasContext
*s
)
500 #ifdef CONFIG_DEBUG_TCG
501 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
502 fprintf(stderr
, "target-arm: FP access check missing for "
503 "instruction 0x%08x\n", s
->insn
);
509 /* Return the offset into CPUARMState of an element of specified
510 * size, 'element' places in from the least significant end of
511 * the FP/vector register Qn.
513 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
514 int element
, TCGMemOp size
)
517 #ifdef HOST_WORDS_BIGENDIAN
518 /* This is complicated slightly because vfp.regs[2n] is
519 * still the low half and vfp.regs[2n+1] the high half
520 * of the 128 bit vector, even on big endian systems.
521 * Calculate the offset assuming a fully bigendian 128 bits,
522 * then XOR to account for the order of the two 64 bit halves.
524 offs
+= (16 - ((element
+ 1) * (1 << size
)));
527 offs
+= element
* (1 << size
);
529 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
530 assert_fp_access_checked(s
);
534 /* Return the offset into CPUARMState of a slice (from
535 * the least significant end) of FP register Qn (ie
537 * (Note that this is not the same mapping as for A32; see cpu.h)
539 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
541 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
542 #ifdef HOST_WORDS_BIGENDIAN
543 offs
+= (8 - (1 << size
));
545 assert_fp_access_checked(s
);
549 /* Offset of the high half of the 128 bit vector Qn */
550 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
552 assert_fp_access_checked(s
);
553 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
556 /* Convenience accessors for reading and writing single and double
557 * FP registers. Writing clears the upper parts of the associated
558 * 128 bit vector register, as required by the architecture.
559 * Note that unlike the GP register accessors, the values returned
560 * by the read functions must be manually freed.
562 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
564 TCGv_i64 v
= tcg_temp_new_i64();
566 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
570 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
572 TCGv_i32 v
= tcg_temp_new_i32();
574 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
578 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
580 TCGv_i64 tcg_zero
= tcg_const_i64(0);
582 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
583 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
584 tcg_temp_free_i64(tcg_zero
);
587 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
589 TCGv_i64 tmp
= tcg_temp_new_i64();
591 tcg_gen_extu_i32_i64(tmp
, v
);
592 write_fp_dreg(s
, reg
, tmp
);
593 tcg_temp_free_i64(tmp
);
596 static TCGv_ptr
get_fpstatus_ptr(void)
598 TCGv_ptr statusptr
= tcg_temp_new_ptr();
601 /* In A64 all instructions (both FP and Neon) use the FPCR;
602 * there is no equivalent of the A32 Neon "standard FPSCR value"
603 * and all operations use vfp.fp_status.
605 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
606 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
610 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
611 * than the 32 bit equivalent.
613 static inline void gen_set_NZ64(TCGv_i64 result
)
615 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
616 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
619 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
620 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
623 gen_set_NZ64(result
);
625 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
626 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
628 tcg_gen_movi_i32(cpu_CF
, 0);
629 tcg_gen_movi_i32(cpu_VF
, 0);
632 /* dest = T0 + T1; compute C, N, V and Z flags */
633 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
636 TCGv_i64 result
, flag
, tmp
;
637 result
= tcg_temp_new_i64();
638 flag
= tcg_temp_new_i64();
639 tmp
= tcg_temp_new_i64();
641 tcg_gen_movi_i64(tmp
, 0);
642 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
644 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
646 gen_set_NZ64(result
);
648 tcg_gen_xor_i64(flag
, result
, t0
);
649 tcg_gen_xor_i64(tmp
, t0
, t1
);
650 tcg_gen_andc_i64(flag
, flag
, tmp
);
651 tcg_temp_free_i64(tmp
);
652 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
654 tcg_gen_mov_i64(dest
, result
);
655 tcg_temp_free_i64(result
);
656 tcg_temp_free_i64(flag
);
658 /* 32 bit arithmetic */
659 TCGv_i32 t0_32
= tcg_temp_new_i32();
660 TCGv_i32 t1_32
= tcg_temp_new_i32();
661 TCGv_i32 tmp
= tcg_temp_new_i32();
663 tcg_gen_movi_i32(tmp
, 0);
664 tcg_gen_extrl_i64_i32(t0_32
, t0
);
665 tcg_gen_extrl_i64_i32(t1_32
, t1
);
666 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
667 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
668 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
669 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
670 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
671 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
673 tcg_temp_free_i32(tmp
);
674 tcg_temp_free_i32(t0_32
);
675 tcg_temp_free_i32(t1_32
);
679 /* dest = T0 - T1; compute C, N, V and Z flags */
680 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
683 /* 64 bit arithmetic */
684 TCGv_i64 result
, flag
, tmp
;
686 result
= tcg_temp_new_i64();
687 flag
= tcg_temp_new_i64();
688 tcg_gen_sub_i64(result
, t0
, t1
);
690 gen_set_NZ64(result
);
692 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
693 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
695 tcg_gen_xor_i64(flag
, result
, t0
);
696 tmp
= tcg_temp_new_i64();
697 tcg_gen_xor_i64(tmp
, t0
, t1
);
698 tcg_gen_and_i64(flag
, flag
, tmp
);
699 tcg_temp_free_i64(tmp
);
700 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
701 tcg_gen_mov_i64(dest
, result
);
702 tcg_temp_free_i64(flag
);
703 tcg_temp_free_i64(result
);
705 /* 32 bit arithmetic */
706 TCGv_i32 t0_32
= tcg_temp_new_i32();
707 TCGv_i32 t1_32
= tcg_temp_new_i32();
710 tcg_gen_extrl_i64_i32(t0_32
, t0
);
711 tcg_gen_extrl_i64_i32(t1_32
, t1
);
712 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
713 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
714 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
715 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
716 tmp
= tcg_temp_new_i32();
717 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
718 tcg_temp_free_i32(t0_32
);
719 tcg_temp_free_i32(t1_32
);
720 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
721 tcg_temp_free_i32(tmp
);
722 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
726 /* dest = T0 + T1 + CF; do not compute flags. */
727 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
729 TCGv_i64 flag
= tcg_temp_new_i64();
730 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
731 tcg_gen_add_i64(dest
, t0
, t1
);
732 tcg_gen_add_i64(dest
, dest
, flag
);
733 tcg_temp_free_i64(flag
);
736 tcg_gen_ext32u_i64(dest
, dest
);
740 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
741 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
744 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
745 result
= tcg_temp_new_i64();
746 cf_64
= tcg_temp_new_i64();
747 vf_64
= tcg_temp_new_i64();
748 tmp
= tcg_const_i64(0);
750 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
751 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
752 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
753 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
754 gen_set_NZ64(result
);
756 tcg_gen_xor_i64(vf_64
, result
, t0
);
757 tcg_gen_xor_i64(tmp
, t0
, t1
);
758 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
759 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
761 tcg_gen_mov_i64(dest
, result
);
763 tcg_temp_free_i64(tmp
);
764 tcg_temp_free_i64(vf_64
);
765 tcg_temp_free_i64(cf_64
);
766 tcg_temp_free_i64(result
);
768 TCGv_i32 t0_32
, t1_32
, tmp
;
769 t0_32
= tcg_temp_new_i32();
770 t1_32
= tcg_temp_new_i32();
771 tmp
= tcg_const_i32(0);
773 tcg_gen_extrl_i64_i32(t0_32
, t0
);
774 tcg_gen_extrl_i64_i32(t1_32
, t1
);
775 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
776 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
778 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
779 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
780 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
781 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
782 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
784 tcg_temp_free_i32(tmp
);
785 tcg_temp_free_i32(t1_32
);
786 tcg_temp_free_i32(t0_32
);
791 * Load/Store generators
795 * Store from GPR register to memory.
797 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
798 TCGv_i64 tcg_addr
, int size
, int memidx
,
800 unsigned int iss_srt
,
801 bool iss_sf
, bool iss_ar
)
804 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
809 syn
= syn_data_abort_with_iss(0,
815 0, 0, 0, 0, 0, false);
816 disas_set_insn_syndrome(s
, syn
);
820 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
821 TCGv_i64 tcg_addr
, int size
,
823 unsigned int iss_srt
,
824 bool iss_sf
, bool iss_ar
)
826 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
827 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
831 * Load from memory to GPR register
833 static void do_gpr_ld_memidx(DisasContext
*s
,
834 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
835 int size
, bool is_signed
,
836 bool extend
, int memidx
,
837 bool iss_valid
, unsigned int iss_srt
,
838 bool iss_sf
, bool iss_ar
)
840 TCGMemOp memop
= s
->be_data
+ size
;
848 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
850 if (extend
&& is_signed
) {
852 tcg_gen_ext32u_i64(dest
, dest
);
858 syn
= syn_data_abort_with_iss(0,
864 0, 0, 0, 0, 0, false);
865 disas_set_insn_syndrome(s
, syn
);
869 static void do_gpr_ld(DisasContext
*s
,
870 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
871 int size
, bool is_signed
, bool extend
,
872 bool iss_valid
, unsigned int iss_srt
,
873 bool iss_sf
, bool iss_ar
)
875 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
877 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
881 * Store from FP register to memory
883 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
885 /* This writes the bottom N bits of a 128 bit wide vector to memory */
886 TCGv_i64 tmp
= tcg_temp_new_i64();
887 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
889 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
892 bool be
= s
->be_data
== MO_BE
;
893 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
895 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
896 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
898 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
899 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
901 tcg_temp_free_i64(tcg_hiaddr
);
904 tcg_temp_free_i64(tmp
);
908 * Load from memory to FP register
910 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
912 /* This always zero-extends and writes to a full 128 bit wide vector */
913 TCGv_i64 tmplo
= tcg_temp_new_i64();
917 TCGMemOp memop
= s
->be_data
+ size
;
918 tmphi
= tcg_const_i64(0);
919 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
921 bool be
= s
->be_data
== MO_BE
;
924 tmphi
= tcg_temp_new_i64();
925 tcg_hiaddr
= tcg_temp_new_i64();
927 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
928 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
930 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
932 tcg_temp_free_i64(tcg_hiaddr
);
935 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
936 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
938 tcg_temp_free_i64(tmplo
);
939 tcg_temp_free_i64(tmphi
);
943 * Vector load/store helpers.
945 * The principal difference between this and a FP load is that we don't
946 * zero extend as we are filling a partial chunk of the vector register.
947 * These functions don't support 128 bit loads/stores, which would be
948 * normal load/store operations.
950 * The _i32 versions are useful when operating on 32 bit quantities
951 * (eg for floating point single or using Neon helper functions).
954 /* Get value of an element within a vector register */
955 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
956 int element
, TCGMemOp memop
)
958 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
961 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
964 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
967 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
983 g_assert_not_reached();
987 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
988 int element
, TCGMemOp memop
)
990 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
993 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
996 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
999 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1009 g_assert_not_reached();
1013 /* Set value of an element within a vector register */
1014 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1015 int element
, TCGMemOp memop
)
1017 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1020 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1023 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1026 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1032 g_assert_not_reached();
1036 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1037 int destidx
, int element
, TCGMemOp memop
)
1039 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1042 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1045 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1048 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1051 g_assert_not_reached();
1055 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1056 * vector ops all need to do this).
1058 static void clear_vec_high(DisasContext
*s
, int rd
)
1060 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1062 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1063 tcg_temp_free_i64(tcg_zero
);
1066 /* Store from vector register to memory */
1067 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1068 TCGv_i64 tcg_addr
, int size
)
1070 TCGMemOp memop
= s
->be_data
+ size
;
1071 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1073 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1074 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1076 tcg_temp_free_i64(tcg_tmp
);
1079 /* Load from memory to vector register */
1080 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1081 TCGv_i64 tcg_addr
, int size
)
1083 TCGMemOp memop
= s
->be_data
+ size
;
1084 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1086 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1087 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1089 tcg_temp_free_i64(tcg_tmp
);
1092 /* Check that FP/Neon access is enabled. If it is, return
1093 * true. If not, emit code to generate an appropriate exception,
1094 * and return false; the caller should not emit any code for
1095 * the instruction. Note that this check must happen after all
1096 * unallocated-encoding checks (otherwise the syndrome information
1097 * for the resulting exception will be incorrect).
1099 static inline bool fp_access_check(DisasContext
*s
)
1101 assert(!s
->fp_access_checked
);
1102 s
->fp_access_checked
= true;
1104 if (!s
->fp_excp_el
) {
1108 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1114 * This utility function is for doing register extension with an
1115 * optional shift. You will likely want to pass a temporary for the
1116 * destination register. See DecodeRegExtend() in the ARM ARM.
1118 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1119 int option
, unsigned int shift
)
1121 int extsize
= extract32(option
, 0, 2);
1122 bool is_signed
= extract32(option
, 2, 1);
1127 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1130 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1133 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1142 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1145 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1157 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1161 static inline void gen_check_sp_alignment(DisasContext
*s
)
1163 /* The AArch64 architecture mandates that (if enabled via PSTATE
1164 * or SCTLR bits) there is a check that SP is 16-aligned on every
1165 * SP-relative load or store (with an exception generated if it is not).
1166 * In line with general QEMU practice regarding misaligned accesses,
1167 * we omit these checks for the sake of guest program performance.
1168 * This function is provided as a hook so we can more easily add these
1169 * checks in future (possibly as a "favour catching guest program bugs
1170 * over speed" user selectable option).
1175 * This provides a simple table based table lookup decoder. It is
1176 * intended to be used when the relevant bits for decode are too
1177 * awkwardly placed and switch/if based logic would be confusing and
1178 * deeply nested. Since it's a linear search through the table, tables
1179 * should be kept small.
1181 * It returns the first handler where insn & mask == pattern, or
1182 * NULL if there is no match.
1183 * The table is terminated by an empty mask (i.e. 0)
1185 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1188 const AArch64DecodeTable
*tptr
= table
;
1190 while (tptr
->mask
) {
1191 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1192 return tptr
->disas_fn
;
1200 * the instruction disassembly implemented here matches
1201 * the instruction encoding classifications in chapter 3 (C3)
1202 * of the ARM Architecture Reference Manual (DDI0487A_a)
1205 /* C3.2.7 Unconditional branch (immediate)
1207 * +----+-----------+-------------------------------------+
1208 * | op | 0 0 1 0 1 | imm26 |
1209 * +----+-----------+-------------------------------------+
1211 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1213 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1215 if (insn
& (1U << 31)) {
1216 /* C5.6.26 BL Branch with link */
1217 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1220 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1221 gen_goto_tb(s
, 0, addr
);
1224 /* C3.2.1 Compare & branch (immediate)
1225 * 31 30 25 24 23 5 4 0
1226 * +----+-------------+----+---------------------+--------+
1227 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1228 * +----+-------------+----+---------------------+--------+
1230 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1232 unsigned int sf
, op
, rt
;
1234 TCGLabel
*label_match
;
1237 sf
= extract32(insn
, 31, 1);
1238 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1239 rt
= extract32(insn
, 0, 5);
1240 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1242 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1243 label_match
= gen_new_label();
1245 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1246 tcg_cmp
, 0, label_match
);
1248 gen_goto_tb(s
, 0, s
->pc
);
1249 gen_set_label(label_match
);
1250 gen_goto_tb(s
, 1, addr
);
1253 /* C3.2.5 Test & branch (immediate)
1254 * 31 30 25 24 23 19 18 5 4 0
1255 * +----+-------------+----+-------+-------------+------+
1256 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1257 * +----+-------------+----+-------+-------------+------+
1259 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1261 unsigned int bit_pos
, op
, rt
;
1263 TCGLabel
*label_match
;
1266 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1267 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1268 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1269 rt
= extract32(insn
, 0, 5);
1271 tcg_cmp
= tcg_temp_new_i64();
1272 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1273 label_match
= gen_new_label();
1274 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1275 tcg_cmp
, 0, label_match
);
1276 tcg_temp_free_i64(tcg_cmp
);
1277 gen_goto_tb(s
, 0, s
->pc
);
1278 gen_set_label(label_match
);
1279 gen_goto_tb(s
, 1, addr
);
1282 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1283 * 31 25 24 23 5 4 3 0
1284 * +---------------+----+---------------------+----+------+
1285 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1286 * +---------------+----+---------------------+----+------+
1288 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1293 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1294 unallocated_encoding(s
);
1297 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1298 cond
= extract32(insn
, 0, 4);
1301 /* genuinely conditional branches */
1302 TCGLabel
*label_match
= gen_new_label();
1303 arm_gen_test_cc(cond
, label_match
);
1304 gen_goto_tb(s
, 0, s
->pc
);
1305 gen_set_label(label_match
);
1306 gen_goto_tb(s
, 1, addr
);
1308 /* 0xe and 0xf are both "always" conditions */
1309 gen_goto_tb(s
, 0, addr
);
1314 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1315 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1317 unsigned int selector
= crm
<< 3 | op2
;
1320 unallocated_encoding(s
);
1328 s
->is_jmp
= DISAS_WFI
;
1331 s
->is_jmp
= DISAS_YIELD
;
1334 s
->is_jmp
= DISAS_WFE
;
1338 /* we treat all as NOP at least for now */
1341 /* default specified as NOP equivalent */
1346 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1348 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1351 /* CLREX, DSB, DMB, ISB */
1352 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1353 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1358 unallocated_encoding(s
);
1369 case 1: /* MBReqTypes_Reads */
1370 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1372 case 2: /* MBReqTypes_Writes */
1373 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1375 default: /* MBReqTypes_All */
1376 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1382 /* We need to break the TB after this insn to execute
1383 * a self-modified code correctly and also to take
1384 * any pending interrupts immediately.
1386 s
->is_jmp
= DISAS_UPDATE
;
1389 unallocated_encoding(s
);
1394 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1395 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1396 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1398 int op
= op1
<< 3 | op2
;
1400 case 0x05: /* SPSel */
1401 if (s
->current_el
== 0) {
1402 unallocated_encoding(s
);
1406 case 0x1e: /* DAIFSet */
1407 case 0x1f: /* DAIFClear */
1409 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1410 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1411 gen_a64_set_pc_im(s
->pc
- 4);
1412 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1413 tcg_temp_free_i32(tcg_imm
);
1414 tcg_temp_free_i32(tcg_op
);
1415 s
->is_jmp
= DISAS_UPDATE
;
1419 unallocated_encoding(s
);
1424 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1426 TCGv_i32 tmp
= tcg_temp_new_i32();
1427 TCGv_i32 nzcv
= tcg_temp_new_i32();
1429 /* build bit 31, N */
1430 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1431 /* build bit 30, Z */
1432 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1433 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1434 /* build bit 29, C */
1435 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1436 /* build bit 28, V */
1437 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1438 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1439 /* generate result */
1440 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1442 tcg_temp_free_i32(nzcv
);
1443 tcg_temp_free_i32(tmp
);
1446 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1449 TCGv_i32 nzcv
= tcg_temp_new_i32();
1451 /* take NZCV from R[t] */
1452 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1455 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1457 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1458 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1460 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1461 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1463 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1464 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1465 tcg_temp_free_i32(nzcv
);
1468 /* C5.6.129 MRS - move from system register
1469 * C5.6.131 MSR (register) - move to system register
1472 * These are all essentially the same insn in 'read' and 'write'
1473 * versions, with varying op0 fields.
1475 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1476 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1477 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1479 const ARMCPRegInfo
*ri
;
1482 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1483 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1484 crn
, crm
, op0
, op1
, op2
));
1487 /* Unknown register; this might be a guest error or a QEMU
1488 * unimplemented feature.
1490 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1491 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1492 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1493 unallocated_encoding(s
);
1497 /* Check access permissions */
1498 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1499 unallocated_encoding(s
);
1504 /* Emit code to perform further access permissions checks at
1505 * runtime; this may result in an exception.
1508 TCGv_i32 tcg_syn
, tcg_isread
;
1511 gen_a64_set_pc_im(s
->pc
- 4);
1512 tmpptr
= tcg_const_ptr(ri
);
1513 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1514 tcg_syn
= tcg_const_i32(syndrome
);
1515 tcg_isread
= tcg_const_i32(isread
);
1516 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1517 tcg_temp_free_ptr(tmpptr
);
1518 tcg_temp_free_i32(tcg_syn
);
1519 tcg_temp_free_i32(tcg_isread
);
1522 /* Handle special cases first */
1523 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1527 tcg_rt
= cpu_reg(s
, rt
);
1529 gen_get_nzcv(tcg_rt
);
1531 gen_set_nzcv(tcg_rt
);
1534 case ARM_CP_CURRENTEL
:
1535 /* Reads as current EL value from pstate, which is
1536 * guaranteed to be constant by the tb flags.
1538 tcg_rt
= cpu_reg(s
, rt
);
1539 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1542 /* Writes clear the aligned block of memory which rt points into. */
1543 tcg_rt
= cpu_reg(s
, rt
);
1544 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1550 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1554 tcg_rt
= cpu_reg(s
, rt
);
1557 if (ri
->type
& ARM_CP_CONST
) {
1558 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1559 } else if (ri
->readfn
) {
1561 tmpptr
= tcg_const_ptr(ri
);
1562 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1563 tcg_temp_free_ptr(tmpptr
);
1565 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1568 if (ri
->type
& ARM_CP_CONST
) {
1569 /* If not forbidden by access permissions, treat as WI */
1571 } else if (ri
->writefn
) {
1573 tmpptr
= tcg_const_ptr(ri
);
1574 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1575 tcg_temp_free_ptr(tmpptr
);
1577 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1581 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1582 /* I/O operations must end the TB here (whether read or write) */
1584 s
->is_jmp
= DISAS_UPDATE
;
1585 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1586 /* We default to ending the TB on a coprocessor register write,
1587 * but allow this to be suppressed by the register definition
1588 * (usually only necessary to work around guest bugs).
1590 s
->is_jmp
= DISAS_UPDATE
;
1595 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1596 * +---------------------+---+-----+-----+-------+-------+-----+------+
1597 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1598 * +---------------------+---+-----+-----+-------+-------+-----+------+
1600 static void disas_system(DisasContext
*s
, uint32_t insn
)
1602 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1603 l
= extract32(insn
, 21, 1);
1604 op0
= extract32(insn
, 19, 2);
1605 op1
= extract32(insn
, 16, 3);
1606 crn
= extract32(insn
, 12, 4);
1607 crm
= extract32(insn
, 8, 4);
1608 op2
= extract32(insn
, 5, 3);
1609 rt
= extract32(insn
, 0, 5);
1612 if (l
|| rt
!= 31) {
1613 unallocated_encoding(s
);
1617 case 2: /* C5.6.68 HINT */
1618 handle_hint(s
, insn
, op1
, op2
, crm
);
1620 case 3: /* CLREX, DSB, DMB, ISB */
1621 handle_sync(s
, insn
, op1
, op2
, crm
);
1623 case 4: /* C5.6.130 MSR (immediate) */
1624 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1627 unallocated_encoding(s
);
1632 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1635 /* C3.2.3 Exception generation
1637 * 31 24 23 21 20 5 4 2 1 0
1638 * +-----------------+-----+------------------------+-----+----+
1639 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1640 * +-----------------------+------------------------+----------+
1642 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1644 int opc
= extract32(insn
, 21, 3);
1645 int op2_ll
= extract32(insn
, 0, 5);
1646 int imm16
= extract32(insn
, 5, 16);
1651 /* For SVC, HVC and SMC we advance the single-step state
1652 * machine before taking the exception. This is architecturally
1653 * mandated, to ensure that single-stepping a system call
1654 * instruction works properly.
1659 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1660 default_exception_el(s
));
1663 if (s
->current_el
== 0) {
1664 unallocated_encoding(s
);
1667 /* The pre HVC helper handles cases when HVC gets trapped
1668 * as an undefined insn by runtime configuration.
1670 gen_a64_set_pc_im(s
->pc
- 4);
1671 gen_helper_pre_hvc(cpu_env
);
1673 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1676 if (s
->current_el
== 0) {
1677 unallocated_encoding(s
);
1680 gen_a64_set_pc_im(s
->pc
- 4);
1681 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1682 gen_helper_pre_smc(cpu_env
, tmp
);
1683 tcg_temp_free_i32(tmp
);
1685 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1688 unallocated_encoding(s
);
1694 unallocated_encoding(s
);
1698 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1699 default_exception_el(s
));
1703 unallocated_encoding(s
);
1706 /* HLT. This has two purposes.
1707 * Architecturally, it is an external halting debug instruction.
1708 * Since QEMU doesn't implement external debug, we treat this as
1709 * it is required for halting debug disabled: it will UNDEF.
1710 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1712 if (semihosting_enabled() && imm16
== 0xf000) {
1713 #ifndef CONFIG_USER_ONLY
1714 /* In system mode, don't allow userspace access to semihosting,
1715 * to provide some semblance of security (and for consistency
1716 * with our 32-bit semihosting).
1718 if (s
->current_el
== 0) {
1719 unsupported_encoding(s
, insn
);
1723 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1725 unsupported_encoding(s
, insn
);
1729 if (op2_ll
< 1 || op2_ll
> 3) {
1730 unallocated_encoding(s
);
1733 /* DCPS1, DCPS2, DCPS3 */
1734 unsupported_encoding(s
, insn
);
1737 unallocated_encoding(s
);
1742 /* C3.2.7 Unconditional branch (register)
1743 * 31 25 24 21 20 16 15 10 9 5 4 0
1744 * +---------------+-------+-------+-------+------+-------+
1745 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1746 * +---------------+-------+-------+-------+------+-------+
1748 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1750 unsigned int opc
, op2
, op3
, rn
, op4
;
1752 opc
= extract32(insn
, 21, 4);
1753 op2
= extract32(insn
, 16, 5);
1754 op3
= extract32(insn
, 10, 6);
1755 rn
= extract32(insn
, 5, 5);
1756 op4
= extract32(insn
, 0, 5);
1758 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1759 unallocated_encoding(s
);
1767 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1768 /* BLR also needs to load return address */
1770 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1774 if (s
->current_el
== 0) {
1775 unallocated_encoding(s
);
1778 gen_helper_exception_return(cpu_env
);
1779 s
->is_jmp
= DISAS_JUMP
;
1783 unallocated_encoding(s
);
1785 unsupported_encoding(s
, insn
);
1789 unallocated_encoding(s
);
1793 s
->is_jmp
= DISAS_JUMP
;
1796 /* C3.2 Branches, exception generating and system instructions */
1797 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1799 switch (extract32(insn
, 25, 7)) {
1800 case 0x0a: case 0x0b:
1801 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1802 disas_uncond_b_imm(s
, insn
);
1804 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1805 disas_comp_b_imm(s
, insn
);
1807 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1808 disas_test_b_imm(s
, insn
);
1810 case 0x2a: /* Conditional branch (immediate) */
1811 disas_cond_b_imm(s
, insn
);
1813 case 0x6a: /* Exception generation / System */
1814 if (insn
& (1 << 24)) {
1815 disas_system(s
, insn
);
1820 case 0x6b: /* Unconditional branch (register) */
1821 disas_uncond_b_reg(s
, insn
);
1824 unallocated_encoding(s
);
1830 * Load/Store exclusive instructions are implemented by remembering
1831 * the value/address loaded, and seeing if these are the same
1832 * when the store is performed. This is not actually the architecturally
1833 * mandated semantics, but it works for typical guest code sequences
1834 * and avoids having to monitor regular stores.
1836 * The store exclusive uses the atomic cmpxchg primitives to avoid
1837 * races in multi-threaded linux-user and when MTTCG softmmu is
1840 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1841 TCGv_i64 addr
, int size
, bool is_pair
)
1843 TCGv_i64 tmp
= tcg_temp_new_i64();
1844 TCGMemOp memop
= s
->be_data
+ size
;
1846 g_assert(size
<= 3);
1847 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1850 TCGv_i64 addr2
= tcg_temp_new_i64();
1851 TCGv_i64 hitmp
= tcg_temp_new_i64();
1853 g_assert(size
>= 2);
1854 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1855 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1856 tcg_temp_free_i64(addr2
);
1857 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1858 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1859 tcg_temp_free_i64(hitmp
);
1862 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1863 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1865 tcg_temp_free_i64(tmp
);
1866 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1869 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1870 TCGv_i64 inaddr
, int size
, int is_pair
)
1872 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1873 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1876 * [addr + datasize] = {Rt2};
1882 * env->exclusive_addr = -1;
1884 TCGLabel
*fail_label
= gen_new_label();
1885 TCGLabel
*done_label
= gen_new_label();
1886 TCGv_i64 addr
= tcg_temp_local_new_i64();
1889 /* Copy input into a local temp so it is not trashed when the
1890 * basic block ends at the branch insn.
1892 tcg_gen_mov_i64(addr
, inaddr
);
1893 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1895 tmp
= tcg_temp_new_i64();
1898 TCGv_i64 val
= tcg_temp_new_i64();
1899 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1900 tcg_gen_concat32_i64(val
, cpu_exclusive_val
, cpu_exclusive_high
);
1901 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, val
, tmp
,
1903 size
| MO_ALIGN
| s
->be_data
);
1904 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, val
);
1905 tcg_temp_free_i64(val
);
1906 } else if (s
->be_data
== MO_LE
) {
1907 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1910 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1914 TCGv_i64 val
= cpu_reg(s
, rt
);
1915 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, cpu_exclusive_val
, val
,
1917 size
| MO_ALIGN
| s
->be_data
);
1918 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1921 tcg_temp_free_i64(addr
);
1923 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1924 tcg_temp_free_i64(tmp
);
1925 tcg_gen_br(done_label
);
1927 gen_set_label(fail_label
);
1928 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1929 gen_set_label(done_label
);
1930 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1933 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1934 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1936 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1938 int opc0
= extract32(opc
, 0, 1);
1942 regsize
= opc0
? 32 : 64;
1944 regsize
= size
== 3 ? 64 : 32;
1946 return regsize
== 64;
1949 /* C3.3.6 Load/store exclusive
1951 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1952 * +-----+-------------+----+---+----+------+----+-------+------+------+
1953 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1954 * +-----+-------------+----+---+----+------+----+-------+------+------+
1956 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1957 * L: 0 -> store, 1 -> load
1958 * o2: 0 -> exclusive, 1 -> not
1959 * o1: 0 -> single register, 1 -> register pair
1960 * o0: 1 -> load-acquire/store-release, 0 -> not
1962 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1964 int rt
= extract32(insn
, 0, 5);
1965 int rn
= extract32(insn
, 5, 5);
1966 int rt2
= extract32(insn
, 10, 5);
1967 int is_lasr
= extract32(insn
, 15, 1);
1968 int rs
= extract32(insn
, 16, 5);
1969 int is_pair
= extract32(insn
, 21, 1);
1970 int is_store
= !extract32(insn
, 22, 1);
1971 int is_excl
= !extract32(insn
, 23, 1);
1972 int size
= extract32(insn
, 30, 2);
1975 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1976 (!is_excl
&& is_pair
) ||
1977 (is_pair
&& size
< 2)) {
1978 unallocated_encoding(s
);
1983 gen_check_sp_alignment(s
);
1985 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1987 /* Note that since TCG is single threaded load-acquire/store-release
1988 * semantics require no extra if (is_lasr) { ... } handling.
1994 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1996 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2000 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2002 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2005 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2006 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2008 /* Generate ISS for non-exclusive accesses including LASR. */
2011 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2013 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2014 true, rt
, iss_sf
, is_lasr
);
2016 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2017 true, rt
, iss_sf
, is_lasr
);
2019 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2026 * C3.3.5 Load register (literal)
2028 * 31 30 29 27 26 25 24 23 5 4 0
2029 * +-----+-------+---+-----+-------------------+-------+
2030 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2031 * +-----+-------+---+-----+-------------------+-------+
2033 * V: 1 -> vector (simd/fp)
2034 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2035 * 10-> 32 bit signed, 11 -> prefetch
2036 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2038 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2040 int rt
= extract32(insn
, 0, 5);
2041 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2042 bool is_vector
= extract32(insn
, 26, 1);
2043 int opc
= extract32(insn
, 30, 2);
2044 bool is_signed
= false;
2046 TCGv_i64 tcg_rt
, tcg_addr
;
2050 unallocated_encoding(s
);
2054 if (!fp_access_check(s
)) {
2059 /* PRFM (literal) : prefetch */
2062 size
= 2 + extract32(opc
, 0, 1);
2063 is_signed
= extract32(opc
, 1, 1);
2066 tcg_rt
= cpu_reg(s
, rt
);
2068 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2070 do_fp_ld(s
, rt
, tcg_addr
, size
);
2072 /* Only unsigned 32bit loads target 32bit registers. */
2073 bool iss_sf
= opc
!= 0;
2075 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2076 true, rt
, iss_sf
, false);
2078 tcg_temp_free_i64(tcg_addr
);
2082 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2083 * C5.6.81 LDP (Load Pair - non vector)
2084 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2085 * C5.6.176 STNP (Store Pair - non-temporal hint)
2086 * C5.6.177 STP (Store Pair - non vector)
2087 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2088 * C6.3.165 LDP (Load Pair of SIMD&FP)
2089 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2090 * C6.3.284 STP (Store Pair of SIMD&FP)
2092 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2093 * +-----+-------+---+---+-------+---+-----------------------------+
2094 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2095 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2097 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2099 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2100 * V: 0 -> GPR, 1 -> Vector
2101 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2102 * 10 -> signed offset, 11 -> pre-index
2103 * L: 0 -> Store 1 -> Load
2105 * Rt, Rt2 = GPR or SIMD registers to be stored
2106 * Rn = general purpose register containing address
2107 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2109 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2111 int rt
= extract32(insn
, 0, 5);
2112 int rn
= extract32(insn
, 5, 5);
2113 int rt2
= extract32(insn
, 10, 5);
2114 uint64_t offset
= sextract64(insn
, 15, 7);
2115 int index
= extract32(insn
, 23, 2);
2116 bool is_vector
= extract32(insn
, 26, 1);
2117 bool is_load
= extract32(insn
, 22, 1);
2118 int opc
= extract32(insn
, 30, 2);
2120 bool is_signed
= false;
2121 bool postindex
= false;
2124 TCGv_i64 tcg_addr
; /* calculated address */
2128 unallocated_encoding(s
);
2135 size
= 2 + extract32(opc
, 1, 1);
2136 is_signed
= extract32(opc
, 0, 1);
2137 if (!is_load
&& is_signed
) {
2138 unallocated_encoding(s
);
2144 case 1: /* post-index */
2149 /* signed offset with "non-temporal" hint. Since we don't emulate
2150 * caches we don't care about hints to the cache system about
2151 * data access patterns, and handle this identically to plain
2155 /* There is no non-temporal-hint version of LDPSW */
2156 unallocated_encoding(s
);
2161 case 2: /* signed offset, rn not updated */
2164 case 3: /* pre-index */
2170 if (is_vector
&& !fp_access_check(s
)) {
2177 gen_check_sp_alignment(s
);
2180 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2183 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2188 do_fp_ld(s
, rt
, tcg_addr
, size
);
2190 do_fp_st(s
, rt
, tcg_addr
, size
);
2193 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2195 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2196 false, 0, false, false);
2198 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2199 false, 0, false, false);
2202 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2205 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2207 do_fp_st(s
, rt2
, tcg_addr
, size
);
2210 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2212 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2213 false, 0, false, false);
2215 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2216 false, 0, false, false);
2222 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2224 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2226 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2231 * C3.3.8 Load/store (immediate post-indexed)
2232 * C3.3.9 Load/store (immediate pre-indexed)
2233 * C3.3.12 Load/store (unscaled immediate)
2235 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2236 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2237 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2238 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2240 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2242 * V = 0 -> non-vector
2243 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2244 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2246 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2252 int rn
= extract32(insn
, 5, 5);
2253 int imm9
= sextract32(insn
, 12, 9);
2254 int idx
= extract32(insn
, 10, 2);
2255 bool is_signed
= false;
2256 bool is_store
= false;
2257 bool is_extended
= false;
2258 bool is_unpriv
= (idx
== 2);
2259 bool iss_valid
= !is_vector
;
2266 size
|= (opc
& 2) << 1;
2267 if (size
> 4 || is_unpriv
) {
2268 unallocated_encoding(s
);
2271 is_store
= ((opc
& 1) == 0);
2272 if (!fp_access_check(s
)) {
2276 if (size
== 3 && opc
== 2) {
2277 /* PRFM - prefetch */
2279 unallocated_encoding(s
);
2284 if (opc
== 3 && size
> 1) {
2285 unallocated_encoding(s
);
2288 is_store
= (opc
== 0);
2289 is_signed
= extract32(opc
, 1, 1);
2290 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2310 gen_check_sp_alignment(s
);
2312 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2315 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2320 do_fp_st(s
, rt
, tcg_addr
, size
);
2322 do_fp_ld(s
, rt
, tcg_addr
, size
);
2325 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2326 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2327 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2330 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2331 iss_valid
, rt
, iss_sf
, false);
2333 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2334 is_signed
, is_extended
, memidx
,
2335 iss_valid
, rt
, iss_sf
, false);
2340 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2342 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2344 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2349 * C3.3.10 Load/store (register offset)
2351 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2352 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2353 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2354 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2357 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2358 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2360 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2361 * opc<0>: 0 -> store, 1 -> load
2362 * V: 1 -> vector/simd
2363 * opt: extend encoding (see DecodeRegExtend)
2364 * S: if S=1 then scale (essentially index by sizeof(size))
2365 * Rt: register to transfer into/out of
2366 * Rn: address register or SP for base
2367 * Rm: offset register or ZR for offset
2369 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2375 int rn
= extract32(insn
, 5, 5);
2376 int shift
= extract32(insn
, 12, 1);
2377 int rm
= extract32(insn
, 16, 5);
2378 int opt
= extract32(insn
, 13, 3);
2379 bool is_signed
= false;
2380 bool is_store
= false;
2381 bool is_extended
= false;
2386 if (extract32(opt
, 1, 1) == 0) {
2387 unallocated_encoding(s
);
2392 size
|= (opc
& 2) << 1;
2394 unallocated_encoding(s
);
2397 is_store
= !extract32(opc
, 0, 1);
2398 if (!fp_access_check(s
)) {
2402 if (size
== 3 && opc
== 2) {
2403 /* PRFM - prefetch */
2406 if (opc
== 3 && size
> 1) {
2407 unallocated_encoding(s
);
2410 is_store
= (opc
== 0);
2411 is_signed
= extract32(opc
, 1, 1);
2412 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2416 gen_check_sp_alignment(s
);
2418 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2420 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2421 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2423 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2427 do_fp_st(s
, rt
, tcg_addr
, size
);
2429 do_fp_ld(s
, rt
, tcg_addr
, size
);
2432 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2433 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2435 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2436 true, rt
, iss_sf
, false);
2438 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2439 is_signed
, is_extended
,
2440 true, rt
, iss_sf
, false);
2446 * C3.3.13 Load/store (unsigned immediate)
2448 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2449 * +----+-------+---+-----+-----+------------+-------+------+
2450 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2451 * +----+-------+---+-----+-----+------------+-------+------+
2454 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2455 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2457 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2458 * opc<0>: 0 -> store, 1 -> load
2459 * Rn: base address register (inc SP)
2460 * Rt: target register
2462 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2468 int rn
= extract32(insn
, 5, 5);
2469 unsigned int imm12
= extract32(insn
, 10, 12);
2470 unsigned int offset
;
2475 bool is_signed
= false;
2476 bool is_extended
= false;
2479 size
|= (opc
& 2) << 1;
2481 unallocated_encoding(s
);
2484 is_store
= !extract32(opc
, 0, 1);
2485 if (!fp_access_check(s
)) {
2489 if (size
== 3 && opc
== 2) {
2490 /* PRFM - prefetch */
2493 if (opc
== 3 && size
> 1) {
2494 unallocated_encoding(s
);
2497 is_store
= (opc
== 0);
2498 is_signed
= extract32(opc
, 1, 1);
2499 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2503 gen_check_sp_alignment(s
);
2505 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2506 offset
= imm12
<< size
;
2507 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2511 do_fp_st(s
, rt
, tcg_addr
, size
);
2513 do_fp_ld(s
, rt
, tcg_addr
, size
);
2516 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2517 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2519 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2520 true, rt
, iss_sf
, false);
2522 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2523 true, rt
, iss_sf
, false);
2528 /* Load/store register (all forms) */
2529 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2531 int rt
= extract32(insn
, 0, 5);
2532 int opc
= extract32(insn
, 22, 2);
2533 bool is_vector
= extract32(insn
, 26, 1);
2534 int size
= extract32(insn
, 30, 2);
2536 switch (extract32(insn
, 24, 2)) {
2538 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2539 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2541 /* Load/store register (unscaled immediate)
2542 * Load/store immediate pre/post-indexed
2543 * Load/store register unprivileged
2545 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2549 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2552 unallocated_encoding(s
);
2557 /* C3.3.1 AdvSIMD load/store multiple structures
2559 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2560 * +---+---+---------------+---+-------------+--------+------+------+------+
2561 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2562 * +---+---+---------------+---+-------------+--------+------+------+------+
2564 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2566 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2567 * +---+---+---------------+---+---+---------+--------+------+------+------+
2568 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2569 * +---+---+---------------+---+---+---------+--------+------+------+------+
2571 * Rt: first (or only) SIMD&FP register to be transferred
2572 * Rn: base address or SP
2573 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2575 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2577 int rt
= extract32(insn
, 0, 5);
2578 int rn
= extract32(insn
, 5, 5);
2579 int size
= extract32(insn
, 10, 2);
2580 int opcode
= extract32(insn
, 12, 4);
2581 bool is_store
= !extract32(insn
, 22, 1);
2582 bool is_postidx
= extract32(insn
, 23, 1);
2583 bool is_q
= extract32(insn
, 30, 1);
2584 TCGv_i64 tcg_addr
, tcg_rn
;
2586 int ebytes
= 1 << size
;
2587 int elements
= (is_q
? 128 : 64) / (8 << size
);
2588 int rpt
; /* num iterations */
2589 int selem
; /* structure elements */
2592 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2593 unallocated_encoding(s
);
2597 /* From the shared decode logic */
2628 unallocated_encoding(s
);
2632 if (size
== 3 && !is_q
&& selem
!= 1) {
2634 unallocated_encoding(s
);
2638 if (!fp_access_check(s
)) {
2643 gen_check_sp_alignment(s
);
2646 tcg_rn
= cpu_reg_sp(s
, rn
);
2647 tcg_addr
= tcg_temp_new_i64();
2648 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2650 for (r
= 0; r
< rpt
; r
++) {
2652 for (e
= 0; e
< elements
; e
++) {
2653 int tt
= (rt
+ r
) % 32;
2655 for (xs
= 0; xs
< selem
; xs
++) {
2657 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2659 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2661 /* For non-quad operations, setting a slice of the low
2662 * 64 bits of the register clears the high 64 bits (in
2663 * the ARM ARM pseudocode this is implicit in the fact
2664 * that 'rval' is a 64 bit wide variable). We optimize
2665 * by noticing that we only need to do this the first
2666 * time we touch a register.
2668 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2669 clear_vec_high(s
, tt
);
2672 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2679 int rm
= extract32(insn
, 16, 5);
2681 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2683 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2686 tcg_temp_free_i64(tcg_addr
);
2689 /* C3.3.3 AdvSIMD load/store single structure
2691 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2692 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2693 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2694 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2696 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2698 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2699 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2700 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2701 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2703 * Rt: first (or only) SIMD&FP register to be transferred
2704 * Rn: base address or SP
2705 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2706 * index = encoded in Q:S:size dependent on size
2708 * lane_size = encoded in R, opc
2709 * transfer width = encoded in opc, S, size
2711 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2713 int rt
= extract32(insn
, 0, 5);
2714 int rn
= extract32(insn
, 5, 5);
2715 int size
= extract32(insn
, 10, 2);
2716 int S
= extract32(insn
, 12, 1);
2717 int opc
= extract32(insn
, 13, 3);
2718 int R
= extract32(insn
, 21, 1);
2719 int is_load
= extract32(insn
, 22, 1);
2720 int is_postidx
= extract32(insn
, 23, 1);
2721 int is_q
= extract32(insn
, 30, 1);
2723 int scale
= extract32(opc
, 1, 2);
2724 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2725 bool replicate
= false;
2726 int index
= is_q
<< 3 | S
<< 2 | size
;
2728 TCGv_i64 tcg_addr
, tcg_rn
;
2732 if (!is_load
|| S
) {
2733 unallocated_encoding(s
);
2742 if (extract32(size
, 0, 1)) {
2743 unallocated_encoding(s
);
2749 if (extract32(size
, 1, 1)) {
2750 unallocated_encoding(s
);
2753 if (!extract32(size
, 0, 1)) {
2757 unallocated_encoding(s
);
2765 g_assert_not_reached();
2768 if (!fp_access_check(s
)) {
2772 ebytes
= 1 << scale
;
2775 gen_check_sp_alignment(s
);
2778 tcg_rn
= cpu_reg_sp(s
, rn
);
2779 tcg_addr
= tcg_temp_new_i64();
2780 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2782 for (xs
= 0; xs
< selem
; xs
++) {
2784 /* Load and replicate to all elements */
2786 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2788 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2789 get_mem_index(s
), s
->be_data
+ scale
);
2792 mulconst
= 0x0101010101010101ULL
;
2795 mulconst
= 0x0001000100010001ULL
;
2798 mulconst
= 0x0000000100000001ULL
;
2804 g_assert_not_reached();
2807 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2809 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2811 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2813 clear_vec_high(s
, rt
);
2815 tcg_temp_free_i64(tcg_tmp
);
2817 /* Load/store one element per register */
2819 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2821 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2824 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2829 int rm
= extract32(insn
, 16, 5);
2831 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2833 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2836 tcg_temp_free_i64(tcg_addr
);
2839 /* C3.3 Loads and stores */
2840 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2842 switch (extract32(insn
, 24, 6)) {
2843 case 0x08: /* Load/store exclusive */
2844 disas_ldst_excl(s
, insn
);
2846 case 0x18: case 0x1c: /* Load register (literal) */
2847 disas_ld_lit(s
, insn
);
2849 case 0x28: case 0x29:
2850 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2851 disas_ldst_pair(s
, insn
);
2853 case 0x38: case 0x39:
2854 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2855 disas_ldst_reg(s
, insn
);
2857 case 0x0c: /* AdvSIMD load/store multiple structures */
2858 disas_ldst_multiple_struct(s
, insn
);
2860 case 0x0d: /* AdvSIMD load/store single structure */
2861 disas_ldst_single_struct(s
, insn
);
2864 unallocated_encoding(s
);
2869 /* C3.4.6 PC-rel. addressing
2870 * 31 30 29 28 24 23 5 4 0
2871 * +----+-------+-----------+-------------------+------+
2872 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2873 * +----+-------+-----------+-------------------+------+
2875 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2877 unsigned int page
, rd
;
2881 page
= extract32(insn
, 31, 1);
2882 /* SignExtend(immhi:immlo) -> offset */
2883 offset
= sextract64(insn
, 5, 19);
2884 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2885 rd
= extract32(insn
, 0, 5);
2889 /* ADRP (page based) */
2894 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2898 * C3.4.1 Add/subtract (immediate)
2900 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2901 * +--+--+--+-----------+-----+-------------+-----+-----+
2902 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2903 * +--+--+--+-----------+-----+-------------+-----+-----+
2905 * sf: 0 -> 32bit, 1 -> 64bit
2906 * op: 0 -> add , 1 -> sub
2908 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2910 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2912 int rd
= extract32(insn
, 0, 5);
2913 int rn
= extract32(insn
, 5, 5);
2914 uint64_t imm
= extract32(insn
, 10, 12);
2915 int shift
= extract32(insn
, 22, 2);
2916 bool setflags
= extract32(insn
, 29, 1);
2917 bool sub_op
= extract32(insn
, 30, 1);
2918 bool is_64bit
= extract32(insn
, 31, 1);
2920 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2921 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2922 TCGv_i64 tcg_result
;
2931 unallocated_encoding(s
);
2935 tcg_result
= tcg_temp_new_i64();
2938 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2940 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2943 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2945 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2947 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2949 tcg_temp_free_i64(tcg_imm
);
2953 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2955 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2958 tcg_temp_free_i64(tcg_result
);
2961 /* The input should be a value in the bottom e bits (with higher
2962 * bits zero); returns that value replicated into every element
2963 * of size e in a 64 bit integer.
2965 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2975 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2976 static inline uint64_t bitmask64(unsigned int length
)
2978 assert(length
> 0 && length
<= 64);
2979 return ~0ULL >> (64 - length
);
2982 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2983 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2984 * value (ie should cause a guest UNDEF exception), and true if they are
2985 * valid, in which case the decoded bit pattern is written to result.
2987 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2988 unsigned int imms
, unsigned int immr
)
2991 unsigned e
, levels
, s
, r
;
2994 assert(immn
< 2 && imms
< 64 && immr
< 64);
2996 /* The bit patterns we create here are 64 bit patterns which
2997 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2998 * 64 bits each. Each element contains the same value: a run
2999 * of between 1 and e-1 non-zero bits, rotated within the
3000 * element by between 0 and e-1 bits.
3002 * The element size and run length are encoded into immn (1 bit)
3003 * and imms (6 bits) as follows:
3004 * 64 bit elements: immn = 1, imms = <length of run - 1>
3005 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3006 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3007 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3008 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3009 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3010 * Notice that immn = 0, imms = 11111x is the only combination
3011 * not covered by one of the above options; this is reserved.
3012 * Further, <length of run - 1> all-ones is a reserved pattern.
3014 * In all cases the rotation is by immr % e (and immr is 6 bits).
3017 /* First determine the element size */
3018 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3020 /* This is the immn == 0, imms == 0x11111x case */
3030 /* <length of run - 1> mustn't be all-ones. */
3034 /* Create the value of one element: s+1 set bits rotated
3035 * by r within the element (which is e bits wide)...
3037 mask
= bitmask64(s
+ 1);
3039 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3040 mask
&= bitmask64(e
);
3042 /* ...then replicate the element over the whole 64 bit value */
3043 mask
= bitfield_replicate(mask
, e
);
3048 /* C3.4.4 Logical (immediate)
3049 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3050 * +----+-----+-------------+---+------+------+------+------+
3051 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3052 * +----+-----+-------------+---+------+------+------+------+
3054 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3056 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3057 TCGv_i64 tcg_rd
, tcg_rn
;
3059 bool is_and
= false;
3061 sf
= extract32(insn
, 31, 1);
3062 opc
= extract32(insn
, 29, 2);
3063 is_n
= extract32(insn
, 22, 1);
3064 immr
= extract32(insn
, 16, 6);
3065 imms
= extract32(insn
, 10, 6);
3066 rn
= extract32(insn
, 5, 5);
3067 rd
= extract32(insn
, 0, 5);
3070 unallocated_encoding(s
);
3074 if (opc
== 0x3) { /* ANDS */
3075 tcg_rd
= cpu_reg(s
, rd
);
3077 tcg_rd
= cpu_reg_sp(s
, rd
);
3079 tcg_rn
= cpu_reg(s
, rn
);
3081 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3082 /* some immediate field values are reserved */
3083 unallocated_encoding(s
);
3088 wmask
&= 0xffffffff;
3092 case 0x3: /* ANDS */
3094 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3098 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3101 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3104 assert(FALSE
); /* must handle all above */
3108 if (!sf
&& !is_and
) {
3109 /* zero extend final result; we know we can skip this for AND
3110 * since the immediate had the high 32 bits clear.
3112 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3115 if (opc
== 3) { /* ANDS */
3116 gen_logic_CC(sf
, tcg_rd
);
3121 * C3.4.5 Move wide (immediate)
3123 * 31 30 29 28 23 22 21 20 5 4 0
3124 * +--+-----+-------------+-----+----------------+------+
3125 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3126 * +--+-----+-------------+-----+----------------+------+
3128 * sf: 0 -> 32 bit, 1 -> 64 bit
3129 * opc: 00 -> N, 10 -> Z, 11 -> K
3130 * hw: shift/16 (0,16, and sf only 32, 48)
3132 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3134 int rd
= extract32(insn
, 0, 5);
3135 uint64_t imm
= extract32(insn
, 5, 16);
3136 int sf
= extract32(insn
, 31, 1);
3137 int opc
= extract32(insn
, 29, 2);
3138 int pos
= extract32(insn
, 21, 2) << 4;
3139 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3142 if (!sf
&& (pos
>= 32)) {
3143 unallocated_encoding(s
);
3157 tcg_gen_movi_i64(tcg_rd
, imm
);
3160 tcg_imm
= tcg_const_i64(imm
);
3161 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3162 tcg_temp_free_i64(tcg_imm
);
3164 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3168 unallocated_encoding(s
);
3174 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3175 * +----+-----+-------------+---+------+------+------+------+
3176 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3177 * +----+-----+-------------+---+------+------+------+------+
3179 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3181 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3182 TCGv_i64 tcg_rd
, tcg_tmp
;
3184 sf
= extract32(insn
, 31, 1);
3185 opc
= extract32(insn
, 29, 2);
3186 n
= extract32(insn
, 22, 1);
3187 ri
= extract32(insn
, 16, 6);
3188 si
= extract32(insn
, 10, 6);
3189 rn
= extract32(insn
, 5, 5);
3190 rd
= extract32(insn
, 0, 5);
3191 bitsize
= sf
? 64 : 32;
3193 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3194 unallocated_encoding(s
);
3198 tcg_rd
= cpu_reg(s
, rd
);
3200 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3201 to be smaller than bitsize, we'll never reference data outside the
3202 low 32-bits anyway. */
3203 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3205 /* Recognize simple(r) extractions. */
3207 /* Wd<s-r:0> = Wn<s:r> */
3208 len
= (si
- ri
) + 1;
3209 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3210 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3212 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3213 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3216 /* opc == 1, BXFIL fall through to deposit */
3217 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3220 /* Handle the ri > si case with a deposit
3221 * Wd<32+s-r,32-r> = Wn<s:0>
3224 pos
= (bitsize
- ri
) & (bitsize
- 1);
3227 if (opc
== 0 && len
< ri
) {
3228 /* SBFM: sign extend the destination field from len to fill
3229 the balance of the word. Let the deposit below insert all
3230 of those sign bits. */
3231 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3235 if (opc
== 1) { /* BFM, BXFIL */
3236 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3238 /* SBFM or UBFM: We start with zero, and we haven't modified
3239 any bits outside bitsize, therefore the zero-extension
3240 below is unneeded. */
3241 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3246 if (!sf
) { /* zero extend final result */
3247 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3252 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3253 * +----+------+-------------+---+----+------+--------+------+------+
3254 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3255 * +----+------+-------------+---+----+------+--------+------+------+
3257 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3259 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3261 sf
= extract32(insn
, 31, 1);
3262 n
= extract32(insn
, 22, 1);
3263 rm
= extract32(insn
, 16, 5);
3264 imm
= extract32(insn
, 10, 6);
3265 rn
= extract32(insn
, 5, 5);
3266 rd
= extract32(insn
, 0, 5);
3267 op21
= extract32(insn
, 29, 2);
3268 op0
= extract32(insn
, 21, 1);
3269 bitsize
= sf
? 64 : 32;
3271 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3272 unallocated_encoding(s
);
3274 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3276 tcg_rd
= cpu_reg(s
, rd
);
3278 if (unlikely(imm
== 0)) {
3279 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3280 * so an extract from bit 0 is a special case.
3283 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3285 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3287 } else if (rm
== rn
) { /* ROR */
3288 tcg_rm
= cpu_reg(s
, rm
);
3290 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3292 TCGv_i32 tmp
= tcg_temp_new_i32();
3293 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3294 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3295 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3296 tcg_temp_free_i32(tmp
);
3299 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3300 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3301 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3302 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3303 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3305 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3311 /* C3.4 Data processing - immediate */
3312 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3314 switch (extract32(insn
, 23, 6)) {
3315 case 0x20: case 0x21: /* PC-rel. addressing */
3316 disas_pc_rel_adr(s
, insn
);
3318 case 0x22: case 0x23: /* Add/subtract (immediate) */
3319 disas_add_sub_imm(s
, insn
);
3321 case 0x24: /* Logical (immediate) */
3322 disas_logic_imm(s
, insn
);
3324 case 0x25: /* Move wide (immediate) */
3325 disas_movw_imm(s
, insn
);
3327 case 0x26: /* Bitfield */
3328 disas_bitfield(s
, insn
);
3330 case 0x27: /* Extract */
3331 disas_extract(s
, insn
);
3334 unallocated_encoding(s
);
3339 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3340 * Note that it is the caller's responsibility to ensure that the
3341 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3342 * mandated semantics for out of range shifts.
3344 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3345 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3347 switch (shift_type
) {
3348 case A64_SHIFT_TYPE_LSL
:
3349 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3351 case A64_SHIFT_TYPE_LSR
:
3352 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3354 case A64_SHIFT_TYPE_ASR
:
3356 tcg_gen_ext32s_i64(dst
, src
);
3358 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3360 case A64_SHIFT_TYPE_ROR
:
3362 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3365 t0
= tcg_temp_new_i32();
3366 t1
= tcg_temp_new_i32();
3367 tcg_gen_extrl_i64_i32(t0
, src
);
3368 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3369 tcg_gen_rotr_i32(t0
, t0
, t1
);
3370 tcg_gen_extu_i32_i64(dst
, t0
);
3371 tcg_temp_free_i32(t0
);
3372 tcg_temp_free_i32(t1
);
3376 assert(FALSE
); /* all shift types should be handled */
3380 if (!sf
) { /* zero extend final result */
3381 tcg_gen_ext32u_i64(dst
, dst
);
3385 /* Shift a TCGv src by immediate, put result in dst.
3386 * The shift amount must be in range (this should always be true as the
3387 * relevant instructions will UNDEF on bad shift immediates).
3389 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3390 enum a64_shift_type shift_type
, unsigned int shift_i
)
3392 assert(shift_i
< (sf
? 64 : 32));
3395 tcg_gen_mov_i64(dst
, src
);
3397 TCGv_i64 shift_const
;
3399 shift_const
= tcg_const_i64(shift_i
);
3400 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3401 tcg_temp_free_i64(shift_const
);
3405 /* C3.5.10 Logical (shifted register)
3406 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3407 * +----+-----+-----------+-------+---+------+--------+------+------+
3408 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3409 * +----+-----+-----------+-------+---+------+--------+------+------+
3411 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3413 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3414 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3416 sf
= extract32(insn
, 31, 1);
3417 opc
= extract32(insn
, 29, 2);
3418 shift_type
= extract32(insn
, 22, 2);
3419 invert
= extract32(insn
, 21, 1);
3420 rm
= extract32(insn
, 16, 5);
3421 shift_amount
= extract32(insn
, 10, 6);
3422 rn
= extract32(insn
, 5, 5);
3423 rd
= extract32(insn
, 0, 5);
3425 if (!sf
&& (shift_amount
& (1 << 5))) {
3426 unallocated_encoding(s
);
3430 tcg_rd
= cpu_reg(s
, rd
);
3432 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3433 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3434 * register-register MOV and MVN, so it is worth special casing.
3436 tcg_rm
= cpu_reg(s
, rm
);
3438 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3440 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3444 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3446 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3452 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3455 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3458 tcg_rn
= cpu_reg(s
, rn
);
3460 switch (opc
| (invert
<< 2)) {
3463 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3466 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3469 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3473 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3476 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3479 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3487 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3491 gen_logic_CC(sf
, tcg_rd
);
3496 * C3.5.1 Add/subtract (extended register)
3498 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3499 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3500 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3501 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3503 * sf: 0 -> 32bit, 1 -> 64bit
3504 * op: 0 -> add , 1 -> sub
3507 * option: extension type (see DecodeRegExtend)
3508 * imm3: optional shift to Rm
3510 * Rd = Rn + LSL(extend(Rm), amount)
3512 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3514 int rd
= extract32(insn
, 0, 5);
3515 int rn
= extract32(insn
, 5, 5);
3516 int imm3
= extract32(insn
, 10, 3);
3517 int option
= extract32(insn
, 13, 3);
3518 int rm
= extract32(insn
, 16, 5);
3519 bool setflags
= extract32(insn
, 29, 1);
3520 bool sub_op
= extract32(insn
, 30, 1);
3521 bool sf
= extract32(insn
, 31, 1);
3523 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3525 TCGv_i64 tcg_result
;
3528 unallocated_encoding(s
);
3532 /* non-flag setting ops may use SP */
3534 tcg_rd
= cpu_reg_sp(s
, rd
);
3536 tcg_rd
= cpu_reg(s
, rd
);
3538 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3540 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3541 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3543 tcg_result
= tcg_temp_new_i64();
3547 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3549 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3553 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3555 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3560 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3562 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3565 tcg_temp_free_i64(tcg_result
);
3569 * C3.5.2 Add/subtract (shifted register)
3571 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3572 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3573 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3574 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3576 * sf: 0 -> 32bit, 1 -> 64bit
3577 * op: 0 -> add , 1 -> sub
3579 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3580 * imm6: Shift amount to apply to Rm before the add/sub
3582 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3584 int rd
= extract32(insn
, 0, 5);
3585 int rn
= extract32(insn
, 5, 5);
3586 int imm6
= extract32(insn
, 10, 6);
3587 int rm
= extract32(insn
, 16, 5);
3588 int shift_type
= extract32(insn
, 22, 2);
3589 bool setflags
= extract32(insn
, 29, 1);
3590 bool sub_op
= extract32(insn
, 30, 1);
3591 bool sf
= extract32(insn
, 31, 1);
3593 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3594 TCGv_i64 tcg_rn
, tcg_rm
;
3595 TCGv_i64 tcg_result
;
3597 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3598 unallocated_encoding(s
);
3602 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3603 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3605 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3607 tcg_result
= tcg_temp_new_i64();
3611 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3613 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3617 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3619 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3624 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3626 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3629 tcg_temp_free_i64(tcg_result
);
3632 /* C3.5.9 Data-processing (3 source)
3634 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3635 +--+------+-----------+------+------+----+------+------+------+
3636 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3637 +--+------+-----------+------+------+----+------+------+------+
3640 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3642 int rd
= extract32(insn
, 0, 5);
3643 int rn
= extract32(insn
, 5, 5);
3644 int ra
= extract32(insn
, 10, 5);
3645 int rm
= extract32(insn
, 16, 5);
3646 int op_id
= (extract32(insn
, 29, 3) << 4) |
3647 (extract32(insn
, 21, 3) << 1) |
3648 extract32(insn
, 15, 1);
3649 bool sf
= extract32(insn
, 31, 1);
3650 bool is_sub
= extract32(op_id
, 0, 1);
3651 bool is_high
= extract32(op_id
, 2, 1);
3652 bool is_signed
= false;
3657 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3659 case 0x42: /* SMADDL */
3660 case 0x43: /* SMSUBL */
3661 case 0x44: /* SMULH */
3664 case 0x0: /* MADD (32bit) */
3665 case 0x1: /* MSUB (32bit) */
3666 case 0x40: /* MADD (64bit) */
3667 case 0x41: /* MSUB (64bit) */
3668 case 0x4a: /* UMADDL */
3669 case 0x4b: /* UMSUBL */
3670 case 0x4c: /* UMULH */
3673 unallocated_encoding(s
);
3678 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3679 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3680 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3681 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3684 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3686 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3689 tcg_temp_free_i64(low_bits
);
3693 tcg_op1
= tcg_temp_new_i64();
3694 tcg_op2
= tcg_temp_new_i64();
3695 tcg_tmp
= tcg_temp_new_i64();
3698 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3699 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3702 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3703 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3705 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3706 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3710 if (ra
== 31 && !is_sub
) {
3711 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3712 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3714 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3716 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3718 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3723 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3726 tcg_temp_free_i64(tcg_op1
);
3727 tcg_temp_free_i64(tcg_op2
);
3728 tcg_temp_free_i64(tcg_tmp
);
3731 /* C3.5.3 - Add/subtract (with carry)
3732 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3733 * +--+--+--+------------------------+------+---------+------+-----+
3734 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3735 * +--+--+--+------------------------+------+---------+------+-----+
3739 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3741 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3742 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3744 if (extract32(insn
, 10, 6) != 0) {
3745 unallocated_encoding(s
);
3749 sf
= extract32(insn
, 31, 1);
3750 op
= extract32(insn
, 30, 1);
3751 setflags
= extract32(insn
, 29, 1);
3752 rm
= extract32(insn
, 16, 5);
3753 rn
= extract32(insn
, 5, 5);
3754 rd
= extract32(insn
, 0, 5);
3756 tcg_rd
= cpu_reg(s
, rd
);
3757 tcg_rn
= cpu_reg(s
, rn
);
3760 tcg_y
= new_tmp_a64(s
);
3761 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3763 tcg_y
= cpu_reg(s
, rm
);
3767 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3769 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3773 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3774 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3775 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3776 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3777 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3780 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3782 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3783 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3784 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3787 if (!extract32(insn
, 29, 1)) {
3788 unallocated_encoding(s
);
3791 if (insn
& (1 << 10 | 1 << 4)) {
3792 unallocated_encoding(s
);
3795 sf
= extract32(insn
, 31, 1);
3796 op
= extract32(insn
, 30, 1);
3797 is_imm
= extract32(insn
, 11, 1);
3798 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3799 cond
= extract32(insn
, 12, 4);
3800 rn
= extract32(insn
, 5, 5);
3801 nzcv
= extract32(insn
, 0, 4);
3803 /* Set T0 = !COND. */
3804 tcg_t0
= tcg_temp_new_i32();
3805 arm_test_cc(&c
, cond
);
3806 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3809 /* Load the arguments for the new comparison. */
3811 tcg_y
= new_tmp_a64(s
);
3812 tcg_gen_movi_i64(tcg_y
, y
);
3814 tcg_y
= cpu_reg(s
, y
);
3816 tcg_rn
= cpu_reg(s
, rn
);
3818 /* Set the flags for the new comparison. */
3819 tcg_tmp
= tcg_temp_new_i64();
3821 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3823 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3825 tcg_temp_free_i64(tcg_tmp
);
3827 /* If COND was false, force the flags to #nzcv. Compute two masks
3828 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3829 * For tcg hosts that support ANDC, we can make do with just T1.
3830 * In either case, allow the tcg optimizer to delete any unused mask.
3832 tcg_t1
= tcg_temp_new_i32();
3833 tcg_t2
= tcg_temp_new_i32();
3834 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3835 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3837 if (nzcv
& 8) { /* N */
3838 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3840 if (TCG_TARGET_HAS_andc_i32
) {
3841 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3843 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3846 if (nzcv
& 4) { /* Z */
3847 if (TCG_TARGET_HAS_andc_i32
) {
3848 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3850 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3853 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3855 if (nzcv
& 2) { /* C */
3856 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3858 if (TCG_TARGET_HAS_andc_i32
) {
3859 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3861 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3864 if (nzcv
& 1) { /* V */
3865 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3867 if (TCG_TARGET_HAS_andc_i32
) {
3868 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3870 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3873 tcg_temp_free_i32(tcg_t0
);
3874 tcg_temp_free_i32(tcg_t1
);
3875 tcg_temp_free_i32(tcg_t2
);
3878 /* C3.5.6 Conditional select
3879 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3880 * +----+----+---+-----------------+------+------+-----+------+------+
3881 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3882 * +----+----+---+-----------------+------+------+-----+------+------+
3884 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3886 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3887 TCGv_i64 tcg_rd
, zero
;
3890 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3891 /* S == 1 or op2<1> == 1 */
3892 unallocated_encoding(s
);
3895 sf
= extract32(insn
, 31, 1);
3896 else_inv
= extract32(insn
, 30, 1);
3897 rm
= extract32(insn
, 16, 5);
3898 cond
= extract32(insn
, 12, 4);
3899 else_inc
= extract32(insn
, 10, 1);
3900 rn
= extract32(insn
, 5, 5);
3901 rd
= extract32(insn
, 0, 5);
3903 tcg_rd
= cpu_reg(s
, rd
);
3905 a64_test_cc(&c
, cond
);
3906 zero
= tcg_const_i64(0);
3908 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3910 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3912 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3915 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3916 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3917 if (else_inv
&& else_inc
) {
3918 tcg_gen_neg_i64(t_false
, t_false
);
3919 } else if (else_inv
) {
3920 tcg_gen_not_i64(t_false
, t_false
);
3921 } else if (else_inc
) {
3922 tcg_gen_addi_i64(t_false
, t_false
, 1);
3924 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3927 tcg_temp_free_i64(zero
);
3931 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3935 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3936 unsigned int rn
, unsigned int rd
)
3938 TCGv_i64 tcg_rd
, tcg_rn
;
3939 tcg_rd
= cpu_reg(s
, rd
);
3940 tcg_rn
= cpu_reg(s
, rn
);
3943 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3945 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3946 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3947 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3948 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3949 tcg_temp_free_i32(tcg_tmp32
);
3953 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3954 unsigned int rn
, unsigned int rd
)
3956 TCGv_i64 tcg_rd
, tcg_rn
;
3957 tcg_rd
= cpu_reg(s
, rd
);
3958 tcg_rn
= cpu_reg(s
, rn
);
3961 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3963 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3964 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3965 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3966 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3967 tcg_temp_free_i32(tcg_tmp32
);
3971 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3972 unsigned int rn
, unsigned int rd
)
3974 TCGv_i64 tcg_rd
, tcg_rn
;
3975 tcg_rd
= cpu_reg(s
, rd
);
3976 tcg_rn
= cpu_reg(s
, rn
);
3979 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3981 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3982 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3983 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3984 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3985 tcg_temp_free_i32(tcg_tmp32
);
3989 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3990 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3991 unsigned int rn
, unsigned int rd
)
3994 unallocated_encoding(s
);
3997 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4000 /* C5.6.149 REV with sf==0, opcode==2
4001 * C5.6.151 REV32 (sf==1, opcode==2)
4003 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4004 unsigned int rn
, unsigned int rd
)
4006 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4009 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4010 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4012 /* bswap32_i64 requires zero high word */
4013 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4014 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4015 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4016 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4017 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4019 tcg_temp_free_i64(tcg_tmp
);
4021 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4022 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4026 /* C5.6.150 REV16 (opcode==1) */
4027 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4028 unsigned int rn
, unsigned int rd
)
4030 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4031 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4032 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4034 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
4035 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
4037 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
4038 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4039 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4040 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
4043 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4044 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4045 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4046 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
4048 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
4049 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4050 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
4053 tcg_temp_free_i64(tcg_tmp
);
4056 /* C3.5.7 Data-processing (1 source)
4057 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4058 * +----+---+---+-----------------+---------+--------+------+------+
4059 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4060 * +----+---+---+-----------------+---------+--------+------+------+
4062 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4064 unsigned int sf
, opcode
, rn
, rd
;
4066 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4067 unallocated_encoding(s
);
4071 sf
= extract32(insn
, 31, 1);
4072 opcode
= extract32(insn
, 10, 6);
4073 rn
= extract32(insn
, 5, 5);
4074 rd
= extract32(insn
, 0, 5);
4078 handle_rbit(s
, sf
, rn
, rd
);
4081 handle_rev16(s
, sf
, rn
, rd
);
4084 handle_rev32(s
, sf
, rn
, rd
);
4087 handle_rev64(s
, sf
, rn
, rd
);
4090 handle_clz(s
, sf
, rn
, rd
);
4093 handle_cls(s
, sf
, rn
, rd
);
4098 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4099 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4101 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4102 tcg_rd
= cpu_reg(s
, rd
);
4104 if (!sf
&& is_signed
) {
4105 tcg_n
= new_tmp_a64(s
);
4106 tcg_m
= new_tmp_a64(s
);
4107 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4108 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4110 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4111 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4115 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4117 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4120 if (!sf
) { /* zero extend final result */
4121 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4125 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4126 static void handle_shift_reg(DisasContext
*s
,
4127 enum a64_shift_type shift_type
, unsigned int sf
,
4128 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4130 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4131 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4132 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4134 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4135 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4136 tcg_temp_free_i64(tcg_shift
);
4139 /* CRC32[BHWX], CRC32C[BHWX] */
4140 static void handle_crc32(DisasContext
*s
,
4141 unsigned int sf
, unsigned int sz
, bool crc32c
,
4142 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4144 TCGv_i64 tcg_acc
, tcg_val
;
4147 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4148 || (sf
== 1 && sz
!= 3)
4149 || (sf
== 0 && sz
== 3)) {
4150 unallocated_encoding(s
);
4155 tcg_val
= cpu_reg(s
, rm
);
4169 g_assert_not_reached();
4171 tcg_val
= new_tmp_a64(s
);
4172 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4175 tcg_acc
= cpu_reg(s
, rn
);
4176 tcg_bytes
= tcg_const_i32(1 << sz
);
4179 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4181 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4184 tcg_temp_free_i32(tcg_bytes
);
4187 /* C3.5.8 Data-processing (2 source)
4188 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4189 * +----+---+---+-----------------+------+--------+------+------+
4190 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4191 * +----+---+---+-----------------+------+--------+------+------+
4193 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4195 unsigned int sf
, rm
, opcode
, rn
, rd
;
4196 sf
= extract32(insn
, 31, 1);
4197 rm
= extract32(insn
, 16, 5);
4198 opcode
= extract32(insn
, 10, 6);
4199 rn
= extract32(insn
, 5, 5);
4200 rd
= extract32(insn
, 0, 5);
4202 if (extract32(insn
, 29, 1)) {
4203 unallocated_encoding(s
);
4209 handle_div(s
, false, sf
, rm
, rn
, rd
);
4212 handle_div(s
, true, sf
, rm
, rn
, rd
);
4215 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4218 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4221 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4224 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4233 case 23: /* CRC32 */
4235 int sz
= extract32(opcode
, 0, 2);
4236 bool crc32c
= extract32(opcode
, 2, 1);
4237 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4241 unallocated_encoding(s
);
4246 /* C3.5 Data processing - register */
4247 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4249 switch (extract32(insn
, 24, 5)) {
4250 case 0x0a: /* Logical (shifted register) */
4251 disas_logic_reg(s
, insn
);
4253 case 0x0b: /* Add/subtract */
4254 if (insn
& (1 << 21)) { /* (extended register) */
4255 disas_add_sub_ext_reg(s
, insn
);
4257 disas_add_sub_reg(s
, insn
);
4260 case 0x1b: /* Data-processing (3 source) */
4261 disas_data_proc_3src(s
, insn
);
4264 switch (extract32(insn
, 21, 3)) {
4265 case 0x0: /* Add/subtract (with carry) */
4266 disas_adc_sbc(s
, insn
);
4268 case 0x2: /* Conditional compare */
4269 disas_cc(s
, insn
); /* both imm and reg forms */
4271 case 0x4: /* Conditional select */
4272 disas_cond_select(s
, insn
);
4274 case 0x6: /* Data-processing */
4275 if (insn
& (1 << 30)) { /* (1 source) */
4276 disas_data_proc_1src(s
, insn
);
4277 } else { /* (2 source) */
4278 disas_data_proc_2src(s
, insn
);
4282 unallocated_encoding(s
);
4287 unallocated_encoding(s
);
4292 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4293 unsigned int rn
, unsigned int rm
,
4294 bool cmp_with_zero
, bool signal_all_nans
)
4296 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4297 TCGv_ptr fpst
= get_fpstatus_ptr();
4300 TCGv_i64 tcg_vn
, tcg_vm
;
4302 tcg_vn
= read_fp_dreg(s
, rn
);
4303 if (cmp_with_zero
) {
4304 tcg_vm
= tcg_const_i64(0);
4306 tcg_vm
= read_fp_dreg(s
, rm
);
4308 if (signal_all_nans
) {
4309 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4311 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4313 tcg_temp_free_i64(tcg_vn
);
4314 tcg_temp_free_i64(tcg_vm
);
4316 TCGv_i32 tcg_vn
, tcg_vm
;
4318 tcg_vn
= read_fp_sreg(s
, rn
);
4319 if (cmp_with_zero
) {
4320 tcg_vm
= tcg_const_i32(0);
4322 tcg_vm
= read_fp_sreg(s
, rm
);
4324 if (signal_all_nans
) {
4325 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4327 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4329 tcg_temp_free_i32(tcg_vn
);
4330 tcg_temp_free_i32(tcg_vm
);
4333 tcg_temp_free_ptr(fpst
);
4335 gen_set_nzcv(tcg_flags
);
4337 tcg_temp_free_i64(tcg_flags
);
4340 /* C3.6.22 Floating point compare
4341 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4342 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4343 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4344 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4346 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4348 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4350 mos
= extract32(insn
, 29, 3);
4351 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4352 rm
= extract32(insn
, 16, 5);
4353 op
= extract32(insn
, 14, 2);
4354 rn
= extract32(insn
, 5, 5);
4355 opc
= extract32(insn
, 3, 2);
4356 op2r
= extract32(insn
, 0, 3);
4358 if (mos
|| op
|| op2r
|| type
> 1) {
4359 unallocated_encoding(s
);
4363 if (!fp_access_check(s
)) {
4367 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4370 /* C3.6.23 Floating point conditional compare
4371 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4372 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4373 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4374 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4376 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4378 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4380 TCGLabel
*label_continue
= NULL
;
4382 mos
= extract32(insn
, 29, 3);
4383 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4384 rm
= extract32(insn
, 16, 5);
4385 cond
= extract32(insn
, 12, 4);
4386 rn
= extract32(insn
, 5, 5);
4387 op
= extract32(insn
, 4, 1);
4388 nzcv
= extract32(insn
, 0, 4);
4390 if (mos
|| type
> 1) {
4391 unallocated_encoding(s
);
4395 if (!fp_access_check(s
)) {
4399 if (cond
< 0x0e) { /* not always */
4400 TCGLabel
*label_match
= gen_new_label();
4401 label_continue
= gen_new_label();
4402 arm_gen_test_cc(cond
, label_match
);
4404 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4405 gen_set_nzcv(tcg_flags
);
4406 tcg_temp_free_i64(tcg_flags
);
4407 tcg_gen_br(label_continue
);
4408 gen_set_label(label_match
);
4411 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4414 gen_set_label(label_continue
);
4418 /* C3.6.24 Floating point conditional select
4419 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4420 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4421 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4422 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4424 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4426 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4427 TCGv_i64 t_true
, t_false
, t_zero
;
4430 mos
= extract32(insn
, 29, 3);
4431 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4432 rm
= extract32(insn
, 16, 5);
4433 cond
= extract32(insn
, 12, 4);
4434 rn
= extract32(insn
, 5, 5);
4435 rd
= extract32(insn
, 0, 5);
4437 if (mos
|| type
> 1) {
4438 unallocated_encoding(s
);
4442 if (!fp_access_check(s
)) {
4446 /* Zero extend sreg inputs to 64 bits now. */
4447 t_true
= tcg_temp_new_i64();
4448 t_false
= tcg_temp_new_i64();
4449 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4450 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4452 a64_test_cc(&c
, cond
);
4453 t_zero
= tcg_const_i64(0);
4454 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4455 tcg_temp_free_i64(t_zero
);
4456 tcg_temp_free_i64(t_false
);
4459 /* Note that sregs write back zeros to the high bits,
4460 and we've already done the zero-extension. */
4461 write_fp_dreg(s
, rd
, t_true
);
4462 tcg_temp_free_i64(t_true
);
4465 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4466 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4472 fpst
= get_fpstatus_ptr();
4473 tcg_op
= read_fp_sreg(s
, rn
);
4474 tcg_res
= tcg_temp_new_i32();
4477 case 0x0: /* FMOV */
4478 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4480 case 0x1: /* FABS */
4481 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4483 case 0x2: /* FNEG */
4484 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4486 case 0x3: /* FSQRT */
4487 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4489 case 0x8: /* FRINTN */
4490 case 0x9: /* FRINTP */
4491 case 0xa: /* FRINTM */
4492 case 0xb: /* FRINTZ */
4493 case 0xc: /* FRINTA */
4495 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4497 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4498 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4500 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4501 tcg_temp_free_i32(tcg_rmode
);
4504 case 0xe: /* FRINTX */
4505 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4507 case 0xf: /* FRINTI */
4508 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4514 write_fp_sreg(s
, rd
, tcg_res
);
4516 tcg_temp_free_ptr(fpst
);
4517 tcg_temp_free_i32(tcg_op
);
4518 tcg_temp_free_i32(tcg_res
);
4521 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4522 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4528 fpst
= get_fpstatus_ptr();
4529 tcg_op
= read_fp_dreg(s
, rn
);
4530 tcg_res
= tcg_temp_new_i64();
4533 case 0x0: /* FMOV */
4534 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4536 case 0x1: /* FABS */
4537 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4539 case 0x2: /* FNEG */
4540 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4542 case 0x3: /* FSQRT */
4543 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4545 case 0x8: /* FRINTN */
4546 case 0x9: /* FRINTP */
4547 case 0xa: /* FRINTM */
4548 case 0xb: /* FRINTZ */
4549 case 0xc: /* FRINTA */
4551 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4553 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4554 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4556 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4557 tcg_temp_free_i32(tcg_rmode
);
4560 case 0xe: /* FRINTX */
4561 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4563 case 0xf: /* FRINTI */
4564 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4570 write_fp_dreg(s
, rd
, tcg_res
);
4572 tcg_temp_free_ptr(fpst
);
4573 tcg_temp_free_i64(tcg_op
);
4574 tcg_temp_free_i64(tcg_res
);
4577 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4578 int rd
, int rn
, int dtype
, int ntype
)
4583 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4585 /* Single to double */
4586 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4587 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4588 write_fp_dreg(s
, rd
, tcg_rd
);
4589 tcg_temp_free_i64(tcg_rd
);
4591 /* Single to half */
4592 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4593 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4594 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4595 write_fp_sreg(s
, rd
, tcg_rd
);
4596 tcg_temp_free_i32(tcg_rd
);
4598 tcg_temp_free_i32(tcg_rn
);
4603 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4604 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4606 /* Double to single */
4607 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4609 /* Double to half */
4610 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4611 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4613 write_fp_sreg(s
, rd
, tcg_rd
);
4614 tcg_temp_free_i32(tcg_rd
);
4615 tcg_temp_free_i64(tcg_rn
);
4620 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4621 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4623 /* Half to single */
4624 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4625 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4626 write_fp_sreg(s
, rd
, tcg_rd
);
4627 tcg_temp_free_i32(tcg_rd
);
4629 /* Half to double */
4630 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4631 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4632 write_fp_dreg(s
, rd
, tcg_rd
);
4633 tcg_temp_free_i64(tcg_rd
);
4635 tcg_temp_free_i32(tcg_rn
);
4643 /* C3.6.25 Floating point data-processing (1 source)
4644 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4645 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4646 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4647 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4649 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4651 int type
= extract32(insn
, 22, 2);
4652 int opcode
= extract32(insn
, 15, 6);
4653 int rn
= extract32(insn
, 5, 5);
4654 int rd
= extract32(insn
, 0, 5);
4657 case 0x4: case 0x5: case 0x7:
4659 /* FCVT between half, single and double precision */
4660 int dtype
= extract32(opcode
, 0, 2);
4661 if (type
== 2 || dtype
== type
) {
4662 unallocated_encoding(s
);
4665 if (!fp_access_check(s
)) {
4669 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4675 /* 32-to-32 and 64-to-64 ops */
4678 if (!fp_access_check(s
)) {
4682 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4685 if (!fp_access_check(s
)) {
4689 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4692 unallocated_encoding(s
);
4696 unallocated_encoding(s
);
4701 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4702 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4703 int rd
, int rn
, int rm
)
4710 tcg_res
= tcg_temp_new_i32();
4711 fpst
= get_fpstatus_ptr();
4712 tcg_op1
= read_fp_sreg(s
, rn
);
4713 tcg_op2
= read_fp_sreg(s
, rm
);
4716 case 0x0: /* FMUL */
4717 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4719 case 0x1: /* FDIV */
4720 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4722 case 0x2: /* FADD */
4723 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4725 case 0x3: /* FSUB */
4726 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4728 case 0x4: /* FMAX */
4729 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4731 case 0x5: /* FMIN */
4732 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4734 case 0x6: /* FMAXNM */
4735 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4737 case 0x7: /* FMINNM */
4738 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4740 case 0x8: /* FNMUL */
4741 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4742 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4746 write_fp_sreg(s
, rd
, tcg_res
);
4748 tcg_temp_free_ptr(fpst
);
4749 tcg_temp_free_i32(tcg_op1
);
4750 tcg_temp_free_i32(tcg_op2
);
4751 tcg_temp_free_i32(tcg_res
);
4754 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4755 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4756 int rd
, int rn
, int rm
)
4763 tcg_res
= tcg_temp_new_i64();
4764 fpst
= get_fpstatus_ptr();
4765 tcg_op1
= read_fp_dreg(s
, rn
);
4766 tcg_op2
= read_fp_dreg(s
, rm
);
4769 case 0x0: /* FMUL */
4770 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4772 case 0x1: /* FDIV */
4773 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4775 case 0x2: /* FADD */
4776 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4778 case 0x3: /* FSUB */
4779 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4781 case 0x4: /* FMAX */
4782 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4784 case 0x5: /* FMIN */
4785 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4787 case 0x6: /* FMAXNM */
4788 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4790 case 0x7: /* FMINNM */
4791 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4793 case 0x8: /* FNMUL */
4794 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4795 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4799 write_fp_dreg(s
, rd
, tcg_res
);
4801 tcg_temp_free_ptr(fpst
);
4802 tcg_temp_free_i64(tcg_op1
);
4803 tcg_temp_free_i64(tcg_op2
);
4804 tcg_temp_free_i64(tcg_res
);
4807 /* C3.6.26 Floating point data-processing (2 source)
4808 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4809 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4810 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4811 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4813 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4815 int type
= extract32(insn
, 22, 2);
4816 int rd
= extract32(insn
, 0, 5);
4817 int rn
= extract32(insn
, 5, 5);
4818 int rm
= extract32(insn
, 16, 5);
4819 int opcode
= extract32(insn
, 12, 4);
4822 unallocated_encoding(s
);
4828 if (!fp_access_check(s
)) {
4831 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4834 if (!fp_access_check(s
)) {
4837 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4840 unallocated_encoding(s
);
4844 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4845 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4846 int rd
, int rn
, int rm
, int ra
)
4848 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4849 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4850 TCGv_ptr fpst
= get_fpstatus_ptr();
4852 tcg_op1
= read_fp_sreg(s
, rn
);
4853 tcg_op2
= read_fp_sreg(s
, rm
);
4854 tcg_op3
= read_fp_sreg(s
, ra
);
4856 /* These are fused multiply-add, and must be done as one
4857 * floating point operation with no rounding between the
4858 * multiplication and addition steps.
4859 * NB that doing the negations here as separate steps is
4860 * correct : an input NaN should come out with its sign bit
4861 * flipped if it is a negated-input.
4864 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4868 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4871 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4873 write_fp_sreg(s
, rd
, tcg_res
);
4875 tcg_temp_free_ptr(fpst
);
4876 tcg_temp_free_i32(tcg_op1
);
4877 tcg_temp_free_i32(tcg_op2
);
4878 tcg_temp_free_i32(tcg_op3
);
4879 tcg_temp_free_i32(tcg_res
);
4882 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4883 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4884 int rd
, int rn
, int rm
, int ra
)
4886 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4887 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4888 TCGv_ptr fpst
= get_fpstatus_ptr();
4890 tcg_op1
= read_fp_dreg(s
, rn
);
4891 tcg_op2
= read_fp_dreg(s
, rm
);
4892 tcg_op3
= read_fp_dreg(s
, ra
);
4894 /* These are fused multiply-add, and must be done as one
4895 * floating point operation with no rounding between the
4896 * multiplication and addition steps.
4897 * NB that doing the negations here as separate steps is
4898 * correct : an input NaN should come out with its sign bit
4899 * flipped if it is a negated-input.
4902 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4906 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4909 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4911 write_fp_dreg(s
, rd
, tcg_res
);
4913 tcg_temp_free_ptr(fpst
);
4914 tcg_temp_free_i64(tcg_op1
);
4915 tcg_temp_free_i64(tcg_op2
);
4916 tcg_temp_free_i64(tcg_op3
);
4917 tcg_temp_free_i64(tcg_res
);
4920 /* C3.6.27 Floating point data-processing (3 source)
4921 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4922 * +---+---+---+-----------+------+----+------+----+------+------+------+
4923 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4924 * +---+---+---+-----------+------+----+------+----+------+------+------+
4926 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4928 int type
= extract32(insn
, 22, 2);
4929 int rd
= extract32(insn
, 0, 5);
4930 int rn
= extract32(insn
, 5, 5);
4931 int ra
= extract32(insn
, 10, 5);
4932 int rm
= extract32(insn
, 16, 5);
4933 bool o0
= extract32(insn
, 15, 1);
4934 bool o1
= extract32(insn
, 21, 1);
4938 if (!fp_access_check(s
)) {
4941 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4944 if (!fp_access_check(s
)) {
4947 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4950 unallocated_encoding(s
);
4954 /* C3.6.28 Floating point immediate
4955 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4956 * +---+---+---+-----------+------+---+------------+-------+------+------+
4957 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4958 * +---+---+---+-----------+------+---+------------+-------+------+------+
4960 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4962 int rd
= extract32(insn
, 0, 5);
4963 int imm8
= extract32(insn
, 13, 8);
4964 int is_double
= extract32(insn
, 22, 2);
4968 if (is_double
> 1) {
4969 unallocated_encoding(s
);
4973 if (!fp_access_check(s
)) {
4977 /* The imm8 encodes the sign bit, enough bits to represent
4978 * an exponent in the range 01....1xx to 10....0xx,
4979 * and the most significant 4 bits of the mantissa; see
4980 * VFPExpandImm() in the v8 ARM ARM.
4983 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4984 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4985 extract32(imm8
, 0, 6);
4988 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4989 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4990 (extract32(imm8
, 0, 6) << 3);
4994 tcg_res
= tcg_const_i64(imm
);
4995 write_fp_dreg(s
, rd
, tcg_res
);
4996 tcg_temp_free_i64(tcg_res
);
4999 /* Handle floating point <=> fixed point conversions. Note that we can
5000 * also deal with fp <=> integer conversions as a special case (scale == 64)
5001 * OPTME: consider handling that special case specially or at least skipping
5002 * the call to scalbn in the helpers for zero shifts.
5004 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5005 bool itof
, int rmode
, int scale
, int sf
, int type
)
5007 bool is_signed
= !(opcode
& 1);
5008 bool is_double
= type
;
5009 TCGv_ptr tcg_fpstatus
;
5012 tcg_fpstatus
= get_fpstatus_ptr();
5014 tcg_shift
= tcg_const_i32(64 - scale
);
5017 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5019 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5022 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5024 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5027 tcg_int
= tcg_extend
;
5031 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5033 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5034 tcg_shift
, tcg_fpstatus
);
5036 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5037 tcg_shift
, tcg_fpstatus
);
5039 write_fp_dreg(s
, rd
, tcg_double
);
5040 tcg_temp_free_i64(tcg_double
);
5042 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5044 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5045 tcg_shift
, tcg_fpstatus
);
5047 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5048 tcg_shift
, tcg_fpstatus
);
5050 write_fp_sreg(s
, rd
, tcg_single
);
5051 tcg_temp_free_i32(tcg_single
);
5054 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5057 if (extract32(opcode
, 2, 1)) {
5058 /* There are too many rounding modes to all fit into rmode,
5059 * so FCVTA[US] is a special case.
5061 rmode
= FPROUNDING_TIEAWAY
;
5064 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5066 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5069 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5072 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5073 tcg_shift
, tcg_fpstatus
);
5075 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5076 tcg_shift
, tcg_fpstatus
);
5080 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5081 tcg_shift
, tcg_fpstatus
);
5083 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5084 tcg_shift
, tcg_fpstatus
);
5087 tcg_temp_free_i64(tcg_double
);
5089 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5092 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5093 tcg_shift
, tcg_fpstatus
);
5095 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5096 tcg_shift
, tcg_fpstatus
);
5099 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5101 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5102 tcg_shift
, tcg_fpstatus
);
5104 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5105 tcg_shift
, tcg_fpstatus
);
5107 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5108 tcg_temp_free_i32(tcg_dest
);
5110 tcg_temp_free_i32(tcg_single
);
5113 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5114 tcg_temp_free_i32(tcg_rmode
);
5117 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5121 tcg_temp_free_ptr(tcg_fpstatus
);
5122 tcg_temp_free_i32(tcg_shift
);
5125 /* C3.6.29 Floating point <-> fixed point conversions
5126 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5127 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5128 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5129 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5131 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5133 int rd
= extract32(insn
, 0, 5);
5134 int rn
= extract32(insn
, 5, 5);
5135 int scale
= extract32(insn
, 10, 6);
5136 int opcode
= extract32(insn
, 16, 3);
5137 int rmode
= extract32(insn
, 19, 2);
5138 int type
= extract32(insn
, 22, 2);
5139 bool sbit
= extract32(insn
, 29, 1);
5140 bool sf
= extract32(insn
, 31, 1);
5143 if (sbit
|| (type
> 1)
5144 || (!sf
&& scale
< 32)) {
5145 unallocated_encoding(s
);
5149 switch ((rmode
<< 3) | opcode
) {
5150 case 0x2: /* SCVTF */
5151 case 0x3: /* UCVTF */
5154 case 0x18: /* FCVTZS */
5155 case 0x19: /* FCVTZU */
5159 unallocated_encoding(s
);
5163 if (!fp_access_check(s
)) {
5167 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5170 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5172 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5173 * without conversion.
5177 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5183 TCGv_i64 tmp
= tcg_temp_new_i64();
5184 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5185 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5186 tcg_gen_movi_i64(tmp
, 0);
5187 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5188 tcg_temp_free_i64(tmp
);
5194 TCGv_i64 tmp
= tcg_const_i64(0);
5195 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5196 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5197 tcg_temp_free_i64(tmp
);
5201 /* 64 bit to top half. */
5202 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5206 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5211 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5215 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5218 /* 64 bits from top half */
5219 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5225 /* C3.6.30 Floating point <-> integer conversions
5226 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5227 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5228 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5229 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5231 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5233 int rd
= extract32(insn
, 0, 5);
5234 int rn
= extract32(insn
, 5, 5);
5235 int opcode
= extract32(insn
, 16, 3);
5236 int rmode
= extract32(insn
, 19, 2);
5237 int type
= extract32(insn
, 22, 2);
5238 bool sbit
= extract32(insn
, 29, 1);
5239 bool sf
= extract32(insn
, 31, 1);
5242 unallocated_encoding(s
);
5248 bool itof
= opcode
& 1;
5251 unallocated_encoding(s
);
5255 switch (sf
<< 3 | type
<< 1 | rmode
) {
5256 case 0x0: /* 32 bit */
5257 case 0xa: /* 64 bit */
5258 case 0xd: /* 64 bit to top half of quad */
5261 /* all other sf/type/rmode combinations are invalid */
5262 unallocated_encoding(s
);
5266 if (!fp_access_check(s
)) {
5269 handle_fmov(s
, rd
, rn
, type
, itof
);
5271 /* actual FP conversions */
5272 bool itof
= extract32(opcode
, 1, 1);
5274 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5275 unallocated_encoding(s
);
5279 if (!fp_access_check(s
)) {
5282 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5286 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5287 * 31 30 29 28 25 24 0
5288 * +---+---+---+---------+-----------------------------+
5289 * | | 0 | | 1 1 1 1 | |
5290 * +---+---+---+---------+-----------------------------+
5292 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5294 if (extract32(insn
, 24, 1)) {
5295 /* Floating point data-processing (3 source) */
5296 disas_fp_3src(s
, insn
);
5297 } else if (extract32(insn
, 21, 1) == 0) {
5298 /* Floating point to fixed point conversions */
5299 disas_fp_fixed_conv(s
, insn
);
5301 switch (extract32(insn
, 10, 2)) {
5303 /* Floating point conditional compare */
5304 disas_fp_ccomp(s
, insn
);
5307 /* Floating point data-processing (2 source) */
5308 disas_fp_2src(s
, insn
);
5311 /* Floating point conditional select */
5312 disas_fp_csel(s
, insn
);
5315 switch (ctz32(extract32(insn
, 12, 4))) {
5316 case 0: /* [15:12] == xxx1 */
5317 /* Floating point immediate */
5318 disas_fp_imm(s
, insn
);
5320 case 1: /* [15:12] == xx10 */
5321 /* Floating point compare */
5322 disas_fp_compare(s
, insn
);
5324 case 2: /* [15:12] == x100 */
5325 /* Floating point data-processing (1 source) */
5326 disas_fp_1src(s
, insn
);
5328 case 3: /* [15:12] == 1000 */
5329 unallocated_encoding(s
);
5331 default: /* [15:12] == 0000 */
5332 /* Floating point <-> integer conversions */
5333 disas_fp_int_conv(s
, insn
);
5341 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5344 /* Extract 64 bits from the middle of two concatenated 64 bit
5345 * vector register slices left:right. The extracted bits start
5346 * at 'pos' bits into the right (least significant) side.
5347 * We return the result in tcg_right, and guarantee not to
5350 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5351 assert(pos
> 0 && pos
< 64);
5353 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5354 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5355 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5357 tcg_temp_free_i64(tcg_tmp
);
5361 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5362 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5363 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5364 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5366 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5368 int is_q
= extract32(insn
, 30, 1);
5369 int op2
= extract32(insn
, 22, 2);
5370 int imm4
= extract32(insn
, 11, 4);
5371 int rm
= extract32(insn
, 16, 5);
5372 int rn
= extract32(insn
, 5, 5);
5373 int rd
= extract32(insn
, 0, 5);
5374 int pos
= imm4
<< 3;
5375 TCGv_i64 tcg_resl
, tcg_resh
;
5377 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5378 unallocated_encoding(s
);
5382 if (!fp_access_check(s
)) {
5386 tcg_resh
= tcg_temp_new_i64();
5387 tcg_resl
= tcg_temp_new_i64();
5389 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5390 * either extracting 128 bits from a 128:128 concatenation, or
5391 * extracting 64 bits from a 64:64 concatenation.
5394 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5396 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5397 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5399 tcg_gen_movi_i64(tcg_resh
, 0);
5406 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5407 EltPosns
*elt
= eltposns
;
5414 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5416 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5419 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5420 tcg_hh
= tcg_temp_new_i64();
5421 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5422 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5423 tcg_temp_free_i64(tcg_hh
);
5427 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5428 tcg_temp_free_i64(tcg_resl
);
5429 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5430 tcg_temp_free_i64(tcg_resh
);
5434 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5435 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5436 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5437 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5439 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5441 int op2
= extract32(insn
, 22, 2);
5442 int is_q
= extract32(insn
, 30, 1);
5443 int rm
= extract32(insn
, 16, 5);
5444 int rn
= extract32(insn
, 5, 5);
5445 int rd
= extract32(insn
, 0, 5);
5446 int is_tblx
= extract32(insn
, 12, 1);
5447 int len
= extract32(insn
, 13, 2);
5448 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5449 TCGv_i32 tcg_regno
, tcg_numregs
;
5452 unallocated_encoding(s
);
5456 if (!fp_access_check(s
)) {
5460 /* This does a table lookup: for every byte element in the input
5461 * we index into a table formed from up to four vector registers,
5462 * and then the output is the result of the lookups. Our helper
5463 * function does the lookup operation for a single 64 bit part of
5466 tcg_resl
= tcg_temp_new_i64();
5467 tcg_resh
= tcg_temp_new_i64();
5470 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5472 tcg_gen_movi_i64(tcg_resl
, 0);
5474 if (is_tblx
&& is_q
) {
5475 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5477 tcg_gen_movi_i64(tcg_resh
, 0);
5480 tcg_idx
= tcg_temp_new_i64();
5481 tcg_regno
= tcg_const_i32(rn
);
5482 tcg_numregs
= tcg_const_i32(len
+ 1);
5483 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5484 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5485 tcg_regno
, tcg_numregs
);
5487 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5488 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5489 tcg_regno
, tcg_numregs
);
5491 tcg_temp_free_i64(tcg_idx
);
5492 tcg_temp_free_i32(tcg_regno
);
5493 tcg_temp_free_i32(tcg_numregs
);
5495 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5496 tcg_temp_free_i64(tcg_resl
);
5497 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5498 tcg_temp_free_i64(tcg_resh
);
5501 /* C3.6.3 ZIP/UZP/TRN
5502 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5503 * +---+---+-------------+------+---+------+---+------------------+------+
5504 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5505 * +---+---+-------------+------+---+------+---+------------------+------+
5507 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5509 int rd
= extract32(insn
, 0, 5);
5510 int rn
= extract32(insn
, 5, 5);
5511 int rm
= extract32(insn
, 16, 5);
5512 int size
= extract32(insn
, 22, 2);
5513 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5514 * bit 2 indicates 1 vs 2 variant of the insn.
5516 int opcode
= extract32(insn
, 12, 2);
5517 bool part
= extract32(insn
, 14, 1);
5518 bool is_q
= extract32(insn
, 30, 1);
5519 int esize
= 8 << size
;
5521 int datasize
= is_q
? 128 : 64;
5522 int elements
= datasize
/ esize
;
5523 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5525 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5526 unallocated_encoding(s
);
5530 if (!fp_access_check(s
)) {
5534 tcg_resl
= tcg_const_i64(0);
5535 tcg_resh
= tcg_const_i64(0);
5536 tcg_res
= tcg_temp_new_i64();
5538 for (i
= 0; i
< elements
; i
++) {
5540 case 1: /* UZP1/2 */
5542 int midpoint
= elements
/ 2;
5544 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5546 read_vec_element(s
, tcg_res
, rm
,
5547 2 * (i
- midpoint
) + part
, size
);
5551 case 2: /* TRN1/2 */
5553 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5555 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5558 case 3: /* ZIP1/2 */
5560 int base
= part
* elements
/ 2;
5562 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5564 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5569 g_assert_not_reached();
5574 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5575 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5577 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5578 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5582 tcg_temp_free_i64(tcg_res
);
5584 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5585 tcg_temp_free_i64(tcg_resl
);
5586 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5587 tcg_temp_free_i64(tcg_resh
);
5590 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5591 int opc
, bool is_min
, TCGv_ptr fpst
)
5593 /* Helper function for disas_simd_across_lanes: do a single precision
5594 * min/max operation on the specified two inputs,
5595 * and return the result in tcg_elt1.
5599 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5601 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5606 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5608 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5613 /* C3.6.4 AdvSIMD across lanes
5614 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5615 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5616 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5617 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5619 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5621 int rd
= extract32(insn
, 0, 5);
5622 int rn
= extract32(insn
, 5, 5);
5623 int size
= extract32(insn
, 22, 2);
5624 int opcode
= extract32(insn
, 12, 5);
5625 bool is_q
= extract32(insn
, 30, 1);
5626 bool is_u
= extract32(insn
, 29, 1);
5628 bool is_min
= false;
5632 TCGv_i64 tcg_res
, tcg_elt
;
5635 case 0x1b: /* ADDV */
5637 unallocated_encoding(s
);
5641 case 0x3: /* SADDLV, UADDLV */
5642 case 0xa: /* SMAXV, UMAXV */
5643 case 0x1a: /* SMINV, UMINV */
5644 if (size
== 3 || (size
== 2 && !is_q
)) {
5645 unallocated_encoding(s
);
5649 case 0xc: /* FMAXNMV, FMINNMV */
5650 case 0xf: /* FMAXV, FMINV */
5651 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5652 unallocated_encoding(s
);
5655 /* Bit 1 of size field encodes min vs max, and actual size is always
5656 * 32 bits: adjust the size variable so following code can rely on it
5658 is_min
= extract32(size
, 1, 1);
5663 unallocated_encoding(s
);
5667 if (!fp_access_check(s
)) {
5672 elements
= (is_q
? 128 : 64) / esize
;
5674 tcg_res
= tcg_temp_new_i64();
5675 tcg_elt
= tcg_temp_new_i64();
5677 /* These instructions operate across all lanes of a vector
5678 * to produce a single result. We can guarantee that a 64
5679 * bit intermediate is sufficient:
5680 * + for [US]ADDLV the maximum element size is 32 bits, and
5681 * the result type is 64 bits
5682 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5683 * same as the element size, which is 32 bits at most
5684 * For the integer operations we can choose to work at 64
5685 * or 32 bits and truncate at the end; for simplicity
5686 * we use 64 bits always. The floating point
5687 * ops do require 32 bit intermediates, though.
5690 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5692 for (i
= 1; i
< elements
; i
++) {
5693 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5696 case 0x03: /* SADDLV / UADDLV */
5697 case 0x1b: /* ADDV */
5698 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5700 case 0x0a: /* SMAXV / UMAXV */
5701 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5703 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5705 case 0x1a: /* SMINV / UMINV */
5706 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5708 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5712 g_assert_not_reached();
5717 /* Floating point ops which work on 32 bit (single) intermediates.
5718 * Note that correct NaN propagation requires that we do these
5719 * operations in exactly the order specified by the pseudocode.
5721 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5722 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5723 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5724 TCGv_ptr fpst
= get_fpstatus_ptr();
5726 assert(esize
== 32);
5727 assert(elements
== 4);
5729 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5730 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5731 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5732 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5734 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5736 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5737 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5738 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5739 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5741 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5743 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5745 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5746 tcg_temp_free_i32(tcg_elt1
);
5747 tcg_temp_free_i32(tcg_elt2
);
5748 tcg_temp_free_i32(tcg_elt3
);
5749 tcg_temp_free_ptr(fpst
);
5752 tcg_temp_free_i64(tcg_elt
);
5754 /* Now truncate the result to the width required for the final output */
5755 if (opcode
== 0x03) {
5756 /* SADDLV, UADDLV: result is 2*esize */
5762 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5765 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5768 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5773 g_assert_not_reached();
5776 write_fp_dreg(s
, rd
, tcg_res
);
5777 tcg_temp_free_i64(tcg_res
);
5780 /* C6.3.31 DUP (Element, Vector)
5782 * 31 30 29 21 20 16 15 10 9 5 4 0
5783 * +---+---+-------------------+--------+-------------+------+------+
5784 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5785 * +---+---+-------------------+--------+-------------+------+------+
5787 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5789 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5792 int size
= ctz32(imm5
);
5793 int esize
= 8 << size
;
5794 int elements
= (is_q
? 128 : 64) / esize
;
5798 if (size
> 3 || (size
== 3 && !is_q
)) {
5799 unallocated_encoding(s
);
5803 if (!fp_access_check(s
)) {
5807 index
= imm5
>> (size
+ 1);
5809 tmp
= tcg_temp_new_i64();
5810 read_vec_element(s
, tmp
, rn
, index
, size
);
5812 for (i
= 0; i
< elements
; i
++) {
5813 write_vec_element(s
, tmp
, rd
, i
, size
);
5817 clear_vec_high(s
, rd
);
5820 tcg_temp_free_i64(tmp
);
5823 /* C6.3.31 DUP (element, scalar)
5824 * 31 21 20 16 15 10 9 5 4 0
5825 * +-----------------------+--------+-------------+------+------+
5826 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5827 * +-----------------------+--------+-------------+------+------+
5829 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5832 int size
= ctz32(imm5
);
5837 unallocated_encoding(s
);
5841 if (!fp_access_check(s
)) {
5845 index
= imm5
>> (size
+ 1);
5847 /* This instruction just extracts the specified element and
5848 * zero-extends it into the bottom of the destination register.
5850 tmp
= tcg_temp_new_i64();
5851 read_vec_element(s
, tmp
, rn
, index
, size
);
5852 write_fp_dreg(s
, rd
, tmp
);
5853 tcg_temp_free_i64(tmp
);
5856 /* C6.3.32 DUP (General)
5858 * 31 30 29 21 20 16 15 10 9 5 4 0
5859 * +---+---+-------------------+--------+-------------+------+------+
5860 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5861 * +---+---+-------------------+--------+-------------+------+------+
5863 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5865 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5868 int size
= ctz32(imm5
);
5869 int esize
= 8 << size
;
5870 int elements
= (is_q
? 128 : 64)/esize
;
5873 if (size
> 3 || ((size
== 3) && !is_q
)) {
5874 unallocated_encoding(s
);
5878 if (!fp_access_check(s
)) {
5882 for (i
= 0; i
< elements
; i
++) {
5883 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5886 clear_vec_high(s
, rd
);
5890 /* C6.3.150 INS (Element)
5892 * 31 21 20 16 15 14 11 10 9 5 4 0
5893 * +-----------------------+--------+------------+---+------+------+
5894 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5895 * +-----------------------+--------+------------+---+------+------+
5897 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5898 * index: encoded in imm5<4:size+1>
5900 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5903 int size
= ctz32(imm5
);
5904 int src_index
, dst_index
;
5908 unallocated_encoding(s
);
5912 if (!fp_access_check(s
)) {
5916 dst_index
= extract32(imm5
, 1+size
, 5);
5917 src_index
= extract32(imm4
, size
, 4);
5919 tmp
= tcg_temp_new_i64();
5921 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5922 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5924 tcg_temp_free_i64(tmp
);
5928 /* C6.3.151 INS (General)
5930 * 31 21 20 16 15 10 9 5 4 0
5931 * +-----------------------+--------+-------------+------+------+
5932 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5933 * +-----------------------+--------+-------------+------+------+
5935 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5936 * index: encoded in imm5<4:size+1>
5938 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5940 int size
= ctz32(imm5
);
5944 unallocated_encoding(s
);
5948 if (!fp_access_check(s
)) {
5952 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5953 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5957 * C6.3.321 UMOV (General)
5958 * C6.3.237 SMOV (General)
5960 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5961 * +---+---+-------------------+--------+-------------+------+------+
5962 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5963 * +---+---+-------------------+--------+-------------+------+------+
5965 * U: unsigned when set
5966 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5968 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5969 int rn
, int rd
, int imm5
)
5971 int size
= ctz32(imm5
);
5975 /* Check for UnallocatedEncodings */
5977 if (size
> 2 || (size
== 2 && !is_q
)) {
5978 unallocated_encoding(s
);
5983 || (size
< 3 && is_q
)
5984 || (size
== 3 && !is_q
)) {
5985 unallocated_encoding(s
);
5990 if (!fp_access_check(s
)) {
5994 element
= extract32(imm5
, 1+size
, 4);
5996 tcg_rd
= cpu_reg(s
, rd
);
5997 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5998 if (is_signed
&& !is_q
) {
5999 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6003 /* C3.6.5 AdvSIMD copy
6004 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6005 * +---+---+----+-----------------+------+---+------+---+------+------+
6006 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6007 * +---+---+----+-----------------+------+---+------+---+------+------+
6009 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6011 int rd
= extract32(insn
, 0, 5);
6012 int rn
= extract32(insn
, 5, 5);
6013 int imm4
= extract32(insn
, 11, 4);
6014 int op
= extract32(insn
, 29, 1);
6015 int is_q
= extract32(insn
, 30, 1);
6016 int imm5
= extract32(insn
, 16, 5);
6021 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6023 unallocated_encoding(s
);
6028 /* DUP (element - vector) */
6029 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6033 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6038 handle_simd_insg(s
, rd
, rn
, imm5
);
6040 unallocated_encoding(s
);
6045 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6046 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6049 unallocated_encoding(s
);
6055 /* C3.6.6 AdvSIMD modified immediate
6056 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6057 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6058 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6059 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6061 * There are a number of operations that can be carried out here:
6062 * MOVI - move (shifted) imm into register
6063 * MVNI - move inverted (shifted) imm into register
6064 * ORR - bitwise OR of (shifted) imm with register
6065 * BIC - bitwise clear of (shifted) imm with register
6067 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6069 int rd
= extract32(insn
, 0, 5);
6070 int cmode
= extract32(insn
, 12, 4);
6071 int cmode_3_1
= extract32(cmode
, 1, 3);
6072 int cmode_0
= extract32(cmode
, 0, 1);
6073 int o2
= extract32(insn
, 11, 1);
6074 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6075 bool is_neg
= extract32(insn
, 29, 1);
6076 bool is_q
= extract32(insn
, 30, 1);
6078 TCGv_i64 tcg_rd
, tcg_imm
;
6081 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6082 unallocated_encoding(s
);
6086 if (!fp_access_check(s
)) {
6090 /* See AdvSIMDExpandImm() in ARM ARM */
6091 switch (cmode_3_1
) {
6092 case 0: /* Replicate(Zeros(24):imm8, 2) */
6093 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6094 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6095 case 3: /* Replicate(imm8:Zeros(24), 2) */
6097 int shift
= cmode_3_1
* 8;
6098 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6101 case 4: /* Replicate(Zeros(8):imm8, 4) */
6102 case 5: /* Replicate(imm8:Zeros(8), 4) */
6104 int shift
= (cmode_3_1
& 0x1) * 8;
6105 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6110 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6111 imm
= (abcdefgh
<< 16) | 0xffff;
6113 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6114 imm
= (abcdefgh
<< 8) | 0xff;
6116 imm
= bitfield_replicate(imm
, 32);
6119 if (!cmode_0
&& !is_neg
) {
6120 imm
= bitfield_replicate(abcdefgh
, 8);
6121 } else if (!cmode_0
&& is_neg
) {
6124 for (i
= 0; i
< 8; i
++) {
6125 if ((abcdefgh
) & (1 << i
)) {
6126 imm
|= 0xffULL
<< (i
* 8);
6129 } else if (cmode_0
) {
6131 imm
= (abcdefgh
& 0x3f) << 48;
6132 if (abcdefgh
& 0x80) {
6133 imm
|= 0x8000000000000000ULL
;
6135 if (abcdefgh
& 0x40) {
6136 imm
|= 0x3fc0000000000000ULL
;
6138 imm
|= 0x4000000000000000ULL
;
6141 imm
= (abcdefgh
& 0x3f) << 19;
6142 if (abcdefgh
& 0x80) {
6145 if (abcdefgh
& 0x40) {
6156 if (cmode_3_1
!= 7 && is_neg
) {
6160 tcg_imm
= tcg_const_i64(imm
);
6161 tcg_rd
= new_tmp_a64(s
);
6163 for (i
= 0; i
< 2; i
++) {
6164 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6166 if (i
== 1 && !is_q
) {
6167 /* non-quad ops clear high half of vector */
6168 tcg_gen_movi_i64(tcg_rd
, 0);
6169 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6170 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6173 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6176 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6180 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6182 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6185 tcg_temp_free_i64(tcg_imm
);
6188 /* C3.6.7 AdvSIMD scalar copy
6189 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6190 * +-----+----+-----------------+------+---+------+---+------+------+
6191 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6192 * +-----+----+-----------------+------+---+------+---+------+------+
6194 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6196 int rd
= extract32(insn
, 0, 5);
6197 int rn
= extract32(insn
, 5, 5);
6198 int imm4
= extract32(insn
, 11, 4);
6199 int imm5
= extract32(insn
, 16, 5);
6200 int op
= extract32(insn
, 29, 1);
6202 if (op
!= 0 || imm4
!= 0) {
6203 unallocated_encoding(s
);
6207 /* DUP (element, scalar) */
6208 handle_simd_dupes(s
, rd
, rn
, imm5
);
6211 /* C3.6.8 AdvSIMD scalar pairwise
6212 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6213 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6214 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6215 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6217 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6219 int u
= extract32(insn
, 29, 1);
6220 int size
= extract32(insn
, 22, 2);
6221 int opcode
= extract32(insn
, 12, 5);
6222 int rn
= extract32(insn
, 5, 5);
6223 int rd
= extract32(insn
, 0, 5);
6226 /* For some ops (the FP ones), size[1] is part of the encoding.
6227 * For ADDP strictly it is not but size[1] is always 1 for valid
6230 opcode
|= (extract32(size
, 1, 1) << 5);
6233 case 0x3b: /* ADDP */
6234 if (u
|| size
!= 3) {
6235 unallocated_encoding(s
);
6238 if (!fp_access_check(s
)) {
6242 TCGV_UNUSED_PTR(fpst
);
6244 case 0xc: /* FMAXNMP */
6245 case 0xd: /* FADDP */
6246 case 0xf: /* FMAXP */
6247 case 0x2c: /* FMINNMP */
6248 case 0x2f: /* FMINP */
6249 /* FP op, size[0] is 32 or 64 bit */
6251 unallocated_encoding(s
);
6254 if (!fp_access_check(s
)) {
6258 size
= extract32(size
, 0, 1) ? 3 : 2;
6259 fpst
= get_fpstatus_ptr();
6262 unallocated_encoding(s
);
6267 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6268 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6269 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6271 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6272 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6275 case 0x3b: /* ADDP */
6276 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6278 case 0xc: /* FMAXNMP */
6279 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6281 case 0xd: /* FADDP */
6282 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6284 case 0xf: /* FMAXP */
6285 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6287 case 0x2c: /* FMINNMP */
6288 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6290 case 0x2f: /* FMINP */
6291 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6294 g_assert_not_reached();
6297 write_fp_dreg(s
, rd
, tcg_res
);
6299 tcg_temp_free_i64(tcg_op1
);
6300 tcg_temp_free_i64(tcg_op2
);
6301 tcg_temp_free_i64(tcg_res
);
6303 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6304 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6305 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6307 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6308 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6311 case 0xc: /* FMAXNMP */
6312 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6314 case 0xd: /* FADDP */
6315 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6317 case 0xf: /* FMAXP */
6318 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6320 case 0x2c: /* FMINNMP */
6321 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6323 case 0x2f: /* FMINP */
6324 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6327 g_assert_not_reached();
6330 write_fp_sreg(s
, rd
, tcg_res
);
6332 tcg_temp_free_i32(tcg_op1
);
6333 tcg_temp_free_i32(tcg_op2
);
6334 tcg_temp_free_i32(tcg_res
);
6337 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6338 tcg_temp_free_ptr(fpst
);
6343 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6345 * This code is handles the common shifting code and is used by both
6346 * the vector and scalar code.
6348 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6349 TCGv_i64 tcg_rnd
, bool accumulate
,
6350 bool is_u
, int size
, int shift
)
6352 bool extended_result
= false;
6353 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6355 TCGv_i64 tcg_src_hi
;
6357 if (round
&& size
== 3) {
6358 extended_result
= true;
6359 ext_lshift
= 64 - shift
;
6360 tcg_src_hi
= tcg_temp_new_i64();
6361 } else if (shift
== 64) {
6362 if (!accumulate
&& is_u
) {
6363 /* result is zero */
6364 tcg_gen_movi_i64(tcg_res
, 0);
6369 /* Deal with the rounding step */
6371 if (extended_result
) {
6372 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6374 /* take care of sign extending tcg_res */
6375 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6376 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6377 tcg_src
, tcg_src_hi
,
6380 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6384 tcg_temp_free_i64(tcg_zero
);
6386 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6390 /* Now do the shift right */
6391 if (round
&& extended_result
) {
6392 /* extended case, >64 bit precision required */
6393 if (ext_lshift
== 0) {
6394 /* special case, only high bits matter */
6395 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6397 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6398 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6399 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6404 /* essentially shifting in 64 zeros */
6405 tcg_gen_movi_i64(tcg_src
, 0);
6407 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6411 /* effectively extending the sign-bit */
6412 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6414 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6420 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6422 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6425 if (extended_result
) {
6426 tcg_temp_free_i64(tcg_src_hi
);
6430 /* Common SHL/SLI - Shift left with an optional insert */
6431 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6432 bool insert
, int shift
)
6434 if (insert
) { /* SLI */
6435 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6437 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6441 /* SRI: shift right with insert */
6442 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6443 int size
, int shift
)
6445 int esize
= 8 << size
;
6447 /* shift count same as element size is valid but does nothing;
6448 * special case to avoid potential shift by 64.
6450 if (shift
!= esize
) {
6451 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6452 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6456 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6457 static void handle_scalar_simd_shri(DisasContext
*s
,
6458 bool is_u
, int immh
, int immb
,
6459 int opcode
, int rn
, int rd
)
6462 int immhb
= immh
<< 3 | immb
;
6463 int shift
= 2 * (8 << size
) - immhb
;
6464 bool accumulate
= false;
6466 bool insert
= false;
6471 if (!extract32(immh
, 3, 1)) {
6472 unallocated_encoding(s
);
6476 if (!fp_access_check(s
)) {
6481 case 0x02: /* SSRA / USRA (accumulate) */
6484 case 0x04: /* SRSHR / URSHR (rounding) */
6487 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6488 accumulate
= round
= true;
6490 case 0x08: /* SRI */
6496 uint64_t round_const
= 1ULL << (shift
- 1);
6497 tcg_round
= tcg_const_i64(round_const
);
6499 TCGV_UNUSED_I64(tcg_round
);
6502 tcg_rn
= read_fp_dreg(s
, rn
);
6503 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6506 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6508 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6509 accumulate
, is_u
, size
, shift
);
6512 write_fp_dreg(s
, rd
, tcg_rd
);
6514 tcg_temp_free_i64(tcg_rn
);
6515 tcg_temp_free_i64(tcg_rd
);
6517 tcg_temp_free_i64(tcg_round
);
6521 /* SHL/SLI - Scalar shift left */
6522 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6523 int immh
, int immb
, int opcode
,
6526 int size
= 32 - clz32(immh
) - 1;
6527 int immhb
= immh
<< 3 | immb
;
6528 int shift
= immhb
- (8 << size
);
6529 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6530 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6532 if (!extract32(immh
, 3, 1)) {
6533 unallocated_encoding(s
);
6537 if (!fp_access_check(s
)) {
6541 tcg_rn
= read_fp_dreg(s
, rn
);
6542 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6544 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6546 write_fp_dreg(s
, rd
, tcg_rd
);
6548 tcg_temp_free_i64(tcg_rn
);
6549 tcg_temp_free_i64(tcg_rd
);
6552 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6553 * (signed/unsigned) narrowing */
6554 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6555 bool is_u_shift
, bool is_u_narrow
,
6556 int immh
, int immb
, int opcode
,
6559 int immhb
= immh
<< 3 | immb
;
6560 int size
= 32 - clz32(immh
) - 1;
6561 int esize
= 8 << size
;
6562 int shift
= (2 * esize
) - immhb
;
6563 int elements
= is_scalar
? 1 : (64 / esize
);
6564 bool round
= extract32(opcode
, 0, 1);
6565 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6566 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6567 TCGv_i32 tcg_rd_narrowed
;
6570 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6571 { gen_helper_neon_narrow_sat_s8
,
6572 gen_helper_neon_unarrow_sat8
},
6573 { gen_helper_neon_narrow_sat_s16
,
6574 gen_helper_neon_unarrow_sat16
},
6575 { gen_helper_neon_narrow_sat_s32
,
6576 gen_helper_neon_unarrow_sat32
},
6579 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6580 gen_helper_neon_narrow_sat_u8
,
6581 gen_helper_neon_narrow_sat_u16
,
6582 gen_helper_neon_narrow_sat_u32
,
6585 NeonGenNarrowEnvFn
*narrowfn
;
6591 if (extract32(immh
, 3, 1)) {
6592 unallocated_encoding(s
);
6596 if (!fp_access_check(s
)) {
6601 narrowfn
= unsigned_narrow_fns
[size
];
6603 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6606 tcg_rn
= tcg_temp_new_i64();
6607 tcg_rd
= tcg_temp_new_i64();
6608 tcg_rd_narrowed
= tcg_temp_new_i32();
6609 tcg_final
= tcg_const_i64(0);
6612 uint64_t round_const
= 1ULL << (shift
- 1);
6613 tcg_round
= tcg_const_i64(round_const
);
6615 TCGV_UNUSED_I64(tcg_round
);
6618 for (i
= 0; i
< elements
; i
++) {
6619 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6620 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6621 false, is_u_shift
, size
+1, shift
);
6622 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6623 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6624 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6628 clear_vec_high(s
, rd
);
6629 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6631 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6635 tcg_temp_free_i64(tcg_round
);
6637 tcg_temp_free_i64(tcg_rn
);
6638 tcg_temp_free_i64(tcg_rd
);
6639 tcg_temp_free_i32(tcg_rd_narrowed
);
6640 tcg_temp_free_i64(tcg_final
);
6644 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6645 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6646 bool src_unsigned
, bool dst_unsigned
,
6647 int immh
, int immb
, int rn
, int rd
)
6649 int immhb
= immh
<< 3 | immb
;
6650 int size
= 32 - clz32(immh
) - 1;
6651 int shift
= immhb
- (8 << size
);
6655 assert(!(scalar
&& is_q
));
6658 if (!is_q
&& extract32(immh
, 3, 1)) {
6659 unallocated_encoding(s
);
6663 /* Since we use the variable-shift helpers we must
6664 * replicate the shift count into each element of
6665 * the tcg_shift value.
6669 shift
|= shift
<< 8;
6672 shift
|= shift
<< 16;
6678 g_assert_not_reached();
6682 if (!fp_access_check(s
)) {
6687 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6688 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6689 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6690 { NULL
, gen_helper_neon_qshl_u64
},
6692 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6693 int maxpass
= is_q
? 2 : 1;
6695 for (pass
= 0; pass
< maxpass
; pass
++) {
6696 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6698 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6699 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6700 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6702 tcg_temp_free_i64(tcg_op
);
6704 tcg_temp_free_i64(tcg_shift
);
6707 clear_vec_high(s
, rd
);
6710 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6711 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6713 { gen_helper_neon_qshl_s8
,
6714 gen_helper_neon_qshl_s16
,
6715 gen_helper_neon_qshl_s32
},
6716 { gen_helper_neon_qshlu_s8
,
6717 gen_helper_neon_qshlu_s16
,
6718 gen_helper_neon_qshlu_s32
}
6720 { NULL
, NULL
, NULL
},
6721 { gen_helper_neon_qshl_u8
,
6722 gen_helper_neon_qshl_u16
,
6723 gen_helper_neon_qshl_u32
}
6726 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6727 TCGMemOp memop
= scalar
? size
: MO_32
;
6728 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6730 for (pass
= 0; pass
< maxpass
; pass
++) {
6731 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6733 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6734 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6738 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6741 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6746 g_assert_not_reached();
6748 write_fp_sreg(s
, rd
, tcg_op
);
6750 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6753 tcg_temp_free_i32(tcg_op
);
6755 tcg_temp_free_i32(tcg_shift
);
6757 if (!is_q
&& !scalar
) {
6758 clear_vec_high(s
, rd
);
6763 /* Common vector code for handling integer to FP conversion */
6764 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6765 int elements
, int is_signed
,
6766 int fracbits
, int size
)
6768 bool is_double
= size
== 3 ? true : false;
6769 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6770 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6771 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6772 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6775 for (pass
= 0; pass
< elements
; pass
++) {
6776 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6779 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6781 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6782 tcg_shift
, tcg_fpst
);
6784 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6785 tcg_shift
, tcg_fpst
);
6787 if (elements
== 1) {
6788 write_fp_dreg(s
, rd
, tcg_double
);
6790 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6792 tcg_temp_free_i64(tcg_double
);
6794 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6796 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6797 tcg_shift
, tcg_fpst
);
6799 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6800 tcg_shift
, tcg_fpst
);
6802 if (elements
== 1) {
6803 write_fp_sreg(s
, rd
, tcg_single
);
6805 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6807 tcg_temp_free_i32(tcg_single
);
6811 if (!is_double
&& elements
== 2) {
6812 clear_vec_high(s
, rd
);
6815 tcg_temp_free_i64(tcg_int
);
6816 tcg_temp_free_ptr(tcg_fpst
);
6817 tcg_temp_free_i32(tcg_shift
);
6820 /* UCVTF/SCVTF - Integer to FP conversion */
6821 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6822 bool is_q
, bool is_u
,
6823 int immh
, int immb
, int opcode
,
6826 bool is_double
= extract32(immh
, 3, 1);
6827 int size
= is_double
? MO_64
: MO_32
;
6829 int immhb
= immh
<< 3 | immb
;
6830 int fracbits
= (is_double
? 128 : 64) - immhb
;
6832 if (!extract32(immh
, 2, 2)) {
6833 unallocated_encoding(s
);
6840 elements
= is_double
? 2 : is_q
? 4 : 2;
6841 if (is_double
&& !is_q
) {
6842 unallocated_encoding(s
);
6847 if (!fp_access_check(s
)) {
6851 /* immh == 0 would be a failure of the decode logic */
6854 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6857 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6858 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6859 bool is_q
, bool is_u
,
6860 int immh
, int immb
, int rn
, int rd
)
6862 bool is_double
= extract32(immh
, 3, 1);
6863 int immhb
= immh
<< 3 | immb
;
6864 int fracbits
= (is_double
? 128 : 64) - immhb
;
6866 TCGv_ptr tcg_fpstatus
;
6867 TCGv_i32 tcg_rmode
, tcg_shift
;
6869 if (!extract32(immh
, 2, 2)) {
6870 unallocated_encoding(s
);
6874 if (!is_scalar
&& !is_q
&& is_double
) {
6875 unallocated_encoding(s
);
6879 if (!fp_access_check(s
)) {
6883 assert(!(is_scalar
&& is_q
));
6885 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6886 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6887 tcg_fpstatus
= get_fpstatus_ptr();
6888 tcg_shift
= tcg_const_i32(fracbits
);
6891 int maxpass
= is_scalar
? 1 : 2;
6893 for (pass
= 0; pass
< maxpass
; pass
++) {
6894 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6896 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6898 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6900 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6902 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6903 tcg_temp_free_i64(tcg_op
);
6906 clear_vec_high(s
, rd
);
6909 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6910 for (pass
= 0; pass
< maxpass
; pass
++) {
6911 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6913 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6915 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6917 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6920 write_fp_sreg(s
, rd
, tcg_op
);
6922 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6924 tcg_temp_free_i32(tcg_op
);
6926 if (!is_q
&& !is_scalar
) {
6927 clear_vec_high(s
, rd
);
6931 tcg_temp_free_ptr(tcg_fpstatus
);
6932 tcg_temp_free_i32(tcg_shift
);
6933 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6934 tcg_temp_free_i32(tcg_rmode
);
6937 /* C3.6.9 AdvSIMD scalar shift by immediate
6938 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6939 * +-----+---+-------------+------+------+--------+---+------+------+
6940 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6941 * +-----+---+-------------+------+------+--------+---+------+------+
6943 * This is the scalar version so it works on a fixed sized registers
6945 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6947 int rd
= extract32(insn
, 0, 5);
6948 int rn
= extract32(insn
, 5, 5);
6949 int opcode
= extract32(insn
, 11, 5);
6950 int immb
= extract32(insn
, 16, 3);
6951 int immh
= extract32(insn
, 19, 4);
6952 bool is_u
= extract32(insn
, 29, 1);
6955 unallocated_encoding(s
);
6960 case 0x08: /* SRI */
6962 unallocated_encoding(s
);
6966 case 0x00: /* SSHR / USHR */
6967 case 0x02: /* SSRA / USRA */
6968 case 0x04: /* SRSHR / URSHR */
6969 case 0x06: /* SRSRA / URSRA */
6970 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6972 case 0x0a: /* SHL / SLI */
6973 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6975 case 0x1c: /* SCVTF, UCVTF */
6976 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6979 case 0x10: /* SQSHRUN, SQSHRUN2 */
6980 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6982 unallocated_encoding(s
);
6985 handle_vec_simd_sqshrn(s
, true, false, false, true,
6986 immh
, immb
, opcode
, rn
, rd
);
6988 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6989 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6990 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6991 immh
, immb
, opcode
, rn
, rd
);
6993 case 0xc: /* SQSHLU */
6995 unallocated_encoding(s
);
6998 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7000 case 0xe: /* SQSHL, UQSHL */
7001 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7003 case 0x1f: /* FCVTZS, FCVTZU */
7004 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7007 unallocated_encoding(s
);
7012 /* C3.6.10 AdvSIMD scalar three different
7013 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7014 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7015 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7016 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7018 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7020 bool is_u
= extract32(insn
, 29, 1);
7021 int size
= extract32(insn
, 22, 2);
7022 int opcode
= extract32(insn
, 12, 4);
7023 int rm
= extract32(insn
, 16, 5);
7024 int rn
= extract32(insn
, 5, 5);
7025 int rd
= extract32(insn
, 0, 5);
7028 unallocated_encoding(s
);
7033 case 0x9: /* SQDMLAL, SQDMLAL2 */
7034 case 0xb: /* SQDMLSL, SQDMLSL2 */
7035 case 0xd: /* SQDMULL, SQDMULL2 */
7036 if (size
== 0 || size
== 3) {
7037 unallocated_encoding(s
);
7042 unallocated_encoding(s
);
7046 if (!fp_access_check(s
)) {
7051 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7052 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7053 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7055 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7056 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7058 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7059 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7062 case 0xd: /* SQDMULL, SQDMULL2 */
7064 case 0xb: /* SQDMLSL, SQDMLSL2 */
7065 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7067 case 0x9: /* SQDMLAL, SQDMLAL2 */
7068 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7069 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7073 g_assert_not_reached();
7076 write_fp_dreg(s
, rd
, tcg_res
);
7078 tcg_temp_free_i64(tcg_op1
);
7079 tcg_temp_free_i64(tcg_op2
);
7080 tcg_temp_free_i64(tcg_res
);
7082 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7083 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7084 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7086 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7087 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7089 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7090 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7093 case 0xd: /* SQDMULL, SQDMULL2 */
7095 case 0xb: /* SQDMLSL, SQDMLSL2 */
7096 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7098 case 0x9: /* SQDMLAL, SQDMLAL2 */
7100 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7101 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7102 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7104 tcg_temp_free_i64(tcg_op3
);
7108 g_assert_not_reached();
7111 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7112 write_fp_dreg(s
, rd
, tcg_res
);
7114 tcg_temp_free_i32(tcg_op1
);
7115 tcg_temp_free_i32(tcg_op2
);
7116 tcg_temp_free_i64(tcg_res
);
7120 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7121 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7123 /* Handle 64x64->64 opcodes which are shared between the scalar
7124 * and vector 3-same groups. We cover every opcode where size == 3
7125 * is valid in either the three-reg-same (integer, not pairwise)
7126 * or scalar-three-reg-same groups. (Some opcodes are not yet
7132 case 0x1: /* SQADD */
7134 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7136 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7139 case 0x5: /* SQSUB */
7141 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7143 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7146 case 0x6: /* CMGT, CMHI */
7147 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7148 * We implement this using setcond (test) and then negating.
7150 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7152 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7153 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7155 case 0x7: /* CMGE, CMHS */
7156 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7158 case 0x11: /* CMTST, CMEQ */
7163 /* CMTST : test is "if (X & Y != 0)". */
7164 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7165 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7166 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7168 case 0x8: /* SSHL, USHL */
7170 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7172 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7175 case 0x9: /* SQSHL, UQSHL */
7177 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7179 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7182 case 0xa: /* SRSHL, URSHL */
7184 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7186 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7189 case 0xb: /* SQRSHL, UQRSHL */
7191 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7193 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7196 case 0x10: /* ADD, SUB */
7198 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7200 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7204 g_assert_not_reached();
7208 /* Handle the 3-same-operands float operations; shared by the scalar
7209 * and vector encodings. The caller must filter out any encodings
7210 * not allocated for the encoding it is dealing with.
7212 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7213 int fpopcode
, int rd
, int rn
, int rm
)
7216 TCGv_ptr fpst
= get_fpstatus_ptr();
7218 for (pass
= 0; pass
< elements
; pass
++) {
7221 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7222 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7223 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7225 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7226 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7229 case 0x39: /* FMLS */
7230 /* As usual for ARM, separate negation for fused multiply-add */
7231 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7233 case 0x19: /* FMLA */
7234 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7235 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7238 case 0x18: /* FMAXNM */
7239 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7241 case 0x1a: /* FADD */
7242 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7244 case 0x1b: /* FMULX */
7245 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7247 case 0x1c: /* FCMEQ */
7248 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7250 case 0x1e: /* FMAX */
7251 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7253 case 0x1f: /* FRECPS */
7254 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7256 case 0x38: /* FMINNM */
7257 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7259 case 0x3a: /* FSUB */
7260 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7262 case 0x3e: /* FMIN */
7263 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7265 case 0x3f: /* FRSQRTS */
7266 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7268 case 0x5b: /* FMUL */
7269 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7271 case 0x5c: /* FCMGE */
7272 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7274 case 0x5d: /* FACGE */
7275 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7277 case 0x5f: /* FDIV */
7278 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7280 case 0x7a: /* FABD */
7281 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7282 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7284 case 0x7c: /* FCMGT */
7285 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7287 case 0x7d: /* FACGT */
7288 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7291 g_assert_not_reached();
7294 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7296 tcg_temp_free_i64(tcg_res
);
7297 tcg_temp_free_i64(tcg_op1
);
7298 tcg_temp_free_i64(tcg_op2
);
7301 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7302 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7303 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7305 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7306 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7309 case 0x39: /* FMLS */
7310 /* As usual for ARM, separate negation for fused multiply-add */
7311 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7313 case 0x19: /* FMLA */
7314 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7315 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7318 case 0x1a: /* FADD */
7319 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7321 case 0x1b: /* FMULX */
7322 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7324 case 0x1c: /* FCMEQ */
7325 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7327 case 0x1e: /* FMAX */
7328 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7330 case 0x1f: /* FRECPS */
7331 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7333 case 0x18: /* FMAXNM */
7334 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7336 case 0x38: /* FMINNM */
7337 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7339 case 0x3a: /* FSUB */
7340 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7342 case 0x3e: /* FMIN */
7343 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7345 case 0x3f: /* FRSQRTS */
7346 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7348 case 0x5b: /* FMUL */
7349 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7351 case 0x5c: /* FCMGE */
7352 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7354 case 0x5d: /* FACGE */
7355 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7357 case 0x5f: /* FDIV */
7358 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7360 case 0x7a: /* FABD */
7361 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7362 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7364 case 0x7c: /* FCMGT */
7365 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7367 case 0x7d: /* FACGT */
7368 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7371 g_assert_not_reached();
7374 if (elements
== 1) {
7375 /* scalar single so clear high part */
7376 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7378 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7379 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7380 tcg_temp_free_i64(tcg_tmp
);
7382 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7385 tcg_temp_free_i32(tcg_res
);
7386 tcg_temp_free_i32(tcg_op1
);
7387 tcg_temp_free_i32(tcg_op2
);
7391 tcg_temp_free_ptr(fpst
);
7393 if ((elements
<< size
) < 4) {
7394 /* scalar, or non-quad vector op */
7395 clear_vec_high(s
, rd
);
7399 /* C3.6.11 AdvSIMD scalar three same
7400 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7401 * +-----+---+-----------+------+---+------+--------+---+------+------+
7402 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7403 * +-----+---+-----------+------+---+------+--------+---+------+------+
7405 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7407 int rd
= extract32(insn
, 0, 5);
7408 int rn
= extract32(insn
, 5, 5);
7409 int opcode
= extract32(insn
, 11, 5);
7410 int rm
= extract32(insn
, 16, 5);
7411 int size
= extract32(insn
, 22, 2);
7412 bool u
= extract32(insn
, 29, 1);
7415 if (opcode
>= 0x18) {
7416 /* Floating point: U, size[1] and opcode indicate operation */
7417 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7419 case 0x1b: /* FMULX */
7420 case 0x1f: /* FRECPS */
7421 case 0x3f: /* FRSQRTS */
7422 case 0x5d: /* FACGE */
7423 case 0x7d: /* FACGT */
7424 case 0x1c: /* FCMEQ */
7425 case 0x5c: /* FCMGE */
7426 case 0x7c: /* FCMGT */
7427 case 0x7a: /* FABD */
7430 unallocated_encoding(s
);
7434 if (!fp_access_check(s
)) {
7438 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7443 case 0x1: /* SQADD, UQADD */
7444 case 0x5: /* SQSUB, UQSUB */
7445 case 0x9: /* SQSHL, UQSHL */
7446 case 0xb: /* SQRSHL, UQRSHL */
7448 case 0x8: /* SSHL, USHL */
7449 case 0xa: /* SRSHL, URSHL */
7450 case 0x6: /* CMGT, CMHI */
7451 case 0x7: /* CMGE, CMHS */
7452 case 0x11: /* CMTST, CMEQ */
7453 case 0x10: /* ADD, SUB (vector) */
7455 unallocated_encoding(s
);
7459 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7460 if (size
!= 1 && size
!= 2) {
7461 unallocated_encoding(s
);
7466 unallocated_encoding(s
);
7470 if (!fp_access_check(s
)) {
7474 tcg_rd
= tcg_temp_new_i64();
7477 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7478 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7480 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7481 tcg_temp_free_i64(tcg_rn
);
7482 tcg_temp_free_i64(tcg_rm
);
7484 /* Do a single operation on the lowest element in the vector.
7485 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7486 * no side effects for all these operations.
7487 * OPTME: special-purpose helpers would avoid doing some
7488 * unnecessary work in the helper for the 8 and 16 bit cases.
7490 NeonGenTwoOpEnvFn
*genenvfn
;
7491 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7492 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7493 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7495 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7496 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7499 case 0x1: /* SQADD, UQADD */
7501 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7502 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7503 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7504 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7506 genenvfn
= fns
[size
][u
];
7509 case 0x5: /* SQSUB, UQSUB */
7511 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7512 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7513 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7514 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7516 genenvfn
= fns
[size
][u
];
7519 case 0x9: /* SQSHL, UQSHL */
7521 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7522 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7523 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7524 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7526 genenvfn
= fns
[size
][u
];
7529 case 0xb: /* SQRSHL, UQRSHL */
7531 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7532 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7533 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7534 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7536 genenvfn
= fns
[size
][u
];
7539 case 0x16: /* SQDMULH, SQRDMULH */
7541 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7542 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7543 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7545 assert(size
== 1 || size
== 2);
7546 genenvfn
= fns
[size
- 1][u
];
7550 g_assert_not_reached();
7553 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7554 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7555 tcg_temp_free_i32(tcg_rd32
);
7556 tcg_temp_free_i32(tcg_rn
);
7557 tcg_temp_free_i32(tcg_rm
);
7560 write_fp_dreg(s
, rd
, tcg_rd
);
7562 tcg_temp_free_i64(tcg_rd
);
7565 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7566 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7567 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7569 /* Handle 64->64 opcodes which are shared between the scalar and
7570 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7571 * is valid in either group and also the double-precision fp ops.
7572 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7578 case 0x4: /* CLS, CLZ */
7580 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7582 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7586 /* This opcode is shared with CNT and RBIT but we have earlier
7587 * enforced that size == 3 if and only if this is the NOT insn.
7589 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7591 case 0x7: /* SQABS, SQNEG */
7593 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7595 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7598 case 0xa: /* CMLT */
7599 /* 64 bit integer comparison against zero, result is
7600 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7605 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7606 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7608 case 0x8: /* CMGT, CMGE */
7609 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7611 case 0x9: /* CMEQ, CMLE */
7612 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7614 case 0xb: /* ABS, NEG */
7616 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7618 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7619 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7620 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7622 tcg_temp_free_i64(tcg_zero
);
7625 case 0x2f: /* FABS */
7626 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7628 case 0x6f: /* FNEG */
7629 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7631 case 0x7f: /* FSQRT */
7632 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7634 case 0x1a: /* FCVTNS */
7635 case 0x1b: /* FCVTMS */
7636 case 0x1c: /* FCVTAS */
7637 case 0x3a: /* FCVTPS */
7638 case 0x3b: /* FCVTZS */
7640 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7641 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7642 tcg_temp_free_i32(tcg_shift
);
7645 case 0x5a: /* FCVTNU */
7646 case 0x5b: /* FCVTMU */
7647 case 0x5c: /* FCVTAU */
7648 case 0x7a: /* FCVTPU */
7649 case 0x7b: /* FCVTZU */
7651 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7652 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7653 tcg_temp_free_i32(tcg_shift
);
7656 case 0x18: /* FRINTN */
7657 case 0x19: /* FRINTM */
7658 case 0x38: /* FRINTP */
7659 case 0x39: /* FRINTZ */
7660 case 0x58: /* FRINTA */
7661 case 0x79: /* FRINTI */
7662 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7664 case 0x59: /* FRINTX */
7665 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7668 g_assert_not_reached();
7672 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7673 bool is_scalar
, bool is_u
, bool is_q
,
7674 int size
, int rn
, int rd
)
7676 bool is_double
= (size
== 3);
7679 if (!fp_access_check(s
)) {
7683 fpst
= get_fpstatus_ptr();
7686 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7687 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7688 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7689 NeonGenTwoDoubleOPFn
*genfn
;
7694 case 0x2e: /* FCMLT (zero) */
7697 case 0x2c: /* FCMGT (zero) */
7698 genfn
= gen_helper_neon_cgt_f64
;
7700 case 0x2d: /* FCMEQ (zero) */
7701 genfn
= gen_helper_neon_ceq_f64
;
7703 case 0x6d: /* FCMLE (zero) */
7706 case 0x6c: /* FCMGE (zero) */
7707 genfn
= gen_helper_neon_cge_f64
;
7710 g_assert_not_reached();
7713 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7714 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7716 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7718 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7720 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7723 clear_vec_high(s
, rd
);
7726 tcg_temp_free_i64(tcg_res
);
7727 tcg_temp_free_i64(tcg_zero
);
7728 tcg_temp_free_i64(tcg_op
);
7730 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7731 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7732 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7733 NeonGenTwoSingleOPFn
*genfn
;
7735 int pass
, maxpasses
;
7738 case 0x2e: /* FCMLT (zero) */
7741 case 0x2c: /* FCMGT (zero) */
7742 genfn
= gen_helper_neon_cgt_f32
;
7744 case 0x2d: /* FCMEQ (zero) */
7745 genfn
= gen_helper_neon_ceq_f32
;
7747 case 0x6d: /* FCMLE (zero) */
7750 case 0x6c: /* FCMGE (zero) */
7751 genfn
= gen_helper_neon_cge_f32
;
7754 g_assert_not_reached();
7760 maxpasses
= is_q
? 4 : 2;
7763 for (pass
= 0; pass
< maxpasses
; pass
++) {
7764 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7766 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7768 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7771 write_fp_sreg(s
, rd
, tcg_res
);
7773 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7776 tcg_temp_free_i32(tcg_res
);
7777 tcg_temp_free_i32(tcg_zero
);
7778 tcg_temp_free_i32(tcg_op
);
7779 if (!is_q
&& !is_scalar
) {
7780 clear_vec_high(s
, rd
);
7784 tcg_temp_free_ptr(fpst
);
7787 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7788 bool is_scalar
, bool is_u
, bool is_q
,
7789 int size
, int rn
, int rd
)
7791 bool is_double
= (size
== 3);
7792 TCGv_ptr fpst
= get_fpstatus_ptr();
7795 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7796 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7799 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7800 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7802 case 0x3d: /* FRECPE */
7803 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7805 case 0x3f: /* FRECPX */
7806 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7808 case 0x7d: /* FRSQRTE */
7809 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7812 g_assert_not_reached();
7814 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7817 clear_vec_high(s
, rd
);
7820 tcg_temp_free_i64(tcg_res
);
7821 tcg_temp_free_i64(tcg_op
);
7823 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7824 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7825 int pass
, maxpasses
;
7830 maxpasses
= is_q
? 4 : 2;
7833 for (pass
= 0; pass
< maxpasses
; pass
++) {
7834 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7837 case 0x3c: /* URECPE */
7838 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7840 case 0x3d: /* FRECPE */
7841 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7843 case 0x3f: /* FRECPX */
7844 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7846 case 0x7d: /* FRSQRTE */
7847 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7850 g_assert_not_reached();
7854 write_fp_sreg(s
, rd
, tcg_res
);
7856 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7859 tcg_temp_free_i32(tcg_res
);
7860 tcg_temp_free_i32(tcg_op
);
7861 if (!is_q
&& !is_scalar
) {
7862 clear_vec_high(s
, rd
);
7865 tcg_temp_free_ptr(fpst
);
7868 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7869 int opcode
, bool u
, bool is_q
,
7870 int size
, int rn
, int rd
)
7872 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7873 * in the source becomes a size element in the destination).
7876 TCGv_i32 tcg_res
[2];
7877 int destelt
= is_q
? 2 : 0;
7878 int passes
= scalar
? 1 : 2;
7881 tcg_res
[1] = tcg_const_i32(0);
7884 for (pass
= 0; pass
< passes
; pass
++) {
7885 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7886 NeonGenNarrowFn
*genfn
= NULL
;
7887 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7890 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7892 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7894 tcg_res
[pass
] = tcg_temp_new_i32();
7897 case 0x12: /* XTN, SQXTUN */
7899 static NeonGenNarrowFn
* const xtnfns
[3] = {
7900 gen_helper_neon_narrow_u8
,
7901 gen_helper_neon_narrow_u16
,
7902 tcg_gen_extrl_i64_i32
,
7904 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7905 gen_helper_neon_unarrow_sat8
,
7906 gen_helper_neon_unarrow_sat16
,
7907 gen_helper_neon_unarrow_sat32
,
7910 genenvfn
= sqxtunfns
[size
];
7912 genfn
= xtnfns
[size
];
7916 case 0x14: /* SQXTN, UQXTN */
7918 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7919 { gen_helper_neon_narrow_sat_s8
,
7920 gen_helper_neon_narrow_sat_u8
},
7921 { gen_helper_neon_narrow_sat_s16
,
7922 gen_helper_neon_narrow_sat_u16
},
7923 { gen_helper_neon_narrow_sat_s32
,
7924 gen_helper_neon_narrow_sat_u32
},
7926 genenvfn
= fns
[size
][u
];
7929 case 0x16: /* FCVTN, FCVTN2 */
7930 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7932 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7934 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7935 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7936 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7937 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7938 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7939 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7940 tcg_temp_free_i32(tcg_lo
);
7941 tcg_temp_free_i32(tcg_hi
);
7944 case 0x56: /* FCVTXN, FCVTXN2 */
7945 /* 64 bit to 32 bit float conversion
7946 * with von Neumann rounding (round to odd)
7949 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7952 g_assert_not_reached();
7956 genfn(tcg_res
[pass
], tcg_op
);
7957 } else if (genenvfn
) {
7958 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7961 tcg_temp_free_i64(tcg_op
);
7964 for (pass
= 0; pass
< 2; pass
++) {
7965 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7966 tcg_temp_free_i32(tcg_res
[pass
]);
7969 clear_vec_high(s
, rd
);
7973 /* Remaining saturating accumulating ops */
7974 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7975 bool is_q
, int size
, int rn
, int rd
)
7977 bool is_double
= (size
== 3);
7980 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7981 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7984 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7985 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7986 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7988 if (is_u
) { /* USQADD */
7989 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7990 } else { /* SUQADD */
7991 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7993 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7996 clear_vec_high(s
, rd
);
7999 tcg_temp_free_i64(tcg_rd
);
8000 tcg_temp_free_i64(tcg_rn
);
8002 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8003 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8004 int pass
, maxpasses
;
8009 maxpasses
= is_q
? 4 : 2;
8012 for (pass
= 0; pass
< maxpasses
; pass
++) {
8014 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8015 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8017 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8018 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8021 if (is_u
) { /* USQADD */
8024 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8027 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8030 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8033 g_assert_not_reached();
8035 } else { /* SUQADD */
8038 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8041 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8044 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8047 g_assert_not_reached();
8052 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8053 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8054 tcg_temp_free_i64(tcg_zero
);
8056 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8060 clear_vec_high(s
, rd
);
8063 tcg_temp_free_i32(tcg_rd
);
8064 tcg_temp_free_i32(tcg_rn
);
8068 /* C3.6.12 AdvSIMD scalar two reg misc
8069 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8070 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8071 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8072 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8074 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8076 int rd
= extract32(insn
, 0, 5);
8077 int rn
= extract32(insn
, 5, 5);
8078 int opcode
= extract32(insn
, 12, 5);
8079 int size
= extract32(insn
, 22, 2);
8080 bool u
= extract32(insn
, 29, 1);
8081 bool is_fcvt
= false;
8084 TCGv_ptr tcg_fpstatus
;
8087 case 0x3: /* USQADD / SUQADD*/
8088 if (!fp_access_check(s
)) {
8091 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8093 case 0x7: /* SQABS / SQNEG */
8095 case 0xa: /* CMLT */
8097 unallocated_encoding(s
);
8101 case 0x8: /* CMGT, CMGE */
8102 case 0x9: /* CMEQ, CMLE */
8103 case 0xb: /* ABS, NEG */
8105 unallocated_encoding(s
);
8109 case 0x12: /* SQXTUN */
8111 unallocated_encoding(s
);
8115 case 0x14: /* SQXTN, UQXTN */
8117 unallocated_encoding(s
);
8120 if (!fp_access_check(s
)) {
8123 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8128 /* Floating point: U, size[1] and opcode indicate operation;
8129 * size[0] indicates single or double precision.
8131 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8132 size
= extract32(size
, 0, 1) ? 3 : 2;
8134 case 0x2c: /* FCMGT (zero) */
8135 case 0x2d: /* FCMEQ (zero) */
8136 case 0x2e: /* FCMLT (zero) */
8137 case 0x6c: /* FCMGE (zero) */
8138 case 0x6d: /* FCMLE (zero) */
8139 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8141 case 0x1d: /* SCVTF */
8142 case 0x5d: /* UCVTF */
8144 bool is_signed
= (opcode
== 0x1d);
8145 if (!fp_access_check(s
)) {
8148 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8151 case 0x3d: /* FRECPE */
8152 case 0x3f: /* FRECPX */
8153 case 0x7d: /* FRSQRTE */
8154 if (!fp_access_check(s
)) {
8157 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8159 case 0x1a: /* FCVTNS */
8160 case 0x1b: /* FCVTMS */
8161 case 0x3a: /* FCVTPS */
8162 case 0x3b: /* FCVTZS */
8163 case 0x5a: /* FCVTNU */
8164 case 0x5b: /* FCVTMU */
8165 case 0x7a: /* FCVTPU */
8166 case 0x7b: /* FCVTZU */
8168 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8170 case 0x1c: /* FCVTAS */
8171 case 0x5c: /* FCVTAU */
8172 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8174 rmode
= FPROUNDING_TIEAWAY
;
8176 case 0x56: /* FCVTXN, FCVTXN2 */
8178 unallocated_encoding(s
);
8181 if (!fp_access_check(s
)) {
8184 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8187 unallocated_encoding(s
);
8192 unallocated_encoding(s
);
8196 if (!fp_access_check(s
)) {
8201 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8202 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8203 tcg_fpstatus
= get_fpstatus_ptr();
8205 TCGV_UNUSED_I32(tcg_rmode
);
8206 TCGV_UNUSED_PTR(tcg_fpstatus
);
8210 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8211 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8213 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8214 write_fp_dreg(s
, rd
, tcg_rd
);
8215 tcg_temp_free_i64(tcg_rd
);
8216 tcg_temp_free_i64(tcg_rn
);
8218 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8219 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8221 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8224 case 0x7: /* SQABS, SQNEG */
8226 NeonGenOneOpEnvFn
*genfn
;
8227 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8228 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8229 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8230 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8232 genfn
= fns
[size
][u
];
8233 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8236 case 0x1a: /* FCVTNS */
8237 case 0x1b: /* FCVTMS */
8238 case 0x1c: /* FCVTAS */
8239 case 0x3a: /* FCVTPS */
8240 case 0x3b: /* FCVTZS */
8242 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8243 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8244 tcg_temp_free_i32(tcg_shift
);
8247 case 0x5a: /* FCVTNU */
8248 case 0x5b: /* FCVTMU */
8249 case 0x5c: /* FCVTAU */
8250 case 0x7a: /* FCVTPU */
8251 case 0x7b: /* FCVTZU */
8253 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8254 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8255 tcg_temp_free_i32(tcg_shift
);
8259 g_assert_not_reached();
8262 write_fp_sreg(s
, rd
, tcg_rd
);
8263 tcg_temp_free_i32(tcg_rd
);
8264 tcg_temp_free_i32(tcg_rn
);
8268 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8269 tcg_temp_free_i32(tcg_rmode
);
8270 tcg_temp_free_ptr(tcg_fpstatus
);
8274 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8275 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8276 int immh
, int immb
, int opcode
, int rn
, int rd
)
8278 int size
= 32 - clz32(immh
) - 1;
8279 int immhb
= immh
<< 3 | immb
;
8280 int shift
= 2 * (8 << size
) - immhb
;
8281 bool accumulate
= false;
8283 bool insert
= false;
8284 int dsize
= is_q
? 128 : 64;
8285 int esize
= 8 << size
;
8286 int elements
= dsize
/esize
;
8287 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8288 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8289 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8293 if (extract32(immh
, 3, 1) && !is_q
) {
8294 unallocated_encoding(s
);
8298 if (size
> 3 && !is_q
) {
8299 unallocated_encoding(s
);
8303 if (!fp_access_check(s
)) {
8308 case 0x02: /* SSRA / USRA (accumulate) */
8311 case 0x04: /* SRSHR / URSHR (rounding) */
8314 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8315 accumulate
= round
= true;
8317 case 0x08: /* SRI */
8323 uint64_t round_const
= 1ULL << (shift
- 1);
8324 tcg_round
= tcg_const_i64(round_const
);
8326 TCGV_UNUSED_I64(tcg_round
);
8329 for (i
= 0; i
< elements
; i
++) {
8330 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8331 if (accumulate
|| insert
) {
8332 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8336 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8338 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8339 accumulate
, is_u
, size
, shift
);
8342 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8346 clear_vec_high(s
, rd
);
8350 tcg_temp_free_i64(tcg_round
);
8354 /* SHL/SLI - Vector shift left */
8355 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8356 int immh
, int immb
, int opcode
, int rn
, int rd
)
8358 int size
= 32 - clz32(immh
) - 1;
8359 int immhb
= immh
<< 3 | immb
;
8360 int shift
= immhb
- (8 << size
);
8361 int dsize
= is_q
? 128 : 64;
8362 int esize
= 8 << size
;
8363 int elements
= dsize
/esize
;
8364 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8365 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8368 if (extract32(immh
, 3, 1) && !is_q
) {
8369 unallocated_encoding(s
);
8373 if (size
> 3 && !is_q
) {
8374 unallocated_encoding(s
);
8378 if (!fp_access_check(s
)) {
8382 for (i
= 0; i
< elements
; i
++) {
8383 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8385 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8388 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8390 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8394 clear_vec_high(s
, rd
);
8398 /* USHLL/SHLL - Vector shift left with widening */
8399 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8400 int immh
, int immb
, int opcode
, int rn
, int rd
)
8402 int size
= 32 - clz32(immh
) - 1;
8403 int immhb
= immh
<< 3 | immb
;
8404 int shift
= immhb
- (8 << size
);
8406 int esize
= 8 << size
;
8407 int elements
= dsize
/esize
;
8408 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8409 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8413 unallocated_encoding(s
);
8417 if (!fp_access_check(s
)) {
8421 /* For the LL variants the store is larger than the load,
8422 * so if rd == rn we would overwrite parts of our input.
8423 * So load everything right now and use shifts in the main loop.
8425 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8427 for (i
= 0; i
< elements
; i
++) {
8428 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8429 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8430 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8431 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8435 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8436 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8437 int immh
, int immb
, int opcode
, int rn
, int rd
)
8439 int immhb
= immh
<< 3 | immb
;
8440 int size
= 32 - clz32(immh
) - 1;
8442 int esize
= 8 << size
;
8443 int elements
= dsize
/esize
;
8444 int shift
= (2 * esize
) - immhb
;
8445 bool round
= extract32(opcode
, 0, 1);
8446 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8450 if (extract32(immh
, 3, 1)) {
8451 unallocated_encoding(s
);
8455 if (!fp_access_check(s
)) {
8459 tcg_rn
= tcg_temp_new_i64();
8460 tcg_rd
= tcg_temp_new_i64();
8461 tcg_final
= tcg_temp_new_i64();
8462 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8465 uint64_t round_const
= 1ULL << (shift
- 1);
8466 tcg_round
= tcg_const_i64(round_const
);
8468 TCGV_UNUSED_I64(tcg_round
);
8471 for (i
= 0; i
< elements
; i
++) {
8472 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8473 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8474 false, true, size
+1, shift
);
8476 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8480 clear_vec_high(s
, rd
);
8481 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8483 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8487 tcg_temp_free_i64(tcg_round
);
8489 tcg_temp_free_i64(tcg_rn
);
8490 tcg_temp_free_i64(tcg_rd
);
8491 tcg_temp_free_i64(tcg_final
);
8496 /* C3.6.14 AdvSIMD shift by immediate
8497 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8498 * +---+---+---+-------------+------+------+--------+---+------+------+
8499 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8500 * +---+---+---+-------------+------+------+--------+---+------+------+
8502 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8504 int rd
= extract32(insn
, 0, 5);
8505 int rn
= extract32(insn
, 5, 5);
8506 int opcode
= extract32(insn
, 11, 5);
8507 int immb
= extract32(insn
, 16, 3);
8508 int immh
= extract32(insn
, 19, 4);
8509 bool is_u
= extract32(insn
, 29, 1);
8510 bool is_q
= extract32(insn
, 30, 1);
8513 case 0x08: /* SRI */
8515 unallocated_encoding(s
);
8519 case 0x00: /* SSHR / USHR */
8520 case 0x02: /* SSRA / USRA (accumulate) */
8521 case 0x04: /* SRSHR / URSHR (rounding) */
8522 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8523 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8525 case 0x0a: /* SHL / SLI */
8526 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8528 case 0x10: /* SHRN */
8529 case 0x11: /* RSHRN / SQRSHRUN */
8531 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8534 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8537 case 0x12: /* SQSHRN / UQSHRN */
8538 case 0x13: /* SQRSHRN / UQRSHRN */
8539 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8542 case 0x14: /* SSHLL / USHLL */
8543 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8545 case 0x1c: /* SCVTF / UCVTF */
8546 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8549 case 0xc: /* SQSHLU */
8551 unallocated_encoding(s
);
8554 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8556 case 0xe: /* SQSHL, UQSHL */
8557 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8559 case 0x1f: /* FCVTZS/ FCVTZU */
8560 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8563 unallocated_encoding(s
);
8568 /* Generate code to do a "long" addition or subtraction, ie one done in
8569 * TCGv_i64 on vector lanes twice the width specified by size.
8571 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8572 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8574 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8575 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8576 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8577 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8579 NeonGenTwo64OpFn
*genfn
;
8582 genfn
= fns
[size
][is_sub
];
8583 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8586 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8587 int opcode
, int rd
, int rn
, int rm
)
8589 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8590 TCGv_i64 tcg_res
[2];
8593 tcg_res
[0] = tcg_temp_new_i64();
8594 tcg_res
[1] = tcg_temp_new_i64();
8596 /* Does this op do an adding accumulate, a subtracting accumulate,
8597 * or no accumulate at all?
8615 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8616 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8619 /* size == 2 means two 32x32->64 operations; this is worth special
8620 * casing because we can generally handle it inline.
8623 for (pass
= 0; pass
< 2; pass
++) {
8624 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8625 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8626 TCGv_i64 tcg_passres
;
8627 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8629 int elt
= pass
+ is_q
* 2;
8631 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8632 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8635 tcg_passres
= tcg_res
[pass
];
8637 tcg_passres
= tcg_temp_new_i64();
8641 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8642 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8644 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8645 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8647 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8648 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8650 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8651 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8653 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8654 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8655 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8657 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8658 tcg_temp_free_i64(tcg_tmp1
);
8659 tcg_temp_free_i64(tcg_tmp2
);
8662 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8663 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8664 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8665 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8667 case 9: /* SQDMLAL, SQDMLAL2 */
8668 case 11: /* SQDMLSL, SQDMLSL2 */
8669 case 13: /* SQDMULL, SQDMULL2 */
8670 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8671 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8672 tcg_passres
, tcg_passres
);
8675 g_assert_not_reached();
8678 if (opcode
== 9 || opcode
== 11) {
8679 /* saturating accumulate ops */
8681 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8683 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8684 tcg_res
[pass
], tcg_passres
);
8685 } else if (accop
> 0) {
8686 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8687 } else if (accop
< 0) {
8688 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8692 tcg_temp_free_i64(tcg_passres
);
8695 tcg_temp_free_i64(tcg_op1
);
8696 tcg_temp_free_i64(tcg_op2
);
8699 /* size 0 or 1, generally helper functions */
8700 for (pass
= 0; pass
< 2; pass
++) {
8701 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8702 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8703 TCGv_i64 tcg_passres
;
8704 int elt
= pass
+ is_q
* 2;
8706 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8707 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8710 tcg_passres
= tcg_res
[pass
];
8712 tcg_passres
= tcg_temp_new_i64();
8716 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8717 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8719 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8720 static NeonGenWidenFn
* const widenfns
[2][2] = {
8721 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8722 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8724 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8726 widenfn(tcg_op2_64
, tcg_op2
);
8727 widenfn(tcg_passres
, tcg_op1
);
8728 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8729 tcg_passres
, tcg_op2_64
);
8730 tcg_temp_free_i64(tcg_op2_64
);
8733 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8734 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8737 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8739 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8743 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8745 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8749 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8750 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8751 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8754 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8756 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8760 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8762 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8766 case 9: /* SQDMLAL, SQDMLAL2 */
8767 case 11: /* SQDMLSL, SQDMLSL2 */
8768 case 13: /* SQDMULL, SQDMULL2 */
8770 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8771 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8772 tcg_passres
, tcg_passres
);
8774 case 14: /* PMULL */
8776 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8779 g_assert_not_reached();
8781 tcg_temp_free_i32(tcg_op1
);
8782 tcg_temp_free_i32(tcg_op2
);
8785 if (opcode
== 9 || opcode
== 11) {
8786 /* saturating accumulate ops */
8788 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8790 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8794 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8795 tcg_res
[pass
], tcg_passres
);
8797 tcg_temp_free_i64(tcg_passres
);
8802 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8803 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8804 tcg_temp_free_i64(tcg_res
[0]);
8805 tcg_temp_free_i64(tcg_res
[1]);
8808 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8809 int opcode
, int rd
, int rn
, int rm
)
8811 TCGv_i64 tcg_res
[2];
8812 int part
= is_q
? 2 : 0;
8815 for (pass
= 0; pass
< 2; pass
++) {
8816 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8817 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8818 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8819 static NeonGenWidenFn
* const widenfns
[3][2] = {
8820 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8821 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8822 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8824 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8826 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8827 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8828 widenfn(tcg_op2_wide
, tcg_op2
);
8829 tcg_temp_free_i32(tcg_op2
);
8830 tcg_res
[pass
] = tcg_temp_new_i64();
8831 gen_neon_addl(size
, (opcode
== 3),
8832 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8833 tcg_temp_free_i64(tcg_op1
);
8834 tcg_temp_free_i64(tcg_op2_wide
);
8837 for (pass
= 0; pass
< 2; pass
++) {
8838 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8839 tcg_temp_free_i64(tcg_res
[pass
]);
8843 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8845 tcg_gen_addi_i64(in
, in
, 1U << 31);
8846 tcg_gen_extrh_i64_i32(res
, in
);
8849 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8850 int opcode
, int rd
, int rn
, int rm
)
8852 TCGv_i32 tcg_res
[2];
8853 int part
= is_q
? 2 : 0;
8856 for (pass
= 0; pass
< 2; pass
++) {
8857 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8858 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8859 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8860 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8861 { gen_helper_neon_narrow_high_u8
,
8862 gen_helper_neon_narrow_round_high_u8
},
8863 { gen_helper_neon_narrow_high_u16
,
8864 gen_helper_neon_narrow_round_high_u16
},
8865 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8867 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8869 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8870 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8872 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8874 tcg_temp_free_i64(tcg_op1
);
8875 tcg_temp_free_i64(tcg_op2
);
8877 tcg_res
[pass
] = tcg_temp_new_i32();
8878 gennarrow(tcg_res
[pass
], tcg_wideres
);
8879 tcg_temp_free_i64(tcg_wideres
);
8882 for (pass
= 0; pass
< 2; pass
++) {
8883 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8884 tcg_temp_free_i32(tcg_res
[pass
]);
8887 clear_vec_high(s
, rd
);
8891 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8893 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8894 * is the only three-reg-diff instruction which produces a
8895 * 128-bit wide result from a single operation. However since
8896 * it's possible to calculate the two halves more or less
8897 * separately we just use two helper calls.
8899 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8900 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8901 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8903 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8904 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8905 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8906 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8907 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8908 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8910 tcg_temp_free_i64(tcg_op1
);
8911 tcg_temp_free_i64(tcg_op2
);
8912 tcg_temp_free_i64(tcg_res
);
8915 /* C3.6.15 AdvSIMD three different
8916 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8917 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8918 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8919 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8921 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8923 /* Instructions in this group fall into three basic classes
8924 * (in each case with the operation working on each element in
8925 * the input vectors):
8926 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8928 * (2) wide 64 x 128 -> 128
8929 * (3) narrowing 128 x 128 -> 64
8930 * Here we do initial decode, catch unallocated cases and
8931 * dispatch to separate functions for each class.
8933 int is_q
= extract32(insn
, 30, 1);
8934 int is_u
= extract32(insn
, 29, 1);
8935 int size
= extract32(insn
, 22, 2);
8936 int opcode
= extract32(insn
, 12, 4);
8937 int rm
= extract32(insn
, 16, 5);
8938 int rn
= extract32(insn
, 5, 5);
8939 int rd
= extract32(insn
, 0, 5);
8942 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8943 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8944 /* 64 x 128 -> 128 */
8946 unallocated_encoding(s
);
8949 if (!fp_access_check(s
)) {
8952 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8954 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8955 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8956 /* 128 x 128 -> 64 */
8958 unallocated_encoding(s
);
8961 if (!fp_access_check(s
)) {
8964 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8966 case 14: /* PMULL, PMULL2 */
8967 if (is_u
|| size
== 1 || size
== 2) {
8968 unallocated_encoding(s
);
8972 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8973 unallocated_encoding(s
);
8976 if (!fp_access_check(s
)) {
8979 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8983 case 9: /* SQDMLAL, SQDMLAL2 */
8984 case 11: /* SQDMLSL, SQDMLSL2 */
8985 case 13: /* SQDMULL, SQDMULL2 */
8986 if (is_u
|| size
== 0) {
8987 unallocated_encoding(s
);
8991 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8992 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8993 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8994 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8995 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8996 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8997 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8998 /* 64 x 64 -> 128 */
9000 unallocated_encoding(s
);
9004 if (!fp_access_check(s
)) {
9008 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9011 /* opcode 15 not allocated */
9012 unallocated_encoding(s
);
9017 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9018 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9020 int rd
= extract32(insn
, 0, 5);
9021 int rn
= extract32(insn
, 5, 5);
9022 int rm
= extract32(insn
, 16, 5);
9023 int size
= extract32(insn
, 22, 2);
9024 bool is_u
= extract32(insn
, 29, 1);
9025 bool is_q
= extract32(insn
, 30, 1);
9026 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9029 if (!fp_access_check(s
)) {
9033 tcg_op1
= tcg_temp_new_i64();
9034 tcg_op2
= tcg_temp_new_i64();
9035 tcg_res
[0] = tcg_temp_new_i64();
9036 tcg_res
[1] = tcg_temp_new_i64();
9038 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9039 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9040 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9045 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9048 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9051 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9054 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9059 /* B* ops need res loaded to operate on */
9060 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9065 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9067 case 1: /* BSL bitwise select */
9068 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9069 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9070 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9072 case 2: /* BIT, bitwise insert if true */
9073 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9074 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9075 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9077 case 3: /* BIF, bitwise insert if false */
9078 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9079 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9080 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9086 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9088 tcg_gen_movi_i64(tcg_res
[1], 0);
9090 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9092 tcg_temp_free_i64(tcg_op1
);
9093 tcg_temp_free_i64(tcg_op2
);
9094 tcg_temp_free_i64(tcg_res
[0]);
9095 tcg_temp_free_i64(tcg_res
[1]);
9098 /* Helper functions for 32 bit comparisons */
9099 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9101 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9104 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9106 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9109 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9111 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9114 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9116 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9119 /* Pairwise op subgroup of C3.6.16.
9121 * This is called directly or via the handle_3same_float for float pairwise
9122 * operations where the opcode and size are calculated differently.
9124 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9125 int size
, int rn
, int rm
, int rd
)
9130 /* Floating point operations need fpst */
9131 if (opcode
>= 0x58) {
9132 fpst
= get_fpstatus_ptr();
9134 TCGV_UNUSED_PTR(fpst
);
9137 if (!fp_access_check(s
)) {
9141 /* These operations work on the concatenated rm:rn, with each pair of
9142 * adjacent elements being operated on to produce an element in the result.
9145 TCGv_i64 tcg_res
[2];
9147 for (pass
= 0; pass
< 2; pass
++) {
9148 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9149 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9150 int passreg
= (pass
== 0) ? rn
: rm
;
9152 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9153 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9154 tcg_res
[pass
] = tcg_temp_new_i64();
9157 case 0x17: /* ADDP */
9158 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9160 case 0x58: /* FMAXNMP */
9161 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9163 case 0x5a: /* FADDP */
9164 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9166 case 0x5e: /* FMAXP */
9167 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9169 case 0x78: /* FMINNMP */
9170 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9172 case 0x7e: /* FMINP */
9173 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9176 g_assert_not_reached();
9179 tcg_temp_free_i64(tcg_op1
);
9180 tcg_temp_free_i64(tcg_op2
);
9183 for (pass
= 0; pass
< 2; pass
++) {
9184 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9185 tcg_temp_free_i64(tcg_res
[pass
]);
9188 int maxpass
= is_q
? 4 : 2;
9189 TCGv_i32 tcg_res
[4];
9191 for (pass
= 0; pass
< maxpass
; pass
++) {
9192 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9193 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9194 NeonGenTwoOpFn
*genfn
= NULL
;
9195 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9196 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9198 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9199 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9200 tcg_res
[pass
] = tcg_temp_new_i32();
9203 case 0x17: /* ADDP */
9205 static NeonGenTwoOpFn
* const fns
[3] = {
9206 gen_helper_neon_padd_u8
,
9207 gen_helper_neon_padd_u16
,
9213 case 0x14: /* SMAXP, UMAXP */
9215 static NeonGenTwoOpFn
* const fns
[3][2] = {
9216 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9217 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9218 { gen_max_s32
, gen_max_u32
},
9220 genfn
= fns
[size
][u
];
9223 case 0x15: /* SMINP, UMINP */
9225 static NeonGenTwoOpFn
* const fns
[3][2] = {
9226 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9227 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9228 { gen_min_s32
, gen_min_u32
},
9230 genfn
= fns
[size
][u
];
9233 /* The FP operations are all on single floats (32 bit) */
9234 case 0x58: /* FMAXNMP */
9235 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9237 case 0x5a: /* FADDP */
9238 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9240 case 0x5e: /* FMAXP */
9241 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9243 case 0x78: /* FMINNMP */
9244 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9246 case 0x7e: /* FMINP */
9247 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9250 g_assert_not_reached();
9253 /* FP ops called directly, otherwise call now */
9255 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9258 tcg_temp_free_i32(tcg_op1
);
9259 tcg_temp_free_i32(tcg_op2
);
9262 for (pass
= 0; pass
< maxpass
; pass
++) {
9263 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9264 tcg_temp_free_i32(tcg_res
[pass
]);
9267 clear_vec_high(s
, rd
);
9271 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9272 tcg_temp_free_ptr(fpst
);
9276 /* Floating point op subgroup of C3.6.16. */
9277 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9279 /* For floating point ops, the U, size[1] and opcode bits
9280 * together indicate the operation. size[0] indicates single
9283 int fpopcode
= extract32(insn
, 11, 5)
9284 | (extract32(insn
, 23, 1) << 5)
9285 | (extract32(insn
, 29, 1) << 6);
9286 int is_q
= extract32(insn
, 30, 1);
9287 int size
= extract32(insn
, 22, 1);
9288 int rm
= extract32(insn
, 16, 5);
9289 int rn
= extract32(insn
, 5, 5);
9290 int rd
= extract32(insn
, 0, 5);
9292 int datasize
= is_q
? 128 : 64;
9293 int esize
= 32 << size
;
9294 int elements
= datasize
/ esize
;
9296 if (size
== 1 && !is_q
) {
9297 unallocated_encoding(s
);
9302 case 0x58: /* FMAXNMP */
9303 case 0x5a: /* FADDP */
9304 case 0x5e: /* FMAXP */
9305 case 0x78: /* FMINNMP */
9306 case 0x7e: /* FMINP */
9307 if (size
&& !is_q
) {
9308 unallocated_encoding(s
);
9311 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9314 case 0x1b: /* FMULX */
9315 case 0x1f: /* FRECPS */
9316 case 0x3f: /* FRSQRTS */
9317 case 0x5d: /* FACGE */
9318 case 0x7d: /* FACGT */
9319 case 0x19: /* FMLA */
9320 case 0x39: /* FMLS */
9321 case 0x18: /* FMAXNM */
9322 case 0x1a: /* FADD */
9323 case 0x1c: /* FCMEQ */
9324 case 0x1e: /* FMAX */
9325 case 0x38: /* FMINNM */
9326 case 0x3a: /* FSUB */
9327 case 0x3e: /* FMIN */
9328 case 0x5b: /* FMUL */
9329 case 0x5c: /* FCMGE */
9330 case 0x5f: /* FDIV */
9331 case 0x7a: /* FABD */
9332 case 0x7c: /* FCMGT */
9333 if (!fp_access_check(s
)) {
9337 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9340 unallocated_encoding(s
);
9345 /* Integer op subgroup of C3.6.16. */
9346 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9348 int is_q
= extract32(insn
, 30, 1);
9349 int u
= extract32(insn
, 29, 1);
9350 int size
= extract32(insn
, 22, 2);
9351 int opcode
= extract32(insn
, 11, 5);
9352 int rm
= extract32(insn
, 16, 5);
9353 int rn
= extract32(insn
, 5, 5);
9354 int rd
= extract32(insn
, 0, 5);
9358 case 0x13: /* MUL, PMUL */
9359 if (u
&& size
!= 0) {
9360 unallocated_encoding(s
);
9364 case 0x0: /* SHADD, UHADD */
9365 case 0x2: /* SRHADD, URHADD */
9366 case 0x4: /* SHSUB, UHSUB */
9367 case 0xc: /* SMAX, UMAX */
9368 case 0xd: /* SMIN, UMIN */
9369 case 0xe: /* SABD, UABD */
9370 case 0xf: /* SABA, UABA */
9371 case 0x12: /* MLA, MLS */
9373 unallocated_encoding(s
);
9377 case 0x16: /* SQDMULH, SQRDMULH */
9378 if (size
== 0 || size
== 3) {
9379 unallocated_encoding(s
);
9384 if (size
== 3 && !is_q
) {
9385 unallocated_encoding(s
);
9391 if (!fp_access_check(s
)) {
9397 for (pass
= 0; pass
< 2; pass
++) {
9398 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9399 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9400 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9402 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9403 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9405 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9407 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9409 tcg_temp_free_i64(tcg_res
);
9410 tcg_temp_free_i64(tcg_op1
);
9411 tcg_temp_free_i64(tcg_op2
);
9414 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9415 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9416 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9417 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9418 NeonGenTwoOpFn
*genfn
= NULL
;
9419 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9421 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9422 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9425 case 0x0: /* SHADD, UHADD */
9427 static NeonGenTwoOpFn
* const fns
[3][2] = {
9428 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9429 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9430 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9432 genfn
= fns
[size
][u
];
9435 case 0x1: /* SQADD, UQADD */
9437 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9438 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9439 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9440 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9442 genenvfn
= fns
[size
][u
];
9445 case 0x2: /* SRHADD, URHADD */
9447 static NeonGenTwoOpFn
* const fns
[3][2] = {
9448 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9449 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9450 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9452 genfn
= fns
[size
][u
];
9455 case 0x4: /* SHSUB, UHSUB */
9457 static NeonGenTwoOpFn
* const fns
[3][2] = {
9458 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9459 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9460 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9462 genfn
= fns
[size
][u
];
9465 case 0x5: /* SQSUB, UQSUB */
9467 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9468 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9469 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9470 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9472 genenvfn
= fns
[size
][u
];
9475 case 0x6: /* CMGT, CMHI */
9477 static NeonGenTwoOpFn
* const fns
[3][2] = {
9478 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9479 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9480 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9482 genfn
= fns
[size
][u
];
9485 case 0x7: /* CMGE, CMHS */
9487 static NeonGenTwoOpFn
* const fns
[3][2] = {
9488 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9489 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9490 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9492 genfn
= fns
[size
][u
];
9495 case 0x8: /* SSHL, USHL */
9497 static NeonGenTwoOpFn
* const fns
[3][2] = {
9498 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9499 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9500 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9502 genfn
= fns
[size
][u
];
9505 case 0x9: /* SQSHL, UQSHL */
9507 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9508 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9509 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9510 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9512 genenvfn
= fns
[size
][u
];
9515 case 0xa: /* SRSHL, URSHL */
9517 static NeonGenTwoOpFn
* const fns
[3][2] = {
9518 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9519 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9520 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9522 genfn
= fns
[size
][u
];
9525 case 0xb: /* SQRSHL, UQRSHL */
9527 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9528 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9529 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9530 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9532 genenvfn
= fns
[size
][u
];
9535 case 0xc: /* SMAX, UMAX */
9537 static NeonGenTwoOpFn
* const fns
[3][2] = {
9538 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9539 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9540 { gen_max_s32
, gen_max_u32
},
9542 genfn
= fns
[size
][u
];
9546 case 0xd: /* SMIN, UMIN */
9548 static NeonGenTwoOpFn
* const fns
[3][2] = {
9549 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9550 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9551 { gen_min_s32
, gen_min_u32
},
9553 genfn
= fns
[size
][u
];
9556 case 0xe: /* SABD, UABD */
9557 case 0xf: /* SABA, UABA */
9559 static NeonGenTwoOpFn
* const fns
[3][2] = {
9560 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9561 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9562 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9564 genfn
= fns
[size
][u
];
9567 case 0x10: /* ADD, SUB */
9569 static NeonGenTwoOpFn
* const fns
[3][2] = {
9570 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9571 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9572 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9574 genfn
= fns
[size
][u
];
9577 case 0x11: /* CMTST, CMEQ */
9579 static NeonGenTwoOpFn
* const fns
[3][2] = {
9580 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9581 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9582 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9584 genfn
= fns
[size
][u
];
9587 case 0x13: /* MUL, PMUL */
9591 genfn
= gen_helper_neon_mul_p8
;
9594 /* fall through : MUL */
9595 case 0x12: /* MLA, MLS */
9597 static NeonGenTwoOpFn
* const fns
[3] = {
9598 gen_helper_neon_mul_u8
,
9599 gen_helper_neon_mul_u16
,
9605 case 0x16: /* SQDMULH, SQRDMULH */
9607 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9608 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9609 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9611 assert(size
== 1 || size
== 2);
9612 genenvfn
= fns
[size
- 1][u
];
9616 g_assert_not_reached();
9620 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9622 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9625 if (opcode
== 0xf || opcode
== 0x12) {
9626 /* SABA, UABA, MLA, MLS: accumulating ops */
9627 static NeonGenTwoOpFn
* const fns
[3][2] = {
9628 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9629 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9630 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9632 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9634 genfn
= fns
[size
][is_sub
];
9635 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9636 genfn(tcg_res
, tcg_op1
, tcg_res
);
9639 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9641 tcg_temp_free_i32(tcg_res
);
9642 tcg_temp_free_i32(tcg_op1
);
9643 tcg_temp_free_i32(tcg_op2
);
9648 clear_vec_high(s
, rd
);
9652 /* C3.6.16 AdvSIMD three same
9653 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9654 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9655 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9656 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9658 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9660 int opcode
= extract32(insn
, 11, 5);
9663 case 0x3: /* logic ops */
9664 disas_simd_3same_logic(s
, insn
);
9666 case 0x17: /* ADDP */
9667 case 0x14: /* SMAXP, UMAXP */
9668 case 0x15: /* SMINP, UMINP */
9670 /* Pairwise operations */
9671 int is_q
= extract32(insn
, 30, 1);
9672 int u
= extract32(insn
, 29, 1);
9673 int size
= extract32(insn
, 22, 2);
9674 int rm
= extract32(insn
, 16, 5);
9675 int rn
= extract32(insn
, 5, 5);
9676 int rd
= extract32(insn
, 0, 5);
9677 if (opcode
== 0x17) {
9678 if (u
|| (size
== 3 && !is_q
)) {
9679 unallocated_encoding(s
);
9684 unallocated_encoding(s
);
9688 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9692 /* floating point ops, sz[1] and U are part of opcode */
9693 disas_simd_3same_float(s
, insn
);
9696 disas_simd_3same_int(s
, insn
);
9701 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9702 int size
, int rn
, int rd
)
9704 /* Handle 2-reg-misc ops which are widening (so each size element
9705 * in the source becomes a 2*size element in the destination.
9706 * The only instruction like this is FCVTL.
9711 /* 32 -> 64 bit fp conversion */
9712 TCGv_i64 tcg_res
[2];
9713 int srcelt
= is_q
? 2 : 0;
9715 for (pass
= 0; pass
< 2; pass
++) {
9716 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9717 tcg_res
[pass
] = tcg_temp_new_i64();
9719 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9720 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9721 tcg_temp_free_i32(tcg_op
);
9723 for (pass
= 0; pass
< 2; pass
++) {
9724 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9725 tcg_temp_free_i64(tcg_res
[pass
]);
9728 /* 16 -> 32 bit fp conversion */
9729 int srcelt
= is_q
? 4 : 0;
9730 TCGv_i32 tcg_res
[4];
9732 for (pass
= 0; pass
< 4; pass
++) {
9733 tcg_res
[pass
] = tcg_temp_new_i32();
9735 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9736 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9739 for (pass
= 0; pass
< 4; pass
++) {
9740 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9741 tcg_temp_free_i32(tcg_res
[pass
]);
9746 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9747 bool is_q
, int size
, int rn
, int rd
)
9749 int op
= (opcode
<< 1) | u
;
9750 int opsz
= op
+ size
;
9751 int grp_size
= 3 - opsz
;
9752 int dsize
= is_q
? 128 : 64;
9756 unallocated_encoding(s
);
9760 if (!fp_access_check(s
)) {
9765 /* Special case bytes, use bswap op on each group of elements */
9766 int groups
= dsize
/ (8 << grp_size
);
9768 for (i
= 0; i
< groups
; i
++) {
9769 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9771 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9774 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9777 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9780 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9783 g_assert_not_reached();
9785 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9786 tcg_temp_free_i64(tcg_tmp
);
9789 clear_vec_high(s
, rd
);
9792 int revmask
= (1 << grp_size
) - 1;
9793 int esize
= 8 << size
;
9794 int elements
= dsize
/ esize
;
9795 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9796 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9797 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9799 for (i
= 0; i
< elements
; i
++) {
9800 int e_rev
= (i
& 0xf) ^ revmask
;
9801 int off
= e_rev
* esize
;
9802 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9804 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9805 tcg_rn
, off
- 64, esize
);
9807 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9810 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9811 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9813 tcg_temp_free_i64(tcg_rd_hi
);
9814 tcg_temp_free_i64(tcg_rd
);
9815 tcg_temp_free_i64(tcg_rn
);
9819 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9820 bool is_q
, int size
, int rn
, int rd
)
9822 /* Implement the pairwise operations from 2-misc:
9823 * SADDLP, UADDLP, SADALP, UADALP.
9824 * These all add pairs of elements in the input to produce a
9825 * double-width result element in the output (possibly accumulating).
9827 bool accum
= (opcode
== 0x6);
9828 int maxpass
= is_q
? 2 : 1;
9830 TCGv_i64 tcg_res
[2];
9833 /* 32 + 32 -> 64 op */
9834 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9836 for (pass
= 0; pass
< maxpass
; pass
++) {
9837 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9838 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9840 tcg_res
[pass
] = tcg_temp_new_i64();
9842 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9843 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9844 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9846 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9847 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9850 tcg_temp_free_i64(tcg_op1
);
9851 tcg_temp_free_i64(tcg_op2
);
9854 for (pass
= 0; pass
< maxpass
; pass
++) {
9855 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9856 NeonGenOneOpFn
*genfn
;
9857 static NeonGenOneOpFn
* const fns
[2][2] = {
9858 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9859 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9862 genfn
= fns
[size
][u
];
9864 tcg_res
[pass
] = tcg_temp_new_i64();
9866 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9867 genfn(tcg_res
[pass
], tcg_op
);
9870 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9872 gen_helper_neon_addl_u16(tcg_res
[pass
],
9873 tcg_res
[pass
], tcg_op
);
9875 gen_helper_neon_addl_u32(tcg_res
[pass
],
9876 tcg_res
[pass
], tcg_op
);
9879 tcg_temp_free_i64(tcg_op
);
9883 tcg_res
[1] = tcg_const_i64(0);
9885 for (pass
= 0; pass
< 2; pass
++) {
9886 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9887 tcg_temp_free_i64(tcg_res
[pass
]);
9891 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9893 /* Implement SHLL and SHLL2 */
9895 int part
= is_q
? 2 : 0;
9896 TCGv_i64 tcg_res
[2];
9898 for (pass
= 0; pass
< 2; pass
++) {
9899 static NeonGenWidenFn
* const widenfns
[3] = {
9900 gen_helper_neon_widen_u8
,
9901 gen_helper_neon_widen_u16
,
9902 tcg_gen_extu_i32_i64
,
9904 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9905 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9907 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9908 tcg_res
[pass
] = tcg_temp_new_i64();
9909 widenfn(tcg_res
[pass
], tcg_op
);
9910 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9912 tcg_temp_free_i32(tcg_op
);
9915 for (pass
= 0; pass
< 2; pass
++) {
9916 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9917 tcg_temp_free_i64(tcg_res
[pass
]);
9921 /* C3.6.17 AdvSIMD two reg misc
9922 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9923 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9924 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9925 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9927 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9929 int size
= extract32(insn
, 22, 2);
9930 int opcode
= extract32(insn
, 12, 5);
9931 bool u
= extract32(insn
, 29, 1);
9932 bool is_q
= extract32(insn
, 30, 1);
9933 int rn
= extract32(insn
, 5, 5);
9934 int rd
= extract32(insn
, 0, 5);
9935 bool need_fpstatus
= false;
9936 bool need_rmode
= false;
9939 TCGv_ptr tcg_fpstatus
;
9942 case 0x0: /* REV64, REV32 */
9943 case 0x1: /* REV16 */
9944 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9946 case 0x5: /* CNT, NOT, RBIT */
9947 if (u
&& size
== 0) {
9948 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9951 } else if (u
&& size
== 1) {
9954 } else if (!u
&& size
== 0) {
9958 unallocated_encoding(s
);
9960 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9961 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9963 unallocated_encoding(s
);
9966 if (!fp_access_check(s
)) {
9970 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9972 case 0x4: /* CLS, CLZ */
9974 unallocated_encoding(s
);
9978 case 0x2: /* SADDLP, UADDLP */
9979 case 0x6: /* SADALP, UADALP */
9981 unallocated_encoding(s
);
9984 if (!fp_access_check(s
)) {
9987 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9989 case 0x13: /* SHLL, SHLL2 */
9990 if (u
== 0 || size
== 3) {
9991 unallocated_encoding(s
);
9994 if (!fp_access_check(s
)) {
9997 handle_shll(s
, is_q
, size
, rn
, rd
);
9999 case 0xa: /* CMLT */
10001 unallocated_encoding(s
);
10005 case 0x8: /* CMGT, CMGE */
10006 case 0x9: /* CMEQ, CMLE */
10007 case 0xb: /* ABS, NEG */
10008 if (size
== 3 && !is_q
) {
10009 unallocated_encoding(s
);
10013 case 0x3: /* SUQADD, USQADD */
10014 if (size
== 3 && !is_q
) {
10015 unallocated_encoding(s
);
10018 if (!fp_access_check(s
)) {
10021 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10023 case 0x7: /* SQABS, SQNEG */
10024 if (size
== 3 && !is_q
) {
10025 unallocated_encoding(s
);
10030 case 0x16 ... 0x1d:
10033 /* Floating point: U, size[1] and opcode indicate operation;
10034 * size[0] indicates single or double precision.
10036 int is_double
= extract32(size
, 0, 1);
10037 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10038 size
= is_double
? 3 : 2;
10040 case 0x2f: /* FABS */
10041 case 0x6f: /* FNEG */
10042 if (size
== 3 && !is_q
) {
10043 unallocated_encoding(s
);
10047 case 0x1d: /* SCVTF */
10048 case 0x5d: /* UCVTF */
10050 bool is_signed
= (opcode
== 0x1d) ? true : false;
10051 int elements
= is_double
? 2 : is_q
? 4 : 2;
10052 if (is_double
&& !is_q
) {
10053 unallocated_encoding(s
);
10056 if (!fp_access_check(s
)) {
10059 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10062 case 0x2c: /* FCMGT (zero) */
10063 case 0x2d: /* FCMEQ (zero) */
10064 case 0x2e: /* FCMLT (zero) */
10065 case 0x6c: /* FCMGE (zero) */
10066 case 0x6d: /* FCMLE (zero) */
10067 if (size
== 3 && !is_q
) {
10068 unallocated_encoding(s
);
10071 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10073 case 0x7f: /* FSQRT */
10074 if (size
== 3 && !is_q
) {
10075 unallocated_encoding(s
);
10079 case 0x1a: /* FCVTNS */
10080 case 0x1b: /* FCVTMS */
10081 case 0x3a: /* FCVTPS */
10082 case 0x3b: /* FCVTZS */
10083 case 0x5a: /* FCVTNU */
10084 case 0x5b: /* FCVTMU */
10085 case 0x7a: /* FCVTPU */
10086 case 0x7b: /* FCVTZU */
10087 need_fpstatus
= true;
10089 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10090 if (size
== 3 && !is_q
) {
10091 unallocated_encoding(s
);
10095 case 0x5c: /* FCVTAU */
10096 case 0x1c: /* FCVTAS */
10097 need_fpstatus
= true;
10099 rmode
= FPROUNDING_TIEAWAY
;
10100 if (size
== 3 && !is_q
) {
10101 unallocated_encoding(s
);
10105 case 0x3c: /* URECPE */
10107 unallocated_encoding(s
);
10111 case 0x3d: /* FRECPE */
10112 case 0x7d: /* FRSQRTE */
10113 if (size
== 3 && !is_q
) {
10114 unallocated_encoding(s
);
10117 if (!fp_access_check(s
)) {
10120 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10122 case 0x56: /* FCVTXN, FCVTXN2 */
10124 unallocated_encoding(s
);
10128 case 0x16: /* FCVTN, FCVTN2 */
10129 /* handle_2misc_narrow does a 2*size -> size operation, but these
10130 * instructions encode the source size rather than dest size.
10132 if (!fp_access_check(s
)) {
10135 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10137 case 0x17: /* FCVTL, FCVTL2 */
10138 if (!fp_access_check(s
)) {
10141 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10143 case 0x18: /* FRINTN */
10144 case 0x19: /* FRINTM */
10145 case 0x38: /* FRINTP */
10146 case 0x39: /* FRINTZ */
10148 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10150 case 0x59: /* FRINTX */
10151 case 0x79: /* FRINTI */
10152 need_fpstatus
= true;
10153 if (size
== 3 && !is_q
) {
10154 unallocated_encoding(s
);
10158 case 0x58: /* FRINTA */
10160 rmode
= FPROUNDING_TIEAWAY
;
10161 need_fpstatus
= true;
10162 if (size
== 3 && !is_q
) {
10163 unallocated_encoding(s
);
10167 case 0x7c: /* URSQRTE */
10169 unallocated_encoding(s
);
10172 need_fpstatus
= true;
10175 unallocated_encoding(s
);
10181 unallocated_encoding(s
);
10185 if (!fp_access_check(s
)) {
10189 if (need_fpstatus
) {
10190 tcg_fpstatus
= get_fpstatus_ptr();
10192 TCGV_UNUSED_PTR(tcg_fpstatus
);
10195 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10196 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10198 TCGV_UNUSED_I32(tcg_rmode
);
10202 /* All 64-bit element operations can be shared with scalar 2misc */
10205 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10206 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10207 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10209 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10211 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10212 tcg_rmode
, tcg_fpstatus
);
10214 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10216 tcg_temp_free_i64(tcg_res
);
10217 tcg_temp_free_i64(tcg_op
);
10222 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10223 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10224 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10227 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10230 /* Special cases for 32 bit elements */
10232 case 0xa: /* CMLT */
10233 /* 32 bit integer comparison against zero, result is
10234 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10237 cond
= TCG_COND_LT
;
10239 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10240 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10242 case 0x8: /* CMGT, CMGE */
10243 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10245 case 0x9: /* CMEQ, CMLE */
10246 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10248 case 0x4: /* CLS */
10250 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10252 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10255 case 0x7: /* SQABS, SQNEG */
10257 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10259 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10262 case 0xb: /* ABS, NEG */
10264 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10266 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10267 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10268 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10269 tcg_zero
, tcg_op
, tcg_res
);
10270 tcg_temp_free_i32(tcg_zero
);
10273 case 0x2f: /* FABS */
10274 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10276 case 0x6f: /* FNEG */
10277 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10279 case 0x7f: /* FSQRT */
10280 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10282 case 0x1a: /* FCVTNS */
10283 case 0x1b: /* FCVTMS */
10284 case 0x1c: /* FCVTAS */
10285 case 0x3a: /* FCVTPS */
10286 case 0x3b: /* FCVTZS */
10288 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10289 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10290 tcg_shift
, tcg_fpstatus
);
10291 tcg_temp_free_i32(tcg_shift
);
10294 case 0x5a: /* FCVTNU */
10295 case 0x5b: /* FCVTMU */
10296 case 0x5c: /* FCVTAU */
10297 case 0x7a: /* FCVTPU */
10298 case 0x7b: /* FCVTZU */
10300 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10301 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10302 tcg_shift
, tcg_fpstatus
);
10303 tcg_temp_free_i32(tcg_shift
);
10306 case 0x18: /* FRINTN */
10307 case 0x19: /* FRINTM */
10308 case 0x38: /* FRINTP */
10309 case 0x39: /* FRINTZ */
10310 case 0x58: /* FRINTA */
10311 case 0x79: /* FRINTI */
10312 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10314 case 0x59: /* FRINTX */
10315 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10317 case 0x7c: /* URSQRTE */
10318 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10321 g_assert_not_reached();
10324 /* Use helpers for 8 and 16 bit elements */
10326 case 0x5: /* CNT, RBIT */
10327 /* For these two insns size is part of the opcode specifier
10328 * (handled earlier); they always operate on byte elements.
10331 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10333 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10336 case 0x7: /* SQABS, SQNEG */
10338 NeonGenOneOpEnvFn
*genfn
;
10339 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10340 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10341 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10343 genfn
= fns
[size
][u
];
10344 genfn(tcg_res
, cpu_env
, tcg_op
);
10347 case 0x8: /* CMGT, CMGE */
10348 case 0x9: /* CMEQ, CMLE */
10349 case 0xa: /* CMLT */
10351 static NeonGenTwoOpFn
* const fns
[3][2] = {
10352 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10353 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10354 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10356 NeonGenTwoOpFn
*genfn
;
10359 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10361 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10362 comp
= (opcode
- 0x8) * 2 + u
;
10363 /* ...but LE, LT are implemented as reverse GE, GT */
10364 reverse
= (comp
> 2);
10368 genfn
= fns
[comp
][size
];
10370 genfn(tcg_res
, tcg_zero
, tcg_op
);
10372 genfn(tcg_res
, tcg_op
, tcg_zero
);
10374 tcg_temp_free_i32(tcg_zero
);
10377 case 0xb: /* ABS, NEG */
10379 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10381 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10383 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10385 tcg_temp_free_i32(tcg_zero
);
10388 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10390 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10394 case 0x4: /* CLS, CLZ */
10397 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10399 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10403 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10405 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10410 g_assert_not_reached();
10414 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10416 tcg_temp_free_i32(tcg_res
);
10417 tcg_temp_free_i32(tcg_op
);
10421 clear_vec_high(s
, rd
);
10425 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10426 tcg_temp_free_i32(tcg_rmode
);
10428 if (need_fpstatus
) {
10429 tcg_temp_free_ptr(tcg_fpstatus
);
10433 /* C3.6.13 AdvSIMD scalar x indexed element
10434 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10435 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10436 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10437 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10438 * C3.6.18 AdvSIMD vector x indexed element
10439 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10440 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10441 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10442 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10444 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10446 /* This encoding has two kinds of instruction:
10447 * normal, where we perform elt x idxelt => elt for each
10448 * element in the vector
10449 * long, where we perform elt x idxelt and generate a result of
10450 * double the width of the input element
10451 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10453 bool is_scalar
= extract32(insn
, 28, 1);
10454 bool is_q
= extract32(insn
, 30, 1);
10455 bool u
= extract32(insn
, 29, 1);
10456 int size
= extract32(insn
, 22, 2);
10457 int l
= extract32(insn
, 21, 1);
10458 int m
= extract32(insn
, 20, 1);
10459 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10460 int rm
= extract32(insn
, 16, 4);
10461 int opcode
= extract32(insn
, 12, 4);
10462 int h
= extract32(insn
, 11, 1);
10463 int rn
= extract32(insn
, 5, 5);
10464 int rd
= extract32(insn
, 0, 5);
10465 bool is_long
= false;
10466 bool is_fp
= false;
10471 case 0x0: /* MLA */
10472 case 0x4: /* MLS */
10473 if (!u
|| is_scalar
) {
10474 unallocated_encoding(s
);
10478 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10479 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10480 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10482 unallocated_encoding(s
);
10487 case 0x3: /* SQDMLAL, SQDMLAL2 */
10488 case 0x7: /* SQDMLSL, SQDMLSL2 */
10489 case 0xb: /* SQDMULL, SQDMULL2 */
10492 case 0xc: /* SQDMULH */
10493 case 0xd: /* SQRDMULH */
10495 unallocated_encoding(s
);
10499 case 0x8: /* MUL */
10500 if (u
|| is_scalar
) {
10501 unallocated_encoding(s
);
10505 case 0x1: /* FMLA */
10506 case 0x5: /* FMLS */
10508 unallocated_encoding(s
);
10512 case 0x9: /* FMUL, FMULX */
10513 if (!extract32(size
, 1, 1)) {
10514 unallocated_encoding(s
);
10520 unallocated_encoding(s
);
10525 /* low bit of size indicates single/double */
10526 size
= extract32(size
, 0, 1) ? 3 : 2;
10528 index
= h
<< 1 | l
;
10531 unallocated_encoding(s
);
10540 index
= h
<< 2 | l
<< 1 | m
;
10543 index
= h
<< 1 | l
;
10547 unallocated_encoding(s
);
10552 if (!fp_access_check(s
)) {
10557 fpst
= get_fpstatus_ptr();
10559 TCGV_UNUSED_PTR(fpst
);
10563 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10566 assert(is_fp
&& is_q
&& !is_long
);
10568 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10570 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10571 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10572 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10574 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10577 case 0x5: /* FMLS */
10578 /* As usual for ARM, separate negation for fused multiply-add */
10579 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10581 case 0x1: /* FMLA */
10582 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10583 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10585 case 0x9: /* FMUL, FMULX */
10587 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10589 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10593 g_assert_not_reached();
10596 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10597 tcg_temp_free_i64(tcg_op
);
10598 tcg_temp_free_i64(tcg_res
);
10602 clear_vec_high(s
, rd
);
10605 tcg_temp_free_i64(tcg_idx
);
10606 } else if (!is_long
) {
10607 /* 32 bit floating point, or 16 or 32 bit integer.
10608 * For the 16 bit scalar case we use the usual Neon helpers and
10609 * rely on the fact that 0 op 0 == 0 with no side effects.
10611 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10612 int pass
, maxpasses
;
10617 maxpasses
= is_q
? 4 : 2;
10620 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10622 if (size
== 1 && !is_scalar
) {
10623 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10624 * the index into both halves of the 32 bit tcg_idx and then use
10625 * the usual Neon helpers.
10627 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10630 for (pass
= 0; pass
< maxpasses
; pass
++) {
10631 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10632 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10634 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10637 case 0x0: /* MLA */
10638 case 0x4: /* MLS */
10639 case 0x8: /* MUL */
10641 static NeonGenTwoOpFn
* const fns
[2][2] = {
10642 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10643 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10645 NeonGenTwoOpFn
*genfn
;
10646 bool is_sub
= opcode
== 0x4;
10649 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10651 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10653 if (opcode
== 0x8) {
10656 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10657 genfn
= fns
[size
- 1][is_sub
];
10658 genfn(tcg_res
, tcg_op
, tcg_res
);
10661 case 0x5: /* FMLS */
10662 /* As usual for ARM, separate negation for fused multiply-add */
10663 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10665 case 0x1: /* FMLA */
10666 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10667 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10669 case 0x9: /* FMUL, FMULX */
10671 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10673 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10676 case 0xc: /* SQDMULH */
10678 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10681 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10685 case 0xd: /* SQRDMULH */
10687 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10690 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10695 g_assert_not_reached();
10699 write_fp_sreg(s
, rd
, tcg_res
);
10701 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10704 tcg_temp_free_i32(tcg_op
);
10705 tcg_temp_free_i32(tcg_res
);
10708 tcg_temp_free_i32(tcg_idx
);
10711 clear_vec_high(s
, rd
);
10714 /* long ops: 16x16->32 or 32x32->64 */
10715 TCGv_i64 tcg_res
[2];
10717 bool satop
= extract32(opcode
, 0, 1);
10718 TCGMemOp memop
= MO_32
;
10725 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10727 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10729 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10730 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10731 TCGv_i64 tcg_passres
;
10737 passelt
= pass
+ (is_q
* 2);
10740 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10742 tcg_res
[pass
] = tcg_temp_new_i64();
10744 if (opcode
== 0xa || opcode
== 0xb) {
10745 /* Non-accumulating ops */
10746 tcg_passres
= tcg_res
[pass
];
10748 tcg_passres
= tcg_temp_new_i64();
10751 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10752 tcg_temp_free_i64(tcg_op
);
10755 /* saturating, doubling */
10756 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10757 tcg_passres
, tcg_passres
);
10760 if (opcode
== 0xa || opcode
== 0xb) {
10764 /* Accumulating op: handle accumulate step */
10765 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10768 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10769 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10771 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10772 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10774 case 0x7: /* SQDMLSL, SQDMLSL2 */
10775 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10777 case 0x3: /* SQDMLAL, SQDMLAL2 */
10778 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10783 g_assert_not_reached();
10785 tcg_temp_free_i64(tcg_passres
);
10787 tcg_temp_free_i64(tcg_idx
);
10790 clear_vec_high(s
, rd
);
10793 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10796 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10799 /* The simplest way to handle the 16x16 indexed ops is to
10800 * duplicate the index into both halves of the 32 bit tcg_idx
10801 * and then use the usual Neon helpers.
10803 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10806 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10807 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10808 TCGv_i64 tcg_passres
;
10811 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10813 read_vec_element_i32(s
, tcg_op
, rn
,
10814 pass
+ (is_q
* 2), MO_32
);
10817 tcg_res
[pass
] = tcg_temp_new_i64();
10819 if (opcode
== 0xa || opcode
== 0xb) {
10820 /* Non-accumulating ops */
10821 tcg_passres
= tcg_res
[pass
];
10823 tcg_passres
= tcg_temp_new_i64();
10826 if (memop
& MO_SIGN
) {
10827 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10829 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10832 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10833 tcg_passres
, tcg_passres
);
10835 tcg_temp_free_i32(tcg_op
);
10837 if (opcode
== 0xa || opcode
== 0xb) {
10841 /* Accumulating op: handle accumulate step */
10842 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10845 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10846 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10849 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10850 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10853 case 0x7: /* SQDMLSL, SQDMLSL2 */
10854 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10856 case 0x3: /* SQDMLAL, SQDMLAL2 */
10857 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10862 g_assert_not_reached();
10864 tcg_temp_free_i64(tcg_passres
);
10866 tcg_temp_free_i32(tcg_idx
);
10869 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10874 tcg_res
[1] = tcg_const_i64(0);
10877 for (pass
= 0; pass
< 2; pass
++) {
10878 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10879 tcg_temp_free_i64(tcg_res
[pass
]);
10883 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10884 tcg_temp_free_ptr(fpst
);
10888 /* C3.6.19 Crypto AES
10889 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10890 * +-----------------+------+-----------+--------+-----+------+------+
10891 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10892 * +-----------------+------+-----------+--------+-----+------+------+
10894 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10896 int size
= extract32(insn
, 22, 2);
10897 int opcode
= extract32(insn
, 12, 5);
10898 int rn
= extract32(insn
, 5, 5);
10899 int rd
= extract32(insn
, 0, 5);
10901 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10902 CryptoThreeOpEnvFn
*genfn
;
10904 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10906 unallocated_encoding(s
);
10911 case 0x4: /* AESE */
10913 genfn
= gen_helper_crypto_aese
;
10915 case 0x6: /* AESMC */
10917 genfn
= gen_helper_crypto_aesmc
;
10919 case 0x5: /* AESD */
10921 genfn
= gen_helper_crypto_aese
;
10923 case 0x7: /* AESIMC */
10925 genfn
= gen_helper_crypto_aesmc
;
10928 unallocated_encoding(s
);
10932 /* Note that we convert the Vx register indexes into the
10933 * index within the vfp.regs[] array, so we can share the
10934 * helper with the AArch32 instructions.
10936 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10937 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10938 tcg_decrypt
= tcg_const_i32(decrypt
);
10940 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10942 tcg_temp_free_i32(tcg_rd_regno
);
10943 tcg_temp_free_i32(tcg_rn_regno
);
10944 tcg_temp_free_i32(tcg_decrypt
);
10947 /* C3.6.20 Crypto three-reg SHA
10948 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10949 * +-----------------+------+---+------+---+--------+-----+------+------+
10950 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10951 * +-----------------+------+---+------+---+--------+-----+------+------+
10953 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10955 int size
= extract32(insn
, 22, 2);
10956 int opcode
= extract32(insn
, 12, 3);
10957 int rm
= extract32(insn
, 16, 5);
10958 int rn
= extract32(insn
, 5, 5);
10959 int rd
= extract32(insn
, 0, 5);
10960 CryptoThreeOpEnvFn
*genfn
;
10961 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10962 int feature
= ARM_FEATURE_V8_SHA256
;
10965 unallocated_encoding(s
);
10970 case 0: /* SHA1C */
10971 case 1: /* SHA1P */
10972 case 2: /* SHA1M */
10973 case 3: /* SHA1SU0 */
10975 feature
= ARM_FEATURE_V8_SHA1
;
10977 case 4: /* SHA256H */
10978 genfn
= gen_helper_crypto_sha256h
;
10980 case 5: /* SHA256H2 */
10981 genfn
= gen_helper_crypto_sha256h2
;
10983 case 6: /* SHA256SU1 */
10984 genfn
= gen_helper_crypto_sha256su1
;
10987 unallocated_encoding(s
);
10991 if (!arm_dc_feature(s
, feature
)) {
10992 unallocated_encoding(s
);
10996 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10997 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10998 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11001 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11003 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11005 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11006 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11007 tcg_temp_free_i32(tcg_opcode
);
11010 tcg_temp_free_i32(tcg_rd_regno
);
11011 tcg_temp_free_i32(tcg_rn_regno
);
11012 tcg_temp_free_i32(tcg_rm_regno
);
11015 /* C3.6.21 Crypto two-reg SHA
11016 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11017 * +-----------------+------+-----------+--------+-----+------+------+
11018 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11019 * +-----------------+------+-----------+--------+-----+------+------+
11021 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11023 int size
= extract32(insn
, 22, 2);
11024 int opcode
= extract32(insn
, 12, 5);
11025 int rn
= extract32(insn
, 5, 5);
11026 int rd
= extract32(insn
, 0, 5);
11027 CryptoTwoOpEnvFn
*genfn
;
11029 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11032 unallocated_encoding(s
);
11037 case 0: /* SHA1H */
11038 feature
= ARM_FEATURE_V8_SHA1
;
11039 genfn
= gen_helper_crypto_sha1h
;
11041 case 1: /* SHA1SU1 */
11042 feature
= ARM_FEATURE_V8_SHA1
;
11043 genfn
= gen_helper_crypto_sha1su1
;
11045 case 2: /* SHA256SU0 */
11046 feature
= ARM_FEATURE_V8_SHA256
;
11047 genfn
= gen_helper_crypto_sha256su0
;
11050 unallocated_encoding(s
);
11054 if (!arm_dc_feature(s
, feature
)) {
11055 unallocated_encoding(s
);
11059 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11060 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11062 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11064 tcg_temp_free_i32(tcg_rd_regno
);
11065 tcg_temp_free_i32(tcg_rn_regno
);
11068 /* C3.6 Data processing - SIMD, inc Crypto
11070 * As the decode gets a little complex we are using a table based
11071 * approach for this part of the decode.
11073 static const AArch64DecodeTable data_proc_simd
[] = {
11074 /* pattern , mask , fn */
11075 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11076 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11077 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11078 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11079 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11080 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11081 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11082 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11083 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11084 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11085 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11086 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11087 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11088 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11089 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11090 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11091 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11092 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11093 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11094 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11095 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11096 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11097 { 0x00000000, 0x00000000, NULL
}
11100 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11102 /* Note that this is called with all non-FP cases from
11103 * table C3-6 so it must UNDEF for entries not specifically
11104 * allocated to instructions in that table.
11106 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11110 unallocated_encoding(s
);
11114 /* C3.6 Data processing - SIMD and floating point */
11115 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11117 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11118 disas_data_proc_fp(s
, insn
);
11120 /* SIMD, including crypto */
11121 disas_data_proc_simd(s
, insn
);
11125 /* C3.1 A64 instruction index by encoding */
11126 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11130 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11134 s
->fp_access_checked
= false;
11136 switch (extract32(insn
, 25, 4)) {
11137 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11138 unallocated_encoding(s
);
11140 case 0x8: case 0x9: /* Data processing - immediate */
11141 disas_data_proc_imm(s
, insn
);
11143 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11144 disas_b_exc_sys(s
, insn
);
11149 case 0xe: /* Loads and stores */
11150 disas_ldst(s
, insn
);
11153 case 0xd: /* Data processing - register */
11154 disas_data_proc_reg(s
, insn
);
11157 case 0xf: /* Data processing - SIMD and floating point */
11158 disas_data_proc_simd_fp(s
, insn
);
11161 assert(FALSE
); /* all 15 cases should be handled above */
11165 /* if we allocated any temporaries, free them here */
11169 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11171 CPUState
*cs
= CPU(cpu
);
11172 CPUARMState
*env
= &cpu
->env
;
11173 DisasContext dc1
, *dc
= &dc1
;
11174 target_ulong pc_start
;
11175 target_ulong next_page_start
;
11183 dc
->is_jmp
= DISAS_NEXT
;
11185 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11189 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11190 * there is no secure EL1, so we route exceptions to EL3.
11192 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11193 !arm_el_is_aa64(env
, 3);
11196 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11197 dc
->condexec_mask
= 0;
11198 dc
->condexec_cond
= 0;
11199 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11200 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11201 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11202 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11203 #if !defined(CONFIG_USER_ONLY)
11204 dc
->user
= (dc
->current_el
== 0);
11206 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11208 dc
->vec_stride
= 0;
11209 dc
->cp_regs
= cpu
->cp_regs
;
11210 dc
->features
= env
->features
;
11212 /* Single step state. The code-generation logic here is:
11214 * generate code with no special handling for single-stepping (except
11215 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11216 * this happens anyway because those changes are all system register or
11218 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11219 * emit code for one insn
11220 * emit code to clear PSTATE.SS
11221 * emit code to generate software step exception for completed step
11222 * end TB (as usual for having generated an exception)
11223 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11224 * emit code to generate a software step exception
11227 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11228 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11229 dc
->is_ldex
= false;
11230 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11232 init_tmp_a64_array(dc
);
11234 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11236 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11237 if (max_insns
== 0) {
11238 max_insns
= CF_COUNT_MASK
;
11240 if (max_insns
> TCG_MAX_INSNS
) {
11241 max_insns
= TCG_MAX_INSNS
;
11246 tcg_clear_temp_count();
11249 dc
->insn_start_idx
= tcg_op_buf_count();
11250 tcg_gen_insn_start(dc
->pc
, 0, 0);
11253 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11255 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11256 if (bp
->pc
== dc
->pc
) {
11257 if (bp
->flags
& BP_CPU
) {
11258 gen_a64_set_pc_im(dc
->pc
);
11259 gen_helper_check_breakpoints(cpu_env
);
11260 /* End the TB early; it likely won't be executed */
11261 dc
->is_jmp
= DISAS_UPDATE
;
11263 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11264 /* The address covered by the breakpoint must be
11265 included in [tb->pc, tb->pc + tb->size) in order
11266 to for it to be properly cleared -- thus we
11267 increment the PC here so that the logic setting
11268 tb->size below does the right thing. */
11270 goto done_generating
;
11277 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11281 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11282 /* Singlestep state is Active-pending.
11283 * If we're in this state at the start of a TB then either
11284 * a) we just took an exception to an EL which is being debugged
11285 * and this is the first insn in the exception handler
11286 * b) debug exceptions were masked and we just unmasked them
11287 * without changing EL (eg by clearing PSTATE.D)
11288 * In either case we're going to take a swstep exception in the
11289 * "did not step an insn" case, and so the syndrome ISV and EX
11290 * bits should be zero.
11292 assert(num_insns
== 1);
11293 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11294 default_exception_el(dc
));
11295 dc
->is_jmp
= DISAS_EXC
;
11299 disas_a64_insn(env
, dc
);
11301 if (tcg_check_temp_count()) {
11302 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11306 /* Translation stops when a conditional branch is encountered.
11307 * Otherwise the subsequent code could get translated several times.
11308 * Also stop translation when a page boundary is reached. This
11309 * ensures prefetch aborts occur at the right place.
11311 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11312 !cs
->singlestep_enabled
&&
11315 dc
->pc
< next_page_start
&&
11316 num_insns
< max_insns
);
11318 if (tb
->cflags
& CF_LAST_IO
) {
11322 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11323 && dc
->is_jmp
!= DISAS_EXC
) {
11324 /* Note that this means single stepping WFI doesn't halt the CPU.
11325 * For conditional branch insns this is harmless unreachable code as
11326 * gen_goto_tb() has already handled emitting the debug exception
11327 * (and thus a tb-jump is not possible when singlestepping).
11329 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11330 if (dc
->is_jmp
!= DISAS_JUMP
) {
11331 gen_a64_set_pc_im(dc
->pc
);
11333 if (cs
->singlestep_enabled
) {
11334 gen_exception_internal(EXCP_DEBUG
);
11336 gen_step_complete_exception(dc
);
11339 switch (dc
->is_jmp
) {
11341 gen_goto_tb(dc
, 1, dc
->pc
);
11345 gen_a64_set_pc_im(dc
->pc
);
11348 /* indicate that the hash table must be used to find the next TB */
11349 tcg_gen_exit_tb(0);
11351 case DISAS_TB_JUMP
:
11356 gen_a64_set_pc_im(dc
->pc
);
11357 gen_helper_wfe(cpu_env
);
11360 gen_a64_set_pc_im(dc
->pc
);
11361 gen_helper_yield(cpu_env
);
11364 /* This is a special case because we don't want to just halt the CPU
11365 * if trying to debug across a WFI.
11367 gen_a64_set_pc_im(dc
->pc
);
11368 gen_helper_wfi(cpu_env
);
11369 /* The helper doesn't necessarily throw an exception, but we
11370 * must go back to the main loop to check for interrupts anyway.
11372 tcg_gen_exit_tb(0);
11378 gen_tb_end(tb
, num_insns
);
11381 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11382 qemu_log_in_addr_range(pc_start
)) {
11384 qemu_log("----------------\n");
11385 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11386 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11387 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11392 tb
->size
= dc
->pc
- pc_start
;
11393 tb
->icount
= num_insns
;