esp: latch individual bits in ESP_RINTR register
[qemu/ar7.git] / target / microblaze / cpu-qom.h
blobe520eefb127e871ffa934ddd1f78e2198fa2d3af
1 /*
2 * QEMU MicroBlaze CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 #ifndef QEMU_MICROBLAZE_CPU_QOM_H
21 #define QEMU_MICROBLAZE_CPU_QOM_H
23 #include "hw/core/cpu.h"
24 #include "qom/object.h"
26 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
28 OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
29 MICROBLAZE_CPU)
31 /**
32 * MicroBlazeCPUClass:
33 * @parent_realize: The parent class' realize handler.
34 * @parent_reset: The parent class' reset handler.
36 * A MicroBlaze CPU model.
38 struct MicroBlazeCPUClass {
39 /*< private >*/
40 CPUClass parent_class;
41 /*< public >*/
43 DeviceRealize parent_realize;
44 DeviceReset parent_reset;
48 #endif