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ssdt-tpm: add generated hex file to git
[qemu/ar7.git] / target-ppc / translate.c
blobc07bb01a7af574cdb5226f93416dfc661432fa3b
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 TCGMemOp default_tcg_memop_mask;
197 #if defined(TARGET_PPC64)
198 int sf_mode;
199 int has_cfar;
200 #endif
201 int fpu_enabled;
202 int altivec_enabled;
203 int vsx_enabled;
204 int spe_enabled;
205 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
206 int singlestep_enabled;
207 uint64_t insns_flags;
208 uint64_t insns_flags2;
209 } DisasContext;
210
211 /* Return true iff byteswap is needed in a scalar memop */
212 static inline bool need_byteswap(const DisasContext *ctx)
213 {
214 #if defined(TARGET_WORDS_BIGENDIAN)
215 return ctx->le_mode;
216 #else
217 return !ctx->le_mode;
218 #endif
219 }
220
221 /* True when active word size < size of target_long. */
222 #ifdef TARGET_PPC64
223 # define NARROW_MODE(C) (!(C)->sf_mode)
224 #else
225 # define NARROW_MODE(C) 0
226 #endif
227
228 struct opc_handler_t {
229 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
230 uint32_t inval1;
231 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
232 uint32_t inval2;
233 /* instruction type */
234 uint64_t type;
235 /* extended instruction type */
236 uint64_t type2;
237 /* handler */
238 void (*handler)(DisasContext *ctx);
239 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
240 const char *oname;
241 #endif
242 #if defined(DO_PPC_STATISTICS)
243 uint64_t count;
244 #endif
245 };
246
247 static inline void gen_reset_fpstatus(void)
248 {
249 gen_helper_reset_fpstatus(cpu_env);
250 }
251
252 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
253 {
254 TCGv_i32 t0 = tcg_temp_new_i32();
255
256 if (set_fprf != 0) {
257 /* This case might be optimized later */
258 tcg_gen_movi_i32(t0, 1);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 if (unlikely(set_rc)) {
261 tcg_gen_mov_i32(cpu_crf[1], t0);
262 }
263 gen_helper_float_check_status(cpu_env);
264 } else if (unlikely(set_rc)) {
265 /* We always need to compute fpcc */
266 tcg_gen_movi_i32(t0, 0);
267 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
268 tcg_gen_mov_i32(cpu_crf[1], t0);
269 }
270
271 tcg_temp_free_i32(t0);
272 }
273
274 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
275 {
276 if (ctx->access_type != access_type) {
277 tcg_gen_movi_i32(cpu_access_type, access_type);
278 ctx->access_type = access_type;
279 }
280 }
281
282 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
283 {
284 if (NARROW_MODE(ctx)) {
285 nip = (uint32_t)nip;
286 }
287 tcg_gen_movi_tl(cpu_nip, nip);
288 }
289
290 void gen_update_current_nip(void *opaque)
291 {
292 DisasContext *ctx = opaque;
293
294 tcg_gen_movi_tl(cpu_nip, ctx->nip);
295 }
296
297 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
298 {
299 TCGv_i32 t0, t1;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
304 t1 = tcg_const_i32(error);
305 gen_helper_raise_exception_err(cpu_env, t0, t1);
306 tcg_temp_free_i32(t0);
307 tcg_temp_free_i32(t1);
308 ctx->exception = (excp);
309 }
310
311 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
312 {
313 TCGv_i32 t0;
314 if (ctx->exception == POWERPC_EXCP_NONE) {
315 gen_update_nip(ctx, ctx->nip);
316 }
317 t0 = tcg_const_i32(excp);
318 gen_helper_raise_exception(cpu_env, t0);
319 tcg_temp_free_i32(t0);
320 ctx->exception = (excp);
321 }
322
323 static inline void gen_debug_exception(DisasContext *ctx)
324 {
325 TCGv_i32 t0;
326
327 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
328 (ctx->exception != POWERPC_EXCP_SYNC)) {
329 gen_update_nip(ctx, ctx->nip);
330 }
331 t0 = tcg_const_i32(EXCP_DEBUG);
332 gen_helper_raise_exception(cpu_env, t0);
333 tcg_temp_free_i32(t0);
334 }
335
336 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
337 {
338 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
339 }
340
341 /* Stop translation */
342 static inline void gen_stop_exception(DisasContext *ctx)
343 {
344 gen_update_nip(ctx, ctx->nip);
345 ctx->exception = POWERPC_EXCP_STOP;
346 }
347
348 /* No need to update nip here, as execution flow will change */
349 static inline void gen_sync_exception(DisasContext *ctx)
350 {
351 ctx->exception = POWERPC_EXCP_SYNC;
352 }
353
354 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
355 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
356
357 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
358 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
359
360 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
361 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
362
363 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
364 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
365
366 typedef struct opcode_t {
367 unsigned char opc1, opc2, opc3;
368 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
369 unsigned char pad[5];
370 #else
371 unsigned char pad[1];
372 #endif
373 opc_handler_t handler;
374 const char *oname;
375 } opcode_t;
376
377 /*****************************************************************************/
378 /*** Instruction decoding ***/
379 #define EXTRACT_HELPER(name, shift, nb) \
380 static inline uint32_t name(uint32_t opcode) \
381 { \
382 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
383 }
384
385 #define EXTRACT_SHELPER(name, shift, nb) \
386 static inline int32_t name(uint32_t opcode) \
387 { \
388 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
389 }
390
391 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
392 static inline uint32_t name(uint32_t opcode) \
393 { \
394 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
395 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
396 }
397 /* Opcode part 1 */
398 EXTRACT_HELPER(opc1, 26, 6);
399 /* Opcode part 2 */
400 EXTRACT_HELPER(opc2, 1, 5);
401 /* Opcode part 3 */
402 EXTRACT_HELPER(opc3, 6, 5);
403 /* Update Cr0 flags */
404 EXTRACT_HELPER(Rc, 0, 1);
405 /* Update Cr6 flags (Altivec) */
406 EXTRACT_HELPER(Rc21, 10, 1);
407 /* Destination */
408 EXTRACT_HELPER(rD, 21, 5);
409 /* Source */
410 EXTRACT_HELPER(rS, 21, 5);
411 /* First operand */
412 EXTRACT_HELPER(rA, 16, 5);
413 /* Second operand */
414 EXTRACT_HELPER(rB, 11, 5);
415 /* Third operand */
416 EXTRACT_HELPER(rC, 6, 5);
417 /*** Get CRn ***/
418 EXTRACT_HELPER(crfD, 23, 3);
419 EXTRACT_HELPER(crfS, 18, 3);
420 EXTRACT_HELPER(crbD, 21, 5);
421 EXTRACT_HELPER(crbA, 16, 5);
422 EXTRACT_HELPER(crbB, 11, 5);
423 /* SPR / TBL */
424 EXTRACT_HELPER(_SPR, 11, 10);
425 static inline uint32_t SPR(uint32_t opcode)
426 {
427 uint32_t sprn = _SPR(opcode);
428
429 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
430 }
431 /*** Get constants ***/
432 /* 16 bits signed immediate value */
433 EXTRACT_SHELPER(SIMM, 0, 16);
434 /* 16 bits unsigned immediate value */
435 EXTRACT_HELPER(UIMM, 0, 16);
436 /* 5 bits signed immediate value */
437 EXTRACT_HELPER(SIMM5, 16, 5);
438 /* 5 bits signed immediate value */
439 EXTRACT_HELPER(UIMM5, 16, 5);
440 /* Bit count */
441 EXTRACT_HELPER(NB, 11, 5);
442 /* Shift count */
443 EXTRACT_HELPER(SH, 11, 5);
444 /* Vector shift count */
445 EXTRACT_HELPER(VSH, 6, 4);
446 /* Mask start */
447 EXTRACT_HELPER(MB, 6, 5);
448 /* Mask end */
449 EXTRACT_HELPER(ME, 1, 5);
450 /* Trap operand */
451 EXTRACT_HELPER(TO, 21, 5);
452
453 EXTRACT_HELPER(CRM, 12, 8);
454 EXTRACT_HELPER(SR, 16, 4);
455
456 /* mtfsf/mtfsfi */
457 EXTRACT_HELPER(FPBF, 23, 3);
458 EXTRACT_HELPER(FPIMM, 12, 4);
459 EXTRACT_HELPER(FPL, 25, 1);
460 EXTRACT_HELPER(FPFLM, 17, 8);
461 EXTRACT_HELPER(FPW, 16, 1);
462
463 /*** Jump target decoding ***/
464 /* Immediate address */
465 static inline target_ulong LI(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0x03FFFFFC;
468 }
469
470 static inline uint32_t BD(uint32_t opcode)
471 {
472 return (opcode >> 0) & 0xFFFC;
473 }
474
475 EXTRACT_HELPER(BO, 21, 5);
476 EXTRACT_HELPER(BI, 16, 5);
477 /* Absolute/relative address */
478 EXTRACT_HELPER(AA, 1, 1);
479 /* Link */
480 EXTRACT_HELPER(LK, 0, 1);
481
482 /* DFP Z22-form */
483 EXTRACT_HELPER(DCM, 10, 6)
484
485 /* DFP Z23-form */
486 EXTRACT_HELPER(RMC, 9, 2)
487
488 /* Create a mask between <start> and <end> bits */
489 static inline target_ulong MASK(uint32_t start, uint32_t end)
490 {
491 target_ulong ret;
492
493 #if defined(TARGET_PPC64)
494 if (likely(start == 0)) {
495 ret = UINT64_MAX << (63 - end);
496 } else if (likely(end == 63)) {
497 ret = UINT64_MAX >> start;
498 }
499 #else
500 if (likely(start == 0)) {
501 ret = UINT32_MAX << (31 - end);
502 } else if (likely(end == 31)) {
503 ret = UINT32_MAX >> start;
504 }
505 #endif
506 else {
507 ret = (((target_ulong)(-1ULL)) >> (start)) ^
508 (((target_ulong)(-1ULL) >> (end)) >> 1);
509 if (unlikely(start > end))
510 return ~ret;
511 }
512
513 return ret;
514 }
515
516 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
517 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
518 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
519 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
520 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
521 EXTRACT_HELPER(DM, 8, 2);
522 EXTRACT_HELPER(UIM, 16, 2);
523 EXTRACT_HELPER(SHW, 8, 2);
524 EXTRACT_HELPER(SP, 19, 2);
525 /*****************************************************************************/
526 /* PowerPC instructions table */
527
528 #if defined(DO_PPC_STATISTICS)
529 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .pad = { 0, }, \
535 .handler = { \
536 .inval1 = invl, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 .oname = stringify(name), \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 .oname = stringify(name), \
557 }, \
558 .oname = stringify(name), \
559 }
560 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
561 { \
562 .opc1 = op1, \
563 .opc2 = op2, \
564 .opc3 = op3, \
565 .pad = { 0, }, \
566 .handler = { \
567 .inval1 = invl, \
568 .type = _typ, \
569 .type2 = _typ2, \
570 .handler = &gen_##name, \
571 .oname = onam, \
572 }, \
573 .oname = onam, \
574 }
575 #else
576 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
577 { \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl, \
584 .type = _typ, \
585 .type2 = _typ2, \
586 .handler = &gen_##name, \
587 }, \
588 .oname = stringify(name), \
589 }
590 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
591 { \
592 .opc1 = op1, \
593 .opc2 = op2, \
594 .opc3 = op3, \
595 .pad = { 0, }, \
596 .handler = { \
597 .inval1 = invl1, \
598 .inval2 = invl2, \
599 .type = _typ, \
600 .type2 = _typ2, \
601 .handler = &gen_##name, \
602 }, \
603 .oname = stringify(name), \
604 }
605 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
606 { \
607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
610 .pad = { 0, }, \
611 .handler = { \
612 .inval1 = invl, \
613 .type = _typ, \
614 .type2 = _typ2, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618 }
619 #endif
620
621 /* SPR load/store helpers */
622 static inline void gen_load_spr(TCGv t, int reg)
623 {
624 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 static inline void gen_store_spr(int reg, TCGv t)
628 {
629 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
630 }
631
632 /* Invalid instruction */
633 static void gen_invalid(DisasContext *ctx)
634 {
635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
636 }
637
638 static opc_handler_t invalid_handler = {
639 .inval1 = 0xFFFFFFFF,
640 .inval2 = 0xFFFFFFFF,
641 .type = PPC_NONE,
642 .type2 = PPC_NONE,
643 .handler = gen_invalid,
644 };
645
646 #if defined(TARGET_PPC64)
647 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
648 /* so the function is wrapped in the standard 64-bit ifdef in order to */
649 /* avoid compiler warnings in 32-bit implementations. */
650 static bool is_user_mode(DisasContext *ctx)
651 {
652 #if defined(CONFIG_USER_ONLY)
653 return true;
654 #else
655 return ctx->mem_idx == 0;
656 #endif
657 }
658 #endif
659
660 /*** Integer comparison ***/
661
662 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
663 {
664 TCGv t0 = tcg_temp_new();
665 TCGv_i32 t1 = tcg_temp_new_i32();
666
667 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
668
669 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
670 tcg_gen_trunc_tl_i32(t1, t0);
671 tcg_gen_shli_i32(t1, t1, CRF_LT);
672 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
673
674 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
675 tcg_gen_trunc_tl_i32(t1, t0);
676 tcg_gen_shli_i32(t1, t1, CRF_GT);
677 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
678
679 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
680 tcg_gen_trunc_tl_i32(t1, t0);
681 tcg_gen_shli_i32(t1, t1, CRF_EQ);
682 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
683
684 tcg_temp_free(t0);
685 tcg_temp_free_i32(t1);
686 }
687
688 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
689 {
690 TCGv t0 = tcg_const_tl(arg1);
691 gen_op_cmp(arg0, t0, s, crf);
692 tcg_temp_free(t0);
693 }
694
695 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
696 {
697 TCGv t0, t1;
698 t0 = tcg_temp_new();
699 t1 = tcg_temp_new();
700 if (s) {
701 tcg_gen_ext32s_tl(t0, arg0);
702 tcg_gen_ext32s_tl(t1, arg1);
703 } else {
704 tcg_gen_ext32u_tl(t0, arg0);
705 tcg_gen_ext32u_tl(t1, arg1);
706 }
707 gen_op_cmp(t0, t1, s, crf);
708 tcg_temp_free(t1);
709 tcg_temp_free(t0);
710 }
711
712 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
713 {
714 TCGv t0 = tcg_const_tl(arg1);
715 gen_op_cmp32(arg0, t0, s, crf);
716 tcg_temp_free(t0);
717 }
718
719 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
720 {
721 if (NARROW_MODE(ctx)) {
722 gen_op_cmpi32(reg, 0, 1, 0);
723 } else {
724 gen_op_cmpi(reg, 0, 1, 0);
725 }
726 }
727
728 /* cmp */
729 static void gen_cmp(DisasContext *ctx)
730 {
731 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
732 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
733 1, crfD(ctx->opcode));
734 } else {
735 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 1, crfD(ctx->opcode));
737 }
738 }
739
740 /* cmpi */
741 static void gen_cmpi(DisasContext *ctx)
742 {
743 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
744 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
745 1, crfD(ctx->opcode));
746 } else {
747 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
748 1, crfD(ctx->opcode));
749 }
750 }
751
752 /* cmpl */
753 static void gen_cmpl(DisasContext *ctx)
754 {
755 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
756 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
757 0, crfD(ctx->opcode));
758 } else {
759 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 0, crfD(ctx->opcode));
761 }
762 }
763
764 /* cmpli */
765 static void gen_cmpli(DisasContext *ctx)
766 {
767 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
768 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
769 0, crfD(ctx->opcode));
770 } else {
771 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
772 0, crfD(ctx->opcode));
773 }
774 }
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 int l1, l2;
780 uint32_t bi = rC(ctx->opcode);
781 uint32_t mask;
782 TCGv_i32 t0;
783
784 l1 = gen_new_label();
785 l2 = gen_new_label();
786
787 mask = 1 << (3 - (bi & 0x03));
788 t0 = tcg_temp_new_i32();
789 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
790 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
791 if (rA(ctx->opcode) == 0)
792 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
793 else
794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
795 tcg_gen_br(l2);
796 gen_set_label(l1);
797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
798 gen_set_label(l2);
799 tcg_temp_free_i32(t0);
800 }
801
802 /* cmpb: PowerPC 2.05 specification */
803 static void gen_cmpb(DisasContext *ctx)
804 {
805 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
806 cpu_gpr[rB(ctx->opcode)]);
807 }
808
809 /*** Integer arithmetic ***/
810
811 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
812 TCGv arg1, TCGv arg2, int sub)
813 {
814 TCGv t0 = tcg_temp_new();
815
816 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
817 tcg_gen_xor_tl(t0, arg1, arg2);
818 if (sub) {
819 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
820 } else {
821 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
822 }
823 tcg_temp_free(t0);
824 if (NARROW_MODE(ctx)) {
825 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
826 }
827 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 /* Common add function */
832 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
833 TCGv arg2, bool add_ca, bool compute_ca,
834 bool compute_ov, bool compute_rc0)
835 {
836 TCGv t0 = ret;
837
838 if (compute_ca || compute_ov) {
839 t0 = tcg_temp_new();
840 }
841
842 if (compute_ca) {
843 if (NARROW_MODE(ctx)) {
844 /* Caution: a non-obvious corner case of the spec is that we
845 must produce the *entire* 64-bit addition, but produce the
846 carry into bit 32. */
847 TCGv t1 = tcg_temp_new();
848 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
854 tcg_temp_free(t1);
855 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
856 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
857 } else {
858 TCGv zero = tcg_const_tl(0);
859 if (add_ca) {
860 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
861 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
862 } else {
863 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
864 }
865 tcg_temp_free(zero);
866 }
867 } else {
868 tcg_gen_add_tl(t0, arg1, arg2);
869 if (add_ca) {
870 tcg_gen_add_tl(t0, t0, cpu_ca);
871 }
872 }
873
874 if (compute_ov) {
875 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
876 }
877 if (unlikely(compute_rc0)) {
878 gen_set_Rc0(ctx, t0);
879 }
880
881 if (!TCGV_EQUAL(t0, ret)) {
882 tcg_gen_mov_tl(ret, t0);
883 tcg_temp_free(t0);
884 }
885 }
886 /* Add functions with two operands */
887 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
888 static void glue(gen_, name)(DisasContext *ctx) \
889 { \
890 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
891 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
892 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
893 }
894 /* Add functions with one operand and one immediate */
895 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
896 add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 TCGv t0 = tcg_const_tl(const_val); \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], t0, \
902 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
903 tcg_temp_free(t0); \
904 }
905
906 /* add add. addo addo. */
907 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
908 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
909 /* addc addc. addco addco. */
910 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
911 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
912 /* adde adde. addeo addeo. */
913 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
914 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
915 /* addme addme. addmeo addmeo. */
916 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
917 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
918 /* addze addze. addzeo addzeo.*/
919 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
920 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
921 /* addi */
922 static void gen_addi(DisasContext *ctx)
923 {
924 target_long simm = SIMM(ctx->opcode);
925
926 if (rA(ctx->opcode) == 0) {
927 /* li case */
928 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
929 } else {
930 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
931 cpu_gpr[rA(ctx->opcode)], simm);
932 }
933 }
934 /* addic addic.*/
935 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
936 {
937 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
938 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
939 c, 0, 1, 0, compute_rc0);
940 tcg_temp_free(c);
941 }
942
943 static void gen_addic(DisasContext *ctx)
944 {
945 gen_op_addic(ctx, 0);
946 }
947
948 static void gen_addic_(DisasContext *ctx)
949 {
950 gen_op_addic(ctx, 1);
951 }
952
953 /* addis */
954 static void gen_addis(DisasContext *ctx)
955 {
956 target_long simm = SIMM(ctx->opcode);
957
958 if (rA(ctx->opcode) == 0) {
959 /* lis case */
960 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
961 } else {
962 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
963 cpu_gpr[rA(ctx->opcode)], simm << 16);
964 }
965 }
966
967 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
968 TCGv arg2, int sign, int compute_ov)
969 {
970 int l1 = gen_new_label();
971 int l2 = gen_new_label();
972 TCGv_i32 t0 = tcg_temp_local_new_i32();
973 TCGv_i32 t1 = tcg_temp_local_new_i32();
974
975 tcg_gen_trunc_tl_i32(t0, arg1);
976 tcg_gen_trunc_tl_i32(t1, arg2);
977 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
978 if (sign) {
979 int l3 = gen_new_label();
980 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
981 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
982 gen_set_label(l3);
983 tcg_gen_div_i32(t0, t0, t1);
984 } else {
985 tcg_gen_divu_i32(t0, t0, t1);
986 }
987 if (compute_ov) {
988 tcg_gen_movi_tl(cpu_ov, 0);
989 }
990 tcg_gen_br(l2);
991 gen_set_label(l1);
992 if (sign) {
993 tcg_gen_sari_i32(t0, t0, 31);
994 } else {
995 tcg_gen_movi_i32(t0, 0);
996 }
997 if (compute_ov) {
998 tcg_gen_movi_tl(cpu_ov, 1);
999 tcg_gen_movi_tl(cpu_so, 1);
1000 }
1001 gen_set_label(l2);
1002 tcg_gen_extu_i32_tl(ret, t0);
1003 tcg_temp_free_i32(t0);
1004 tcg_temp_free_i32(t1);
1005 if (unlikely(Rc(ctx->opcode) != 0))
1006 gen_set_Rc0(ctx, ret);
1007 }
1008 /* Div functions */
1009 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 sign, compute_ov); \
1015 }
1016 /* divwu divwu. divwuo divwuo. */
1017 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1018 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1019 /* divw divw. divwo divwo. */
1020 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1021 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1022
1023 /* div[wd]eu[o][.] */
1024 #define GEN_DIVE(name, hlpr, compute_ov) \
1025 static void gen_##name(DisasContext *ctx) \
1026 { \
1027 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1028 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1030 tcg_temp_free_i32(t0); \
1031 if (unlikely(Rc(ctx->opcode) != 0)) { \
1032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1033 } \
1034 }
1035
1036 GEN_DIVE(divweu, divweu, 0);
1037 GEN_DIVE(divweuo, divweu, 1);
1038 GEN_DIVE(divwe, divwe, 0);
1039 GEN_DIVE(divweo, divwe, 1);
1040
1041 #if defined(TARGET_PPC64)
1042 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1043 TCGv arg2, int sign, int compute_ov)
1044 {
1045 int l1 = gen_new_label();
1046 int l2 = gen_new_label();
1047
1048 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1049 if (sign) {
1050 int l3 = gen_new_label();
1051 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1052 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1053 gen_set_label(l3);
1054 tcg_gen_div_i64(ret, arg1, arg2);
1055 } else {
1056 tcg_gen_divu_i64(ret, arg1, arg2);
1057 }
1058 if (compute_ov) {
1059 tcg_gen_movi_tl(cpu_ov, 0);
1060 }
1061 tcg_gen_br(l2);
1062 gen_set_label(l1);
1063 if (sign) {
1064 tcg_gen_sari_i64(ret, arg1, 63);
1065 } else {
1066 tcg_gen_movi_i64(ret, 0);
1067 }
1068 if (compute_ov) {
1069 tcg_gen_movi_tl(cpu_ov, 1);
1070 tcg_gen_movi_tl(cpu_so, 1);
1071 }
1072 gen_set_label(l2);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, ret);
1075 }
1076 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1077 static void glue(gen_, name)(DisasContext *ctx) \
1078 { \
1079 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1081 sign, compute_ov); \
1082 }
1083 /* divwu divwu. divwuo divwuo. */
1084 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1085 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1086 /* divw divw. divwo divwo. */
1087 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1088 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1089
1090 GEN_DIVE(divdeu, divdeu, 0);
1091 GEN_DIVE(divdeuo, divdeu, 1);
1092 GEN_DIVE(divde, divde, 0);
1093 GEN_DIVE(divdeo, divde, 1);
1094 #endif
1095
1096 /* mulhw mulhw. */
1097 static void gen_mulhw(DisasContext *ctx)
1098 {
1099 TCGv_i32 t0 = tcg_temp_new_i32();
1100 TCGv_i32 t1 = tcg_temp_new_i32();
1101
1102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1103 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1104 tcg_gen_muls2_i32(t0, t1, t0, t1);
1105 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1106 tcg_temp_free_i32(t0);
1107 tcg_temp_free_i32(t1);
1108 if (unlikely(Rc(ctx->opcode) != 0))
1109 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1110 }
1111
1112 /* mulhwu mulhwu. */
1113 static void gen_mulhwu(DisasContext *ctx)
1114 {
1115 TCGv_i32 t0 = tcg_temp_new_i32();
1116 TCGv_i32 t1 = tcg_temp_new_i32();
1117
1118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1119 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1120 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1121 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1122 tcg_temp_free_i32(t0);
1123 tcg_temp_free_i32(t1);
1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1126 }
1127
1128 /* mullw mullw. */
1129 static void gen_mullw(DisasContext *ctx)
1130 {
1131 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1132 cpu_gpr[rB(ctx->opcode)]);
1133 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1136 }
1137
1138 /* mullwo mullwo. */
1139 static void gen_mullwo(DisasContext *ctx)
1140 {
1141 TCGv_i32 t0 = tcg_temp_new_i32();
1142 TCGv_i32 t1 = tcg_temp_new_i32();
1143
1144 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1145 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1146 tcg_gen_muls2_i32(t0, t1, t0, t1);
1147 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1148
1149 tcg_gen_sari_i32(t0, t0, 31);
1150 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1151 tcg_gen_extu_i32_tl(cpu_ov, t0);
1152 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1153
1154 tcg_temp_free_i32(t0);
1155 tcg_temp_free_i32(t1);
1156 if (unlikely(Rc(ctx->opcode) != 0))
1157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1158 }
1159
1160 /* mulli */
1161 static void gen_mulli(DisasContext *ctx)
1162 {
1163 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1164 SIMM(ctx->opcode));
1165 }
1166
1167 #if defined(TARGET_PPC64)
1168 /* mulhd mulhd. */
1169 static void gen_mulhd(DisasContext *ctx)
1170 {
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178 }
1179
1180 /* mulhdu mulhdu. */
1181 static void gen_mulhdu(DisasContext *ctx)
1182 {
1183 TCGv lo = tcg_temp_new();
1184 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1185 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1186 tcg_temp_free(lo);
1187 if (unlikely(Rc(ctx->opcode) != 0)) {
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 }
1191
1192 /* mulld mulld. */
1193 static void gen_mulld(DisasContext *ctx)
1194 {
1195 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 if (unlikely(Rc(ctx->opcode) != 0))
1198 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1199 }
1200
1201 /* mulldo mulldo. */
1202 static void gen_mulldo(DisasContext *ctx)
1203 {
1204 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209 }
1210 #endif
1211
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
1216 {
1217 TCGv t0 = ret;
1218
1219 if (compute_ca || compute_ov) {
1220 t0 = tcg_temp_new();
1221 }
1222
1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1 = tcg_temp_new();
1230 TCGv t1 = tcg_temp_new();
1231 tcg_gen_not_tl(inv1, arg1);
1232 if (add_ca) {
1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
1234 } else {
1235 tcg_gen_addi_tl(t0, arg2, 1);
1236 }
1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1238 tcg_gen_add_tl(t0, t0, inv1);
1239 tcg_temp_free(inv1);
1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1244 } else if (add_ca) {
1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1250 tcg_temp_free(zero);
1251 tcg_temp_free(inv1);
1252 } else {
1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1254 tcg_gen_sub_tl(t0, arg2, arg1);
1255 }
1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
1262 } else {
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 }
1265
1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
1269 if (unlikely(compute_rc0)) {
1270 gen_set_Rc0(ctx, t0);
1271 }
1272
1273 if (!TCGV_EQUAL(t0, ret)) {
1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
1276 }
1277 }
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1281 { \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1285 }
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1290 { \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1296 }
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1312
1313 /* subfic */
1314 static void gen_subfic(DisasContext *ctx)
1315 {
1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
1320 }
1321
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324 {
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329 }
1330
1331 static void gen_neg(DisasContext *ctx)
1332 {
1333 gen_op_arith_neg(ctx, 0);
1334 }
1335
1336 static void gen_nego(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 1);
1339 }
1340
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1344 { \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1349 }
1350
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1353 { \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1357 }
1358
1359 /* and & and. */
1360 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1361 /* andc & andc. */
1362 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1363
1364 /* andi. */
1365 static void gen_andi_(DisasContext *ctx)
1366 {
1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1369 }
1370
1371 /* andis. */
1372 static void gen_andis_(DisasContext *ctx)
1373 {
1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* cntlzw */
1379 static void gen_cntlzw(DisasContext *ctx)
1380 {
1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385 /* eqv & eqv. */
1386 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1391 /* nand & nand. */
1392 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1393 /* nor & nor. */
1394 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1395
1396 /* or & or. */
1397 static void gen_or(DisasContext *ctx)
1398 {
1399 int rs, ra, rb;
1400
1401 rs = rS(ctx->opcode);
1402 ra = rA(ctx->opcode);
1403 rb = rB(ctx->opcode);
1404 /* Optimisation for mr. ri case */
1405 if (rs != ra || rs != rb) {
1406 if (rs != rb)
1407 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1408 else
1409 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1410 if (unlikely(Rc(ctx->opcode) != 0))
1411 gen_set_Rc0(ctx, cpu_gpr[ra]);
1412 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1413 gen_set_Rc0(ctx, cpu_gpr[rs]);
1414 #if defined(TARGET_PPC64)
1415 } else {
1416 int prio = 0;
1417
1418 switch (rs) {
1419 case 1:
1420 /* Set process priority to low */
1421 prio = 2;
1422 break;
1423 case 6:
1424 /* Set process priority to medium-low */
1425 prio = 3;
1426 break;
1427 case 2:
1428 /* Set process priority to normal */
1429 prio = 4;
1430 break;
1431 #if !defined(CONFIG_USER_ONLY)
1432 case 31:
1433 if (ctx->mem_idx > 0) {
1434 /* Set process priority to very low */
1435 prio = 1;
1436 }
1437 break;
1438 case 5:
1439 if (ctx->mem_idx > 0) {
1440 /* Set process priority to medium-hight */
1441 prio = 5;
1442 }
1443 break;
1444 case 3:
1445 if (ctx->mem_idx > 0) {
1446 /* Set process priority to high */
1447 prio = 6;
1448 }
1449 break;
1450 case 7:
1451 if (ctx->mem_idx > 1) {
1452 /* Set process priority to very high */
1453 prio = 7;
1454 }
1455 break;
1456 #endif
1457 default:
1458 /* nop */
1459 break;
1460 }
1461 if (prio) {
1462 TCGv t0 = tcg_temp_new();
1463 gen_load_spr(t0, SPR_PPR);
1464 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1465 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1466 gen_store_spr(SPR_PPR, t0);
1467 tcg_temp_free(t0);
1468 }
1469 #endif
1470 }
1471 }
1472 /* orc & orc. */
1473 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1474
1475 /* xor & xor. */
1476 static void gen_xor(DisasContext *ctx)
1477 {
1478 /* Optimisation for "set to zero" case */
1479 if (rS(ctx->opcode) != rB(ctx->opcode))
1480 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1481 else
1482 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486
1487 /* ori */
1488 static void gen_ori(DisasContext *ctx)
1489 {
1490 target_ulong uimm = UIMM(ctx->opcode);
1491
1492 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1493 /* NOP */
1494 /* XXX: should handle special NOPs for POWER series */
1495 return;
1496 }
1497 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1498 }
1499
1500 /* oris */
1501 static void gen_oris(DisasContext *ctx)
1502 {
1503 target_ulong uimm = UIMM(ctx->opcode);
1504
1505 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1506 /* NOP */
1507 return;
1508 }
1509 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1510 }
1511
1512 /* xori */
1513 static void gen_xori(DisasContext *ctx)
1514 {
1515 target_ulong uimm = UIMM(ctx->opcode);
1516
1517 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1518 /* NOP */
1519 return;
1520 }
1521 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1522 }
1523
1524 /* xoris */
1525 static void gen_xoris(DisasContext *ctx)
1526 {
1527 target_ulong uimm = UIMM(ctx->opcode);
1528
1529 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1530 /* NOP */
1531 return;
1532 }
1533 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1534 }
1535
1536 /* popcntb : PowerPC 2.03 specification */
1537 static void gen_popcntb(DisasContext *ctx)
1538 {
1539 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1540 }
1541
1542 static void gen_popcntw(DisasContext *ctx)
1543 {
1544 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 #if defined(TARGET_PPC64)
1548 /* popcntd: PowerPC 2.06 specification */
1549 static void gen_popcntd(DisasContext *ctx)
1550 {
1551 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1552 }
1553 #endif
1554
1555 /* prtyw: PowerPC 2.05 specification */
1556 static void gen_prtyw(DisasContext *ctx)
1557 {
1558 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1559 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1560 TCGv t0 = tcg_temp_new();
1561 tcg_gen_shri_tl(t0, rs, 16);
1562 tcg_gen_xor_tl(ra, rs, t0);
1563 tcg_gen_shri_tl(t0, ra, 8);
1564 tcg_gen_xor_tl(ra, ra, t0);
1565 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1566 tcg_temp_free(t0);
1567 }
1568
1569 #if defined(TARGET_PPC64)
1570 /* prtyd: PowerPC 2.05 specification */
1571 static void gen_prtyd(DisasContext *ctx)
1572 {
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 32);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 16);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_shri_tl(t0, ra, 8);
1581 tcg_gen_xor_tl(ra, ra, t0);
1582 tcg_gen_andi_tl(ra, ra, 1);
1583 tcg_temp_free(t0);
1584 }
1585 #endif
1586
1587 #if defined(TARGET_PPC64)
1588 /* bpermd */
1589 static void gen_bpermd(DisasContext *ctx)
1590 {
1591 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1592 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1593 }
1594 #endif
1595
1596 #if defined(TARGET_PPC64)
1597 /* extsw & extsw. */
1598 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1599
1600 /* cntlzd */
1601 static void gen_cntlzd(DisasContext *ctx)
1602 {
1603 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1604 if (unlikely(Rc(ctx->opcode) != 0))
1605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1606 }
1607 #endif
1608
1609 /*** Integer rotate ***/
1610
1611 /* rlwimi & rlwimi. */
1612 static void gen_rlwimi(DisasContext *ctx)
1613 {
1614 uint32_t mb, me, sh;
1615
1616 mb = MB(ctx->opcode);
1617 me = ME(ctx->opcode);
1618 sh = SH(ctx->opcode);
1619 if (likely(sh == 0 && mb == 0 && me == 31)) {
1620 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 } else {
1622 target_ulong mask;
1623 TCGv t1;
1624 TCGv t0 = tcg_temp_new();
1625 #if defined(TARGET_PPC64)
1626 TCGv_i32 t2 = tcg_temp_new_i32();
1627 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1628 tcg_gen_rotli_i32(t2, t2, sh);
1629 tcg_gen_extu_i32_i64(t0, t2);
1630 tcg_temp_free_i32(t2);
1631 #else
1632 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1633 #endif
1634 #if defined(TARGET_PPC64)
1635 mb += 32;
1636 me += 32;
1637 #endif
1638 mask = MASK(mb, me);
1639 t1 = tcg_temp_new();
1640 tcg_gen_andi_tl(t0, t0, mask);
1641 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1642 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1643 tcg_temp_free(t0);
1644 tcg_temp_free(t1);
1645 }
1646 if (unlikely(Rc(ctx->opcode) != 0))
1647 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1648 }
1649
1650 /* rlwinm & rlwinm. */
1651 static void gen_rlwinm(DisasContext *ctx)
1652 {
1653 uint32_t mb, me, sh;
1654
1655 sh = SH(ctx->opcode);
1656 mb = MB(ctx->opcode);
1657 me = ME(ctx->opcode);
1658
1659 if (likely(mb == 0 && me == (31 - sh))) {
1660 if (likely(sh == 0)) {
1661 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1662 } else {
1663 TCGv t0 = tcg_temp_new();
1664 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1665 tcg_gen_shli_tl(t0, t0, sh);
1666 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1667 tcg_temp_free(t0);
1668 }
1669 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1670 TCGv t0 = tcg_temp_new();
1671 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_shri_tl(t0, t0, mb);
1673 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1674 tcg_temp_free(t0);
1675 } else {
1676 TCGv t0 = tcg_temp_new();
1677 #if defined(TARGET_PPC64)
1678 TCGv_i32 t1 = tcg_temp_new_i32();
1679 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1680 tcg_gen_rotli_i32(t1, t1, sh);
1681 tcg_gen_extu_i32_i64(t0, t1);
1682 tcg_temp_free_i32(t1);
1683 #else
1684 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1685 #endif
1686 #if defined(TARGET_PPC64)
1687 mb += 32;
1688 me += 32;
1689 #endif
1690 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1691 tcg_temp_free(t0);
1692 }
1693 if (unlikely(Rc(ctx->opcode) != 0))
1694 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1695 }
1696
1697 /* rlwnm & rlwnm. */
1698 static void gen_rlwnm(DisasContext *ctx)
1699 {
1700 uint32_t mb, me;
1701 TCGv t0;
1702 #if defined(TARGET_PPC64)
1703 TCGv_i32 t1, t2;
1704 #endif
1705
1706 mb = MB(ctx->opcode);
1707 me = ME(ctx->opcode);
1708 t0 = tcg_temp_new();
1709 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1710 #if defined(TARGET_PPC64)
1711 t1 = tcg_temp_new_i32();
1712 t2 = tcg_temp_new_i32();
1713 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1714 tcg_gen_trunc_i64_i32(t2, t0);
1715 tcg_gen_rotl_i32(t1, t1, t2);
1716 tcg_gen_extu_i32_i64(t0, t1);
1717 tcg_temp_free_i32(t1);
1718 tcg_temp_free_i32(t2);
1719 #else
1720 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1721 #endif
1722 if (unlikely(mb != 0 || me != 31)) {
1723 #if defined(TARGET_PPC64)
1724 mb += 32;
1725 me += 32;
1726 #endif
1727 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1728 } else {
1729 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1730 }
1731 tcg_temp_free(t0);
1732 if (unlikely(Rc(ctx->opcode) != 0))
1733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1734 }
1735
1736 #if defined(TARGET_PPC64)
1737 #define GEN_PPC64_R2(name, opc1, opc2) \
1738 static void glue(gen_, name##0)(DisasContext *ctx) \
1739 { \
1740 gen_##name(ctx, 0); \
1741 } \
1742 \
1743 static void glue(gen_, name##1)(DisasContext *ctx) \
1744 { \
1745 gen_##name(ctx, 1); \
1746 }
1747 #define GEN_PPC64_R4(name, opc1, opc2) \
1748 static void glue(gen_, name##0)(DisasContext *ctx) \
1749 { \
1750 gen_##name(ctx, 0, 0); \
1751 } \
1752 \
1753 static void glue(gen_, name##1)(DisasContext *ctx) \
1754 { \
1755 gen_##name(ctx, 0, 1); \
1756 } \
1757 \
1758 static void glue(gen_, name##2)(DisasContext *ctx) \
1759 { \
1760 gen_##name(ctx, 1, 0); \
1761 } \
1762 \
1763 static void glue(gen_, name##3)(DisasContext *ctx) \
1764 { \
1765 gen_##name(ctx, 1, 1); \
1766 }
1767
1768 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1769 uint32_t sh)
1770 {
1771 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1772 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1773 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1774 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1775 } else {
1776 TCGv t0 = tcg_temp_new();
1777 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778 if (likely(mb == 0 && me == 63)) {
1779 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1780 } else {
1781 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1782 }
1783 tcg_temp_free(t0);
1784 }
1785 if (unlikely(Rc(ctx->opcode) != 0))
1786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1787 }
1788 /* rldicl - rldicl. */
1789 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1790 {
1791 uint32_t sh, mb;
1792
1793 sh = SH(ctx->opcode) | (shn << 5);
1794 mb = MB(ctx->opcode) | (mbn << 5);
1795 gen_rldinm(ctx, mb, 63, sh);
1796 }
1797 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1798 /* rldicr - rldicr. */
1799 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1800 {
1801 uint32_t sh, me;
1802
1803 sh = SH(ctx->opcode) | (shn << 5);
1804 me = MB(ctx->opcode) | (men << 5);
1805 gen_rldinm(ctx, 0, me, sh);
1806 }
1807 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1808 /* rldic - rldic. */
1809 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1810 {
1811 uint32_t sh, mb;
1812
1813 sh = SH(ctx->opcode) | (shn << 5);
1814 mb = MB(ctx->opcode) | (mbn << 5);
1815 gen_rldinm(ctx, mb, 63 - sh, sh);
1816 }
1817 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1818
1819 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1820 {
1821 TCGv t0;
1822
1823 t0 = tcg_temp_new();
1824 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1825 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1826 if (unlikely(mb != 0 || me != 63)) {
1827 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1828 } else {
1829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1830 }
1831 tcg_temp_free(t0);
1832 if (unlikely(Rc(ctx->opcode) != 0))
1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1834 }
1835
1836 /* rldcl - rldcl. */
1837 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1838 {
1839 uint32_t mb;
1840
1841 mb = MB(ctx->opcode) | (mbn << 5);
1842 gen_rldnm(ctx, mb, 63);
1843 }
1844 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1845 /* rldcr - rldcr. */
1846 static inline void gen_rldcr(DisasContext *ctx, int men)
1847 {
1848 uint32_t me;
1849
1850 me = MB(ctx->opcode) | (men << 5);
1851 gen_rldnm(ctx, 0, me);
1852 }
1853 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1854 /* rldimi - rldimi. */
1855 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1856 {
1857 uint32_t sh, mb, me;
1858
1859 sh = SH(ctx->opcode) | (shn << 5);
1860 mb = MB(ctx->opcode) | (mbn << 5);
1861 me = 63 - sh;
1862 if (unlikely(sh == 0 && mb == 0)) {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1864 } else {
1865 TCGv t0, t1;
1866 target_ulong mask;
1867
1868 t0 = tcg_temp_new();
1869 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1870 t1 = tcg_temp_new();
1871 mask = MASK(mb, me);
1872 tcg_gen_andi_tl(t0, t0, mask);
1873 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1874 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1875 tcg_temp_free(t0);
1876 tcg_temp_free(t1);
1877 }
1878 if (unlikely(Rc(ctx->opcode) != 0))
1879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1880 }
1881 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1882 #endif
1883
1884 /*** Integer shift ***/
1885
1886 /* slw & slw. */
1887 static void gen_slw(DisasContext *ctx)
1888 {
1889 TCGv t0, t1;
1890
1891 t0 = tcg_temp_new();
1892 /* AND rS with a mask that is 0 when rB >= 0x20 */
1893 #if defined(TARGET_PPC64)
1894 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1895 tcg_gen_sari_tl(t0, t0, 0x3f);
1896 #else
1897 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1898 tcg_gen_sari_tl(t0, t0, 0x1f);
1899 #endif
1900 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1901 t1 = tcg_temp_new();
1902 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1903 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1904 tcg_temp_free(t1);
1905 tcg_temp_free(t0);
1906 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1907 if (unlikely(Rc(ctx->opcode) != 0))
1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1909 }
1910
1911 /* sraw & sraw. */
1912 static void gen_sraw(DisasContext *ctx)
1913 {
1914 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1915 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1916 if (unlikely(Rc(ctx->opcode) != 0))
1917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1918 }
1919
1920 /* srawi & srawi. */
1921 static void gen_srawi(DisasContext *ctx)
1922 {
1923 int sh = SH(ctx->opcode);
1924 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1925 TCGv src = cpu_gpr[rS(ctx->opcode)];
1926 if (sh == 0) {
1927 tcg_gen_mov_tl(dst, src);
1928 tcg_gen_movi_tl(cpu_ca, 0);
1929 } else {
1930 TCGv t0;
1931 tcg_gen_ext32s_tl(dst, src);
1932 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1933 t0 = tcg_temp_new();
1934 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1935 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1936 tcg_temp_free(t0);
1937 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1938 tcg_gen_sari_tl(dst, dst, sh);
1939 }
1940 if (unlikely(Rc(ctx->opcode) != 0)) {
1941 gen_set_Rc0(ctx, dst);
1942 }
1943 }
1944
1945 /* srw & srw. */
1946 static void gen_srw(DisasContext *ctx)
1947 {
1948 TCGv t0, t1;
1949
1950 t0 = tcg_temp_new();
1951 /* AND rS with a mask that is 0 when rB >= 0x20 */
1952 #if defined(TARGET_PPC64)
1953 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1954 tcg_gen_sari_tl(t0, t0, 0x3f);
1955 #else
1956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1957 tcg_gen_sari_tl(t0, t0, 0x1f);
1958 #endif
1959 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1960 tcg_gen_ext32u_tl(t0, t0);
1961 t1 = tcg_temp_new();
1962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1963 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1964 tcg_temp_free(t1);
1965 tcg_temp_free(t0);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968 }
1969
1970 #if defined(TARGET_PPC64)
1971 /* sld & sld. */
1972 static void gen_sld(DisasContext *ctx)
1973 {
1974 TCGv t0, t1;
1975
1976 t0 = tcg_temp_new();
1977 /* AND rS with a mask that is 0 when rB >= 0x40 */
1978 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1979 tcg_gen_sari_tl(t0, t0, 0x3f);
1980 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1981 t1 = tcg_temp_new();
1982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1984 tcg_temp_free(t1);
1985 tcg_temp_free(t0);
1986 if (unlikely(Rc(ctx->opcode) != 0))
1987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988 }
1989
1990 /* srad & srad. */
1991 static void gen_srad(DisasContext *ctx)
1992 {
1993 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1994 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1995 if (unlikely(Rc(ctx->opcode) != 0))
1996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1997 }
1998 /* sradi & sradi. */
1999 static inline void gen_sradi(DisasContext *ctx, int n)
2000 {
2001 int sh = SH(ctx->opcode) + (n << 5);
2002 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2003 TCGv src = cpu_gpr[rS(ctx->opcode)];
2004 if (sh == 0) {
2005 tcg_gen_mov_tl(dst, src);
2006 tcg_gen_movi_tl(cpu_ca, 0);
2007 } else {
2008 TCGv t0;
2009 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2010 t0 = tcg_temp_new();
2011 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2012 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2013 tcg_temp_free(t0);
2014 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2015 tcg_gen_sari_tl(dst, src, sh);
2016 }
2017 if (unlikely(Rc(ctx->opcode) != 0)) {
2018 gen_set_Rc0(ctx, dst);
2019 }
2020 }
2021
2022 static void gen_sradi0(DisasContext *ctx)
2023 {
2024 gen_sradi(ctx, 0);
2025 }
2026
2027 static void gen_sradi1(DisasContext *ctx)
2028 {
2029 gen_sradi(ctx, 1);
2030 }
2031
2032 /* srd & srd. */
2033 static void gen_srd(DisasContext *ctx)
2034 {
2035 TCGv t0, t1;
2036
2037 t0 = tcg_temp_new();
2038 /* AND rS with a mask that is 0 when rB >= 0x40 */
2039 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2040 tcg_gen_sari_tl(t0, t0, 0x3f);
2041 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2042 t1 = tcg_temp_new();
2043 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2044 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2045 tcg_temp_free(t1);
2046 tcg_temp_free(t0);
2047 if (unlikely(Rc(ctx->opcode) != 0))
2048 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2049 }
2050 #endif
2051
2052 /*** Floating-Point arithmetic ***/
2053 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2054 static void gen_f##name(DisasContext *ctx) \
2055 { \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2058 return; \
2059 } \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2066 if (isfloat) { \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2069 } \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2071 Rc(ctx->opcode) != 0); \
2072 }
2073
2074 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2075 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2076 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2077
2078 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2079 static void gen_f##name(DisasContext *ctx) \
2080 { \
2081 if (unlikely(!ctx->fpu_enabled)) { \
2082 gen_exception(ctx, POWERPC_EXCP_FPU); \
2083 return; \
2084 } \
2085 /* NIP cannot be restored if the memory exception comes from an helper */ \
2086 gen_update_nip(ctx, ctx->nip - 4); \
2087 gen_reset_fpstatus(); \
2088 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2089 cpu_fpr[rA(ctx->opcode)], \
2090 cpu_fpr[rB(ctx->opcode)]); \
2091 if (isfloat) { \
2092 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2093 cpu_fpr[rD(ctx->opcode)]); \
2094 } \
2095 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2096 set_fprf, Rc(ctx->opcode) != 0); \
2097 }
2098 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2099 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2100 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2101
2102 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2103 static void gen_f##name(DisasContext *ctx) \
2104 { \
2105 if (unlikely(!ctx->fpu_enabled)) { \
2106 gen_exception(ctx, POWERPC_EXCP_FPU); \
2107 return; \
2108 } \
2109 /* NIP cannot be restored if the memory exception comes from an helper */ \
2110 gen_update_nip(ctx, ctx->nip - 4); \
2111 gen_reset_fpstatus(); \
2112 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2113 cpu_fpr[rA(ctx->opcode)], \
2114 cpu_fpr[rC(ctx->opcode)]); \
2115 if (isfloat) { \
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rD(ctx->opcode)]); \
2118 } \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2120 set_fprf, Rc(ctx->opcode) != 0); \
2121 }
2122 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2123 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2124 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2125
2126 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2127 static void gen_f##name(DisasContext *ctx) \
2128 { \
2129 if (unlikely(!ctx->fpu_enabled)) { \
2130 gen_exception(ctx, POWERPC_EXCP_FPU); \
2131 return; \
2132 } \
2133 /* NIP cannot be restored if the memory exception comes from an helper */ \
2134 gen_update_nip(ctx, ctx->nip - 4); \
2135 gen_reset_fpstatus(); \
2136 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2137 cpu_fpr[rB(ctx->opcode)]); \
2138 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2139 set_fprf, Rc(ctx->opcode) != 0); \
2140 }
2141
2142 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2143 static void gen_f##name(DisasContext *ctx) \
2144 { \
2145 if (unlikely(!ctx->fpu_enabled)) { \
2146 gen_exception(ctx, POWERPC_EXCP_FPU); \
2147 return; \
2148 } \
2149 /* NIP cannot be restored if the memory exception comes from an helper */ \
2150 gen_update_nip(ctx, ctx->nip - 4); \
2151 gen_reset_fpstatus(); \
2152 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2153 cpu_fpr[rB(ctx->opcode)]); \
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2155 set_fprf, Rc(ctx->opcode) != 0); \
2156 }
2157
2158 /* fadd - fadds */
2159 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2160 /* fdiv - fdivs */
2161 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2162 /* fmul - fmuls */
2163 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2164
2165 /* fre */
2166 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2167
2168 /* fres */
2169 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2170
2171 /* frsqrte */
2172 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2173
2174 /* frsqrtes */
2175 static void gen_frsqrtes(DisasContext *ctx)
2176 {
2177 if (unlikely(!ctx->fpu_enabled)) {
2178 gen_exception(ctx, POWERPC_EXCP_FPU);
2179 return;
2180 }
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx, ctx->nip - 4);
2183 gen_reset_fpstatus();
2184 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2185 cpu_fpr[rB(ctx->opcode)]);
2186 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2187 cpu_fpr[rD(ctx->opcode)]);
2188 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2189 }
2190
2191 /* fsel */
2192 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2193 /* fsub - fsubs */
2194 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2195 /* Optional: */
2196
2197 /* fsqrt */
2198 static void gen_fsqrt(DisasContext *ctx)
2199 {
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 /* NIP cannot be restored if the memory exception comes from an helper */
2205 gen_update_nip(ctx, ctx->nip - 4);
2206 gen_reset_fpstatus();
2207 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2208 cpu_fpr[rB(ctx->opcode)]);
2209 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2210 }
2211
2212 static void gen_fsqrts(DisasContext *ctx)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 /* NIP cannot be restored if the memory exception comes from an helper */
2219 gen_update_nip(ctx, ctx->nip - 4);
2220 gen_reset_fpstatus();
2221 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2222 cpu_fpr[rB(ctx->opcode)]);
2223 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2224 cpu_fpr[rD(ctx->opcode)]);
2225 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2226 }
2227
2228 /*** Floating-Point multiply-and-add ***/
2229 /* fmadd - fmadds */
2230 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2231 /* fmsub - fmsubs */
2232 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2233 /* fnmadd - fnmadds */
2234 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2235 /* fnmsub - fnmsubs */
2236 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2237
2238 /*** Floating-Point round & convert ***/
2239 /* fctiw */
2240 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2241 /* fctiwu */
2242 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2243 /* fctiwz */
2244 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2245 /* fctiwuz */
2246 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2247 /* frsp */
2248 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2249 #if defined(TARGET_PPC64)
2250 /* fcfid */
2251 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2252 /* fcfids */
2253 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2254 /* fcfidu */
2255 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2256 /* fcfidus */
2257 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2258 /* fctid */
2259 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2260 /* fctidu */
2261 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2262 /* fctidz */
2263 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2264 /* fctidu */
2265 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2266 #endif
2267
2268 /* frin */
2269 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2270 /* friz */
2271 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2272 /* frip */
2273 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2274 /* frim */
2275 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2276
2277 static void gen_ftdiv(DisasContext *ctx)
2278 {
2279 if (unlikely(!ctx->fpu_enabled)) {
2280 gen_exception(ctx, POWERPC_EXCP_FPU);
2281 return;
2282 }
2283 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2284 cpu_fpr[rB(ctx->opcode)]);
2285 }
2286
2287 static void gen_ftsqrt(DisasContext *ctx)
2288 {
2289 if (unlikely(!ctx->fpu_enabled)) {
2290 gen_exception(ctx, POWERPC_EXCP_FPU);
2291 return;
2292 }
2293 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2294 }
2295
2296
2297
2298 /*** Floating-Point compare ***/
2299
2300 /* fcmpo */
2301 static void gen_fcmpo(DisasContext *ctx)
2302 {
2303 TCGv_i32 crf;
2304 if (unlikely(!ctx->fpu_enabled)) {
2305 gen_exception(ctx, POWERPC_EXCP_FPU);
2306 return;
2307 }
2308 /* NIP cannot be restored if the memory exception comes from an helper */
2309 gen_update_nip(ctx, ctx->nip - 4);
2310 gen_reset_fpstatus();
2311 crf = tcg_const_i32(crfD(ctx->opcode));
2312 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2313 cpu_fpr[rB(ctx->opcode)], crf);
2314 tcg_temp_free_i32(crf);
2315 gen_helper_float_check_status(cpu_env);
2316 }
2317
2318 /* fcmpu */
2319 static void gen_fcmpu(DisasContext *ctx)
2320 {
2321 TCGv_i32 crf;
2322 if (unlikely(!ctx->fpu_enabled)) {
2323 gen_exception(ctx, POWERPC_EXCP_FPU);
2324 return;
2325 }
2326 /* NIP cannot be restored if the memory exception comes from an helper */
2327 gen_update_nip(ctx, ctx->nip - 4);
2328 gen_reset_fpstatus();
2329 crf = tcg_const_i32(crfD(ctx->opcode));
2330 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2331 cpu_fpr[rB(ctx->opcode)], crf);
2332 tcg_temp_free_i32(crf);
2333 gen_helper_float_check_status(cpu_env);
2334 }
2335
2336 /*** Floating-point move ***/
2337 /* fabs */
2338 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2339 static void gen_fabs(DisasContext *ctx)
2340 {
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2346 ~(1ULL << 63));
2347 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2348 }
2349
2350 /* fmr - fmr. */
2351 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2352 static void gen_fmr(DisasContext *ctx)
2353 {
2354 if (unlikely(!ctx->fpu_enabled)) {
2355 gen_exception(ctx, POWERPC_EXCP_FPU);
2356 return;
2357 }
2358 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2359 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2360 }
2361
2362 /* fnabs */
2363 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2364 static void gen_fnabs(DisasContext *ctx)
2365 {
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2371 1ULL << 63);
2372 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2373 }
2374
2375 /* fneg */
2376 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2377 static void gen_fneg(DisasContext *ctx)
2378 {
2379 if (unlikely(!ctx->fpu_enabled)) {
2380 gen_exception(ctx, POWERPC_EXCP_FPU);
2381 return;
2382 }
2383 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2384 1ULL << 63);
2385 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2386 }
2387
2388 /* fcpsgn: PowerPC 2.05 specification */
2389 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2390 static void gen_fcpsgn(DisasContext *ctx)
2391 {
2392 if (unlikely(!ctx->fpu_enabled)) {
2393 gen_exception(ctx, POWERPC_EXCP_FPU);
2394 return;
2395 }
2396 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2397 cpu_fpr[rB(ctx->opcode)], 0, 63);
2398 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2399 }
2400
2401 static void gen_fmrgew(DisasContext *ctx)
2402 {
2403 TCGv_i64 b0;
2404 if (unlikely(!ctx->fpu_enabled)) {
2405 gen_exception(ctx, POWERPC_EXCP_FPU);
2406 return;
2407 }
2408 b0 = tcg_temp_new_i64();
2409 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2410 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2411 b0, 0, 32);
2412 tcg_temp_free_i64(b0);
2413 }
2414
2415 static void gen_fmrgow(DisasContext *ctx)
2416 {
2417 if (unlikely(!ctx->fpu_enabled)) {
2418 gen_exception(ctx, POWERPC_EXCP_FPU);
2419 return;
2420 }
2421 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2422 cpu_fpr[rB(ctx->opcode)],
2423 cpu_fpr[rA(ctx->opcode)],
2424 32, 32);
2425 }
2426
2427 /*** Floating-Point status & ctrl register ***/
2428
2429 /* mcrfs */
2430 static void gen_mcrfs(DisasContext *ctx)
2431 {
2432 TCGv tmp = tcg_temp_new();
2433 int bfa;
2434
2435 if (unlikely(!ctx->fpu_enabled)) {
2436 gen_exception(ctx, POWERPC_EXCP_FPU);
2437 return;
2438 }
2439 bfa = 4 * (7 - crfS(ctx->opcode));
2440 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2441 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2442 tcg_temp_free(tmp);
2443 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2444 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2445 }
2446
2447 /* mffs */
2448 static void gen_mffs(DisasContext *ctx)
2449 {
2450 if (unlikely(!ctx->fpu_enabled)) {
2451 gen_exception(ctx, POWERPC_EXCP_FPU);
2452 return;
2453 }
2454 gen_reset_fpstatus();
2455 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2456 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2457 }
2458
2459 /* mtfsb0 */
2460 static void gen_mtfsb0(DisasContext *ctx)
2461 {
2462 uint8_t crb;
2463
2464 if (unlikely(!ctx->fpu_enabled)) {
2465 gen_exception(ctx, POWERPC_EXCP_FPU);
2466 return;
2467 }
2468 crb = 31 - crbD(ctx->opcode);
2469 gen_reset_fpstatus();
2470 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2471 TCGv_i32 t0;
2472 /* NIP cannot be restored if the memory exception comes from an helper */
2473 gen_update_nip(ctx, ctx->nip - 4);
2474 t0 = tcg_const_i32(crb);
2475 gen_helper_fpscr_clrbit(cpu_env, t0);
2476 tcg_temp_free_i32(t0);
2477 }
2478 if (unlikely(Rc(ctx->opcode) != 0)) {
2479 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2480 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2481 }
2482 }
2483
2484 /* mtfsb1 */
2485 static void gen_mtfsb1(DisasContext *ctx)
2486 {
2487 uint8_t crb;
2488
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 crb = 31 - crbD(ctx->opcode);
2494 gen_reset_fpstatus();
2495 /* XXX: we pretend we can only do IEEE floating-point computations */
2496 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2497 TCGv_i32 t0;
2498 /* NIP cannot be restored if the memory exception comes from an helper */
2499 gen_update_nip(ctx, ctx->nip - 4);
2500 t0 = tcg_const_i32(crb);
2501 gen_helper_fpscr_setbit(cpu_env, t0);
2502 tcg_temp_free_i32(t0);
2503 }
2504 if (unlikely(Rc(ctx->opcode) != 0)) {
2505 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2506 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2507 }
2508 /* We can raise a differed exception */
2509 gen_helper_float_check_status(cpu_env);
2510 }
2511
2512 /* mtfsf */
2513 static void gen_mtfsf(DisasContext *ctx)
2514 {
2515 TCGv_i32 t0;
2516 int flm, l, w;
2517
2518 if (unlikely(!ctx->fpu_enabled)) {
2519 gen_exception(ctx, POWERPC_EXCP_FPU);
2520 return;
2521 }
2522 flm = FPFLM(ctx->opcode);
2523 l = FPL(ctx->opcode);
2524 w = FPW(ctx->opcode);
2525 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2526 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2527 return;
2528 }
2529 /* NIP cannot be restored if the memory exception comes from an helper */
2530 gen_update_nip(ctx, ctx->nip - 4);
2531 gen_reset_fpstatus();
2532 if (l) {
2533 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2534 } else {
2535 t0 = tcg_const_i32(flm << (w * 8));
2536 }
2537 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2538 tcg_temp_free_i32(t0);
2539 if (unlikely(Rc(ctx->opcode) != 0)) {
2540 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2541 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2542 }
2543 /* We can raise a differed exception */
2544 gen_helper_float_check_status(cpu_env);
2545 }
2546
2547 /* mtfsfi */
2548 static void gen_mtfsfi(DisasContext *ctx)
2549 {
2550 int bf, sh, w;
2551 TCGv_i64 t0;
2552 TCGv_i32 t1;
2553
2554 if (unlikely(!ctx->fpu_enabled)) {
2555 gen_exception(ctx, POWERPC_EXCP_FPU);
2556 return;
2557 }
2558 w = FPW(ctx->opcode);
2559 bf = FPBF(ctx->opcode);
2560 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2561 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2562 return;
2563 }
2564 sh = (8 * w) + 7 - bf;
2565 /* NIP cannot be restored if the memory exception comes from an helper */
2566 gen_update_nip(ctx, ctx->nip - 4);
2567 gen_reset_fpstatus();
2568 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2569 t1 = tcg_const_i32(1 << sh);
2570 gen_helper_store_fpscr(cpu_env, t0, t1);
2571 tcg_temp_free_i64(t0);
2572 tcg_temp_free_i32(t1);
2573 if (unlikely(Rc(ctx->opcode) != 0)) {
2574 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2575 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2576 }
2577 /* We can raise a differed exception */
2578 gen_helper_float_check_status(cpu_env);
2579 }
2580
2581 /*** Addressing modes ***/
2582 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2583 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2584 target_long maskl)
2585 {
2586 target_long simm = SIMM(ctx->opcode);
2587
2588 simm &= ~maskl;
2589 if (rA(ctx->opcode) == 0) {
2590 if (NARROW_MODE(ctx)) {
2591 simm = (uint32_t)simm;
2592 }
2593 tcg_gen_movi_tl(EA, simm);
2594 } else if (likely(simm != 0)) {
2595 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2596 if (NARROW_MODE(ctx)) {
2597 tcg_gen_ext32u_tl(EA, EA);
2598 }
2599 } else {
2600 if (NARROW_MODE(ctx)) {
2601 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2602 } else {
2603 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2604 }
2605 }
2606 }
2607
2608 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2609 {
2610 if (rA(ctx->opcode) == 0) {
2611 if (NARROW_MODE(ctx)) {
2612 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2613 } else {
2614 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2615 }
2616 } else {
2617 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2618 if (NARROW_MODE(ctx)) {
2619 tcg_gen_ext32u_tl(EA, EA);
2620 }
2621 }
2622 }
2623
2624 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2625 {
2626 if (rA(ctx->opcode) == 0) {
2627 tcg_gen_movi_tl(EA, 0);
2628 } else if (NARROW_MODE(ctx)) {
2629 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2630 } else {
2631 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2632 }
2633 }
2634
2635 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2636 target_long val)
2637 {
2638 tcg_gen_addi_tl(ret, arg1, val);
2639 if (NARROW_MODE(ctx)) {
2640 tcg_gen_ext32u_tl(ret, ret);
2641 }
2642 }
2643
2644 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2645 {
2646 int l1 = gen_new_label();
2647 TCGv t0 = tcg_temp_new();
2648 TCGv_i32 t1, t2;
2649 /* NIP cannot be restored if the memory exception comes from an helper */
2650 gen_update_nip(ctx, ctx->nip - 4);
2651 tcg_gen_andi_tl(t0, EA, mask);
2652 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2653 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2654 t2 = tcg_const_i32(0);
2655 gen_helper_raise_exception_err(cpu_env, t1, t2);
2656 tcg_temp_free_i32(t1);
2657 tcg_temp_free_i32(t2);
2658 gen_set_label(l1);
2659 tcg_temp_free(t0);
2660 }
2661
2662 /*** Integer load ***/
2663 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2664 {
2665 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2666 }
2667
2668 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2669 {
2670 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2671 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2672 }
2673
2674 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2675 {
2676 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2677 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2678 }
2679
2680 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2681 {
2682 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2683 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2684 }
2685
2686 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2687 {
2688 TCGv tmp = tcg_temp_new();
2689 gen_qemu_ld32u(ctx, tmp, addr);
2690 tcg_gen_extu_tl_i64(val, tmp);
2691 tcg_temp_free(tmp);
2692 }
2693
2694 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2695 {
2696 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2697 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2698 }
2699
2700 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2701 {
2702 TCGv tmp = tcg_temp_new();
2703 gen_qemu_ld32s(ctx, tmp, addr);
2704 tcg_gen_ext_tl_i64(val, tmp);
2705 tcg_temp_free(tmp);
2706 }
2707
2708 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2709 {
2710 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2711 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2712 }
2713
2714 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2715 {
2716 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2717 }
2718
2719 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2720 {
2721 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2722 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2723 }
2724
2725 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2726 {
2727 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2728 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2729 }
2730
2731 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2732 {
2733 TCGv tmp = tcg_temp_new();
2734 tcg_gen_trunc_i64_tl(tmp, val);
2735 gen_qemu_st32(ctx, tmp, addr);
2736 tcg_temp_free(tmp);
2737 }
2738
2739 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2740 {
2741 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2742 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2743 }
2744
2745 #define GEN_LD(name, ldop, opc, type) \
2746 static void glue(gen_, name)(DisasContext *ctx) \
2747 { \
2748 TCGv EA; \
2749 gen_set_access_type(ctx, ACCESS_INT); \
2750 EA = tcg_temp_new(); \
2751 gen_addr_imm_index(ctx, EA, 0); \
2752 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2753 tcg_temp_free(EA); \
2754 }
2755
2756 #define GEN_LDU(name, ldop, opc, type) \
2757 static void glue(gen_, name##u)(DisasContext *ctx) \
2758 { \
2759 TCGv EA; \
2760 if (unlikely(rA(ctx->opcode) == 0 || \
2761 rA(ctx->opcode) == rD(ctx->opcode))) { \
2762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2763 return; \
2764 } \
2765 gen_set_access_type(ctx, ACCESS_INT); \
2766 EA = tcg_temp_new(); \
2767 if (type == PPC_64B) \
2768 gen_addr_imm_index(ctx, EA, 0x03); \
2769 else \
2770 gen_addr_imm_index(ctx, EA, 0); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2773 tcg_temp_free(EA); \
2774 }
2775
2776 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2777 static void glue(gen_, name##ux)(DisasContext *ctx) \
2778 { \
2779 TCGv EA; \
2780 if (unlikely(rA(ctx->opcode) == 0 || \
2781 rA(ctx->opcode) == rD(ctx->opcode))) { \
2782 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2783 return; \
2784 } \
2785 gen_set_access_type(ctx, ACCESS_INT); \
2786 EA = tcg_temp_new(); \
2787 gen_addr_reg_index(ctx, EA); \
2788 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2790 tcg_temp_free(EA); \
2791 }
2792
2793 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2794 static void glue(gen_, name##x)(DisasContext *ctx) \
2795 { \
2796 TCGv EA; \
2797 gen_set_access_type(ctx, ACCESS_INT); \
2798 EA = tcg_temp_new(); \
2799 gen_addr_reg_index(ctx, EA); \
2800 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2801 tcg_temp_free(EA); \
2802 }
2803 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2804 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2805
2806 #define GEN_LDS(name, ldop, op, type) \
2807 GEN_LD(name, ldop, op | 0x20, type); \
2808 GEN_LDU(name, ldop, op | 0x21, type); \
2809 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2810 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2811
2812 /* lbz lbzu lbzux lbzx */
2813 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2814 /* lha lhau lhaux lhax */
2815 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2816 /* lhz lhzu lhzux lhzx */
2817 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2818 /* lwz lwzu lwzux lwzx */
2819 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2820 #if defined(TARGET_PPC64)
2821 /* lwaux */
2822 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2823 /* lwax */
2824 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2825 /* ldux */
2826 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2827 /* ldx */
2828 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2829
2830 static void gen_ld(DisasContext *ctx)
2831 {
2832 TCGv EA;
2833 if (Rc(ctx->opcode)) {
2834 if (unlikely(rA(ctx->opcode) == 0 ||
2835 rA(ctx->opcode) == rD(ctx->opcode))) {
2836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2837 return;
2838 }
2839 }
2840 gen_set_access_type(ctx, ACCESS_INT);
2841 EA = tcg_temp_new();
2842 gen_addr_imm_index(ctx, EA, 0x03);
2843 if (ctx->opcode & 0x02) {
2844 /* lwa (lwau is undefined) */
2845 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2846 } else {
2847 /* ld - ldu */
2848 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2849 }
2850 if (Rc(ctx->opcode))
2851 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2852 tcg_temp_free(EA);
2853 }
2854
2855 /* lq */
2856 static void gen_lq(DisasContext *ctx)
2857 {
2858 int ra, rd;
2859 TCGv EA;
2860
2861 /* lq is a legal user mode instruction starting in ISA 2.07 */
2862 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2863 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2864
2865 if (!legal_in_user_mode && is_user_mode(ctx)) {
2866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2867 return;
2868 }
2869
2870 if (!le_is_supported && ctx->le_mode) {
2871 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2872 return;
2873 }
2874
2875 ra = rA(ctx->opcode);
2876 rd = rD(ctx->opcode);
2877 if (unlikely((rd & 1) || rd == ra)) {
2878 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2879 return;
2880 }
2881
2882 gen_set_access_type(ctx, ACCESS_INT);
2883 EA = tcg_temp_new();
2884 gen_addr_imm_index(ctx, EA, 0x0F);
2885
2886 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2887 64-bit byteswap already. */
2888 if (unlikely(ctx->le_mode)) {
2889 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2890 gen_addr_add(ctx, EA, EA, 8);
2891 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2892 } else {
2893 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2894 gen_addr_add(ctx, EA, EA, 8);
2895 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2896 }
2897 tcg_temp_free(EA);
2898 }
2899 #endif
2900
2901 /*** Integer store ***/
2902 #define GEN_ST(name, stop, opc, type) \
2903 static void glue(gen_, name)(DisasContext *ctx) \
2904 { \
2905 TCGv EA; \
2906 gen_set_access_type(ctx, ACCESS_INT); \
2907 EA = tcg_temp_new(); \
2908 gen_addr_imm_index(ctx, EA, 0); \
2909 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2910 tcg_temp_free(EA); \
2911 }
2912
2913 #define GEN_STU(name, stop, opc, type) \
2914 static void glue(gen_, stop##u)(DisasContext *ctx) \
2915 { \
2916 TCGv EA; \
2917 if (unlikely(rA(ctx->opcode) == 0)) { \
2918 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2919 return; \
2920 } \
2921 gen_set_access_type(ctx, ACCESS_INT); \
2922 EA = tcg_temp_new(); \
2923 if (type == PPC_64B) \
2924 gen_addr_imm_index(ctx, EA, 0x03); \
2925 else \
2926 gen_addr_imm_index(ctx, EA, 0); \
2927 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2928 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2929 tcg_temp_free(EA); \
2930 }
2931
2932 #define GEN_STUX(name, stop, opc2, opc3, type) \
2933 static void glue(gen_, name##ux)(DisasContext *ctx) \
2934 { \
2935 TCGv EA; \
2936 if (unlikely(rA(ctx->opcode) == 0)) { \
2937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2938 return; \
2939 } \
2940 gen_set_access_type(ctx, ACCESS_INT); \
2941 EA = tcg_temp_new(); \
2942 gen_addr_reg_index(ctx, EA); \
2943 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2944 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2945 tcg_temp_free(EA); \
2946 }
2947
2948 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2949 static void glue(gen_, name##x)(DisasContext *ctx) \
2950 { \
2951 TCGv EA; \
2952 gen_set_access_type(ctx, ACCESS_INT); \
2953 EA = tcg_temp_new(); \
2954 gen_addr_reg_index(ctx, EA); \
2955 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2956 tcg_temp_free(EA); \
2957 }
2958 #define GEN_STX(name, stop, opc2, opc3, type) \
2959 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2960
2961 #define GEN_STS(name, stop, op, type) \
2962 GEN_ST(name, stop, op | 0x20, type); \
2963 GEN_STU(name, stop, op | 0x21, type); \
2964 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2965 GEN_STX(name, stop, 0x17, op | 0x00, type)
2966
2967 /* stb stbu stbux stbx */
2968 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2969 /* sth sthu sthux sthx */
2970 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2971 /* stw stwu stwux stwx */
2972 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2973 #if defined(TARGET_PPC64)
2974 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2975 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2976
2977 static void gen_std(DisasContext *ctx)
2978 {
2979 int rs;
2980 TCGv EA;
2981
2982 rs = rS(ctx->opcode);
2983 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2984
2985 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2986 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2987
2988 if (!legal_in_user_mode && is_user_mode(ctx)) {
2989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2990 return;
2991 }
2992
2993 if (!le_is_supported && ctx->le_mode) {
2994 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2995 return;
2996 }
2997
2998 if (unlikely(rs & 1)) {
2999 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3000 return;
3001 }
3002 gen_set_access_type(ctx, ACCESS_INT);
3003 EA = tcg_temp_new();
3004 gen_addr_imm_index(ctx, EA, 0x03);
3005
3006 /* We only need to swap high and low halves. gen_qemu_st64 does
3007 necessary 64-bit byteswap already. */
3008 if (unlikely(ctx->le_mode)) {
3009 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3010 gen_addr_add(ctx, EA, EA, 8);
3011 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3012 } else {
3013 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3014 gen_addr_add(ctx, EA, EA, 8);
3015 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3016 }
3017 tcg_temp_free(EA);
3018 } else {
3019 /* std / stdu*/
3020 if (Rc(ctx->opcode)) {
3021 if (unlikely(rA(ctx->opcode) == 0)) {
3022 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3023 return;
3024 }
3025 }
3026 gen_set_access_type(ctx, ACCESS_INT);
3027 EA = tcg_temp_new();
3028 gen_addr_imm_index(ctx, EA, 0x03);
3029 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3030 if (Rc(ctx->opcode))
3031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3032 tcg_temp_free(EA);
3033 }
3034 }
3035 #endif
3036 /*** Integer load and store with byte reverse ***/
3037
3038 /* lhbrx */
3039 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3040 {
3041 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3042 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3043 }
3044 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3045
3046 /* lwbrx */
3047 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3048 {
3049 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3050 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3051 }
3052 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3053
3054 #if defined(TARGET_PPC64)
3055 /* ldbrx */
3056 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3057 {
3058 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3059 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3060 }
3061 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3062 #endif /* TARGET_PPC64 */
3063
3064 /* sthbrx */
3065 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3066 {
3067 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3068 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3069 }
3070 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3071
3072 /* stwbrx */
3073 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3074 {
3075 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3076 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3077 }
3078 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3079
3080 #if defined(TARGET_PPC64)
3081 /* stdbrx */
3082 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3083 {
3084 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3085 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3086 }
3087 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3088 #endif /* TARGET_PPC64 */
3089
3090 /*** Integer load and store multiple ***/
3091
3092 /* lmw */
3093 static void gen_lmw(DisasContext *ctx)
3094 {
3095 TCGv t0;
3096 TCGv_i32 t1;
3097 gen_set_access_type(ctx, ACCESS_INT);
3098 /* NIP cannot be restored if the memory exception comes from an helper */
3099 gen_update_nip(ctx, ctx->nip - 4);
3100 t0 = tcg_temp_new();
3101 t1 = tcg_const_i32(rD(ctx->opcode));
3102 gen_addr_imm_index(ctx, t0, 0);
3103 gen_helper_lmw(cpu_env, t0, t1);
3104 tcg_temp_free(t0);
3105 tcg_temp_free_i32(t1);
3106 }
3107
3108 /* stmw */
3109 static void gen_stmw(DisasContext *ctx)
3110 {
3111 TCGv t0;
3112 TCGv_i32 t1;
3113 gen_set_access_type(ctx, ACCESS_INT);
3114 /* NIP cannot be restored if the memory exception comes from an helper */
3115 gen_update_nip(ctx, ctx->nip - 4);
3116 t0 = tcg_temp_new();
3117 t1 = tcg_const_i32(rS(ctx->opcode));
3118 gen_addr_imm_index(ctx, t0, 0);
3119 gen_helper_stmw(cpu_env, t0, t1);
3120 tcg_temp_free(t0);
3121 tcg_temp_free_i32(t1);
3122 }
3123
3124 /*** Integer load and store strings ***/
3125
3126 /* lswi */
3127 /* PowerPC32 specification says we must generate an exception if
3128 * rA is in the range of registers to be loaded.
3129 * In an other hand, IBM says this is valid, but rA won't be loaded.
3130 * For now, I'll follow the spec...
3131 */
3132 static void gen_lswi(DisasContext *ctx)
3133 {
3134 TCGv t0;
3135 TCGv_i32 t1, t2;
3136 int nb = NB(ctx->opcode);
3137 int start = rD(ctx->opcode);
3138 int ra = rA(ctx->opcode);
3139 int nr;
3140
3141 if (nb == 0)
3142 nb = 32;
3143 nr = nb / 4;
3144 if (unlikely(((start + nr) > 32 &&
3145 start <= ra && (start + nr - 32) > ra) ||
3146 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3147 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3148 return;
3149 }
3150 gen_set_access_type(ctx, ACCESS_INT);
3151 /* NIP cannot be restored if the memory exception comes from an helper */
3152 gen_update_nip(ctx, ctx->nip - 4);
3153 t0 = tcg_temp_new();
3154 gen_addr_register(ctx, t0);
3155 t1 = tcg_const_i32(nb);
3156 t2 = tcg_const_i32(start);
3157 gen_helper_lsw(cpu_env, t0, t1, t2);
3158 tcg_temp_free(t0);
3159 tcg_temp_free_i32(t1);
3160 tcg_temp_free_i32(t2);
3161 }
3162
3163 /* lswx */
3164 static void gen_lswx(DisasContext *ctx)
3165 {
3166 TCGv t0;
3167 TCGv_i32 t1, t2, t3;
3168 gen_set_access_type(ctx, ACCESS_INT);
3169 /* NIP cannot be restored if the memory exception comes from an helper */
3170 gen_update_nip(ctx, ctx->nip - 4);
3171 t0 = tcg_temp_new();
3172 gen_addr_reg_index(ctx, t0);
3173 t1 = tcg_const_i32(rD(ctx->opcode));
3174 t2 = tcg_const_i32(rA(ctx->opcode));
3175 t3 = tcg_const_i32(rB(ctx->opcode));
3176 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3177 tcg_temp_free(t0);
3178 tcg_temp_free_i32(t1);
3179 tcg_temp_free_i32(t2);
3180 tcg_temp_free_i32(t3);
3181 }
3182
3183 /* stswi */
3184 static void gen_stswi(DisasContext *ctx)
3185 {
3186 TCGv t0;
3187 TCGv_i32 t1, t2;
3188 int nb = NB(ctx->opcode);
3189 gen_set_access_type(ctx, ACCESS_INT);
3190 /* NIP cannot be restored if the memory exception comes from an helper */
3191 gen_update_nip(ctx, ctx->nip - 4);
3192 t0 = tcg_temp_new();
3193 gen_addr_register(ctx, t0);
3194 if (nb == 0)
3195 nb = 32;
3196 t1 = tcg_const_i32(nb);
3197 t2 = tcg_const_i32(rS(ctx->opcode));
3198 gen_helper_stsw(cpu_env, t0, t1, t2);
3199 tcg_temp_free(t0);
3200 tcg_temp_free_i32(t1);
3201 tcg_temp_free_i32(t2);
3202 }
3203
3204 /* stswx */
3205 static void gen_stswx(DisasContext *ctx)
3206 {
3207 TCGv t0;
3208 TCGv_i32 t1, t2;
3209 gen_set_access_type(ctx, ACCESS_INT);
3210 /* NIP cannot be restored if the memory exception comes from an helper */
3211 gen_update_nip(ctx, ctx->nip - 4);
3212 t0 = tcg_temp_new();
3213 gen_addr_reg_index(ctx, t0);
3214 t1 = tcg_temp_new_i32();
3215 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3216 tcg_gen_andi_i32(t1, t1, 0x7F);
3217 t2 = tcg_const_i32(rS(ctx->opcode));
3218 gen_helper_stsw(cpu_env, t0, t1, t2);
3219 tcg_temp_free(t0);
3220 tcg_temp_free_i32(t1);
3221 tcg_temp_free_i32(t2);
3222 }
3223
3224 /*** Memory synchronisation ***/
3225 /* eieio */
3226 static void gen_eieio(DisasContext *ctx)
3227 {
3228 }
3229
3230 /* isync */
3231 static void gen_isync(DisasContext *ctx)
3232 {
3233 gen_stop_exception(ctx);
3234 }
3235
3236 #define LARX(name, len, loadop) \
3237 static void gen_##name(DisasContext *ctx) \
3238 { \
3239 TCGv t0; \
3240 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3241 gen_set_access_type(ctx, ACCESS_RES); \
3242 t0 = tcg_temp_local_new(); \
3243 gen_addr_reg_index(ctx, t0); \
3244 if ((len) > 1) { \
3245 gen_check_align(ctx, t0, (len)-1); \
3246 } \
3247 gen_qemu_##loadop(ctx, gpr, t0); \
3248 tcg_gen_mov_tl(cpu_reserve, t0); \
3249 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3250 tcg_temp_free(t0); \
3251 }
3252
3253 /* lwarx */
3254 LARX(lbarx, 1, ld8u);
3255 LARX(lharx, 2, ld16u);
3256 LARX(lwarx, 4, ld32u);
3257
3258
3259 #if defined(CONFIG_USER_ONLY)
3260 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3261 int reg, int size)
3262 {
3263 TCGv t0 = tcg_temp_new();
3264 uint32_t save_exception = ctx->exception;
3265
3266 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3267 tcg_gen_movi_tl(t0, (size << 5) | reg);
3268 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3269 tcg_temp_free(t0);
3270 gen_update_nip(ctx, ctx->nip-4);
3271 ctx->exception = POWERPC_EXCP_BRANCH;
3272 gen_exception(ctx, POWERPC_EXCP_STCX);
3273 ctx->exception = save_exception;
3274 }
3275 #else
3276 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3277 int reg, int size)
3278 {
3279 int l1;
3280
3281 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3282 l1 = gen_new_label();
3283 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3284 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3285 #if defined(TARGET_PPC64)
3286 if (size == 8) {
3287 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3288 } else
3289 #endif
3290 if (size == 4) {
3291 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3292 } else if (size == 2) {
3293 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3294 #if defined(TARGET_PPC64)
3295 } else if (size == 16) {
3296 TCGv gpr1, gpr2 , EA8;
3297 if (unlikely(ctx->le_mode)) {
3298 gpr1 = cpu_gpr[reg+1];
3299 gpr2 = cpu_gpr[reg];
3300 } else {
3301 gpr1 = cpu_gpr[reg];
3302 gpr2 = cpu_gpr[reg+1];
3303 }
3304 gen_qemu_st64(ctx, gpr1, EA);
3305 EA8 = tcg_temp_local_new();
3306 gen_addr_add(ctx, EA8, EA, 8);
3307 gen_qemu_st64(ctx, gpr2, EA8);
3308 tcg_temp_free(EA8);
3309 #endif
3310 } else {
3311 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3312 }
3313 gen_set_label(l1);
3314 tcg_gen_movi_tl(cpu_reserve, -1);
3315 }
3316 #endif
3317
3318 #define STCX(name, len) \
3319 static void gen_##name(DisasContext *ctx) \
3320 { \
3321 TCGv t0; \
3322 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3323 gen_inval_exception(ctx, \
3324 POWERPC_EXCP_INVAL_INVAL); \
3325 return; \
3326 } \
3327 gen_set_access_type(ctx, ACCESS_RES); \
3328 t0 = tcg_temp_local_new(); \
3329 gen_addr_reg_index(ctx, t0); \
3330 if (len > 1) { \
3331 gen_check_align(ctx, t0, (len)-1); \
3332 } \
3333 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3334 tcg_temp_free(t0); \
3335 }
3336
3337 STCX(stbcx_, 1);
3338 STCX(sthcx_, 2);
3339 STCX(stwcx_, 4);
3340
3341 #if defined(TARGET_PPC64)
3342 /* ldarx */
3343 LARX(ldarx, 8, ld64);
3344
3345 /* lqarx */
3346 static void gen_lqarx(DisasContext *ctx)
3347 {
3348 TCGv EA;
3349 int rd = rD(ctx->opcode);
3350 TCGv gpr1, gpr2;
3351
3352 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3353 (rd == rB(ctx->opcode)))) {
3354 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3355 return;
3356 }
3357
3358 gen_set_access_type(ctx, ACCESS_RES);
3359 EA = tcg_temp_local_new();
3360 gen_addr_reg_index(ctx, EA);
3361 gen_check_align(ctx, EA, 15);
3362 if (unlikely(ctx->le_mode)) {
3363 gpr1 = cpu_gpr[rd+1];
3364 gpr2 = cpu_gpr[rd];
3365 } else {
3366 gpr1 = cpu_gpr[rd];
3367 gpr2 = cpu_gpr[rd+1];
3368 }
3369 gen_qemu_ld64(ctx, gpr1, EA);
3370 tcg_gen_mov_tl(cpu_reserve, EA);
3371
3372 gen_addr_add(ctx, EA, EA, 8);
3373 gen_qemu_ld64(ctx, gpr2, EA);
3374
3375 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3376 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3377
3378 tcg_temp_free(EA);
3379 }
3380
3381 /* stdcx. */
3382 STCX(stdcx_, 8);
3383 STCX(stqcx_, 16);
3384 #endif /* defined(TARGET_PPC64) */
3385
3386 /* sync */
3387 static void gen_sync(DisasContext *ctx)
3388 {
3389 }
3390
3391 /* wait */
3392 static void gen_wait(DisasContext *ctx)
3393 {
3394 TCGv_i32 t0 = tcg_temp_new_i32();
3395 tcg_gen_st_i32(t0, cpu_env,
3396 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3397 tcg_temp_free_i32(t0);
3398 /* Stop translation, as the CPU is supposed to sleep from now */
3399 gen_exception_err(ctx, EXCP_HLT, 1);
3400 }
3401
3402 /*** Floating-point load ***/
3403 #define GEN_LDF(name, ldop, opc, type) \
3404 static void glue(gen_, name)(DisasContext *ctx) \
3405 { \
3406 TCGv EA; \
3407 if (unlikely(!ctx->fpu_enabled)) { \
3408 gen_exception(ctx, POWERPC_EXCP_FPU); \
3409 return; \
3410 } \
3411 gen_set_access_type(ctx, ACCESS_FLOAT); \
3412 EA = tcg_temp_new(); \
3413 gen_addr_imm_index(ctx, EA, 0); \
3414 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3415 tcg_temp_free(EA); \
3416 }
3417
3418 #define GEN_LDUF(name, ldop, opc, type) \
3419 static void glue(gen_, name##u)(DisasContext *ctx) \
3420 { \
3421 TCGv EA; \
3422 if (unlikely(!ctx->fpu_enabled)) { \
3423 gen_exception(ctx, POWERPC_EXCP_FPU); \
3424 return; \
3425 } \
3426 if (unlikely(rA(ctx->opcode) == 0)) { \
3427 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3428 return; \
3429 } \
3430 gen_set_access_type(ctx, ACCESS_FLOAT); \
3431 EA = tcg_temp_new(); \
3432 gen_addr_imm_index(ctx, EA, 0); \
3433 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3434 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3435 tcg_temp_free(EA); \
3436 }
3437
3438 #define GEN_LDUXF(name, ldop, opc, type) \
3439 static void glue(gen_, name##ux)(DisasContext *ctx) \
3440 { \
3441 TCGv EA; \
3442 if (unlikely(!ctx->fpu_enabled)) { \
3443 gen_exception(ctx, POWERPC_EXCP_FPU); \
3444 return; \
3445 } \
3446 if (unlikely(rA(ctx->opcode) == 0)) { \
3447 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3448 return; \
3449 } \
3450 gen_set_access_type(ctx, ACCESS_FLOAT); \
3451 EA = tcg_temp_new(); \
3452 gen_addr_reg_index(ctx, EA); \
3453 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3454 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3455 tcg_temp_free(EA); \
3456 }
3457
3458 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3459 static void glue(gen_, name##x)(DisasContext *ctx) \
3460 { \
3461 TCGv EA; \
3462 if (unlikely(!ctx->fpu_enabled)) { \
3463 gen_exception(ctx, POWERPC_EXCP_FPU); \
3464 return; \
3465 } \
3466 gen_set_access_type(ctx, ACCESS_FLOAT); \
3467 EA = tcg_temp_new(); \
3468 gen_addr_reg_index(ctx, EA); \
3469 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3470 tcg_temp_free(EA); \
3471 }
3472
3473 #define GEN_LDFS(name, ldop, op, type) \
3474 GEN_LDF(name, ldop, op | 0x20, type); \
3475 GEN_LDUF(name, ldop, op | 0x21, type); \
3476 GEN_LDUXF(name, ldop, op | 0x01, type); \
3477 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3478
3479 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3480 {
3481 TCGv t0 = tcg_temp_new();
3482 TCGv_i32 t1 = tcg_temp_new_i32();
3483 gen_qemu_ld32u(ctx, t0, arg2);
3484 tcg_gen_trunc_tl_i32(t1, t0);
3485 tcg_temp_free(t0);
3486 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3487 tcg_temp_free_i32(t1);
3488 }
3489
3490 /* lfd lfdu lfdux lfdx */
3491 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3492 /* lfs lfsu lfsux lfsx */
3493 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3494
3495 /* lfdp */
3496 static void gen_lfdp(DisasContext *ctx)
3497 {
3498 TCGv EA;
3499 if (unlikely(!ctx->fpu_enabled)) {
3500 gen_exception(ctx, POWERPC_EXCP_FPU);
3501 return;
3502 }
3503 gen_set_access_type(ctx, ACCESS_FLOAT);
3504 EA = tcg_temp_new();
3505 gen_addr_imm_index(ctx, EA, 0);
3506 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3507 64-bit byteswap already. */
3508 if (unlikely(ctx->le_mode)) {
3509 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3510 tcg_gen_addi_tl(EA, EA, 8);
3511 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3512 } else {
3513 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3514 tcg_gen_addi_tl(EA, EA, 8);
3515 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3516 }
3517 tcg_temp_free(EA);
3518 }
3519
3520 /* lfdpx */
3521 static void gen_lfdpx(DisasContext *ctx)
3522 {
3523 TCGv EA;
3524 if (unlikely(!ctx->fpu_enabled)) {
3525 gen_exception(ctx, POWERPC_EXCP_FPU);
3526 return;
3527 }
3528 gen_set_access_type(ctx, ACCESS_FLOAT);
3529 EA = tcg_temp_new();
3530 gen_addr_reg_index(ctx, EA);
3531 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3532 64-bit byteswap already. */
3533 if (unlikely(ctx->le_mode)) {
3534 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3535 tcg_gen_addi_tl(EA, EA, 8);
3536 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3537 } else {
3538 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3539 tcg_gen_addi_tl(EA, EA, 8);
3540 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3541 }
3542 tcg_temp_free(EA);
3543 }
3544
3545 /* lfiwax */
3546 static void gen_lfiwax(DisasContext *ctx)
3547 {
3548 TCGv EA;
3549 TCGv t0;
3550 if (unlikely(!ctx->fpu_enabled)) {
3551 gen_exception(ctx, POWERPC_EXCP_FPU);
3552 return;
3553 }
3554 gen_set_access_type(ctx, ACCESS_FLOAT);
3555 EA = tcg_temp_new();
3556 t0 = tcg_temp_new();
3557 gen_addr_reg_index(ctx, EA);
3558 gen_qemu_ld32s(ctx, t0, EA);
3559 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3560 tcg_temp_free(EA);
3561 tcg_temp_free(t0);
3562 }
3563
3564 /* lfiwzx */
3565 static void gen_lfiwzx(DisasContext *ctx)
3566 {
3567 TCGv EA;
3568 if (unlikely(!ctx->fpu_enabled)) {
3569 gen_exception(ctx, POWERPC_EXCP_FPU);
3570 return;
3571 }
3572 gen_set_access_type(ctx, ACCESS_FLOAT);
3573 EA = tcg_temp_new();
3574 gen_addr_reg_index(ctx, EA);
3575 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3576 tcg_temp_free(EA);
3577 }
3578 /*** Floating-point store ***/
3579 #define GEN_STF(name, stop, opc, type) \
3580 static void glue(gen_, name)(DisasContext *ctx) \
3581 { \
3582 TCGv EA; \
3583 if (unlikely(!ctx->fpu_enabled)) { \
3584 gen_exception(ctx, POWERPC_EXCP_FPU); \
3585 return; \
3586 } \
3587 gen_set_access_type(ctx, ACCESS_FLOAT); \
3588 EA = tcg_temp_new(); \
3589 gen_addr_imm_index(ctx, EA, 0); \
3590 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3591 tcg_temp_free(EA); \
3592 }
3593
3594 #define GEN_STUF(name, stop, opc, type) \
3595 static void glue(gen_, name##u)(DisasContext *ctx) \
3596 { \
3597 TCGv EA; \
3598 if (unlikely(!ctx->fpu_enabled)) { \
3599 gen_exception(ctx, POWERPC_EXCP_FPU); \
3600 return; \
3601 } \
3602 if (unlikely(rA(ctx->opcode) == 0)) { \
3603 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3604 return; \
3605 } \
3606 gen_set_access_type(ctx, ACCESS_FLOAT); \
3607 EA = tcg_temp_new(); \
3608 gen_addr_imm_index(ctx, EA, 0); \
3609 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3610 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3611 tcg_temp_free(EA); \
3612 }
3613
3614 #define GEN_STUXF(name, stop, opc, type) \
3615 static void glue(gen_, name##ux)(DisasContext *ctx) \
3616 { \
3617 TCGv EA; \
3618 if (unlikely(!ctx->fpu_enabled)) { \
3619 gen_exception(ctx, POWERPC_EXCP_FPU); \
3620 return; \
3621 } \
3622 if (unlikely(rA(ctx->opcode) == 0)) { \
3623 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3624 return; \
3625 } \
3626 gen_set_access_type(ctx, ACCESS_FLOAT); \
3627 EA = tcg_temp_new(); \
3628 gen_addr_reg_index(ctx, EA); \
3629 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3631 tcg_temp_free(EA); \
3632 }
3633
3634 #define GEN_STXF(name, stop, opc2, opc3, type) \
3635 static void glue(gen_, name##x)(DisasContext *ctx) \
3636 { \
3637 TCGv EA; \
3638 if (unlikely(!ctx->fpu_enabled)) { \
3639 gen_exception(ctx, POWERPC_EXCP_FPU); \
3640 return; \
3641 } \
3642 gen_set_access_type(ctx, ACCESS_FLOAT); \
3643 EA = tcg_temp_new(); \
3644 gen_addr_reg_index(ctx, EA); \
3645 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3646 tcg_temp_free(EA); \
3647 }
3648
3649 #define GEN_STFS(name, stop, op, type) \
3650 GEN_STF(name, stop, op | 0x20, type); \
3651 GEN_STUF(name, stop, op | 0x21, type); \
3652 GEN_STUXF(name, stop, op | 0x01, type); \
3653 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3654
3655 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3656 {
3657 TCGv_i32 t0 = tcg_temp_new_i32();
3658 TCGv t1 = tcg_temp_new();
3659 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3660 tcg_gen_extu_i32_tl(t1, t0);
3661 tcg_temp_free_i32(t0);
3662 gen_qemu_st32(ctx, t1, arg2);
3663 tcg_temp_free(t1);
3664 }
3665
3666 /* stfd stfdu stfdux stfdx */
3667 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3668 /* stfs stfsu stfsux stfsx */
3669 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3670
3671 /* stfdp */
3672 static void gen_stfdp(DisasContext *ctx)
3673 {
3674 TCGv EA;
3675 if (unlikely(!ctx->fpu_enabled)) {
3676 gen_exception(ctx, POWERPC_EXCP_FPU);
3677 return;
3678 }
3679 gen_set_access_type(ctx, ACCESS_FLOAT);
3680 EA = tcg_temp_new();
3681 gen_addr_imm_index(ctx, EA, 0);
3682 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3683 64-bit byteswap already. */
3684 if (unlikely(ctx->le_mode)) {
3685 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3686 tcg_gen_addi_tl(EA, EA, 8);
3687 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3688 } else {
3689 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3690 tcg_gen_addi_tl(EA, EA, 8);
3691 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3692 }
3693 tcg_temp_free(EA);
3694 }
3695
3696 /* stfdpx */
3697 static void gen_stfdpx(DisasContext *ctx)
3698 {
3699 TCGv EA;
3700 if (unlikely(!ctx->fpu_enabled)) {
3701 gen_exception(ctx, POWERPC_EXCP_FPU);
3702 return;
3703 }
3704 gen_set_access_type(ctx, ACCESS_FLOAT);
3705 EA = tcg_temp_new();
3706 gen_addr_reg_index(ctx, EA);
3707 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3708 64-bit byteswap already. */
3709 if (unlikely(ctx->le_mode)) {
3710 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3711 tcg_gen_addi_tl(EA, EA, 8);
3712 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3713 } else {
3714 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3715 tcg_gen_addi_tl(EA, EA, 8);
3716 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3717 }
3718 tcg_temp_free(EA);
3719 }
3720
3721 /* Optional: */
3722 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3723 {
3724 TCGv t0 = tcg_temp_new();
3725 tcg_gen_trunc_i64_tl(t0, arg1),
3726 gen_qemu_st32(ctx, t0, arg2);
3727 tcg_temp_free(t0);
3728 }
3729 /* stfiwx */
3730 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3731
3732 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3733 {
3734 #if defined(TARGET_PPC64)
3735 if (ctx->has_cfar)
3736 tcg_gen_movi_tl(cpu_cfar, nip);
3737 #endif
3738 }
3739
3740 /*** Branch ***/
3741 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3742 {
3743 TranslationBlock *tb;
3744 tb = ctx->tb;
3745 if (NARROW_MODE(ctx)) {
3746 dest = (uint32_t) dest;
3747 }
3748 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3749 likely(!ctx->singlestep_enabled)) {
3750 tcg_gen_goto_tb(n);
3751 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3752 tcg_gen_exit_tb((uintptr_t)tb + n);
3753 } else {
3754 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3755 if (unlikely(ctx->singlestep_enabled)) {
3756 if ((ctx->singlestep_enabled &
3757 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3758 (ctx->exception == POWERPC_EXCP_BRANCH ||
3759 ctx->exception == POWERPC_EXCP_TRACE)) {
3760 target_ulong tmp = ctx->nip;
3761 ctx->nip = dest;
3762 gen_exception(ctx, POWERPC_EXCP_TRACE);
3763 ctx->nip = tmp;
3764 }
3765 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3766 gen_debug_exception(ctx);
3767 }
3768 }
3769 tcg_gen_exit_tb(0);
3770 }
3771 }
3772
3773 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3774 {
3775 if (NARROW_MODE(ctx)) {
3776 nip = (uint32_t)nip;
3777 }
3778 tcg_gen_movi_tl(cpu_lr, nip);
3779 }
3780
3781 /* b ba bl bla */
3782 static void gen_b(DisasContext *ctx)
3783 {
3784 target_ulong li, target;
3785
3786 ctx->exception = POWERPC_EXCP_BRANCH;
3787 /* sign extend LI */
3788 li = LI(ctx->opcode);
3789 li = (li ^ 0x02000000) - 0x02000000;
3790 if (likely(AA(ctx->opcode) == 0)) {
3791 target = ctx->nip + li - 4;
3792 } else {
3793 target = li;
3794 }
3795 if (LK(ctx->opcode)) {
3796 gen_setlr(ctx, ctx->nip);
3797 }
3798 gen_update_cfar(ctx, ctx->nip);
3799 gen_goto_tb(ctx, 0, target);
3800 }
3801
3802 #define BCOND_IM 0
3803 #define BCOND_LR 1
3804 #define BCOND_CTR 2
3805 #define BCOND_TAR 3
3806
3807 static inline void gen_bcond(DisasContext *ctx, int type)
3808 {
3809 uint32_t bo = BO(ctx->opcode);
3810 int l1;
3811 TCGv target;
3812
3813 ctx->exception = POWERPC_EXCP_BRANCH;
3814 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3815 target = tcg_temp_local_new();
3816 if (type == BCOND_CTR)
3817 tcg_gen_mov_tl(target, cpu_ctr);
3818 else if (type == BCOND_TAR)
3819 gen_load_spr(target, SPR_TAR);
3820 else
3821 tcg_gen_mov_tl(target, cpu_lr);
3822 } else {
3823 TCGV_UNUSED(target);
3824 }
3825 if (LK(ctx->opcode))
3826 gen_setlr(ctx, ctx->nip);
3827 l1 = gen_new_label();
3828 if ((bo & 0x4) == 0) {
3829 /* Decrement and test CTR */
3830 TCGv temp = tcg_temp_new();
3831 if (unlikely(type == BCOND_CTR)) {
3832 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3833 return;
3834 }
3835 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3836 if (NARROW_MODE(ctx)) {
3837 tcg_gen_ext32u_tl(temp, cpu_ctr);
3838 } else {
3839 tcg_gen_mov_tl(temp, cpu_ctr);
3840 }
3841 if (bo & 0x2) {
3842 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3843 } else {
3844 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3845 }
3846 tcg_temp_free(temp);
3847 }
3848 if ((bo & 0x10) == 0) {
3849 /* Test CR */
3850 uint32_t bi = BI(ctx->opcode);
3851 uint32_t mask = 1 << (3 - (bi & 0x03));
3852 TCGv_i32 temp = tcg_temp_new_i32();
3853
3854 if (bo & 0x8) {
3855 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3856 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3857 } else {
3858 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3859 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3860 }
3861 tcg_temp_free_i32(temp);
3862 }
3863 gen_update_cfar(ctx, ctx->nip);
3864 if (type == BCOND_IM) {
3865 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3866 if (likely(AA(ctx->opcode) == 0)) {
3867 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3868 } else {
3869 gen_goto_tb(ctx, 0, li);
3870 }
3871 gen_set_label(l1);
3872 gen_goto_tb(ctx, 1, ctx->nip);
3873 } else {
3874 if (NARROW_MODE(ctx)) {
3875 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3876 } else {
3877 tcg_gen_andi_tl(cpu_nip, target, ~3);
3878 }
3879 tcg_gen_exit_tb(0);
3880 gen_set_label(l1);
3881 gen_update_nip(ctx, ctx->nip);
3882 tcg_gen_exit_tb(0);
3883 }
3884 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3885 tcg_temp_free(target);
3886 }
3887 }
3888
3889 static void gen_bc(DisasContext *ctx)
3890 {
3891 gen_bcond(ctx, BCOND_IM);
3892 }
3893
3894 static void gen_bcctr(DisasContext *ctx)
3895 {
3896 gen_bcond(ctx, BCOND_CTR);
3897 }
3898
3899 static void gen_bclr(DisasContext *ctx)
3900 {
3901 gen_bcond(ctx, BCOND_LR);
3902 }
3903
3904 static void gen_bctar(DisasContext *ctx)
3905 {
3906 gen_bcond(ctx, BCOND_TAR);
3907 }
3908
3909 /*** Condition register logical ***/
3910 #define GEN_CRLOGIC(name, tcg_op, opc) \
3911 static void glue(gen_, name)(DisasContext *ctx) \
3912 { \
3913 uint8_t bitmask; \
3914 int sh; \
3915 TCGv_i32 t0, t1; \
3916 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3917 t0 = tcg_temp_new_i32(); \
3918 if (sh > 0) \
3919 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3920 else if (sh < 0) \
3921 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3922 else \
3923 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3924 t1 = tcg_temp_new_i32(); \
3925 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3926 if (sh > 0) \
3927 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3928 else if (sh < 0) \
3929 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3930 else \
3931 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3932 tcg_op(t0, t0, t1); \
3933 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3934 tcg_gen_andi_i32(t0, t0, bitmask); \
3935 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3936 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3937 tcg_temp_free_i32(t0); \
3938 tcg_temp_free_i32(t1); \
3939 }
3940
3941 /* crand */
3942 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3943 /* crandc */
3944 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3945 /* creqv */
3946 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3947 /* crnand */
3948 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3949 /* crnor */
3950 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3951 /* cror */
3952 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3953 /* crorc */
3954 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3955 /* crxor */
3956 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3957
3958 /* mcrf */
3959 static void gen_mcrf(DisasContext *ctx)
3960 {
3961 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3962 }
3963
3964 /*** System linkage ***/
3965
3966 /* rfi (mem_idx only) */
3967 static void gen_rfi(DisasContext *ctx)
3968 {
3969 #if defined(CONFIG_USER_ONLY)
3970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3971 #else
3972 /* Restore CPU state */
3973 if (unlikely(!ctx->mem_idx)) {
3974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3975 return;
3976 }
3977 gen_update_cfar(ctx, ctx->nip);
3978 gen_helper_rfi(cpu_env);
3979 gen_sync_exception(ctx);
3980 #endif
3981 }
3982
3983 #if defined(TARGET_PPC64)
3984 static void gen_rfid(DisasContext *ctx)
3985 {
3986 #if defined(CONFIG_USER_ONLY)
3987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3988 #else
3989 /* Restore CPU state */
3990 if (unlikely(!ctx->mem_idx)) {
3991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3992 return;
3993 }
3994 gen_update_cfar(ctx, ctx->nip);
3995 gen_helper_rfid(cpu_env);
3996 gen_sync_exception(ctx);
3997 #endif
3998 }
3999
4000 static void gen_hrfid(DisasContext *ctx)
4001 {
4002 #if defined(CONFIG_USER_ONLY)
4003 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4004 #else
4005 /* Restore CPU state */
4006 if (unlikely(ctx->mem_idx <= 1)) {
4007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4008 return;
4009 }
4010 gen_helper_hrfid(cpu_env);
4011 gen_sync_exception(ctx);
4012 #endif
4013 }
4014 #endif
4015
4016 /* sc */
4017 #if defined(CONFIG_USER_ONLY)
4018 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4019 #else
4020 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4021 #endif
4022 static void gen_sc(DisasContext *ctx)
4023 {
4024 uint32_t lev;
4025
4026 lev = (ctx->opcode >> 5) & 0x7F;
4027 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4028 }
4029
4030 /*** Trap ***/
4031
4032 /* tw */
4033 static void gen_tw(DisasContext *ctx)
4034 {
4035 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4036 /* Update the nip since this might generate a trap exception */
4037 gen_update_nip(ctx, ctx->nip);
4038 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4039 t0);
4040 tcg_temp_free_i32(t0);
4041 }
4042
4043 /* twi */
4044 static void gen_twi(DisasContext *ctx)
4045 {
4046 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4047 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4048 /* Update the nip since this might generate a trap exception */
4049 gen_update_nip(ctx, ctx->nip);
4050 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4051 tcg_temp_free(t0);
4052 tcg_temp_free_i32(t1);
4053 }
4054
4055 #if defined(TARGET_PPC64)
4056 /* td */
4057 static void gen_td(DisasContext *ctx)
4058 {
4059 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4060 /* Update the nip since this might generate a trap exception */
4061 gen_update_nip(ctx, ctx->nip);
4062 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4063 t0);
4064 tcg_temp_free_i32(t0);
4065 }
4066
4067 /* tdi */
4068 static void gen_tdi(DisasContext *ctx)
4069 {
4070 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4071 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4072 /* Update the nip since this might generate a trap exception */
4073 gen_update_nip(ctx, ctx->nip);
4074 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4075 tcg_temp_free(t0);
4076 tcg_temp_free_i32(t1);
4077 }
4078 #endif
4079
4080 /*** Processor control ***/
4081
4082 static void gen_read_xer(TCGv dst)
4083 {
4084 TCGv t0 = tcg_temp_new();
4085 TCGv t1 = tcg_temp_new();
4086 TCGv t2 = tcg_temp_new();
4087 tcg_gen_mov_tl(dst, cpu_xer);
4088 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4089 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4090 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4091 tcg_gen_or_tl(t0, t0, t1);
4092 tcg_gen_or_tl(dst, dst, t2);
4093 tcg_gen_or_tl(dst, dst, t0);
4094 tcg_temp_free(t0);
4095 tcg_temp_free(t1);
4096 tcg_temp_free(t2);
4097 }
4098
4099 static void gen_write_xer(TCGv src)
4100 {
4101 tcg_gen_andi_tl(cpu_xer, src,
4102 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4103 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4104 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4105 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4106 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4107 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4108 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4109 }
4110
4111 /* mcrxr */
4112 static void gen_mcrxr(DisasContext *ctx)
4113 {
4114 TCGv_i32 t0 = tcg_temp_new_i32();
4115 TCGv_i32 t1 = tcg_temp_new_i32();
4116 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4117
4118 tcg_gen_trunc_tl_i32(t0, cpu_so);
4119 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4120 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4121 tcg_gen_shli_i32(t0, t0, 3);
4122 tcg_gen_shli_i32(t1, t1, 2);
4123 tcg_gen_shli_i32(dst, dst, 1);
4124 tcg_gen_or_i32(dst, dst, t0);
4125 tcg_gen_or_i32(dst, dst, t1);
4126 tcg_temp_free_i32(t0);
4127 tcg_temp_free_i32(t1);
4128
4129 tcg_gen_movi_tl(cpu_so, 0);
4130 tcg_gen_movi_tl(cpu_ov, 0);
4131 tcg_gen_movi_tl(cpu_ca, 0);
4132 }
4133
4134 /* mfcr mfocrf */
4135 static void gen_mfcr(DisasContext *ctx)
4136 {
4137 uint32_t crm, crn;
4138
4139 if (likely(ctx->opcode & 0x00100000)) {
4140 crm = CRM(ctx->opcode);
4141 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4142 crn = ctz32 (crm);
4143 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4144 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4145 cpu_gpr[rD(ctx->opcode)], crn * 4);
4146 }
4147 } else {
4148 TCGv_i32 t0 = tcg_temp_new_i32();
4149 tcg_gen_mov_i32(t0, cpu_crf[0]);
4150 tcg_gen_shli_i32(t0, t0, 4);
4151 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4152 tcg_gen_shli_i32(t0, t0, 4);
4153 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4154 tcg_gen_shli_i32(t0, t0, 4);
4155 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4156 tcg_gen_shli_i32(t0, t0, 4);
4157 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4158 tcg_gen_shli_i32(t0, t0, 4);
4159 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4160 tcg_gen_shli_i32(t0, t0, 4);
4161 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4162 tcg_gen_shli_i32(t0, t0, 4);
4163 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4164 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4165 tcg_temp_free_i32(t0);
4166 }
4167 }
4168
4169 /* mfmsr */
4170 static void gen_mfmsr(DisasContext *ctx)
4171 {
4172 #if defined(CONFIG_USER_ONLY)
4173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4174 #else
4175 if (unlikely(!ctx->mem_idx)) {
4176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4177 return;
4178 }
4179 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4180 #endif
4181 }
4182
4183 static void spr_noaccess(void *opaque, int gprn, int sprn)
4184 {
4185 #if 0
4186 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4187 printf("ERROR: try to access SPR %d !\n", sprn);
4188 #endif
4189 }
4190 #define SPR_NOACCESS (&spr_noaccess)
4191
4192 /* mfspr */
4193 static inline void gen_op_mfspr(DisasContext *ctx)
4194 {
4195 void (*read_cb)(void *opaque, int gprn, int sprn);
4196 uint32_t sprn = SPR(ctx->opcode);
4197
4198 #if !defined(CONFIG_USER_ONLY)
4199 if (ctx->mem_idx == 2)
4200 read_cb = ctx->spr_cb[sprn].hea_read;
4201 else if (ctx->mem_idx)
4202 read_cb = ctx->spr_cb[sprn].oea_read;
4203 else
4204 #endif
4205 read_cb = ctx->spr_cb[sprn].uea_read;
4206 if (likely(read_cb != NULL)) {
4207 if (likely(read_cb != SPR_NOACCESS)) {
4208 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4209 } else {
4210 /* Privilege exception */
4211 /* This is a hack to avoid warnings when running Linux:
4212 * this OS breaks the PowerPC virtualisation model,
4213 * allowing userland application to read the PVR
4214 */
4215 if (sprn != SPR_PVR) {
4216 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4217 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4218 printf("Trying to read privileged spr %d (0x%03x) at "
4219 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4220 }
4221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4222 }
4223 } else {
4224 /* Not defined */
4225 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4226 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4227 printf("Trying to read invalid spr %d (0x%03x) at "
4228 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4229 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4230 }
4231 }
4232
4233 static void gen_mfspr(DisasContext *ctx)
4234 {
4235 gen_op_mfspr(ctx);
4236 }
4237
4238 /* mftb */
4239 static void gen_mftb(DisasContext *ctx)
4240 {
4241 gen_op_mfspr(ctx);
4242 }
4243
4244 /* mtcrf mtocrf*/
4245 static void gen_mtcrf(DisasContext *ctx)
4246 {
4247 uint32_t crm, crn;
4248
4249 crm = CRM(ctx->opcode);
4250 if (likely((ctx->opcode & 0x00100000))) {
4251 if (crm && ((crm & (crm - 1)) == 0)) {
4252 TCGv_i32 temp = tcg_temp_new_i32();
4253 crn = ctz32 (crm);
4254 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4255 tcg_gen_shri_i32(temp, temp, crn * 4);
4256 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4257 tcg_temp_free_i32(temp);
4258 }
4259 } else {
4260 TCGv_i32 temp = tcg_temp_new_i32();
4261 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4262 for (crn = 0 ; crn < 8 ; crn++) {
4263 if (crm & (1 << crn)) {
4264 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4265 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4266 }
4267 }
4268 tcg_temp_free_i32(temp);
4269 }
4270 }
4271
4272 /* mtmsr */
4273 #if defined(TARGET_PPC64)
4274 static void gen_mtmsrd(DisasContext *ctx)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4278 #else
4279 if (unlikely(!ctx->mem_idx)) {
4280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4281 return;
4282 }
4283 if (ctx->opcode & 0x00010000) {
4284 /* Special form that does not need any synchronisation */
4285 TCGv t0 = tcg_temp_new();
4286 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4287 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4288 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4289 tcg_temp_free(t0);
4290 } else {
4291 /* XXX: we need to update nip before the store
4292 * if we enter power saving mode, we will exit the loop
4293 * directly from ppc_store_msr
4294 */
4295 gen_update_nip(ctx, ctx->nip);
4296 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4297 /* Must stop the translation as machine state (may have) changed */
4298 /* Note that mtmsr is not always defined as context-synchronizing */
4299 gen_stop_exception(ctx);
4300 }
4301 #endif
4302 }
4303 #endif
4304
4305 static void gen_mtmsr(DisasContext *ctx)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4309 #else
4310 if (unlikely(!ctx->mem_idx)) {
4311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4312 return;
4313 }
4314 if (ctx->opcode & 0x00010000) {
4315 /* Special form that does not need any synchronisation */
4316 TCGv t0 = tcg_temp_new();
4317 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4318 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4319 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4320 tcg_temp_free(t0);
4321 } else {
4322 TCGv msr = tcg_temp_new();
4323
4324 /* XXX: we need to update nip before the store
4325 * if we enter power saving mode, we will exit the loop
4326 * directly from ppc_store_msr
4327 */
4328 gen_update_nip(ctx, ctx->nip);
4329 #if defined(TARGET_PPC64)
4330 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4331 #else
4332 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4333 #endif
4334 gen_helper_store_msr(cpu_env, msr);
4335 tcg_temp_free(msr);
4336 /* Must stop the translation as machine state (may have) changed */
4337 /* Note that mtmsr is not always defined as context-synchronizing */
4338 gen_stop_exception(ctx);
4339 }
4340 #endif
4341 }
4342
4343 /* mtspr */
4344 static void gen_mtspr(DisasContext *ctx)
4345 {
4346 void (*write_cb)(void *opaque, int sprn, int gprn);
4347 uint32_t sprn = SPR(ctx->opcode);
4348
4349 #if !defined(CONFIG_USER_ONLY)
4350 if (ctx->mem_idx == 2)
4351 write_cb = ctx->spr_cb[sprn].hea_write;
4352 else if (ctx->mem_idx)
4353 write_cb = ctx->spr_cb[sprn].oea_write;
4354 else
4355 #endif
4356 write_cb = ctx->spr_cb[sprn].uea_write;
4357 if (likely(write_cb != NULL)) {
4358 if (likely(write_cb != SPR_NOACCESS)) {
4359 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4360 } else {
4361 /* Privilege exception */
4362 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4363 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4364 printf("Trying to write privileged spr %d (0x%03x) at "
4365 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4367 }
4368 } else {
4369 /* Not defined */
4370 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4371 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4372 printf("Trying to write invalid spr %d (0x%03x) at "
4373 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4374 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4375 }
4376 }
4377
4378 /*** Cache management ***/
4379
4380 /* dcbf */
4381 static void gen_dcbf(DisasContext *ctx)
4382 {
4383 /* XXX: specification says this is treated as a load by the MMU */
4384 TCGv t0;
4385 gen_set_access_type(ctx, ACCESS_CACHE);
4386 t0 = tcg_temp_new();
4387 gen_addr_reg_index(ctx, t0);
4388 gen_qemu_ld8u(ctx, t0, t0);
4389 tcg_temp_free(t0);
4390 }
4391
4392 /* dcbi (Supervisor only) */
4393 static void gen_dcbi(DisasContext *ctx)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 #else
4398 TCGv EA, val;
4399 if (unlikely(!ctx->mem_idx)) {
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 return;
4402 }
4403 EA = tcg_temp_new();
4404 gen_set_access_type(ctx, ACCESS_CACHE);
4405 gen_addr_reg_index(ctx, EA);
4406 val = tcg_temp_new();
4407 /* XXX: specification says this should be treated as a store by the MMU */
4408 gen_qemu_ld8u(ctx, val, EA);
4409 gen_qemu_st8(ctx, val, EA);
4410 tcg_temp_free(val);
4411 tcg_temp_free(EA);
4412 #endif
4413 }
4414
4415 /* dcdst */
4416 static void gen_dcbst(DisasContext *ctx)
4417 {
4418 /* XXX: specification say this is treated as a load by the MMU */
4419 TCGv t0;
4420 gen_set_access_type(ctx, ACCESS_CACHE);
4421 t0 = tcg_temp_new();
4422 gen_addr_reg_index(ctx, t0);
4423 gen_qemu_ld8u(ctx, t0, t0);
4424 tcg_temp_free(t0);
4425 }
4426
4427 /* dcbt */
4428 static void gen_dcbt(DisasContext *ctx)
4429 {
4430 /* interpreted as no-op */
4431 /* XXX: specification say this is treated as a load by the MMU
4432 * but does not generate any exception
4433 */
4434 }
4435
4436 /* dcbtst */
4437 static void gen_dcbtst(DisasContext *ctx)
4438 {
4439 /* interpreted as no-op */
4440 /* XXX: specification say this is treated as a load by the MMU
4441 * but does not generate any exception
4442 */
4443 }
4444
4445 /* dcbtls */
4446 static void gen_dcbtls(DisasContext *ctx)
4447 {
4448 /* Always fails locking the cache */
4449 TCGv t0 = tcg_temp_new();
4450 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4451 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4452 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4453 tcg_temp_free(t0);
4454 }
4455
4456 /* dcbz */
4457 static void gen_dcbz(DisasContext *ctx)
4458 {
4459 TCGv tcgv_addr;
4460 TCGv_i32 tcgv_is_dcbzl;
4461 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4462
4463 gen_set_access_type(ctx, ACCESS_CACHE);
4464 /* NIP cannot be restored if the memory exception comes from an helper */
4465 gen_update_nip(ctx, ctx->nip - 4);
4466 tcgv_addr = tcg_temp_new();
4467 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4468
4469 gen_addr_reg_index(ctx, tcgv_addr);
4470 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4471
4472 tcg_temp_free(tcgv_addr);
4473 tcg_temp_free_i32(tcgv_is_dcbzl);
4474 }
4475
4476 /* dst / dstt */
4477 static void gen_dst(DisasContext *ctx)
4478 {
4479 if (rA(ctx->opcode) == 0) {
4480 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4481 } else {
4482 /* interpreted as no-op */
4483 }
4484 }
4485
4486 /* dstst /dststt */
4487 static void gen_dstst(DisasContext *ctx)
4488 {
4489 if (rA(ctx->opcode) == 0) {
4490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4491 } else {
4492 /* interpreted as no-op */
4493 }
4494
4495 }
4496
4497 /* dss / dssall */
4498 static void gen_dss(DisasContext *ctx)
4499 {
4500 /* interpreted as no-op */
4501 }
4502
4503 /* icbi */
4504 static void gen_icbi(DisasContext *ctx)
4505 {
4506 TCGv t0;
4507 gen_set_access_type(ctx, ACCESS_CACHE);
4508 /* NIP cannot be restored if the memory exception comes from an helper */
4509 gen_update_nip(ctx, ctx->nip - 4);
4510 t0 = tcg_temp_new();
4511 gen_addr_reg_index(ctx, t0);
4512 gen_helper_icbi(cpu_env, t0);
4513 tcg_temp_free(t0);
4514 }
4515
4516 /* Optional: */
4517 /* dcba */
4518 static void gen_dcba(DisasContext *ctx)
4519 {
4520 /* interpreted as no-op */
4521 /* XXX: specification say this is treated as a store by the MMU
4522 * but does not generate any exception
4523 */
4524 }
4525
4526 /*** Segment register manipulation ***/
4527 /* Supervisor only: */
4528
4529 /* mfsr */
4530 static void gen_mfsr(DisasContext *ctx)
4531 {
4532 #if defined(CONFIG_USER_ONLY)
4533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4534 #else
4535 TCGv t0;
4536 if (unlikely(!ctx->mem_idx)) {
4537 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4538 return;
4539 }
4540 t0 = tcg_const_tl(SR(ctx->opcode));
4541 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4542 tcg_temp_free(t0);
4543 #endif
4544 }
4545
4546 /* mfsrin */
4547 static void gen_mfsrin(DisasContext *ctx)
4548 {
4549 #if defined(CONFIG_USER_ONLY)
4550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4551 #else
4552 TCGv t0;
4553 if (unlikely(!ctx->mem_idx)) {
4554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4555 return;
4556 }
4557 t0 = tcg_temp_new();
4558 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4559 tcg_gen_andi_tl(t0, t0, 0xF);
4560 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4561 tcg_temp_free(t0);
4562 #endif
4563 }
4564
4565 /* mtsr */
4566 static void gen_mtsr(DisasContext *ctx)
4567 {
4568 #if defined(CONFIG_USER_ONLY)
4569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4570 #else
4571 TCGv t0;
4572 if (unlikely(!ctx->mem_idx)) {
4573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4574 return;
4575 }
4576 t0 = tcg_const_tl(SR(ctx->opcode));
4577 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4578 tcg_temp_free(t0);
4579 #endif
4580 }
4581
4582 /* mtsrin */
4583 static void gen_mtsrin(DisasContext *ctx)
4584 {
4585 #if defined(CONFIG_USER_ONLY)
4586 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4587 #else
4588 TCGv t0;
4589 if (unlikely(!ctx->mem_idx)) {
4590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4591 return;
4592 }
4593 t0 = tcg_temp_new();
4594 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4595 tcg_gen_andi_tl(t0, t0, 0xF);
4596 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4597 tcg_temp_free(t0);
4598 #endif
4599 }
4600
4601 #if defined(TARGET_PPC64)
4602 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4603
4604 /* mfsr */
4605 static void gen_mfsr_64b(DisasContext *ctx)
4606 {
4607 #if defined(CONFIG_USER_ONLY)
4608 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4609 #else
4610 TCGv t0;
4611 if (unlikely(!ctx->mem_idx)) {
4612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4613 return;
4614 }
4615 t0 = tcg_const_tl(SR(ctx->opcode));
4616 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4617 tcg_temp_free(t0);
4618 #endif
4619 }
4620
4621 /* mfsrin */
4622 static void gen_mfsrin_64b(DisasContext *ctx)
4623 {
4624 #if defined(CONFIG_USER_ONLY)
4625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4626 #else
4627 TCGv t0;
4628 if (unlikely(!ctx->mem_idx)) {
4629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4630 return;
4631 }
4632 t0 = tcg_temp_new();
4633 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4634 tcg_gen_andi_tl(t0, t0, 0xF);
4635 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4636 tcg_temp_free(t0);
4637 #endif
4638 }
4639
4640 /* mtsr */
4641 static void gen_mtsr_64b(DisasContext *ctx)
4642 {
4643 #if defined(CONFIG_USER_ONLY)
4644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4645 #else
4646 TCGv t0;
4647 if (unlikely(!ctx->mem_idx)) {
4648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4649 return;
4650 }
4651 t0 = tcg_const_tl(SR(ctx->opcode));
4652 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4653 tcg_temp_free(t0);
4654 #endif
4655 }
4656
4657 /* mtsrin */
4658 static void gen_mtsrin_64b(DisasContext *ctx)
4659 {
4660 #if defined(CONFIG_USER_ONLY)
4661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4662 #else
4663 TCGv t0;
4664 if (unlikely(!ctx->mem_idx)) {
4665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4666 return;
4667 }
4668 t0 = tcg_temp_new();
4669 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4670 tcg_gen_andi_tl(t0, t0, 0xF);
4671 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4672 tcg_temp_free(t0);
4673 #endif
4674 }
4675
4676 /* slbmte */
4677 static void gen_slbmte(DisasContext *ctx)
4678 {
4679 #if defined(CONFIG_USER_ONLY)
4680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4681 #else
4682 if (unlikely(!ctx->mem_idx)) {
4683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4684 return;
4685 }
4686 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4687 cpu_gpr[rS(ctx->opcode)]);
4688 #endif
4689 }
4690
4691 static void gen_slbmfee(DisasContext *ctx)
4692 {
4693 #if defined(CONFIG_USER_ONLY)
4694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4695 #else
4696 if (unlikely(!ctx->mem_idx)) {
4697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4698 return;
4699 }
4700 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4701 cpu_gpr[rB(ctx->opcode)]);
4702 #endif
4703 }
4704
4705 static void gen_slbmfev(DisasContext *ctx)
4706 {
4707 #if defined(CONFIG_USER_ONLY)
4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4709 #else
4710 if (unlikely(!ctx->mem_idx)) {
4711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4712 return;
4713 }
4714 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4715 cpu_gpr[rB(ctx->opcode)]);
4716 #endif
4717 }
4718 #endif /* defined(TARGET_PPC64) */
4719
4720 /*** Lookaside buffer management ***/
4721 /* Optional & mem_idx only: */
4722
4723 /* tlbia */
4724 static void gen_tlbia(DisasContext *ctx)
4725 {
4726 #if defined(CONFIG_USER_ONLY)
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4728 #else
4729 if (unlikely(!ctx->mem_idx)) {
4730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4731 return;
4732 }
4733 gen_helper_tlbia(cpu_env);
4734 #endif
4735 }
4736
4737 /* tlbiel */
4738 static void gen_tlbiel(DisasContext *ctx)
4739 {
4740 #if defined(CONFIG_USER_ONLY)
4741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4742 #else
4743 if (unlikely(!ctx->mem_idx)) {
4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4745 return;
4746 }
4747 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4748 #endif
4749 }
4750
4751 /* tlbie */
4752 static void gen_tlbie(DisasContext *ctx)
4753 {
4754 #if defined(CONFIG_USER_ONLY)
4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4756 #else
4757 if (unlikely(!ctx->mem_idx)) {
4758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4759 return;
4760 }
4761 if (NARROW_MODE(ctx)) {
4762 TCGv t0 = tcg_temp_new();
4763 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4764 gen_helper_tlbie(cpu_env, t0);
4765 tcg_temp_free(t0);
4766 } else {
4767 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4768 }
4769 #endif
4770 }
4771
4772 /* tlbsync */
4773 static void gen_tlbsync(DisasContext *ctx)
4774 {
4775 #if defined(CONFIG_USER_ONLY)
4776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4777 #else
4778 if (unlikely(!ctx->mem_idx)) {
4779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4780 return;
4781 }
4782 /* This has no effect: it should ensure that all previous
4783 * tlbie have completed
4784 */
4785 gen_stop_exception(ctx);
4786 #endif
4787 }
4788
4789 #if defined(TARGET_PPC64)
4790 /* slbia */
4791 static void gen_slbia(DisasContext *ctx)
4792 {
4793 #if defined(CONFIG_USER_ONLY)
4794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4795 #else
4796 if (unlikely(!ctx->mem_idx)) {
4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4798 return;
4799 }
4800 gen_helper_slbia(cpu_env);
4801 #endif
4802 }
4803
4804 /* slbie */
4805 static void gen_slbie(DisasContext *ctx)
4806 {
4807 #if defined(CONFIG_USER_ONLY)
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809 #else
4810 if (unlikely(!ctx->mem_idx)) {
4811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4812 return;
4813 }
4814 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4815 #endif
4816 }
4817 #endif
4818
4819 /*** External control ***/
4820 /* Optional: */
4821
4822 /* eciwx */
4823 static void gen_eciwx(DisasContext *ctx)
4824 {
4825 TCGv t0;
4826 /* Should check EAR[E] ! */
4827 gen_set_access_type(ctx, ACCESS_EXT);
4828 t0 = tcg_temp_new();
4829 gen_addr_reg_index(ctx, t0);
4830 gen_check_align(ctx, t0, 0x03);
4831 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4832 tcg_temp_free(t0);
4833 }
4834
4835 /* ecowx */
4836 static void gen_ecowx(DisasContext *ctx)
4837 {
4838 TCGv t0;
4839 /* Should check EAR[E] ! */
4840 gen_set_access_type(ctx, ACCESS_EXT);
4841 t0 = tcg_temp_new();
4842 gen_addr_reg_index(ctx, t0);
4843 gen_check_align(ctx, t0, 0x03);
4844 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4845 tcg_temp_free(t0);
4846 }
4847
4848 /* PowerPC 601 specific instructions */
4849
4850 /* abs - abs. */
4851 static void gen_abs(DisasContext *ctx)
4852 {
4853 int l1 = gen_new_label();
4854 int l2 = gen_new_label();
4855 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4856 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4857 tcg_gen_br(l2);
4858 gen_set_label(l1);
4859 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4860 gen_set_label(l2);
4861 if (unlikely(Rc(ctx->opcode) != 0))
4862 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4863 }
4864
4865 /* abso - abso. */
4866 static void gen_abso(DisasContext *ctx)
4867 {
4868 int l1 = gen_new_label();
4869 int l2 = gen_new_label();
4870 int l3 = gen_new_label();
4871 /* Start with XER OV disabled, the most likely case */
4872 tcg_gen_movi_tl(cpu_ov, 0);
4873 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4874 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4875 tcg_gen_movi_tl(cpu_ov, 1);
4876 tcg_gen_movi_tl(cpu_so, 1);
4877 tcg_gen_br(l2);
4878 gen_set_label(l1);
4879 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4880 tcg_gen_br(l3);
4881 gen_set_label(l2);
4882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4883 gen_set_label(l3);
4884 if (unlikely(Rc(ctx->opcode) != 0))
4885 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4886 }
4887
4888 /* clcs */
4889 static void gen_clcs(DisasContext *ctx)
4890 {
4891 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4892 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4893 tcg_temp_free_i32(t0);
4894 /* Rc=1 sets CR0 to an undefined state */
4895 }
4896
4897 /* div - div. */
4898 static void gen_div(DisasContext *ctx)
4899 {
4900 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4901 cpu_gpr[rB(ctx->opcode)]);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4904 }
4905
4906 /* divo - divo. */
4907 static void gen_divo(DisasContext *ctx)
4908 {
4909 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4910 cpu_gpr[rB(ctx->opcode)]);
4911 if (unlikely(Rc(ctx->opcode) != 0))
4912 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4913 }
4914
4915 /* divs - divs. */
4916 static void gen_divs(DisasContext *ctx)
4917 {
4918 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4919 cpu_gpr[rB(ctx->opcode)]);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4922 }
4923
4924 /* divso - divso. */
4925 static void gen_divso(DisasContext *ctx)
4926 {
4927 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4928 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4929 if (unlikely(Rc(ctx->opcode) != 0))
4930 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4931 }
4932
4933 /* doz - doz. */
4934 static void gen_doz(DisasContext *ctx)
4935 {
4936 int l1 = gen_new_label();
4937 int l2 = gen_new_label();
4938 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4939 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4940 tcg_gen_br(l2);
4941 gen_set_label(l1);
4942 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4943 gen_set_label(l2);
4944 if (unlikely(Rc(ctx->opcode) != 0))
4945 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4946 }
4947
4948 /* dozo - dozo. */
4949 static void gen_dozo(DisasContext *ctx)
4950 {
4951 int l1 = gen_new_label();
4952 int l2 = gen_new_label();
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 TCGv t2 = tcg_temp_new();
4956 /* Start with XER OV disabled, the most likely case */
4957 tcg_gen_movi_tl(cpu_ov, 0);
4958 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4959 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4960 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4961 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4962 tcg_gen_andc_tl(t1, t1, t2);
4963 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4964 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4965 tcg_gen_movi_tl(cpu_ov, 1);
4966 tcg_gen_movi_tl(cpu_so, 1);
4967 tcg_gen_br(l2);
4968 gen_set_label(l1);
4969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4970 gen_set_label(l2);
4971 tcg_temp_free(t0);
4972 tcg_temp_free(t1);
4973 tcg_temp_free(t2);
4974 if (unlikely(Rc(ctx->opcode) != 0))
4975 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4976 }
4977
4978 /* dozi */
4979 static void gen_dozi(DisasContext *ctx)
4980 {
4981 target_long simm = SIMM(ctx->opcode);
4982 int l1 = gen_new_label();
4983 int l2 = gen_new_label();
4984 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4985 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4986 tcg_gen_br(l2);
4987 gen_set_label(l1);
4988 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4989 gen_set_label(l2);
4990 if (unlikely(Rc(ctx->opcode) != 0))
4991 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4992 }
4993
4994 /* lscbx - lscbx. */
4995 static void gen_lscbx(DisasContext *ctx)
4996 {
4997 TCGv t0 = tcg_temp_new();
4998 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4999 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5000 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5001
5002 gen_addr_reg_index(ctx, t0);
5003 /* NIP cannot be restored if the memory exception comes from an helper */
5004 gen_update_nip(ctx, ctx->nip - 4);
5005 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5006 tcg_temp_free_i32(t1);
5007 tcg_temp_free_i32(t2);
5008 tcg_temp_free_i32(t3);
5009 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5010 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5011 if (unlikely(Rc(ctx->opcode) != 0))
5012 gen_set_Rc0(ctx, t0);
5013 tcg_temp_free(t0);
5014 }
5015
5016 /* maskg - maskg. */
5017 static void gen_maskg(DisasContext *ctx)
5018 {
5019 int l1 = gen_new_label();
5020 TCGv t0 = tcg_temp_new();
5021 TCGv t1 = tcg_temp_new();
5022 TCGv t2 = tcg_temp_new();
5023 TCGv t3 = tcg_temp_new();
5024 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5025 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5026 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5027 tcg_gen_addi_tl(t2, t0, 1);
5028 tcg_gen_shr_tl(t2, t3, t2);
5029 tcg_gen_shr_tl(t3, t3, t1);
5030 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5031 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5032 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5033 gen_set_label(l1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 tcg_temp_free(t2);
5037 tcg_temp_free(t3);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5040 }
5041
5042 /* maskir - maskir. */
5043 static void gen_maskir(DisasContext *ctx)
5044 {
5045 TCGv t0 = tcg_temp_new();
5046 TCGv t1 = tcg_temp_new();
5047 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5048 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5050 tcg_temp_free(t0);
5051 tcg_temp_free(t1);
5052 if (unlikely(Rc(ctx->opcode) != 0))
5053 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5054 }
5055
5056 /* mul - mul. */
5057 static void gen_mul(DisasContext *ctx)
5058 {
5059 TCGv_i64 t0 = tcg_temp_new_i64();
5060 TCGv_i64 t1 = tcg_temp_new_i64();
5061 TCGv t2 = tcg_temp_new();
5062 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5063 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5064 tcg_gen_mul_i64(t0, t0, t1);
5065 tcg_gen_trunc_i64_tl(t2, t0);
5066 gen_store_spr(SPR_MQ, t2);
5067 tcg_gen_shri_i64(t1, t0, 32);
5068 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5069 tcg_temp_free_i64(t0);
5070 tcg_temp_free_i64(t1);
5071 tcg_temp_free(t2);
5072 if (unlikely(Rc(ctx->opcode) != 0))
5073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5074 }
5075
5076 /* mulo - mulo. */
5077 static void gen_mulo(DisasContext *ctx)
5078 {
5079 int l1 = gen_new_label();
5080 TCGv_i64 t0 = tcg_temp_new_i64();
5081 TCGv_i64 t1 = tcg_temp_new_i64();
5082 TCGv t2 = tcg_temp_new();
5083 /* Start with XER OV disabled, the most likely case */
5084 tcg_gen_movi_tl(cpu_ov, 0);
5085 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5086 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5087 tcg_gen_mul_i64(t0, t0, t1);
5088 tcg_gen_trunc_i64_tl(t2, t0);
5089 gen_store_spr(SPR_MQ, t2);
5090 tcg_gen_shri_i64(t1, t0, 32);
5091 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5092 tcg_gen_ext32s_i64(t1, t0);
5093 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5094 tcg_gen_movi_tl(cpu_ov, 1);
5095 tcg_gen_movi_tl(cpu_so, 1);
5096 gen_set_label(l1);
5097 tcg_temp_free_i64(t0);
5098 tcg_temp_free_i64(t1);
5099 tcg_temp_free(t2);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5102 }
5103
5104 /* nabs - nabs. */
5105 static void gen_nabs(DisasContext *ctx)
5106 {
5107 int l1 = gen_new_label();
5108 int l2 = gen_new_label();
5109 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5110 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5111 tcg_gen_br(l2);
5112 gen_set_label(l1);
5113 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5114 gen_set_label(l2);
5115 if (unlikely(Rc(ctx->opcode) != 0))
5116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5117 }
5118
5119 /* nabso - nabso. */
5120 static void gen_nabso(DisasContext *ctx)
5121 {
5122 int l1 = gen_new_label();
5123 int l2 = gen_new_label();
5124 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5125 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5126 tcg_gen_br(l2);
5127 gen_set_label(l1);
5128 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5129 gen_set_label(l2);
5130 /* nabs never overflows */
5131 tcg_gen_movi_tl(cpu_ov, 0);
5132 if (unlikely(Rc(ctx->opcode) != 0))
5133 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5134 }
5135
5136 /* rlmi - rlmi. */
5137 static void gen_rlmi(DisasContext *ctx)
5138 {
5139 uint32_t mb = MB(ctx->opcode);
5140 uint32_t me = ME(ctx->opcode);
5141 TCGv t0 = tcg_temp_new();
5142 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5143 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5144 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5145 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5146 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5147 tcg_temp_free(t0);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* rrib - rrib. */
5153 static void gen_rrib(DisasContext *ctx)
5154 {
5155 TCGv t0 = tcg_temp_new();
5156 TCGv t1 = tcg_temp_new();
5157 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5158 tcg_gen_movi_tl(t1, 0x80000000);
5159 tcg_gen_shr_tl(t1, t1, t0);
5160 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5161 tcg_gen_and_tl(t0, t0, t1);
5162 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5163 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5164 tcg_temp_free(t0);
5165 tcg_temp_free(t1);
5166 if (unlikely(Rc(ctx->opcode) != 0))
5167 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5168 }
5169
5170 /* sle - sle. */
5171 static void gen_sle(DisasContext *ctx)
5172 {
5173 TCGv t0 = tcg_temp_new();
5174 TCGv t1 = tcg_temp_new();
5175 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5176 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5177 tcg_gen_subfi_tl(t1, 32, t1);
5178 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5179 tcg_gen_or_tl(t1, t0, t1);
5180 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5181 gen_store_spr(SPR_MQ, t1);
5182 tcg_temp_free(t0);
5183 tcg_temp_free(t1);
5184 if (unlikely(Rc(ctx->opcode) != 0))
5185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5186 }
5187
5188 /* sleq - sleq. */
5189 static void gen_sleq(DisasContext *ctx)
5190 {
5191 TCGv t0 = tcg_temp_new();
5192 TCGv t1 = tcg_temp_new();
5193 TCGv t2 = tcg_temp_new();
5194 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5195 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5196 tcg_gen_shl_tl(t2, t2, t0);
5197 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5198 gen_load_spr(t1, SPR_MQ);
5199 gen_store_spr(SPR_MQ, t0);
5200 tcg_gen_and_tl(t0, t0, t2);
5201 tcg_gen_andc_tl(t1, t1, t2);
5202 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5203 tcg_temp_free(t0);
5204 tcg_temp_free(t1);
5205 tcg_temp_free(t2);
5206 if (unlikely(Rc(ctx->opcode) != 0))
5207 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5208 }
5209
5210 /* sliq - sliq. */
5211 static void gen_sliq(DisasContext *ctx)
5212 {
5213 int sh = SH(ctx->opcode);
5214 TCGv t0 = tcg_temp_new();
5215 TCGv t1 = tcg_temp_new();
5216 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5217 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5218 tcg_gen_or_tl(t1, t0, t1);
5219 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5220 gen_store_spr(SPR_MQ, t1);
5221 tcg_temp_free(t0);
5222 tcg_temp_free(t1);
5223 if (unlikely(Rc(ctx->opcode) != 0))
5224 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5225 }
5226
5227 /* slliq - slliq. */
5228 static void gen_slliq(DisasContext *ctx)
5229 {
5230 int sh = SH(ctx->opcode);
5231 TCGv t0 = tcg_temp_new();
5232 TCGv t1 = tcg_temp_new();
5233 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5234 gen_load_spr(t1, SPR_MQ);
5235 gen_store_spr(SPR_MQ, t0);
5236 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5237 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5238 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5239 tcg_temp_free(t0);
5240 tcg_temp_free(t1);
5241 if (unlikely(Rc(ctx->opcode) != 0))
5242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5243 }
5244
5245 /* sllq - sllq. */
5246 static void gen_sllq(DisasContext *ctx)
5247 {
5248 int l1 = gen_new_label();
5249 int l2 = gen_new_label();
5250 TCGv t0 = tcg_temp_local_new();
5251 TCGv t1 = tcg_temp_local_new();
5252 TCGv t2 = tcg_temp_local_new();
5253 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5254 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5255 tcg_gen_shl_tl(t1, t1, t2);
5256 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5257 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5258 gen_load_spr(t0, SPR_MQ);
5259 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5260 tcg_gen_br(l2);
5261 gen_set_label(l1);
5262 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5263 gen_load_spr(t2, SPR_MQ);
5264 tcg_gen_andc_tl(t1, t2, t1);
5265 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5266 gen_set_label(l2);
5267 tcg_temp_free(t0);
5268 tcg_temp_free(t1);
5269 tcg_temp_free(t2);
5270 if (unlikely(Rc(ctx->opcode) != 0))
5271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5272 }
5273
5274 /* slq - slq. */
5275 static void gen_slq(DisasContext *ctx)
5276 {
5277 int l1 = gen_new_label();
5278 TCGv t0 = tcg_temp_new();
5279 TCGv t1 = tcg_temp_new();
5280 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5281 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5282 tcg_gen_subfi_tl(t1, 32, t1);
5283 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5284 tcg_gen_or_tl(t1, t0, t1);
5285 gen_store_spr(SPR_MQ, t1);
5286 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5287 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5288 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5289 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5290 gen_set_label(l1);
5291 tcg_temp_free(t0);
5292 tcg_temp_free(t1);
5293 if (unlikely(Rc(ctx->opcode) != 0))
5294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5295 }
5296
5297 /* sraiq - sraiq. */
5298 static void gen_sraiq(DisasContext *ctx)
5299 {
5300 int sh = SH(ctx->opcode);
5301 int l1 = gen_new_label();
5302 TCGv t0 = tcg_temp_new();
5303 TCGv t1 = tcg_temp_new();
5304 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5305 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5306 tcg_gen_or_tl(t0, t0, t1);
5307 gen_store_spr(SPR_MQ, t0);
5308 tcg_gen_movi_tl(cpu_ca, 0);
5309 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5310 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5311 tcg_gen_movi_tl(cpu_ca, 1);
5312 gen_set_label(l1);
5313 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5314 tcg_temp_free(t0);
5315 tcg_temp_free(t1);
5316 if (unlikely(Rc(ctx->opcode) != 0))
5317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5318 }
5319
5320 /* sraq - sraq. */
5321 static void gen_sraq(DisasContext *ctx)
5322 {
5323 int l1 = gen_new_label();
5324 int l2 = gen_new_label();
5325 TCGv t0 = tcg_temp_new();
5326 TCGv t1 = tcg_temp_local_new();
5327 TCGv t2 = tcg_temp_local_new();
5328 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5329 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5330 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5331 tcg_gen_subfi_tl(t2, 32, t2);
5332 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5333 tcg_gen_or_tl(t0, t0, t2);
5334 gen_store_spr(SPR_MQ, t0);
5335 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5336 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5337 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5338 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5339 gen_set_label(l1);
5340 tcg_temp_free(t0);
5341 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5342 tcg_gen_movi_tl(cpu_ca, 0);
5343 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5344 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5345 tcg_gen_movi_tl(cpu_ca, 1);
5346 gen_set_label(l2);
5347 tcg_temp_free(t1);
5348 tcg_temp_free(t2);
5349 if (unlikely(Rc(ctx->opcode) != 0))
5350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5351 }
5352
5353 /* sre - sre. */
5354 static void gen_sre(DisasContext *ctx)
5355 {
5356 TCGv t0 = tcg_temp_new();
5357 TCGv t1 = tcg_temp_new();
5358 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5359 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5360 tcg_gen_subfi_tl(t1, 32, t1);
5361 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5362 tcg_gen_or_tl(t1, t0, t1);
5363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5364 gen_store_spr(SPR_MQ, t1);
5365 tcg_temp_free(t0);
5366 tcg_temp_free(t1);
5367 if (unlikely(Rc(ctx->opcode) != 0))
5368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5369 }
5370
5371 /* srea - srea. */
5372 static void gen_srea(DisasContext *ctx)
5373 {
5374 TCGv t0 = tcg_temp_new();
5375 TCGv t1 = tcg_temp_new();
5376 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5377 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5378 gen_store_spr(SPR_MQ, t0);
5379 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5380 tcg_temp_free(t0);
5381 tcg_temp_free(t1);
5382 if (unlikely(Rc(ctx->opcode) != 0))
5383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5384 }
5385
5386 /* sreq */
5387 static void gen_sreq(DisasContext *ctx)
5388 {
5389 TCGv t0 = tcg_temp_new();
5390 TCGv t1 = tcg_temp_new();
5391 TCGv t2 = tcg_temp_new();
5392 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5393 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5394 tcg_gen_shr_tl(t1, t1, t0);
5395 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5396 gen_load_spr(t2, SPR_MQ);
5397 gen_store_spr(SPR_MQ, t0);
5398 tcg_gen_and_tl(t0, t0, t1);
5399 tcg_gen_andc_tl(t2, t2, t1);
5400 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5401 tcg_temp_free(t0);
5402 tcg_temp_free(t1);
5403 tcg_temp_free(t2);
5404 if (unlikely(Rc(ctx->opcode) != 0))
5405 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5406 }
5407
5408 /* sriq */
5409 static void gen_sriq(DisasContext *ctx)
5410 {
5411 int sh = SH(ctx->opcode);
5412 TCGv t0 = tcg_temp_new();
5413 TCGv t1 = tcg_temp_new();
5414 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5415 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5416 tcg_gen_or_tl(t1, t0, t1);
5417 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5418 gen_store_spr(SPR_MQ, t1);
5419 tcg_temp_free(t0);
5420 tcg_temp_free(t1);
5421 if (unlikely(Rc(ctx->opcode) != 0))
5422 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5423 }
5424
5425 /* srliq */
5426 static void gen_srliq(DisasContext *ctx)
5427 {
5428 int sh = SH(ctx->opcode);
5429 TCGv t0 = tcg_temp_new();
5430 TCGv t1 = tcg_temp_new();
5431 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5432 gen_load_spr(t1, SPR_MQ);
5433 gen_store_spr(SPR_MQ, t0);
5434 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5435 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5436 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5437 tcg_temp_free(t0);
5438 tcg_temp_free(t1);
5439 if (unlikely(Rc(ctx->opcode) != 0))
5440 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5441 }
5442
5443 /* srlq */
5444 static void gen_srlq(DisasContext *ctx)
5445 {
5446 int l1 = gen_new_label();
5447 int l2 = gen_new_label();
5448 TCGv t0 = tcg_temp_local_new();
5449 TCGv t1 = tcg_temp_local_new();
5450 TCGv t2 = tcg_temp_local_new();
5451 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5452 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5453 tcg_gen_shr_tl(t2, t1, t2);
5454 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5455 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5456 gen_load_spr(t0, SPR_MQ);
5457 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5458 tcg_gen_br(l2);
5459 gen_set_label(l1);
5460 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5461 tcg_gen_and_tl(t0, t0, t2);
5462 gen_load_spr(t1, SPR_MQ);
5463 tcg_gen_andc_tl(t1, t1, t2);
5464 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5465 gen_set_label(l2);
5466 tcg_temp_free(t0);
5467 tcg_temp_free(t1);
5468 tcg_temp_free(t2);
5469 if (unlikely(Rc(ctx->opcode) != 0))
5470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5471 }
5472
5473 /* srq */
5474 static void gen_srq(DisasContext *ctx)
5475 {
5476 int l1 = gen_new_label();
5477 TCGv t0 = tcg_temp_new();
5478 TCGv t1 = tcg_temp_new();
5479 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5480 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5481 tcg_gen_subfi_tl(t1, 32, t1);
5482 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5483 tcg_gen_or_tl(t1, t0, t1);
5484 gen_store_spr(SPR_MQ, t1);
5485 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5486 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5487 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5488 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5489 gen_set_label(l1);
5490 tcg_temp_free(t0);
5491 tcg_temp_free(t1);
5492 if (unlikely(Rc(ctx->opcode) != 0))
5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5494 }
5495
5496 /* PowerPC 602 specific instructions */
5497
5498 /* dsa */
5499 static void gen_dsa(DisasContext *ctx)
5500 {
5501 /* XXX: TODO */
5502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5503 }
5504
5505 /* esa */
5506 static void gen_esa(DisasContext *ctx)
5507 {
5508 /* XXX: TODO */
5509 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5510 }
5511
5512 /* mfrom */
5513 static void gen_mfrom(DisasContext *ctx)
5514 {
5515 #if defined(CONFIG_USER_ONLY)
5516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5517 #else
5518 if (unlikely(!ctx->mem_idx)) {
5519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5520 return;
5521 }
5522 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5523 #endif
5524 }
5525
5526 /* 602 - 603 - G2 TLB management */
5527
5528 /* tlbld */
5529 static void gen_tlbld_6xx(DisasContext *ctx)
5530 {
5531 #if defined(CONFIG_USER_ONLY)
5532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5533 #else
5534 if (unlikely(!ctx->mem_idx)) {
5535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5536 return;
5537 }
5538 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5539 #endif
5540 }
5541
5542 /* tlbli */
5543 static void gen_tlbli_6xx(DisasContext *ctx)
5544 {
5545 #if defined(CONFIG_USER_ONLY)
5546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5547 #else
5548 if (unlikely(!ctx->mem_idx)) {
5549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5550 return;
5551 }
5552 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5553 #endif
5554 }
5555
5556 /* 74xx TLB management */
5557
5558 /* tlbld */
5559 static void gen_tlbld_74xx(DisasContext *ctx)
5560 {
5561 #if defined(CONFIG_USER_ONLY)
5562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5563 #else
5564 if (unlikely(!ctx->mem_idx)) {
5565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5566 return;
5567 }
5568 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5569 #endif
5570 }
5571
5572 /* tlbli */
5573 static void gen_tlbli_74xx(DisasContext *ctx)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5577 #else
5578 if (unlikely(!ctx->mem_idx)) {
5579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5580 return;
5581 }
5582 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5583 #endif
5584 }
5585
5586 /* POWER instructions not in PowerPC 601 */
5587
5588 /* clf */
5589 static void gen_clf(DisasContext *ctx)
5590 {
5591 /* Cache line flush: implemented as no-op */
5592 }
5593
5594 /* cli */
5595 static void gen_cli(DisasContext *ctx)
5596 {
5597 /* Cache line invalidate: privileged and treated as no-op */
5598 #if defined(CONFIG_USER_ONLY)
5599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5600 #else
5601 if (unlikely(!ctx->mem_idx)) {
5602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5603 return;
5604 }
5605 #endif
5606 }
5607
5608 /* dclst */
5609 static void gen_dclst(DisasContext *ctx)
5610 {
5611 /* Data cache line store: treated as no-op */
5612 }
5613
5614 static void gen_mfsri(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5618 #else
5619 int ra = rA(ctx->opcode);
5620 int rd = rD(ctx->opcode);
5621 TCGv t0;
5622 if (unlikely(!ctx->mem_idx)) {
5623 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5624 return;
5625 }
5626 t0 = tcg_temp_new();
5627 gen_addr_reg_index(ctx, t0);
5628 tcg_gen_shri_tl(t0, t0, 28);
5629 tcg_gen_andi_tl(t0, t0, 0xF);
5630 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5631 tcg_temp_free(t0);
5632 if (ra != 0 && ra != rd)
5633 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5634 #endif
5635 }
5636
5637 static void gen_rac(DisasContext *ctx)
5638 {
5639 #if defined(CONFIG_USER_ONLY)
5640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5641 #else
5642 TCGv t0;
5643 if (unlikely(!ctx->mem_idx)) {
5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5645 return;
5646 }
5647 t0 = tcg_temp_new();
5648 gen_addr_reg_index(ctx, t0);
5649 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5650 tcg_temp_free(t0);
5651 #endif
5652 }
5653
5654 static void gen_rfsvc(DisasContext *ctx)
5655 {
5656 #if defined(CONFIG_USER_ONLY)
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5658 #else
5659 if (unlikely(!ctx->mem_idx)) {
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5661 return;
5662 }
5663 gen_helper_rfsvc(cpu_env);
5664 gen_sync_exception(ctx);
5665 #endif
5666 }
5667
5668 /* svc is not implemented for now */
5669
5670 /* POWER2 specific instructions */
5671 /* Quad manipulation (load/store two floats at a time) */
5672
5673 /* lfq */
5674 static void gen_lfq(DisasContext *ctx)
5675 {
5676 int rd = rD(ctx->opcode);
5677 TCGv t0;
5678 gen_set_access_type(ctx, ACCESS_FLOAT);
5679 t0 = tcg_temp_new();
5680 gen_addr_imm_index(ctx, t0, 0);
5681 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5682 gen_addr_add(ctx, t0, t0, 8);
5683 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5684 tcg_temp_free(t0);
5685 }
5686
5687 /* lfqu */
5688 static void gen_lfqu(DisasContext *ctx)
5689 {
5690 int ra = rA(ctx->opcode);
5691 int rd = rD(ctx->opcode);
5692 TCGv t0, t1;
5693 gen_set_access_type(ctx, ACCESS_FLOAT);
5694 t0 = tcg_temp_new();
5695 t1 = tcg_temp_new();
5696 gen_addr_imm_index(ctx, t0, 0);
5697 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5698 gen_addr_add(ctx, t1, t0, 8);
5699 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5700 if (ra != 0)
5701 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5702 tcg_temp_free(t0);
5703 tcg_temp_free(t1);
5704 }
5705
5706 /* lfqux */
5707 static void gen_lfqux(DisasContext *ctx)
5708 {
5709 int ra = rA(ctx->opcode);
5710 int rd = rD(ctx->opcode);
5711 gen_set_access_type(ctx, ACCESS_FLOAT);
5712 TCGv t0, t1;
5713 t0 = tcg_temp_new();
5714 gen_addr_reg_index(ctx, t0);
5715 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5716 t1 = tcg_temp_new();
5717 gen_addr_add(ctx, t1, t0, 8);
5718 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5719 tcg_temp_free(t1);
5720 if (ra != 0)
5721 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5722 tcg_temp_free(t0);
5723 }
5724
5725 /* lfqx */
5726 static void gen_lfqx(DisasContext *ctx)
5727 {
5728 int rd = rD(ctx->opcode);
5729 TCGv t0;
5730 gen_set_access_type(ctx, ACCESS_FLOAT);
5731 t0 = tcg_temp_new();
5732 gen_addr_reg_index(ctx, t0);
5733 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5734 gen_addr_add(ctx, t0, t0, 8);
5735 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5736 tcg_temp_free(t0);
5737 }
5738
5739 /* stfq */
5740 static void gen_stfq(DisasContext *ctx)
5741 {
5742 int rd = rD(ctx->opcode);
5743 TCGv t0;
5744 gen_set_access_type(ctx, ACCESS_FLOAT);
5745 t0 = tcg_temp_new();
5746 gen_addr_imm_index(ctx, t0, 0);
5747 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5748 gen_addr_add(ctx, t0, t0, 8);
5749 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5750 tcg_temp_free(t0);
5751 }
5752
5753 /* stfqu */
5754 static void gen_stfqu(DisasContext *ctx)
5755 {
5756 int ra = rA(ctx->opcode);
5757 int rd = rD(ctx->opcode);
5758 TCGv t0, t1;
5759 gen_set_access_type(ctx, ACCESS_FLOAT);
5760 t0 = tcg_temp_new();
5761 gen_addr_imm_index(ctx, t0, 0);
5762 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5763 t1 = tcg_temp_new();
5764 gen_addr_add(ctx, t1, t0, 8);
5765 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5766 tcg_temp_free(t1);
5767 if (ra != 0)
5768 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5769 tcg_temp_free(t0);
5770 }
5771
5772 /* stfqux */
5773 static void gen_stfqux(DisasContext *ctx)
5774 {
5775 int ra = rA(ctx->opcode);
5776 int rd = rD(ctx->opcode);
5777 TCGv t0, t1;
5778 gen_set_access_type(ctx, ACCESS_FLOAT);
5779 t0 = tcg_temp_new();
5780 gen_addr_reg_index(ctx, t0);
5781 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5782 t1 = tcg_temp_new();
5783 gen_addr_add(ctx, t1, t0, 8);
5784 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5785 tcg_temp_free(t1);
5786 if (ra != 0)
5787 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5788 tcg_temp_free(t0);
5789 }
5790
5791 /* stfqx */
5792 static void gen_stfqx(DisasContext *ctx)
5793 {
5794 int rd = rD(ctx->opcode);
5795 TCGv t0;
5796 gen_set_access_type(ctx, ACCESS_FLOAT);
5797 t0 = tcg_temp_new();
5798 gen_addr_reg_index(ctx, t0);
5799 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5800 gen_addr_add(ctx, t0, t0, 8);
5801 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5802 tcg_temp_free(t0);
5803 }
5804
5805 /* BookE specific instructions */
5806
5807 /* XXX: not implemented on 440 ? */
5808 static void gen_mfapidi(DisasContext *ctx)
5809 {
5810 /* XXX: TODO */
5811 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5812 }
5813
5814 /* XXX: not implemented on 440 ? */
5815 static void gen_tlbiva(DisasContext *ctx)
5816 {
5817 #if defined(CONFIG_USER_ONLY)
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5819 #else
5820 TCGv t0;
5821 if (unlikely(!ctx->mem_idx)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 t0 = tcg_temp_new();
5826 gen_addr_reg_index(ctx, t0);
5827 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5828 tcg_temp_free(t0);
5829 #endif
5830 }
5831
5832 /* All 405 MAC instructions are translated here */
5833 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5834 int ra, int rb, int rt, int Rc)
5835 {
5836 TCGv t0, t1;
5837
5838 t0 = tcg_temp_local_new();
5839 t1 = tcg_temp_local_new();
5840
5841 switch (opc3 & 0x0D) {
5842 case 0x05:
5843 /* macchw - macchw. - macchwo - macchwo. */
5844 /* macchws - macchws. - macchwso - macchwso. */
5845 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5846 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5847 /* mulchw - mulchw. */
5848 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5849 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5850 tcg_gen_ext16s_tl(t1, t1);
5851 break;
5852 case 0x04:
5853 /* macchwu - macchwu. - macchwuo - macchwuo. */
5854 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5855 /* mulchwu - mulchwu. */
5856 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5857 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5858 tcg_gen_ext16u_tl(t1, t1);
5859 break;
5860 case 0x01:
5861 /* machhw - machhw. - machhwo - machhwo. */
5862 /* machhws - machhws. - machhwso - machhwso. */
5863 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5864 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5865 /* mulhhw - mulhhw. */
5866 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5867 tcg_gen_ext16s_tl(t0, t0);
5868 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5869 tcg_gen_ext16s_tl(t1, t1);
5870 break;
5871 case 0x00:
5872 /* machhwu - machhwu. - machhwuo - machhwuo. */
5873 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5874 /* mulhhwu - mulhhwu. */
5875 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5876 tcg_gen_ext16u_tl(t0, t0);
5877 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5878 tcg_gen_ext16u_tl(t1, t1);
5879 break;
5880 case 0x0D:
5881 /* maclhw - maclhw. - maclhwo - maclhwo. */
5882 /* maclhws - maclhws. - maclhwso - maclhwso. */
5883 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5884 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5885 /* mullhw - mullhw. */
5886 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5887 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5888 break;
5889 case 0x0C:
5890 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5891 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5892 /* mullhwu - mullhwu. */
5893 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5894 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5895 break;
5896 }
5897 if (opc2 & 0x04) {
5898 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5899 tcg_gen_mul_tl(t1, t0, t1);
5900 if (opc2 & 0x02) {
5901 /* nmultiply-and-accumulate (0x0E) */
5902 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5903 } else {
5904 /* multiply-and-accumulate (0x0C) */
5905 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5906 }
5907
5908 if (opc3 & 0x12) {
5909 /* Check overflow and/or saturate */
5910 int l1 = gen_new_label();
5911
5912 if (opc3 & 0x10) {
5913 /* Start with XER OV disabled, the most likely case */
5914 tcg_gen_movi_tl(cpu_ov, 0);
5915 }
5916 if (opc3 & 0x01) {
5917 /* Signed */
5918 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5919 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5920 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5921 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5922 if (opc3 & 0x02) {
5923 /* Saturate */
5924 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5925 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5926 }
5927 } else {
5928 /* Unsigned */
5929 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5930 if (opc3 & 0x02) {
5931 /* Saturate */
5932 tcg_gen_movi_tl(t0, UINT32_MAX);
5933 }
5934 }
5935 if (opc3 & 0x10) {
5936 /* Check overflow */
5937 tcg_gen_movi_tl(cpu_ov, 1);
5938 tcg_gen_movi_tl(cpu_so, 1);
5939 }
5940 gen_set_label(l1);
5941 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5942 }
5943 } else {
5944 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5945 }
5946 tcg_temp_free(t0);
5947 tcg_temp_free(t1);
5948 if (unlikely(Rc) != 0) {
5949 /* Update Rc0 */
5950 gen_set_Rc0(ctx, cpu_gpr[rt]);
5951 }
5952 }
5953
5954 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5955 static void glue(gen_, name)(DisasContext *ctx) \
5956 { \
5957 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5958 rD(ctx->opcode), Rc(ctx->opcode)); \
5959 }
5960
5961 /* macchw - macchw. */
5962 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5963 /* macchwo - macchwo. */
5964 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5965 /* macchws - macchws. */
5966 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5967 /* macchwso - macchwso. */
5968 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5969 /* macchwsu - macchwsu. */
5970 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5971 /* macchwsuo - macchwsuo. */
5972 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5973 /* macchwu - macchwu. */
5974 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5975 /* macchwuo - macchwuo. */
5976 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5977 /* machhw - machhw. */
5978 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5979 /* machhwo - machhwo. */
5980 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5981 /* machhws - machhws. */
5982 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5983 /* machhwso - machhwso. */
5984 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5985 /* machhwsu - machhwsu. */
5986 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5987 /* machhwsuo - machhwsuo. */
5988 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5989 /* machhwu - machhwu. */
5990 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5991 /* machhwuo - machhwuo. */
5992 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5993 /* maclhw - maclhw. */
5994 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5995 /* maclhwo - maclhwo. */
5996 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5997 /* maclhws - maclhws. */
5998 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5999 /* maclhwso - maclhwso. */
6000 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6001 /* maclhwu - maclhwu. */
6002 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6003 /* maclhwuo - maclhwuo. */
6004 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6005 /* maclhwsu - maclhwsu. */
6006 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6007 /* maclhwsuo - maclhwsuo. */
6008 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6009 /* nmacchw - nmacchw. */
6010 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6011 /* nmacchwo - nmacchwo. */
6012 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6013 /* nmacchws - nmacchws. */
6014 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6015 /* nmacchwso - nmacchwso. */
6016 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6017 /* nmachhw - nmachhw. */
6018 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6019 /* nmachhwo - nmachhwo. */
6020 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6021 /* nmachhws - nmachhws. */
6022 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6023 /* nmachhwso - nmachhwso. */
6024 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6025 /* nmaclhw - nmaclhw. */
6026 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6027 /* nmaclhwo - nmaclhwo. */
6028 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6029 /* nmaclhws - nmaclhws. */
6030 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6031 /* nmaclhwso - nmaclhwso. */
6032 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6033
6034 /* mulchw - mulchw. */
6035 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6036 /* mulchwu - mulchwu. */
6037 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6038 /* mulhhw - mulhhw. */
6039 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6040 /* mulhhwu - mulhhwu. */
6041 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6042 /* mullhw - mullhw. */
6043 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6044 /* mullhwu - mullhwu. */
6045 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6046
6047 /* mfdcr */
6048 static void gen_mfdcr(DisasContext *ctx)
6049 {
6050 #if defined(CONFIG_USER_ONLY)
6051 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6052 #else
6053 TCGv dcrn;
6054 if (unlikely(!ctx->mem_idx)) {
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6056 return;
6057 }
6058 /* NIP cannot be restored if the memory exception comes from an helper */
6059 gen_update_nip(ctx, ctx->nip - 4);
6060 dcrn = tcg_const_tl(SPR(ctx->opcode));
6061 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6062 tcg_temp_free(dcrn);
6063 #endif
6064 }
6065
6066 /* mtdcr */
6067 static void gen_mtdcr(DisasContext *ctx)
6068 {
6069 #if defined(CONFIG_USER_ONLY)
6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6071 #else
6072 TCGv dcrn;
6073 if (unlikely(!ctx->mem_idx)) {
6074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6075 return;
6076 }
6077 /* NIP cannot be restored if the memory exception comes from an helper */
6078 gen_update_nip(ctx, ctx->nip - 4);
6079 dcrn = tcg_const_tl(SPR(ctx->opcode));
6080 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6081 tcg_temp_free(dcrn);
6082 #endif
6083 }
6084
6085 /* mfdcrx */
6086 /* XXX: not implemented on 440 ? */
6087 static void gen_mfdcrx(DisasContext *ctx)
6088 {
6089 #if defined(CONFIG_USER_ONLY)
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6091 #else
6092 if (unlikely(!ctx->mem_idx)) {
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6094 return;
6095 }
6096 /* NIP cannot be restored if the memory exception comes from an helper */
6097 gen_update_nip(ctx, ctx->nip - 4);
6098 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6099 cpu_gpr[rA(ctx->opcode)]);
6100 /* Note: Rc update flag set leads to undefined state of Rc0 */
6101 #endif
6102 }
6103
6104 /* mtdcrx */
6105 /* XXX: not implemented on 440 ? */
6106 static void gen_mtdcrx(DisasContext *ctx)
6107 {
6108 #if defined(CONFIG_USER_ONLY)
6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6110 #else
6111 if (unlikely(!ctx->mem_idx)) {
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6113 return;
6114 }
6115 /* NIP cannot be restored if the memory exception comes from an helper */
6116 gen_update_nip(ctx, ctx->nip - 4);
6117 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6118 cpu_gpr[rS(ctx->opcode)]);
6119 /* Note: Rc update flag set leads to undefined state of Rc0 */
6120 #endif
6121 }
6122
6123 /* mfdcrux (PPC 460) : user-mode access to DCR */
6124 static void gen_mfdcrux(DisasContext *ctx)
6125 {
6126 /* NIP cannot be restored if the memory exception comes from an helper */
6127 gen_update_nip(ctx, ctx->nip - 4);
6128 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6129 cpu_gpr[rA(ctx->opcode)]);
6130 /* Note: Rc update flag set leads to undefined state of Rc0 */
6131 }
6132
6133 /* mtdcrux (PPC 460) : user-mode access to DCR */
6134 static void gen_mtdcrux(DisasContext *ctx)
6135 {
6136 /* NIP cannot be restored if the memory exception comes from an helper */
6137 gen_update_nip(ctx, ctx->nip - 4);
6138 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6139 cpu_gpr[rS(ctx->opcode)]);
6140 /* Note: Rc update flag set leads to undefined state of Rc0 */
6141 }
6142
6143 /* dccci */
6144 static void gen_dccci(DisasContext *ctx)
6145 {
6146 #if defined(CONFIG_USER_ONLY)
6147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6148 #else
6149 if (unlikely(!ctx->mem_idx)) {
6150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6151 return;
6152 }
6153 /* interpreted as no-op */
6154 #endif
6155 }
6156
6157 /* dcread */
6158 static void gen_dcread(DisasContext *ctx)
6159 {
6160 #if defined(CONFIG_USER_ONLY)
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6162 #else
6163 TCGv EA, val;
6164 if (unlikely(!ctx->mem_idx)) {
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6166 return;
6167 }
6168 gen_set_access_type(ctx, ACCESS_CACHE);
6169 EA = tcg_temp_new();
6170 gen_addr_reg_index(ctx, EA);
6171 val = tcg_temp_new();
6172 gen_qemu_ld32u(ctx, val, EA);
6173 tcg_temp_free(val);
6174 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6175 tcg_temp_free(EA);
6176 #endif
6177 }
6178
6179 /* icbt */
6180 static void gen_icbt_40x(DisasContext *ctx)
6181 {
6182 /* interpreted as no-op */
6183 /* XXX: specification say this is treated as a load by the MMU
6184 * but does not generate any exception
6185 */
6186 }
6187
6188 /* iccci */
6189 static void gen_iccci(DisasContext *ctx)
6190 {
6191 #if defined(CONFIG_USER_ONLY)
6192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6193 #else
6194 if (unlikely(!ctx->mem_idx)) {
6195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6196 return;
6197 }
6198 /* interpreted as no-op */
6199 #endif
6200 }
6201
6202 /* icread */
6203 static void gen_icread(DisasContext *ctx)
6204 {
6205 #if defined(CONFIG_USER_ONLY)
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 #else
6208 if (unlikely(!ctx->mem_idx)) {
6209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6210 return;
6211 }
6212 /* interpreted as no-op */
6213 #endif
6214 }
6215
6216 /* rfci (mem_idx only) */
6217 static void gen_rfci_40x(DisasContext *ctx)
6218 {
6219 #if defined(CONFIG_USER_ONLY)
6220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6221 #else
6222 if (unlikely(!ctx->mem_idx)) {
6223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6224 return;
6225 }
6226 /* Restore CPU state */
6227 gen_helper_40x_rfci(cpu_env);
6228 gen_sync_exception(ctx);
6229 #endif
6230 }
6231
6232 static void gen_rfci(DisasContext *ctx)
6233 {
6234 #if defined(CONFIG_USER_ONLY)
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6236 #else
6237 if (unlikely(!ctx->mem_idx)) {
6238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6239 return;
6240 }
6241 /* Restore CPU state */
6242 gen_helper_rfci(cpu_env);
6243 gen_sync_exception(ctx);
6244 #endif
6245 }
6246
6247 /* BookE specific */
6248
6249 /* XXX: not implemented on 440 ? */
6250 static void gen_rfdi(DisasContext *ctx)
6251 {
6252 #if defined(CONFIG_USER_ONLY)
6253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6254 #else
6255 if (unlikely(!ctx->mem_idx)) {
6256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6257 return;
6258 }
6259 /* Restore CPU state */
6260 gen_helper_rfdi(cpu_env);
6261 gen_sync_exception(ctx);
6262 #endif
6263 }
6264
6265 /* XXX: not implemented on 440 ? */
6266 static void gen_rfmci(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 #else
6271 if (unlikely(!ctx->mem_idx)) {
6272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6273 return;
6274 }
6275 /* Restore CPU state */
6276 gen_helper_rfmci(cpu_env);
6277 gen_sync_exception(ctx);
6278 #endif
6279 }
6280
6281 /* TLB management - PowerPC 405 implementation */
6282
6283 /* tlbre */
6284 static void gen_tlbre_40x(DisasContext *ctx)
6285 {
6286 #if defined(CONFIG_USER_ONLY)
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6288 #else
6289 if (unlikely(!ctx->mem_idx)) {
6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6291 return;
6292 }
6293 switch (rB(ctx->opcode)) {
6294 case 0:
6295 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6296 cpu_gpr[rA(ctx->opcode)]);
6297 break;
6298 case 1:
6299 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6300 cpu_gpr[rA(ctx->opcode)]);
6301 break;
6302 default:
6303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6304 break;
6305 }
6306 #endif
6307 }
6308
6309 /* tlbsx - tlbsx. */
6310 static void gen_tlbsx_40x(DisasContext *ctx)
6311 {
6312 #if defined(CONFIG_USER_ONLY)
6313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6314 #else
6315 TCGv t0;
6316 if (unlikely(!ctx->mem_idx)) {
6317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6318 return;
6319 }
6320 t0 = tcg_temp_new();
6321 gen_addr_reg_index(ctx, t0);
6322 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6323 tcg_temp_free(t0);
6324 if (Rc(ctx->opcode)) {
6325 int l1 = gen_new_label();
6326 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6327 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6328 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6329 gen_set_label(l1);
6330 }
6331 #endif
6332 }
6333
6334 /* tlbwe */
6335 static void gen_tlbwe_40x(DisasContext *ctx)
6336 {
6337 #if defined(CONFIG_USER_ONLY)
6338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6339 #else
6340 if (unlikely(!ctx->mem_idx)) {
6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6342 return;
6343 }
6344 switch (rB(ctx->opcode)) {
6345 case 0:
6346 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6347 cpu_gpr[rS(ctx->opcode)]);
6348 break;
6349 case 1:
6350 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6351 cpu_gpr[rS(ctx->opcode)]);
6352 break;
6353 default:
6354 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6355 break;
6356 }
6357 #endif
6358 }
6359
6360 /* TLB management - PowerPC 440 implementation */
6361
6362 /* tlbre */
6363 static void gen_tlbre_440(DisasContext *ctx)
6364 {
6365 #if defined(CONFIG_USER_ONLY)
6366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6367 #else
6368 if (unlikely(!ctx->mem_idx)) {
6369 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6370 return;
6371 }
6372 switch (rB(ctx->opcode)) {
6373 case 0:
6374 case 1:
6375 case 2:
6376 {
6377 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6378 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6379 t0, cpu_gpr[rA(ctx->opcode)]);
6380 tcg_temp_free_i32(t0);
6381 }
6382 break;
6383 default:
6384 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6385 break;
6386 }
6387 #endif
6388 }
6389
6390 /* tlbsx - tlbsx. */
6391 static void gen_tlbsx_440(DisasContext *ctx)
6392 {
6393 #if defined(CONFIG_USER_ONLY)
6394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6395 #else
6396 TCGv t0;
6397 if (unlikely(!ctx->mem_idx)) {
6398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6399 return;
6400 }
6401 t0 = tcg_temp_new();
6402 gen_addr_reg_index(ctx, t0);
6403 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6404 tcg_temp_free(t0);
6405 if (Rc(ctx->opcode)) {
6406 int l1 = gen_new_label();
6407 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6408 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6409 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6410 gen_set_label(l1);
6411 }
6412 #endif
6413 }
6414
6415 /* tlbwe */
6416 static void gen_tlbwe_440(DisasContext *ctx)
6417 {
6418 #if defined(CONFIG_USER_ONLY)
6419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6420 #else
6421 if (unlikely(!ctx->mem_idx)) {
6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6423 return;
6424 }
6425 switch (rB(ctx->opcode)) {
6426 case 0:
6427 case 1:
6428 case 2:
6429 {
6430 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6431 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6432 cpu_gpr[rS(ctx->opcode)]);
6433 tcg_temp_free_i32(t0);
6434 }
6435 break;
6436 default:
6437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6438 break;
6439 }
6440 #endif
6441 }
6442
6443 /* TLB management - PowerPC BookE 2.06 implementation */
6444
6445 /* tlbre */
6446 static void gen_tlbre_booke206(DisasContext *ctx)
6447 {
6448 #if defined(CONFIG_USER_ONLY)
6449 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6450 #else
6451 if (unlikely(!ctx->mem_idx)) {
6452 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6453 return;
6454 }
6455
6456 gen_helper_booke206_tlbre(cpu_env);
6457 #endif
6458 }
6459
6460 /* tlbsx - tlbsx. */
6461 static void gen_tlbsx_booke206(DisasContext *ctx)
6462 {
6463 #if defined(CONFIG_USER_ONLY)
6464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6465 #else
6466 TCGv t0;
6467 if (unlikely(!ctx->mem_idx)) {
6468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6469 return;
6470 }
6471
6472 if (rA(ctx->opcode)) {
6473 t0 = tcg_temp_new();
6474 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6475 } else {
6476 t0 = tcg_const_tl(0);
6477 }
6478
6479 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6480 gen_helper_booke206_tlbsx(cpu_env, t0);
6481 tcg_temp_free(t0);
6482 #endif
6483 }
6484
6485 /* tlbwe */
6486 static void gen_tlbwe_booke206(DisasContext *ctx)
6487 {
6488 #if defined(CONFIG_USER_ONLY)
6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6490 #else
6491 if (unlikely(!ctx->mem_idx)) {
6492 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6493 return;
6494 }
6495 gen_update_nip(ctx, ctx->nip - 4);
6496 gen_helper_booke206_tlbwe(cpu_env);
6497 #endif
6498 }
6499
6500 static void gen_tlbivax_booke206(DisasContext *ctx)
6501 {
6502 #if defined(CONFIG_USER_ONLY)
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504 #else
6505 TCGv t0;
6506 if (unlikely(!ctx->mem_idx)) {
6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6508 return;
6509 }
6510
6511 t0 = tcg_temp_new();
6512 gen_addr_reg_index(ctx, t0);
6513
6514 gen_helper_booke206_tlbivax(cpu_env, t0);
6515 tcg_temp_free(t0);
6516 #endif
6517 }
6518
6519 static void gen_tlbilx_booke206(DisasContext *ctx)
6520 {
6521 #if defined(CONFIG_USER_ONLY)
6522 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6523 #else
6524 TCGv t0;
6525 if (unlikely(!ctx->mem_idx)) {
6526 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6527 return;
6528 }
6529
6530 t0 = tcg_temp_new();
6531 gen_addr_reg_index(ctx, t0);
6532
6533 switch((ctx->opcode >> 21) & 0x3) {
6534 case 0:
6535 gen_helper_booke206_tlbilx0(cpu_env, t0);
6536 break;
6537 case 1:
6538 gen_helper_booke206_tlbilx1(cpu_env, t0);
6539 break;
6540 case 3:
6541 gen_helper_booke206_tlbilx3(cpu_env, t0);
6542 break;
6543 default:
6544 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6545 break;
6546 }
6547
6548 tcg_temp_free(t0);
6549 #endif
6550 }
6551
6552
6553 /* wrtee */
6554 static void gen_wrtee(DisasContext *ctx)
6555 {
6556 #if defined(CONFIG_USER_ONLY)
6557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6558 #else
6559 TCGv t0;
6560 if (unlikely(!ctx->mem_idx)) {
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 return;
6563 }
6564 t0 = tcg_temp_new();
6565 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6566 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6567 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6568 tcg_temp_free(t0);
6569 /* Stop translation to have a chance to raise an exception
6570 * if we just set msr_ee to 1
6571 */
6572 gen_stop_exception(ctx);
6573 #endif
6574 }
6575
6576 /* wrteei */
6577 static void gen_wrteei(DisasContext *ctx)
6578 {
6579 #if defined(CONFIG_USER_ONLY)
6580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6581 #else
6582 if (unlikely(!ctx->mem_idx)) {
6583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6584 return;
6585 }
6586 if (ctx->opcode & 0x00008000) {
6587 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6588 /* Stop translation to have a chance to raise an exception */
6589 gen_stop_exception(ctx);
6590 } else {
6591 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6592 }
6593 #endif
6594 }
6595
6596 /* PowerPC 440 specific instructions */
6597
6598 /* dlmzb */
6599 static void gen_dlmzb(DisasContext *ctx)
6600 {
6601 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6602 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6603 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6604 tcg_temp_free_i32(t0);
6605 }
6606
6607 /* mbar replaces eieio on 440 */
6608 static void gen_mbar(DisasContext *ctx)
6609 {
6610 /* interpreted as no-op */
6611 }
6612
6613 /* msync replaces sync on 440 */
6614 static void gen_msync_4xx(DisasContext *ctx)
6615 {
6616 /* interpreted as no-op */
6617 }
6618
6619 /* icbt */
6620 static void gen_icbt_440(DisasContext *ctx)
6621 {
6622 /* interpreted as no-op */
6623 /* XXX: specification say this is treated as a load by the MMU
6624 * but does not generate any exception
6625 */
6626 }
6627
6628 /* Embedded.Processor Control */
6629
6630 static void gen_msgclr(DisasContext *ctx)
6631 {
6632 #if defined(CONFIG_USER_ONLY)
6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 #else
6635 if (unlikely(ctx->mem_idx == 0)) {
6636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6637 return;
6638 }
6639
6640 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6641 #endif
6642 }
6643
6644 static void gen_msgsnd(DisasContext *ctx)
6645 {
6646 #if defined(CONFIG_USER_ONLY)
6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6648 #else
6649 if (unlikely(ctx->mem_idx == 0)) {
6650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6651 return;
6652 }
6653
6654 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6655 #endif
6656 }
6657
6658 /*** Altivec vector extension ***/
6659 /* Altivec registers moves */
6660
6661 static inline TCGv_ptr gen_avr_ptr(int reg)
6662 {
6663 TCGv_ptr r = tcg_temp_new_ptr();
6664 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6665 return r;
6666 }
6667
6668 #define GEN_VR_LDX(name, opc2, opc3) \
6669 static void glue(gen_, name)(DisasContext *ctx) \
6670 { \
6671 TCGv EA; \
6672 if (unlikely(!ctx->altivec_enabled)) { \
6673 gen_exception(ctx, POWERPC_EXCP_VPU); \
6674 return; \
6675 } \
6676 gen_set_access_type(ctx, ACCESS_INT); \
6677 EA = tcg_temp_new(); \
6678 gen_addr_reg_index(ctx, EA); \
6679 tcg_gen_andi_tl(EA, EA, ~0xf); \
6680 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6681 64-bit byteswap already. */ \
6682 if (ctx->le_mode) { \
6683 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6684 tcg_gen_addi_tl(EA, EA, 8); \
6685 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6686 } else { \
6687 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6688 tcg_gen_addi_tl(EA, EA, 8); \
6689 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6690 } \
6691 tcg_temp_free(EA); \
6692 }
6693
6694 #define GEN_VR_STX(name, opc2, opc3) \
6695 static void gen_st##name(DisasContext *ctx) \
6696 { \
6697 TCGv EA; \
6698 if (unlikely(!ctx->altivec_enabled)) { \
6699 gen_exception(ctx, POWERPC_EXCP_VPU); \
6700 return; \
6701 } \
6702 gen_set_access_type(ctx, ACCESS_INT); \
6703 EA = tcg_temp_new(); \
6704 gen_addr_reg_index(ctx, EA); \
6705 tcg_gen_andi_tl(EA, EA, ~0xf); \
6706 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6707 64-bit byteswap already. */ \
6708 if (ctx->le_mode) { \
6709 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6710 tcg_gen_addi_tl(EA, EA, 8); \
6711 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6712 } else { \
6713 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6714 tcg_gen_addi_tl(EA, EA, 8); \
6715 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6716 } \
6717 tcg_temp_free(EA); \
6718 }
6719
6720 #define GEN_VR_LVE(name, opc2, opc3) \
6721 static void gen_lve##name(DisasContext *ctx) \
6722 { \
6723 TCGv EA; \
6724 TCGv_ptr rs; \
6725 if (unlikely(!ctx->altivec_enabled)) { \
6726 gen_exception(ctx, POWERPC_EXCP_VPU); \
6727 return; \
6728 } \
6729 gen_set_access_type(ctx, ACCESS_INT); \
6730 EA = tcg_temp_new(); \
6731 gen_addr_reg_index(ctx, EA); \
6732 rs = gen_avr_ptr(rS(ctx->opcode)); \
6733 gen_helper_lve##name(cpu_env, rs, EA); \
6734 tcg_temp_free(EA); \
6735 tcg_temp_free_ptr(rs); \
6736 }
6737
6738 #define GEN_VR_STVE(name, opc2, opc3) \
6739 static void gen_stve##name(DisasContext *ctx) \
6740 { \
6741 TCGv EA; \
6742 TCGv_ptr rs; \
6743 if (unlikely(!ctx->altivec_enabled)) { \
6744 gen_exception(ctx, POWERPC_EXCP_VPU); \
6745 return; \
6746 } \
6747 gen_set_access_type(ctx, ACCESS_INT); \
6748 EA = tcg_temp_new(); \
6749 gen_addr_reg_index(ctx, EA); \
6750 rs = gen_avr_ptr(rS(ctx->opcode)); \
6751 gen_helper_stve##name(cpu_env, rs, EA); \
6752 tcg_temp_free(EA); \
6753 tcg_temp_free_ptr(rs); \
6754 }
6755
6756 GEN_VR_LDX(lvx, 0x07, 0x03);
6757 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6758 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6759
6760 GEN_VR_LVE(bx, 0x07, 0x00);
6761 GEN_VR_LVE(hx, 0x07, 0x01);
6762 GEN_VR_LVE(wx, 0x07, 0x02);
6763
6764 GEN_VR_STX(svx, 0x07, 0x07);
6765 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6766 GEN_VR_STX(svxl, 0x07, 0x0F);
6767
6768 GEN_VR_STVE(bx, 0x07, 0x04);
6769 GEN_VR_STVE(hx, 0x07, 0x05);
6770 GEN_VR_STVE(wx, 0x07, 0x06);
6771
6772 static void gen_lvsl(DisasContext *ctx)
6773 {
6774 TCGv_ptr rd;
6775 TCGv EA;
6776 if (unlikely(!ctx->altivec_enabled)) {
6777 gen_exception(ctx, POWERPC_EXCP_VPU);
6778 return;
6779 }
6780 EA = tcg_temp_new();
6781 gen_addr_reg_index(ctx, EA);
6782 rd = gen_avr_ptr(rD(ctx->opcode));
6783 gen_helper_lvsl(rd, EA);
6784 tcg_temp_free(EA);
6785 tcg_temp_free_ptr(rd);
6786 }
6787
6788 static void gen_lvsr(DisasContext *ctx)
6789 {
6790 TCGv_ptr rd;
6791 TCGv EA;
6792 if (unlikely(!ctx->altivec_enabled)) {
6793 gen_exception(ctx, POWERPC_EXCP_VPU);
6794 return;
6795 }
6796 EA = tcg_temp_new();
6797 gen_addr_reg_index(ctx, EA);
6798 rd = gen_avr_ptr(rD(ctx->opcode));
6799 gen_helper_lvsr(rd, EA);
6800 tcg_temp_free(EA);
6801 tcg_temp_free_ptr(rd);
6802 }
6803
6804 static void gen_mfvscr(DisasContext *ctx)
6805 {
6806 TCGv_i32 t;
6807 if (unlikely(!ctx->altivec_enabled)) {
6808 gen_exception(ctx, POWERPC_EXCP_VPU);
6809 return;
6810 }
6811 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6812 t = tcg_temp_new_i32();
6813 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6814 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6815 tcg_temp_free_i32(t);
6816 }
6817
6818 static void gen_mtvscr(DisasContext *ctx)
6819 {
6820 TCGv_ptr p;
6821 if (unlikely(!ctx->altivec_enabled)) {
6822 gen_exception(ctx, POWERPC_EXCP_VPU);
6823 return;
6824 }
6825 p = gen_avr_ptr(rD(ctx->opcode));
6826 gen_helper_mtvscr(cpu_env, p);
6827 tcg_temp_free_ptr(p);
6828 }
6829
6830 /* Logical operations */
6831 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6832 static void glue(gen_, name)(DisasContext *ctx) \
6833 { \
6834 if (unlikely(!ctx->altivec_enabled)) { \
6835 gen_exception(ctx, POWERPC_EXCP_VPU); \
6836 return; \
6837 } \
6838 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6839 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6840 }
6841
6842 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6843 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6844 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6845 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6846 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6847 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6848 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6849 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6850
6851 #define GEN_VXFORM(name, opc2, opc3) \
6852 static void glue(gen_, name)(DisasContext *ctx) \
6853 { \
6854 TCGv_ptr ra, rb, rd; \
6855 if (unlikely(!ctx->altivec_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_VPU); \
6857 return; \
6858 } \
6859 ra = gen_avr_ptr(rA(ctx->opcode)); \
6860 rb = gen_avr_ptr(rB(ctx->opcode)); \
6861 rd = gen_avr_ptr(rD(ctx->opcode)); \
6862 gen_helper_##name (rd, ra, rb); \
6863 tcg_temp_free_ptr(ra); \
6864 tcg_temp_free_ptr(rb); \
6865 tcg_temp_free_ptr(rd); \
6866 }
6867
6868 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6869 static void glue(gen_, name)(DisasContext *ctx) \
6870 { \
6871 TCGv_ptr ra, rb, rd; \
6872 if (unlikely(!ctx->altivec_enabled)) { \
6873 gen_exception(ctx, POWERPC_EXCP_VPU); \
6874 return; \
6875 } \
6876 ra = gen_avr_ptr(rA(ctx->opcode)); \
6877 rb = gen_avr_ptr(rB(ctx->opcode)); \
6878 rd = gen_avr_ptr(rD(ctx->opcode)); \
6879 gen_helper_##name(cpu_env, rd, ra, rb); \
6880 tcg_temp_free_ptr(ra); \
6881 tcg_temp_free_ptr(rb); \
6882 tcg_temp_free_ptr(rd); \
6883 }
6884
6885 #define GEN_VXFORM3(name, opc2, opc3) \
6886 static void glue(gen_, name)(DisasContext *ctx) \
6887 { \
6888 TCGv_ptr ra, rb, rc, rd; \
6889 if (unlikely(!ctx->altivec_enabled)) { \
6890 gen_exception(ctx, POWERPC_EXCP_VPU); \
6891 return; \
6892 } \
6893 ra = gen_avr_ptr(rA(ctx->opcode)); \
6894 rb = gen_avr_ptr(rB(ctx->opcode)); \
6895 rc = gen_avr_ptr(rC(ctx->opcode)); \
6896 rd = gen_avr_ptr(rD(ctx->opcode)); \
6897 gen_helper_##name(rd, ra, rb, rc); \
6898 tcg_temp_free_ptr(ra); \
6899 tcg_temp_free_ptr(rb); \
6900 tcg_temp_free_ptr(rc); \
6901 tcg_temp_free_ptr(rd); \
6902 }
6903
6904 /*
6905 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6906 * an opcode bit. In general, these pairs come from different
6907 * versions of the ISA, so we must also support a pair of flags for
6908 * each instruction.
6909 */
6910 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6911 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6912 { \
6913 if ((Rc(ctx->opcode) == 0) && \
6914 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6915 gen_##name0(ctx); \
6916 } else if ((Rc(ctx->opcode) == 1) && \
6917 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6918 gen_##name1(ctx); \
6919 } else { \
6920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6921 } \
6922 }
6923
6924 GEN_VXFORM(vaddubm, 0, 0);
6925 GEN_VXFORM(vadduhm, 0, 1);
6926 GEN_VXFORM(vadduwm, 0, 2);
6927 GEN_VXFORM(vaddudm, 0, 3);
6928 GEN_VXFORM(vsububm, 0, 16);
6929 GEN_VXFORM(vsubuhm, 0, 17);
6930 GEN_VXFORM(vsubuwm, 0, 18);
6931 GEN_VXFORM(vsubudm, 0, 19);
6932 GEN_VXFORM(vmaxub, 1, 0);
6933 GEN_VXFORM(vmaxuh, 1, 1);
6934 GEN_VXFORM(vmaxuw, 1, 2);
6935 GEN_VXFORM(vmaxud, 1, 3);
6936 GEN_VXFORM(vmaxsb, 1, 4);
6937 GEN_VXFORM(vmaxsh, 1, 5);
6938 GEN_VXFORM(vmaxsw, 1, 6);
6939 GEN_VXFORM(vmaxsd, 1, 7);
6940 GEN_VXFORM(vminub, 1, 8);
6941 GEN_VXFORM(vminuh, 1, 9);
6942 GEN_VXFORM(vminuw, 1, 10);
6943 GEN_VXFORM(vminud, 1, 11);
6944 GEN_VXFORM(vminsb, 1, 12);
6945 GEN_VXFORM(vminsh, 1, 13);
6946 GEN_VXFORM(vminsw, 1, 14);
6947 GEN_VXFORM(vminsd, 1, 15);
6948 GEN_VXFORM(vavgub, 1, 16);
6949 GEN_VXFORM(vavguh, 1, 17);
6950 GEN_VXFORM(vavguw, 1, 18);
6951 GEN_VXFORM(vavgsb, 1, 20);
6952 GEN_VXFORM(vavgsh, 1, 21);
6953 GEN_VXFORM(vavgsw, 1, 22);
6954 GEN_VXFORM(vmrghb, 6, 0);
6955 GEN_VXFORM(vmrghh, 6, 1);
6956 GEN_VXFORM(vmrghw, 6, 2);
6957 GEN_VXFORM(vmrglb, 6, 4);
6958 GEN_VXFORM(vmrglh, 6, 5);
6959 GEN_VXFORM(vmrglw, 6, 6);
6960
6961 static void gen_vmrgew(DisasContext *ctx)
6962 {
6963 TCGv_i64 tmp;
6964 int VT, VA, VB;
6965 if (unlikely(!ctx->altivec_enabled)) {
6966 gen_exception(ctx, POWERPC_EXCP_VPU);
6967 return;
6968 }
6969 VT = rD(ctx->opcode);
6970 VA = rA(ctx->opcode);
6971 VB = rB(ctx->opcode);
6972 tmp = tcg_temp_new_i64();
6973 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6974 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6975 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6976 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6977 tcg_temp_free_i64(tmp);
6978 }
6979
6980 static void gen_vmrgow(DisasContext *ctx)
6981 {
6982 int VT, VA, VB;
6983 if (unlikely(!ctx->altivec_enabled)) {
6984 gen_exception(ctx, POWERPC_EXCP_VPU);
6985 return;
6986 }
6987 VT = rD(ctx->opcode);
6988 VA = rA(ctx->opcode);
6989 VB = rB(ctx->opcode);
6990
6991 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
6992 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
6993 }
6994
6995 GEN_VXFORM(vmuloub, 4, 0);
6996 GEN_VXFORM(vmulouh, 4, 1);
6997 GEN_VXFORM(vmulouw, 4, 2);
6998 GEN_VXFORM(vmuluwm, 4, 2);
6999 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7000 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7001 GEN_VXFORM(vmulosb, 4, 4);
7002 GEN_VXFORM(vmulosh, 4, 5);
7003 GEN_VXFORM(vmulosw, 4, 6);
7004 GEN_VXFORM(vmuleub, 4, 8);
7005 GEN_VXFORM(vmuleuh, 4, 9);
7006 GEN_VXFORM(vmuleuw, 4, 10);
7007 GEN_VXFORM(vmulesb, 4, 12);
7008 GEN_VXFORM(vmulesh, 4, 13);
7009 GEN_VXFORM(vmulesw, 4, 14);
7010 GEN_VXFORM(vslb, 2, 4);
7011 GEN_VXFORM(vslh, 2, 5);
7012 GEN_VXFORM(vslw, 2, 6);
7013 GEN_VXFORM(vsld, 2, 23);
7014 GEN_VXFORM(vsrb, 2, 8);
7015 GEN_VXFORM(vsrh, 2, 9);
7016 GEN_VXFORM(vsrw, 2, 10);
7017 GEN_VXFORM(vsrd, 2, 27);
7018 GEN_VXFORM(vsrab, 2, 12);
7019 GEN_VXFORM(vsrah, 2, 13);
7020 GEN_VXFORM(vsraw, 2, 14);
7021 GEN_VXFORM(vsrad, 2, 15);
7022 GEN_VXFORM(vslo, 6, 16);
7023 GEN_VXFORM(vsro, 6, 17);
7024 GEN_VXFORM(vaddcuw, 0, 6);
7025 GEN_VXFORM(vsubcuw, 0, 22);
7026 GEN_VXFORM_ENV(vaddubs, 0, 8);
7027 GEN_VXFORM_ENV(vadduhs, 0, 9);
7028 GEN_VXFORM_ENV(vadduws, 0, 10);
7029 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7030 GEN_VXFORM_ENV(vaddshs, 0, 13);
7031 GEN_VXFORM_ENV(vaddsws, 0, 14);
7032 GEN_VXFORM_ENV(vsububs, 0, 24);
7033 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7034 GEN_VXFORM_ENV(vsubuws, 0, 26);
7035 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7036 GEN_VXFORM_ENV(vsubshs, 0, 29);
7037 GEN_VXFORM_ENV(vsubsws, 0, 30);
7038 GEN_VXFORM(vadduqm, 0, 4);
7039 GEN_VXFORM(vaddcuq, 0, 5);
7040 GEN_VXFORM3(vaddeuqm, 30, 0);
7041 GEN_VXFORM3(vaddecuq, 30, 0);
7042 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7043 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7044 GEN_VXFORM(vsubuqm, 0, 20);
7045 GEN_VXFORM(vsubcuq, 0, 21);
7046 GEN_VXFORM3(vsubeuqm, 31, 0);
7047 GEN_VXFORM3(vsubecuq, 31, 0);
7048 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7049 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7050 GEN_VXFORM(vrlb, 2, 0);
7051 GEN_VXFORM(vrlh, 2, 1);
7052 GEN_VXFORM(vrlw, 2, 2);
7053 GEN_VXFORM(vrld, 2, 3);
7054 GEN_VXFORM(vsl, 2, 7);
7055 GEN_VXFORM(vsr, 2, 11);
7056 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7057 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7058 GEN_VXFORM_ENV(vpkudum, 7, 17);
7059 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7060 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7061 GEN_VXFORM_ENV(vpkudus, 7, 19);
7062 GEN_VXFORM_ENV(vpkshus, 7, 4);
7063 GEN_VXFORM_ENV(vpkswus, 7, 5);
7064 GEN_VXFORM_ENV(vpksdus, 7, 21);
7065 GEN_VXFORM_ENV(vpkshss, 7, 6);
7066 GEN_VXFORM_ENV(vpkswss, 7, 7);
7067 GEN_VXFORM_ENV(vpksdss, 7, 23);
7068 GEN_VXFORM(vpkpx, 7, 12);
7069 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7070 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7071 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7072 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7073 GEN_VXFORM_ENV(vsumsws, 4, 30);
7074 GEN_VXFORM_ENV(vaddfp, 5, 0);
7075 GEN_VXFORM_ENV(vsubfp, 5, 1);
7076 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7077 GEN_VXFORM_ENV(vminfp, 5, 17);
7078
7079 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7080 static void glue(gen_, name)(DisasContext *ctx) \
7081 { \
7082 TCGv_ptr ra, rb, rd; \
7083 if (unlikely(!ctx->altivec_enabled)) { \
7084 gen_exception(ctx, POWERPC_EXCP_VPU); \
7085 return; \
7086 } \
7087 ra = gen_avr_ptr(rA(ctx->opcode)); \
7088 rb = gen_avr_ptr(rB(ctx->opcode)); \
7089 rd = gen_avr_ptr(rD(ctx->opcode)); \
7090 gen_helper_##opname(cpu_env, rd, ra, rb); \
7091 tcg_temp_free_ptr(ra); \
7092 tcg_temp_free_ptr(rb); \
7093 tcg_temp_free_ptr(rd); \
7094 }
7095
7096 #define GEN_VXRFORM(name, opc2, opc3) \
7097 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7098 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7099
7100 /*
7101 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7102 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7103 * come from different versions of the ISA, so we must also support a
7104 * pair of flags for each instruction.
7105 */
7106 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7107 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7108 { \
7109 if ((Rc(ctx->opcode) == 0) && \
7110 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7111 if (Rc21(ctx->opcode) == 0) { \
7112 gen_##name0(ctx); \
7113 } else { \
7114 gen_##name0##_(ctx); \
7115 } \
7116 } else if ((Rc(ctx->opcode) == 1) && \
7117 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7118 if (Rc21(ctx->opcode) == 0) { \
7119 gen_##name1(ctx); \
7120 } else { \
7121 gen_##name1##_(ctx); \
7122 } \
7123 } else { \
7124 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7125 } \
7126 }
7127
7128 GEN_VXRFORM(vcmpequb, 3, 0)
7129 GEN_VXRFORM(vcmpequh, 3, 1)
7130 GEN_VXRFORM(vcmpequw, 3, 2)
7131 GEN_VXRFORM(vcmpequd, 3, 3)
7132 GEN_VXRFORM(vcmpgtsb, 3, 12)
7133 GEN_VXRFORM(vcmpgtsh, 3, 13)
7134 GEN_VXRFORM(vcmpgtsw, 3, 14)
7135 GEN_VXRFORM(vcmpgtsd, 3, 15)
7136 GEN_VXRFORM(vcmpgtub, 3, 8)
7137 GEN_VXRFORM(vcmpgtuh, 3, 9)
7138 GEN_VXRFORM(vcmpgtuw, 3, 10)
7139 GEN_VXRFORM(vcmpgtud, 3, 11)
7140 GEN_VXRFORM(vcmpeqfp, 3, 3)
7141 GEN_VXRFORM(vcmpgefp, 3, 7)
7142 GEN_VXRFORM(vcmpgtfp, 3, 11)
7143 GEN_VXRFORM(vcmpbfp, 3, 15)
7144
7145 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7146 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7147 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7148 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7149 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7150 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7151
7152 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7153 static void glue(gen_, name)(DisasContext *ctx) \
7154 { \
7155 TCGv_ptr rd; \
7156 TCGv_i32 simm; \
7157 if (unlikely(!ctx->altivec_enabled)) { \
7158 gen_exception(ctx, POWERPC_EXCP_VPU); \
7159 return; \
7160 } \
7161 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7162 rd = gen_avr_ptr(rD(ctx->opcode)); \
7163 gen_helper_##name (rd, simm); \
7164 tcg_temp_free_i32(simm); \
7165 tcg_temp_free_ptr(rd); \
7166 }
7167
7168 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7169 GEN_VXFORM_SIMM(vspltish, 6, 13);
7170 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7171
7172 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7173 static void glue(gen_, name)(DisasContext *ctx) \
7174 { \
7175 TCGv_ptr rb, rd; \
7176 if (unlikely(!ctx->altivec_enabled)) { \
7177 gen_exception(ctx, POWERPC_EXCP_VPU); \
7178 return; \
7179 } \
7180 rb = gen_avr_ptr(rB(ctx->opcode)); \
7181 rd = gen_avr_ptr(rD(ctx->opcode)); \
7182 gen_helper_##name (rd, rb); \
7183 tcg_temp_free_ptr(rb); \
7184 tcg_temp_free_ptr(rd); \
7185 }
7186
7187 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7188 static void glue(gen_, name)(DisasContext *ctx) \
7189 { \
7190 TCGv_ptr rb, rd; \
7191 \
7192 if (unlikely(!ctx->altivec_enabled)) { \
7193 gen_exception(ctx, POWERPC_EXCP_VPU); \
7194 return; \
7195 } \
7196 rb = gen_avr_ptr(rB(ctx->opcode)); \
7197 rd = gen_avr_ptr(rD(ctx->opcode)); \
7198 gen_helper_##name(cpu_env, rd, rb); \
7199 tcg_temp_free_ptr(rb); \
7200 tcg_temp_free_ptr(rd); \
7201 }
7202
7203 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7204 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7205 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7206 GEN_VXFORM_NOA(vupklsb, 7, 10);
7207 GEN_VXFORM_NOA(vupklsh, 7, 11);
7208 GEN_VXFORM_NOA(vupklsw, 7, 27);
7209 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7210 GEN_VXFORM_NOA(vupklpx, 7, 15);
7211 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7212 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7213 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7214 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7215 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7216 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7217 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7218 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7219
7220 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7221 static void glue(gen_, name)(DisasContext *ctx) \
7222 { \
7223 TCGv_ptr rd; \
7224 TCGv_i32 simm; \
7225 if (unlikely(!ctx->altivec_enabled)) { \
7226 gen_exception(ctx, POWERPC_EXCP_VPU); \
7227 return; \
7228 } \
7229 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7230 rd = gen_avr_ptr(rD(ctx->opcode)); \
7231 gen_helper_##name (rd, simm); \
7232 tcg_temp_free_i32(simm); \
7233 tcg_temp_free_ptr(rd); \
7234 }
7235
7236 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7237 static void glue(gen_, name)(DisasContext *ctx) \
7238 { \
7239 TCGv_ptr rb, rd; \
7240 TCGv_i32 uimm; \
7241 if (unlikely(!ctx->altivec_enabled)) { \
7242 gen_exception(ctx, POWERPC_EXCP_VPU); \
7243 return; \
7244 } \
7245 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7246 rb = gen_avr_ptr(rB(ctx->opcode)); \
7247 rd = gen_avr_ptr(rD(ctx->opcode)); \
7248 gen_helper_##name (rd, rb, uimm); \
7249 tcg_temp_free_i32(uimm); \
7250 tcg_temp_free_ptr(rb); \
7251 tcg_temp_free_ptr(rd); \
7252 }
7253
7254 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7255 static void glue(gen_, name)(DisasContext *ctx) \
7256 { \
7257 TCGv_ptr rb, rd; \
7258 TCGv_i32 uimm; \
7259 \
7260 if (unlikely(!ctx->altivec_enabled)) { \
7261 gen_exception(ctx, POWERPC_EXCP_VPU); \
7262 return; \
7263 } \
7264 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7265 rb = gen_avr_ptr(rB(ctx->opcode)); \
7266 rd = gen_avr_ptr(rD(ctx->opcode)); \
7267 gen_helper_##name(cpu_env, rd, rb, uimm); \
7268 tcg_temp_free_i32(uimm); \
7269 tcg_temp_free_ptr(rb); \
7270 tcg_temp_free_ptr(rd); \
7271 }
7272
7273 GEN_VXFORM_UIMM(vspltb, 6, 8);
7274 GEN_VXFORM_UIMM(vsplth, 6, 9);
7275 GEN_VXFORM_UIMM(vspltw, 6, 10);
7276 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7277 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7278 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7279 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7280
7281 static void gen_vsldoi(DisasContext *ctx)
7282 {
7283 TCGv_ptr ra, rb, rd;
7284 TCGv_i32 sh;
7285 if (unlikely(!ctx->altivec_enabled)) {
7286 gen_exception(ctx, POWERPC_EXCP_VPU);
7287 return;
7288 }
7289 ra = gen_avr_ptr(rA(ctx->opcode));
7290 rb = gen_avr_ptr(rB(ctx->opcode));
7291 rd = gen_avr_ptr(rD(ctx->opcode));
7292 sh = tcg_const_i32(VSH(ctx->opcode));
7293 gen_helper_vsldoi (rd, ra, rb, sh);
7294 tcg_temp_free_ptr(ra);
7295 tcg_temp_free_ptr(rb);
7296 tcg_temp_free_ptr(rd);
7297 tcg_temp_free_i32(sh);
7298 }
7299
7300 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7301 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7302 { \
7303 TCGv_ptr ra, rb, rc, rd; \
7304 if (unlikely(!ctx->altivec_enabled)) { \
7305 gen_exception(ctx, POWERPC_EXCP_VPU); \
7306 return; \
7307 } \
7308 ra = gen_avr_ptr(rA(ctx->opcode)); \
7309 rb = gen_avr_ptr(rB(ctx->opcode)); \
7310 rc = gen_avr_ptr(rC(ctx->opcode)); \
7311 rd = gen_avr_ptr(rD(ctx->opcode)); \
7312 if (Rc(ctx->opcode)) { \
7313 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7314 } else { \
7315 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7316 } \
7317 tcg_temp_free_ptr(ra); \
7318 tcg_temp_free_ptr(rb); \
7319 tcg_temp_free_ptr(rc); \
7320 tcg_temp_free_ptr(rd); \
7321 }
7322
7323 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7324
7325 static void gen_vmladduhm(DisasContext *ctx)
7326 {
7327 TCGv_ptr ra, rb, rc, rd;
7328 if (unlikely(!ctx->altivec_enabled)) {
7329 gen_exception(ctx, POWERPC_EXCP_VPU);
7330 return;
7331 }
7332 ra = gen_avr_ptr(rA(ctx->opcode));
7333 rb = gen_avr_ptr(rB(ctx->opcode));
7334 rc = gen_avr_ptr(rC(ctx->opcode));
7335 rd = gen_avr_ptr(rD(ctx->opcode));
7336 gen_helper_vmladduhm(rd, ra, rb, rc);
7337 tcg_temp_free_ptr(ra);
7338 tcg_temp_free_ptr(rb);
7339 tcg_temp_free_ptr(rc);
7340 tcg_temp_free_ptr(rd);
7341 }
7342
7343 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7344 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7345 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7346 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7347 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7348
7349 GEN_VXFORM_NOA(vclzb, 1, 28)
7350 GEN_VXFORM_NOA(vclzh, 1, 29)
7351 GEN_VXFORM_NOA(vclzw, 1, 30)
7352 GEN_VXFORM_NOA(vclzd, 1, 31)
7353 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7354 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7355 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7356 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7357 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7358 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7359 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7360 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7361 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7362 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7363 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7364 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7365 GEN_VXFORM(vbpermq, 6, 21);
7366 GEN_VXFORM_NOA(vgbbd, 6, 20);
7367 GEN_VXFORM(vpmsumb, 4, 16)
7368 GEN_VXFORM(vpmsumh, 4, 17)
7369 GEN_VXFORM(vpmsumw, 4, 18)
7370 GEN_VXFORM(vpmsumd, 4, 19)
7371
7372 #define GEN_BCD(op) \
7373 static void gen_##op(DisasContext *ctx) \
7374 { \
7375 TCGv_ptr ra, rb, rd; \
7376 TCGv_i32 ps; \
7377 \
7378 if (unlikely(!ctx->altivec_enabled)) { \
7379 gen_exception(ctx, POWERPC_EXCP_VPU); \
7380 return; \
7381 } \
7382 \
7383 ra = gen_avr_ptr(rA(ctx->opcode)); \
7384 rb = gen_avr_ptr(rB(ctx->opcode)); \
7385 rd = gen_avr_ptr(rD(ctx->opcode)); \
7386 \
7387 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7388 \
7389 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7390 \
7391 tcg_temp_free_ptr(ra); \
7392 tcg_temp_free_ptr(rb); \
7393 tcg_temp_free_ptr(rd); \
7394 tcg_temp_free_i32(ps); \
7395 }
7396
7397 GEN_BCD(bcdadd)
7398 GEN_BCD(bcdsub)
7399
7400 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7401 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7402 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7403 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7404 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7405 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7406 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7407 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7408
7409 static void gen_vsbox(DisasContext *ctx)
7410 {
7411 TCGv_ptr ra, rd;
7412 if (unlikely(!ctx->altivec_enabled)) {
7413 gen_exception(ctx, POWERPC_EXCP_VPU);
7414 return;
7415 }
7416 ra = gen_avr_ptr(rA(ctx->opcode));
7417 rd = gen_avr_ptr(rD(ctx->opcode));
7418 gen_helper_vsbox(rd, ra);
7419 tcg_temp_free_ptr(ra);
7420 tcg_temp_free_ptr(rd);
7421 }
7422
7423 GEN_VXFORM(vcipher, 4, 20)
7424 GEN_VXFORM(vcipherlast, 4, 20)
7425 GEN_VXFORM(vncipher, 4, 21)
7426 GEN_VXFORM(vncipherlast, 4, 21)
7427
7428 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7429 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7430 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7431 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7432
7433 #define VSHASIGMA(op) \
7434 static void gen_##op(DisasContext *ctx) \
7435 { \
7436 TCGv_ptr ra, rd; \
7437 TCGv_i32 st_six; \
7438 if (unlikely(!ctx->altivec_enabled)) { \
7439 gen_exception(ctx, POWERPC_EXCP_VPU); \
7440 return; \
7441 } \
7442 ra = gen_avr_ptr(rA(ctx->opcode)); \
7443 rd = gen_avr_ptr(rD(ctx->opcode)); \
7444 st_six = tcg_const_i32(rB(ctx->opcode)); \
7445 gen_helper_##op(rd, ra, st_six); \
7446 tcg_temp_free_ptr(ra); \
7447 tcg_temp_free_ptr(rd); \
7448 tcg_temp_free_i32(st_six); \
7449 }
7450
7451 VSHASIGMA(vshasigmaw)
7452 VSHASIGMA(vshasigmad)
7453
7454 GEN_VXFORM3(vpermxor, 22, 0xFF)
7455 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7456 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7457
7458 /*** VSX extension ***/
7459
7460 static inline TCGv_i64 cpu_vsrh(int n)
7461 {
7462 if (n < 32) {
7463 return cpu_fpr[n];
7464 } else {
7465 return cpu_avrh[n-32];
7466 }
7467 }
7468
7469 static inline TCGv_i64 cpu_vsrl(int n)
7470 {
7471 if (n < 32) {
7472 return cpu_vsr[n];
7473 } else {
7474 return cpu_avrl[n-32];
7475 }
7476 }
7477
7478 #define VSX_LOAD_SCALAR(name, operation) \
7479 static void gen_##name(DisasContext *ctx) \
7480 { \
7481 TCGv EA; \
7482 if (unlikely(!ctx->vsx_enabled)) { \
7483 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7484 return; \
7485 } \
7486 gen_set_access_type(ctx, ACCESS_INT); \
7487 EA = tcg_temp_new(); \
7488 gen_addr_reg_index(ctx, EA); \
7489 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7490 /* NOTE: cpu_vsrl is undefined */ \
7491 tcg_temp_free(EA); \
7492 }
7493
7494 VSX_LOAD_SCALAR(lxsdx, ld64)
7495 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7496 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7497 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7498
7499 static void gen_lxvd2x(DisasContext *ctx)
7500 {
7501 TCGv EA;
7502 if (unlikely(!ctx->vsx_enabled)) {
7503 gen_exception(ctx, POWERPC_EXCP_VSXU);
7504 return;
7505 }
7506 gen_set_access_type(ctx, ACCESS_INT);
7507 EA = tcg_temp_new();
7508 gen_addr_reg_index(ctx, EA);
7509 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7510 tcg_gen_addi_tl(EA, EA, 8);
7511 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7512 tcg_temp_free(EA);
7513 }
7514
7515 static void gen_lxvdsx(DisasContext *ctx)
7516 {
7517 TCGv EA;
7518 if (unlikely(!ctx->vsx_enabled)) {
7519 gen_exception(ctx, POWERPC_EXCP_VSXU);
7520 return;
7521 }
7522 gen_set_access_type(ctx, ACCESS_INT);
7523 EA = tcg_temp_new();
7524 gen_addr_reg_index(ctx, EA);
7525 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7526 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7527 tcg_temp_free(EA);
7528 }
7529
7530 static void gen_lxvw4x(DisasContext *ctx)
7531 {
7532 TCGv EA;
7533 TCGv_i64 tmp;
7534 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7535 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7536 if (unlikely(!ctx->vsx_enabled)) {
7537 gen_exception(ctx, POWERPC_EXCP_VSXU);
7538 return;
7539 }
7540 gen_set_access_type(ctx, ACCESS_INT);
7541 EA = tcg_temp_new();
7542 tmp = tcg_temp_new_i64();
7543
7544 gen_addr_reg_index(ctx, EA);
7545 gen_qemu_ld32u_i64(ctx, tmp, EA);
7546 tcg_gen_addi_tl(EA, EA, 4);
7547 gen_qemu_ld32u_i64(ctx, xth, EA);
7548 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7549
7550 tcg_gen_addi_tl(EA, EA, 4);
7551 gen_qemu_ld32u_i64(ctx, tmp, EA);
7552 tcg_gen_addi_tl(EA, EA, 4);
7553 gen_qemu_ld32u_i64(ctx, xtl, EA);
7554 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7555
7556 tcg_temp_free(EA);
7557 tcg_temp_free_i64(tmp);
7558 }
7559
7560 #define VSX_STORE_SCALAR(name, operation) \
7561 static void gen_##name(DisasContext *ctx) \
7562 { \
7563 TCGv EA; \
7564 if (unlikely(!ctx->vsx_enabled)) { \
7565 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7566 return; \
7567 } \
7568 gen_set_access_type(ctx, ACCESS_INT); \
7569 EA = tcg_temp_new(); \
7570 gen_addr_reg_index(ctx, EA); \
7571 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7572 tcg_temp_free(EA); \
7573 }
7574
7575 VSX_STORE_SCALAR(stxsdx, st64)
7576 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7577 VSX_STORE_SCALAR(stxsspx, st32fs)
7578
7579 static void gen_stxvd2x(DisasContext *ctx)
7580 {
7581 TCGv EA;
7582 if (unlikely(!ctx->vsx_enabled)) {
7583 gen_exception(ctx, POWERPC_EXCP_VSXU);
7584 return;
7585 }
7586 gen_set_access_type(ctx, ACCESS_INT);
7587 EA = tcg_temp_new();
7588 gen_addr_reg_index(ctx, EA);
7589 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7590 tcg_gen_addi_tl(EA, EA, 8);
7591 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7592 tcg_temp_free(EA);
7593 }
7594
7595 static void gen_stxvw4x(DisasContext *ctx)
7596 {
7597 TCGv_i64 tmp;
7598 TCGv EA;
7599 if (unlikely(!ctx->vsx_enabled)) {
7600 gen_exception(ctx, POWERPC_EXCP_VSXU);
7601 return;
7602 }
7603 gen_set_access_type(ctx, ACCESS_INT);
7604 EA = tcg_temp_new();
7605 gen_addr_reg_index(ctx, EA);
7606 tmp = tcg_temp_new_i64();
7607
7608 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7609 gen_qemu_st32_i64(ctx, tmp, EA);
7610 tcg_gen_addi_tl(EA, EA, 4);
7611 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7612
7613 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7614 tcg_gen_addi_tl(EA, EA, 4);
7615 gen_qemu_st32_i64(ctx, tmp, EA);
7616 tcg_gen_addi_tl(EA, EA, 4);
7617 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7618
7619 tcg_temp_free(EA);
7620 tcg_temp_free_i64(tmp);
7621 }
7622
7623 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7624 static void gen_##name(DisasContext *ctx) \
7625 { \
7626 if (xS(ctx->opcode) < 32) { \
7627 if (unlikely(!ctx->fpu_enabled)) { \
7628 gen_exception(ctx, POWERPC_EXCP_FPU); \
7629 return; \
7630 } \
7631 } else { \
7632 if (unlikely(!ctx->altivec_enabled)) { \
7633 gen_exception(ctx, POWERPC_EXCP_VPU); \
7634 return; \
7635 } \
7636 } \
7637 TCGv_i64 tmp = tcg_temp_new_i64(); \
7638 tcg_gen_##tcgop1(tmp, source); \
7639 tcg_gen_##tcgop2(target, tmp); \
7640 tcg_temp_free_i64(tmp); \
7641 }
7642
7643
7644 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7645 cpu_vsrh(xS(ctx->opcode)))
7646 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7647 cpu_gpr[rA(ctx->opcode)])
7648 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7649 cpu_gpr[rA(ctx->opcode)])
7650
7651 #if defined(TARGET_PPC64)
7652 #define MV_VSRD(name, target, source) \
7653 static void gen_##name(DisasContext *ctx) \
7654 { \
7655 if (xS(ctx->opcode) < 32) { \
7656 if (unlikely(!ctx->fpu_enabled)) { \
7657 gen_exception(ctx, POWERPC_EXCP_FPU); \
7658 return; \
7659 } \
7660 } else { \
7661 if (unlikely(!ctx->altivec_enabled)) { \
7662 gen_exception(ctx, POWERPC_EXCP_VPU); \
7663 return; \
7664 } \
7665 } \
7666 tcg_gen_mov_i64(target, source); \
7667 }
7668
7669 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7670 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7671
7672 #endif
7673
7674 static void gen_xxpermdi(DisasContext *ctx)
7675 {
7676 if (unlikely(!ctx->vsx_enabled)) {
7677 gen_exception(ctx, POWERPC_EXCP_VSXU);
7678 return;
7679 }
7680
7681 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7682 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7683 TCGv_i64 xh, xl;
7684
7685 xh = tcg_temp_new_i64();
7686 xl = tcg_temp_new_i64();
7687
7688 if ((DM(ctx->opcode) & 2) == 0) {
7689 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7690 } else {
7691 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7692 }
7693 if ((DM(ctx->opcode) & 1) == 0) {
7694 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7695 } else {
7696 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7697 }
7698
7699 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7700 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7701
7702 tcg_temp_free_i64(xh);
7703 tcg_temp_free_i64(xl);
7704 } else {
7705 if ((DM(ctx->opcode) & 2) == 0) {
7706 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7707 } else {
7708 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7709 }
7710 if ((DM(ctx->opcode) & 1) == 0) {
7711 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7712 } else {
7713 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7714 }
7715 }
7716 }
7717
7718 #define OP_ABS 1
7719 #define OP_NABS 2
7720 #define OP_NEG 3
7721 #define OP_CPSGN 4
7722 #define SGN_MASK_DP 0x8000000000000000ull
7723 #define SGN_MASK_SP 0x8000000080000000ull
7724
7725 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7726 static void glue(gen_, name)(DisasContext * ctx) \
7727 { \
7728 TCGv_i64 xb, sgm; \
7729 if (unlikely(!ctx->vsx_enabled)) { \
7730 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7731 return; \
7732 } \
7733 xb = tcg_temp_new_i64(); \
7734 sgm = tcg_temp_new_i64(); \
7735 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7736 tcg_gen_movi_i64(sgm, sgn_mask); \
7737 switch (op) { \
7738 case OP_ABS: { \
7739 tcg_gen_andc_i64(xb, xb, sgm); \
7740 break; \
7741 } \
7742 case OP_NABS: { \
7743 tcg_gen_or_i64(xb, xb, sgm); \
7744 break; \
7745 } \
7746 case OP_NEG: { \
7747 tcg_gen_xor_i64(xb, xb, sgm); \
7748 break; \
7749 } \
7750 case OP_CPSGN: { \
7751 TCGv_i64 xa = tcg_temp_new_i64(); \
7752 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7753 tcg_gen_and_i64(xa, xa, sgm); \
7754 tcg_gen_andc_i64(xb, xb, sgm); \
7755 tcg_gen_or_i64(xb, xb, xa); \
7756 tcg_temp_free_i64(xa); \
7757 break; \
7758 } \
7759 } \
7760 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7761 tcg_temp_free_i64(xb); \
7762 tcg_temp_free_i64(sgm); \
7763 }
7764
7765 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7766 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7767 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7768 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7769
7770 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7771 static void glue(gen_, name)(DisasContext * ctx) \
7772 { \
7773 TCGv_i64 xbh, xbl, sgm; \
7774 if (unlikely(!ctx->vsx_enabled)) { \
7775 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7776 return; \
7777 } \
7778 xbh = tcg_temp_new_i64(); \
7779 xbl = tcg_temp_new_i64(); \
7780 sgm = tcg_temp_new_i64(); \
7781 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7782 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7783 tcg_gen_movi_i64(sgm, sgn_mask); \
7784 switch (op) { \
7785 case OP_ABS: { \
7786 tcg_gen_andc_i64(xbh, xbh, sgm); \
7787 tcg_gen_andc_i64(xbl, xbl, sgm); \
7788 break; \
7789 } \
7790 case OP_NABS: { \
7791 tcg_gen_or_i64(xbh, xbh, sgm); \
7792 tcg_gen_or_i64(xbl, xbl, sgm); \
7793 break; \
7794 } \
7795 case OP_NEG: { \
7796 tcg_gen_xor_i64(xbh, xbh, sgm); \
7797 tcg_gen_xor_i64(xbl, xbl, sgm); \
7798 break; \
7799 } \
7800 case OP_CPSGN: { \
7801 TCGv_i64 xah = tcg_temp_new_i64(); \
7802 TCGv_i64 xal = tcg_temp_new_i64(); \
7803 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7804 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7805 tcg_gen_and_i64(xah, xah, sgm); \
7806 tcg_gen_and_i64(xal, xal, sgm); \
7807 tcg_gen_andc_i64(xbh, xbh, sgm); \
7808 tcg_gen_andc_i64(xbl, xbl, sgm); \
7809 tcg_gen_or_i64(xbh, xbh, xah); \
7810 tcg_gen_or_i64(xbl, xbl, xal); \
7811 tcg_temp_free_i64(xah); \
7812 tcg_temp_free_i64(xal); \
7813 break; \
7814 } \
7815 } \
7816 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7817 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7818 tcg_temp_free_i64(xbh); \
7819 tcg_temp_free_i64(xbl); \
7820 tcg_temp_free_i64(sgm); \
7821 }
7822
7823 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7824 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7825 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7826 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7827 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7828 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7829 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7830 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7831
7832 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7833 static void gen_##name(DisasContext * ctx) \
7834 { \
7835 TCGv_i32 opc; \
7836 if (unlikely(!ctx->vsx_enabled)) { \
7837 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7838 return; \
7839 } \
7840 /* NIP cannot be restored if the memory exception comes from an helper */ \
7841 gen_update_nip(ctx, ctx->nip - 4); \
7842 opc = tcg_const_i32(ctx->opcode); \
7843 gen_helper_##name(cpu_env, opc); \
7844 tcg_temp_free_i32(opc); \
7845 }
7846
7847 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7848 static void gen_##name(DisasContext * ctx) \
7849 { \
7850 if (unlikely(!ctx->vsx_enabled)) { \
7851 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7852 return; \
7853 } \
7854 /* NIP cannot be restored if the exception comes */ \
7855 /* from a helper. */ \
7856 gen_update_nip(ctx, ctx->nip - 4); \
7857 \
7858 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7859 cpu_vsrh(xB(ctx->opcode))); \
7860 }
7861
7862 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7863 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7864 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7865 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7866 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7867 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7868 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7869 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7870 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7871 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7872 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7882 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7883 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7884 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7885 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7887 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7897 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7898 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7899
7900 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7901 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7902 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7903 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7904 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7905 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7906 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7907 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7908 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7909 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7910 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7912 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7914 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7915 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7916 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7917
7918 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7919 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7920 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7921 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7922 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7925 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7926 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7927 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7928 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7954
7955 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7991
7992 #define VSX_LOGICAL(name, tcg_op) \
7993 static void glue(gen_, name)(DisasContext * ctx) \
7994 { \
7995 if (unlikely(!ctx->vsx_enabled)) { \
7996 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7997 return; \
7998 } \
7999 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8000 cpu_vsrh(xB(ctx->opcode))); \
8001 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8002 cpu_vsrl(xB(ctx->opcode))); \
8003 }
8004
8005 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8006 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8007 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8008 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8009 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8010 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8011 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8012 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8013
8014 #define VSX_XXMRG(name, high) \
8015 static void glue(gen_, name)(DisasContext * ctx) \
8016 { \
8017 TCGv_i64 a0, a1, b0, b1; \
8018 if (unlikely(!ctx->vsx_enabled)) { \
8019 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8020 return; \
8021 } \
8022 a0 = tcg_temp_new_i64(); \
8023 a1 = tcg_temp_new_i64(); \
8024 b0 = tcg_temp_new_i64(); \
8025 b1 = tcg_temp_new_i64(); \
8026 if (high) { \
8027 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8028 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8029 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8030 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8031 } else { \
8032 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8033 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8034 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8035 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8036 } \
8037 tcg_gen_shri_i64(a0, a0, 32); \
8038 tcg_gen_shri_i64(b0, b0, 32); \
8039 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8040 b0, a0, 32, 32); \
8041 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8042 b1, a1, 32, 32); \
8043 tcg_temp_free_i64(a0); \
8044 tcg_temp_free_i64(a1); \
8045 tcg_temp_free_i64(b0); \
8046 tcg_temp_free_i64(b1); \
8047 }
8048
8049 VSX_XXMRG(xxmrghw, 1)
8050 VSX_XXMRG(xxmrglw, 0)
8051
8052 static void gen_xxsel(DisasContext * ctx)
8053 {
8054 TCGv_i64 a, b, c;
8055 if (unlikely(!ctx->vsx_enabled)) {
8056 gen_exception(ctx, POWERPC_EXCP_VSXU);
8057 return;
8058 }
8059 a = tcg_temp_new_i64();
8060 b = tcg_temp_new_i64();
8061 c = tcg_temp_new_i64();
8062
8063 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8064 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8065 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8066
8067 tcg_gen_and_i64(b, b, c);
8068 tcg_gen_andc_i64(a, a, c);
8069 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8070
8071 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8072 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8073 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8074
8075 tcg_gen_and_i64(b, b, c);
8076 tcg_gen_andc_i64(a, a, c);
8077 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8078
8079 tcg_temp_free_i64(a);
8080 tcg_temp_free_i64(b);
8081 tcg_temp_free_i64(c);
8082 }
8083
8084 static void gen_xxspltw(DisasContext *ctx)
8085 {
8086 TCGv_i64 b, b2;
8087 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8088 cpu_vsrl(xB(ctx->opcode)) :
8089 cpu_vsrh(xB(ctx->opcode));
8090
8091 if (unlikely(!ctx->vsx_enabled)) {
8092 gen_exception(ctx, POWERPC_EXCP_VSXU);
8093 return;
8094 }
8095
8096 b = tcg_temp_new_i64();
8097 b2 = tcg_temp_new_i64();
8098
8099 if (UIM(ctx->opcode) & 1) {
8100 tcg_gen_ext32u_i64(b, vsr);
8101 } else {
8102 tcg_gen_shri_i64(b, vsr, 32);
8103 }
8104
8105 tcg_gen_shli_i64(b2, b, 32);
8106 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8107 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8108
8109 tcg_temp_free_i64(b);
8110 tcg_temp_free_i64(b2);
8111 }
8112
8113 static void gen_xxsldwi(DisasContext *ctx)
8114 {
8115 TCGv_i64 xth, xtl;
8116 if (unlikely(!ctx->vsx_enabled)) {
8117 gen_exception(ctx, POWERPC_EXCP_VSXU);
8118 return;
8119 }
8120 xth = tcg_temp_new_i64();
8121 xtl = tcg_temp_new_i64();
8122
8123 switch (SHW(ctx->opcode)) {
8124 case 0: {
8125 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8126 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8127 break;
8128 }
8129 case 1: {
8130 TCGv_i64 t0 = tcg_temp_new_i64();
8131 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8132 tcg_gen_shli_i64(xth, xth, 32);
8133 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8134 tcg_gen_shri_i64(t0, t0, 32);
8135 tcg_gen_or_i64(xth, xth, t0);
8136 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8137 tcg_gen_shli_i64(xtl, xtl, 32);
8138 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8139 tcg_gen_shri_i64(t0, t0, 32);
8140 tcg_gen_or_i64(xtl, xtl, t0);
8141 tcg_temp_free_i64(t0);
8142 break;
8143 }
8144 case 2: {
8145 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8146 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8147 break;
8148 }
8149 case 3: {
8150 TCGv_i64 t0 = tcg_temp_new_i64();
8151 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8152 tcg_gen_shli_i64(xth, xth, 32);
8153 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8154 tcg_gen_shri_i64(t0, t0, 32);
8155 tcg_gen_or_i64(xth, xth, t0);
8156 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8157 tcg_gen_shli_i64(xtl, xtl, 32);
8158 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8159 tcg_gen_shri_i64(t0, t0, 32);
8160 tcg_gen_or_i64(xtl, xtl, t0);
8161 tcg_temp_free_i64(t0);
8162 break;
8163 }
8164 }
8165
8166 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8167 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8168
8169 tcg_temp_free_i64(xth);
8170 tcg_temp_free_i64(xtl);
8171 }
8172
8173 /*** Decimal Floating Point ***/
8174
8175 static inline TCGv_ptr gen_fprp_ptr(int reg)
8176 {
8177 TCGv_ptr r = tcg_temp_new_ptr();
8178 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8179 return r;
8180 }
8181
8182 #if defined(TARGET_PPC64)
8183 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8184 {
8185 TCGv_i32 tmp = tcg_temp_new_i32();
8186 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8187 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8188 tcg_temp_free_i32(tmp);
8189 }
8190 #else
8191 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8192 {
8193 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8194 }
8195 #endif
8196
8197 #define GEN_DFP_T_A_B_Rc(name) \
8198 static void gen_##name(DisasContext *ctx) \
8199 { \
8200 TCGv_ptr rd, ra, rb; \
8201 if (unlikely(!ctx->fpu_enabled)) { \
8202 gen_exception(ctx, POWERPC_EXCP_FPU); \
8203 return; \
8204 } \
8205 gen_update_nip(ctx, ctx->nip - 4); \
8206 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8207 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8208 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8209 gen_helper_##name(cpu_env, rd, ra, rb); \
8210 if (unlikely(Rc(ctx->opcode) != 0)) { \
8211 gen_set_cr6_from_fpscr(ctx); \
8212 } \
8213 tcg_temp_free_ptr(rd); \
8214 tcg_temp_free_ptr(ra); \
8215 tcg_temp_free_ptr(rb); \
8216 }
8217
8218 #define GEN_DFP_BF_A_B(name) \
8219 static void gen_##name(DisasContext *ctx) \
8220 { \
8221 TCGv_ptr ra, rb; \
8222 if (unlikely(!ctx->fpu_enabled)) { \
8223 gen_exception(ctx, POWERPC_EXCP_FPU); \
8224 return; \
8225 } \
8226 gen_update_nip(ctx, ctx->nip - 4); \
8227 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8228 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8229 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8230 cpu_env, ra, rb); \
8231 tcg_temp_free_ptr(ra); \
8232 tcg_temp_free_ptr(rb); \
8233 }
8234
8235 #define GEN_DFP_BF_A_DCM(name) \
8236 static void gen_##name(DisasContext *ctx) \
8237 { \
8238 TCGv_ptr ra; \
8239 TCGv_i32 dcm; \
8240 if (unlikely(!ctx->fpu_enabled)) { \
8241 gen_exception(ctx, POWERPC_EXCP_FPU); \
8242 return; \
8243 } \
8244 gen_update_nip(ctx, ctx->nip - 4); \
8245 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8246 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8247 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8248 cpu_env, ra, dcm); \
8249 tcg_temp_free_ptr(ra); \
8250 tcg_temp_free_i32(dcm); \
8251 }
8252
8253 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8254 static void gen_##name(DisasContext *ctx) \
8255 { \
8256 TCGv_ptr rt, rb; \
8257 TCGv_i32 u32_1, u32_2; \
8258 if (unlikely(!ctx->fpu_enabled)) { \
8259 gen_exception(ctx, POWERPC_EXCP_FPU); \
8260 return; \
8261 } \
8262 gen_update_nip(ctx, ctx->nip - 4); \
8263 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8264 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8265 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8266 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8267 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8268 if (unlikely(Rc(ctx->opcode) != 0)) { \
8269 gen_set_cr6_from_fpscr(ctx); \
8270 } \
8271 tcg_temp_free_ptr(rt); \
8272 tcg_temp_free_ptr(rb); \
8273 tcg_temp_free_i32(u32_1); \
8274 tcg_temp_free_i32(u32_2); \
8275 }
8276
8277 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8278 static void gen_##name(DisasContext *ctx) \
8279 { \
8280 TCGv_ptr rt, ra, rb; \
8281 TCGv_i32 i32; \
8282 if (unlikely(!ctx->fpu_enabled)) { \
8283 gen_exception(ctx, POWERPC_EXCP_FPU); \
8284 return; \
8285 } \
8286 gen_update_nip(ctx, ctx->nip - 4); \
8287 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8288 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8289 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8290 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8291 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8292 if (unlikely(Rc(ctx->opcode) != 0)) { \
8293 gen_set_cr6_from_fpscr(ctx); \
8294 } \
8295 tcg_temp_free_ptr(rt); \
8296 tcg_temp_free_ptr(rb); \
8297 tcg_temp_free_ptr(ra); \
8298 tcg_temp_free_i32(i32); \
8299 }
8300
8301 #define GEN_DFP_T_B_Rc(name) \
8302 static void gen_##name(DisasContext *ctx) \
8303 { \
8304 TCGv_ptr rt, rb; \
8305 if (unlikely(!ctx->fpu_enabled)) { \
8306 gen_exception(ctx, POWERPC_EXCP_FPU); \
8307 return; \
8308 } \
8309 gen_update_nip(ctx, ctx->nip - 4); \
8310 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8311 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8312 gen_helper_##name(cpu_env, rt, rb); \
8313 if (unlikely(Rc(ctx->opcode) != 0)) { \
8314 gen_set_cr6_from_fpscr(ctx); \
8315 } \
8316 tcg_temp_free_ptr(rt); \
8317 tcg_temp_free_ptr(rb); \
8318 }
8319
8320 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8321 static void gen_##name(DisasContext *ctx) \
8322 { \
8323 TCGv_ptr rt, rs; \
8324 TCGv_i32 i32; \
8325 if (unlikely(!ctx->fpu_enabled)) { \
8326 gen_exception(ctx, POWERPC_EXCP_FPU); \
8327 return; \
8328 } \
8329 gen_update_nip(ctx, ctx->nip - 4); \
8330 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8331 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8332 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8333 gen_helper_##name(cpu_env, rt, rs, i32); \
8334 if (unlikely(Rc(ctx->opcode) != 0)) { \
8335 gen_set_cr6_from_fpscr(ctx); \
8336 } \
8337 tcg_temp_free_ptr(rt); \
8338 tcg_temp_free_ptr(rs); \
8339 tcg_temp_free_i32(i32); \
8340 }
8341
8342 GEN_DFP_T_A_B_Rc(dadd)
8343 GEN_DFP_T_A_B_Rc(daddq)
8344 GEN_DFP_T_A_B_Rc(dsub)
8345 GEN_DFP_T_A_B_Rc(dsubq)
8346 GEN_DFP_T_A_B_Rc(dmul)
8347 GEN_DFP_T_A_B_Rc(dmulq)
8348 GEN_DFP_T_A_B_Rc(ddiv)
8349 GEN_DFP_T_A_B_Rc(ddivq)
8350 GEN_DFP_BF_A_B(dcmpu)
8351 GEN_DFP_BF_A_B(dcmpuq)
8352 GEN_DFP_BF_A_B(dcmpo)
8353 GEN_DFP_BF_A_B(dcmpoq)
8354 GEN_DFP_BF_A_DCM(dtstdc)
8355 GEN_DFP_BF_A_DCM(dtstdcq)
8356 GEN_DFP_BF_A_DCM(dtstdg)
8357 GEN_DFP_BF_A_DCM(dtstdgq)
8358 GEN_DFP_BF_A_B(dtstex)
8359 GEN_DFP_BF_A_B(dtstexq)
8360 GEN_DFP_BF_A_B(dtstsf)
8361 GEN_DFP_BF_A_B(dtstsfq)
8362 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8363 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8364 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8365 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8366 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8367 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8368 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8369 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8370 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8371 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8372 GEN_DFP_T_B_Rc(dctdp)
8373 GEN_DFP_T_B_Rc(dctqpq)
8374 GEN_DFP_T_B_Rc(drsp)
8375 GEN_DFP_T_B_Rc(drdpq)
8376 GEN_DFP_T_B_Rc(dcffix)
8377 GEN_DFP_T_B_Rc(dcffixq)
8378 GEN_DFP_T_B_Rc(dctfix)
8379 GEN_DFP_T_B_Rc(dctfixq)
8380 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8381 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8382 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8383 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8384 GEN_DFP_T_B_Rc(dxex)
8385 GEN_DFP_T_B_Rc(dxexq)
8386 GEN_DFP_T_A_B_Rc(diex)
8387 GEN_DFP_T_A_B_Rc(diexq)
8388 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8389 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8390 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8391 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8392
8393 /*** SPE extension ***/
8394 /* Register moves */
8395
8396 static inline void gen_evmra(DisasContext *ctx)
8397 {
8398
8399 if (unlikely(!ctx->spe_enabled)) {
8400 gen_exception(ctx, POWERPC_EXCP_SPEU);
8401 return;
8402 }
8403
8404 TCGv_i64 tmp = tcg_temp_new_i64();
8405
8406 /* tmp := rA_lo + rA_hi << 32 */
8407 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8408
8409 /* spe_acc := tmp */
8410 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8411 tcg_temp_free_i64(tmp);
8412
8413 /* rD := rA */
8414 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8415 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8416 }
8417
8418 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8419 {
8420 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8421 }
8422
8423 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8424 {
8425 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8426 }
8427
8428 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8429 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8430 { \
8431 if (Rc(ctx->opcode)) \
8432 gen_##name1(ctx); \
8433 else \
8434 gen_##name0(ctx); \
8435 }
8436
8437 /* Handler for undefined SPE opcodes */
8438 static inline void gen_speundef(DisasContext *ctx)
8439 {
8440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8441 }
8442
8443 /* SPE logic */
8444 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8445 static inline void gen_##name(DisasContext *ctx) \
8446 { \
8447 if (unlikely(!ctx->spe_enabled)) { \
8448 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8449 return; \
8450 } \
8451 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8452 cpu_gpr[rB(ctx->opcode)]); \
8453 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8454 cpu_gprh[rB(ctx->opcode)]); \
8455 }
8456
8457 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8458 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8459 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8460 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8461 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8462 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8463 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8464 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8465
8466 /* SPE logic immediate */
8467 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8468 static inline void gen_##name(DisasContext *ctx) \
8469 { \
8470 TCGv_i32 t0; \
8471 if (unlikely(!ctx->spe_enabled)) { \
8472 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8473 return; \
8474 } \
8475 t0 = tcg_temp_new_i32(); \
8476 \
8477 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8478 tcg_opi(t0, t0, rB(ctx->opcode)); \
8479 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8480 \
8481 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8482 tcg_opi(t0, t0, rB(ctx->opcode)); \
8483 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8484 \
8485 tcg_temp_free_i32(t0); \
8486 }
8487 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8488 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8489 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8490 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8491
8492 /* SPE arithmetic */
8493 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8494 static inline void gen_##name(DisasContext *ctx) \
8495 { \
8496 TCGv_i32 t0; \
8497 if (unlikely(!ctx->spe_enabled)) { \
8498 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8499 return; \
8500 } \
8501 t0 = tcg_temp_new_i32(); \
8502 \
8503 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8504 tcg_op(t0, t0); \
8505 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8506 \
8507 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8508 tcg_op(t0, t0); \
8509 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8510 \
8511 tcg_temp_free_i32(t0); \
8512 }
8513
8514 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8515 {
8516 int l1 = gen_new_label();
8517 int l2 = gen_new_label();
8518
8519 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8520 tcg_gen_neg_i32(ret, arg1);
8521 tcg_gen_br(l2);
8522 gen_set_label(l1);
8523 tcg_gen_mov_i32(ret, arg1);
8524 gen_set_label(l2);
8525 }
8526 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8527 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8528 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8529 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8530 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8531 {
8532 tcg_gen_addi_i32(ret, arg1, 0x8000);
8533 tcg_gen_ext16u_i32(ret, ret);
8534 }
8535 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8536 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8537 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8538
8539 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8540 static inline void gen_##name(DisasContext *ctx) \
8541 { \
8542 TCGv_i32 t0, t1; \
8543 if (unlikely(!ctx->spe_enabled)) { \
8544 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8545 return; \
8546 } \
8547 t0 = tcg_temp_new_i32(); \
8548 t1 = tcg_temp_new_i32(); \
8549 \
8550 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8551 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8552 tcg_op(t0, t0, t1); \
8553 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8554 \
8555 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8556 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8557 tcg_op(t0, t0, t1); \
8558 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8559 \
8560 tcg_temp_free_i32(t0); \
8561 tcg_temp_free_i32(t1); \
8562 }
8563
8564 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8565 {
8566 TCGv_i32 t0;
8567 int l1, l2;
8568
8569 l1 = gen_new_label();
8570 l2 = gen_new_label();
8571 t0 = tcg_temp_local_new_i32();
8572 /* No error here: 6 bits are used */
8573 tcg_gen_andi_i32(t0, arg2, 0x3F);
8574 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8575 tcg_gen_shr_i32(ret, arg1, t0);
8576 tcg_gen_br(l2);
8577 gen_set_label(l1);
8578 tcg_gen_movi_i32(ret, 0);
8579 gen_set_label(l2);
8580 tcg_temp_free_i32(t0);
8581 }
8582 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8583 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8584 {
8585 TCGv_i32 t0;
8586 int l1, l2;
8587
8588 l1 = gen_new_label();
8589 l2 = gen_new_label();
8590 t0 = tcg_temp_local_new_i32();
8591 /* No error here: 6 bits are used */
8592 tcg_gen_andi_i32(t0, arg2, 0x3F);
8593 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8594 tcg_gen_sar_i32(ret, arg1, t0);
8595 tcg_gen_br(l2);
8596 gen_set_label(l1);
8597 tcg_gen_movi_i32(ret, 0);
8598 gen_set_label(l2);
8599 tcg_temp_free_i32(t0);
8600 }
8601 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8602 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8603 {
8604 TCGv_i32 t0;
8605 int l1, l2;
8606
8607 l1 = gen_new_label();
8608 l2 = gen_new_label();
8609 t0 = tcg_temp_local_new_i32();
8610 /* No error here: 6 bits are used */
8611 tcg_gen_andi_i32(t0, arg2, 0x3F);
8612 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8613 tcg_gen_shl_i32(ret, arg1, t0);
8614 tcg_gen_br(l2);
8615 gen_set_label(l1);
8616 tcg_gen_movi_i32(ret, 0);
8617 gen_set_label(l2);
8618 tcg_temp_free_i32(t0);
8619 }
8620 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8621 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8622 {
8623 TCGv_i32 t0 = tcg_temp_new_i32();
8624 tcg_gen_andi_i32(t0, arg2, 0x1F);
8625 tcg_gen_rotl_i32(ret, arg1, t0);
8626 tcg_temp_free_i32(t0);
8627 }
8628 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8629 static inline void gen_evmergehi(DisasContext *ctx)
8630 {
8631 if (unlikely(!ctx->spe_enabled)) {
8632 gen_exception(ctx, POWERPC_EXCP_SPEU);
8633 return;
8634 }
8635 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8636 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8637 }
8638 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8639 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8640 {
8641 tcg_gen_sub_i32(ret, arg2, arg1);
8642 }
8643 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8644
8645 /* SPE arithmetic immediate */
8646 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8647 static inline void gen_##name(DisasContext *ctx) \
8648 { \
8649 TCGv_i32 t0; \
8650 if (unlikely(!ctx->spe_enabled)) { \
8651 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8652 return; \
8653 } \
8654 t0 = tcg_temp_new_i32(); \
8655 \
8656 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8657 tcg_op(t0, t0, rA(ctx->opcode)); \
8658 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8659 \
8660 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8661 tcg_op(t0, t0, rA(ctx->opcode)); \
8662 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8663 \
8664 tcg_temp_free_i32(t0); \
8665 }
8666 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8667 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8668
8669 /* SPE comparison */
8670 #define GEN_SPEOP_COMP(name, tcg_cond) \
8671 static inline void gen_##name(DisasContext *ctx) \
8672 { \
8673 if (unlikely(!ctx->spe_enabled)) { \
8674 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8675 return; \
8676 } \
8677 int l1 = gen_new_label(); \
8678 int l2 = gen_new_label(); \
8679 int l3 = gen_new_label(); \
8680 int l4 = gen_new_label(); \
8681 \
8682 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8683 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8684 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8685 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8686 \
8687 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8688 cpu_gpr[rB(ctx->opcode)], l1); \
8689 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8690 tcg_gen_br(l2); \
8691 gen_set_label(l1); \
8692 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8693 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8694 gen_set_label(l2); \
8695 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8696 cpu_gprh[rB(ctx->opcode)], l3); \
8697 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8698 ~(CRF_CH | CRF_CH_AND_CL)); \
8699 tcg_gen_br(l4); \
8700 gen_set_label(l3); \
8701 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8702 CRF_CH | CRF_CH_OR_CL); \
8703 gen_set_label(l4); \
8704 }
8705 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8706 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8707 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8708 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8709 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8710
8711 /* SPE misc */
8712 static inline void gen_brinc(DisasContext *ctx)
8713 {
8714 /* Note: brinc is usable even if SPE is disabled */
8715 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8716 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8717 }
8718 static inline void gen_evmergelo(DisasContext *ctx)
8719 {
8720 if (unlikely(!ctx->spe_enabled)) {
8721 gen_exception(ctx, POWERPC_EXCP_SPEU);
8722 return;
8723 }
8724 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8725 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8726 }
8727 static inline void gen_evmergehilo(DisasContext *ctx)
8728 {
8729 if (unlikely(!ctx->spe_enabled)) {
8730 gen_exception(ctx, POWERPC_EXCP_SPEU);
8731 return;
8732 }
8733 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8734 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8735 }
8736 static inline void gen_evmergelohi(DisasContext *ctx)
8737 {
8738 if (unlikely(!ctx->spe_enabled)) {
8739 gen_exception(ctx, POWERPC_EXCP_SPEU);
8740 return;
8741 }
8742 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8743 TCGv tmp = tcg_temp_new();
8744 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8746 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8747 tcg_temp_free(tmp);
8748 } else {
8749 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8750 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8751 }
8752 }
8753 static inline void gen_evsplati(DisasContext *ctx)
8754 {
8755 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8756
8757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8758 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8759 }
8760 static inline void gen_evsplatfi(DisasContext *ctx)
8761 {
8762 uint64_t imm = rA(ctx->opcode) << 27;
8763
8764 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8765 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8766 }
8767
8768 static inline void gen_evsel(DisasContext *ctx)
8769 {
8770 int l1 = gen_new_label();
8771 int l2 = gen_new_label();
8772 int l3 = gen_new_label();
8773 int l4 = gen_new_label();
8774 TCGv_i32 t0 = tcg_temp_local_new_i32();
8775 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8776 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8777 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8778 tcg_gen_br(l2);
8779 gen_set_label(l1);
8780 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8781 gen_set_label(l2);
8782 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8783 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8784 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8785 tcg_gen_br(l4);
8786 gen_set_label(l3);
8787 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8788 gen_set_label(l4);
8789 tcg_temp_free_i32(t0);
8790 }
8791
8792 static void gen_evsel0(DisasContext *ctx)
8793 {
8794 gen_evsel(ctx);
8795 }
8796
8797 static void gen_evsel1(DisasContext *ctx)
8798 {
8799 gen_evsel(ctx);
8800 }
8801
8802 static void gen_evsel2(DisasContext *ctx)
8803 {
8804 gen_evsel(ctx);
8805 }
8806
8807 static void gen_evsel3(DisasContext *ctx)
8808 {
8809 gen_evsel(ctx);
8810 }
8811
8812 /* Multiply */
8813
8814 static inline void gen_evmwumi(DisasContext *ctx)
8815 {
8816 TCGv_i64 t0, t1;
8817
8818 if (unlikely(!ctx->spe_enabled)) {
8819 gen_exception(ctx, POWERPC_EXCP_SPEU);
8820 return;
8821 }
8822
8823 t0 = tcg_temp_new_i64();
8824 t1 = tcg_temp_new_i64();
8825
8826 /* t0 := rA; t1 := rB */
8827 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8828 tcg_gen_ext32u_i64(t0, t0);
8829 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8830 tcg_gen_ext32u_i64(t1, t1);
8831
8832 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8833
8834 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8835
8836 tcg_temp_free_i64(t0);
8837 tcg_temp_free_i64(t1);
8838 }
8839
8840 static inline void gen_evmwumia(DisasContext *ctx)
8841 {
8842 TCGv_i64 tmp;
8843
8844 if (unlikely(!ctx->spe_enabled)) {
8845 gen_exception(ctx, POWERPC_EXCP_SPEU);
8846 return;
8847 }
8848
8849 gen_evmwumi(ctx); /* rD := rA * rB */
8850
8851 tmp = tcg_temp_new_i64();
8852
8853 /* acc := rD */
8854 gen_load_gpr64(tmp, rD(ctx->opcode));
8855 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8856 tcg_temp_free_i64(tmp);
8857 }
8858
8859 static inline void gen_evmwumiaa(DisasContext *ctx)
8860 {
8861 TCGv_i64 acc;
8862 TCGv_i64 tmp;
8863
8864 if (unlikely(!ctx->spe_enabled)) {
8865 gen_exception(ctx, POWERPC_EXCP_SPEU);
8866 return;
8867 }
8868
8869 gen_evmwumi(ctx); /* rD := rA * rB */
8870
8871 acc = tcg_temp_new_i64();
8872 tmp = tcg_temp_new_i64();
8873
8874 /* tmp := rD */
8875 gen_load_gpr64(tmp, rD(ctx->opcode));
8876
8877 /* Load acc */
8878 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8879
8880 /* acc := tmp + acc */
8881 tcg_gen_add_i64(acc, acc, tmp);
8882
8883 /* Store acc */
8884 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8885
8886 /* rD := acc */
8887 gen_store_gpr64(rD(ctx->opcode), acc);
8888
8889 tcg_temp_free_i64(acc);
8890 tcg_temp_free_i64(tmp);
8891 }
8892
8893 static inline void gen_evmwsmi(DisasContext *ctx)
8894 {
8895 TCGv_i64 t0, t1;
8896
8897 if (unlikely(!ctx->spe_enabled)) {
8898 gen_exception(ctx, POWERPC_EXCP_SPEU);
8899 return;
8900 }
8901
8902 t0 = tcg_temp_new_i64();
8903 t1 = tcg_temp_new_i64();
8904
8905 /* t0 := rA; t1 := rB */
8906 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8907 tcg_gen_ext32s_i64(t0, t0);
8908 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8909 tcg_gen_ext32s_i64(t1, t1);
8910
8911 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8912
8913 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8914
8915 tcg_temp_free_i64(t0);
8916 tcg_temp_free_i64(t1);
8917 }
8918
8919 static inline void gen_evmwsmia(DisasContext *ctx)
8920 {
8921 TCGv_i64 tmp;
8922
8923 gen_evmwsmi(ctx); /* rD := rA * rB */
8924
8925 tmp = tcg_temp_new_i64();
8926
8927 /* acc := rD */
8928 gen_load_gpr64(tmp, rD(ctx->opcode));
8929 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8930
8931 tcg_temp_free_i64(tmp);
8932 }
8933
8934 static inline void gen_evmwsmiaa(DisasContext *ctx)
8935 {
8936 TCGv_i64 acc = tcg_temp_new_i64();
8937 TCGv_i64 tmp = tcg_temp_new_i64();
8938
8939 gen_evmwsmi(ctx); /* rD := rA * rB */
8940
8941 acc = tcg_temp_new_i64();
8942 tmp = tcg_temp_new_i64();
8943
8944 /* tmp := rD */
8945 gen_load_gpr64(tmp, rD(ctx->opcode));
8946
8947 /* Load acc */
8948 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8949
8950 /* acc := tmp + acc */
8951 tcg_gen_add_i64(acc, acc, tmp);
8952
8953 /* Store acc */
8954 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8955
8956 /* rD := acc */
8957 gen_store_gpr64(rD(ctx->opcode), acc);
8958
8959 tcg_temp_free_i64(acc);
8960 tcg_temp_free_i64(tmp);
8961 }
8962
8963 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8964 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8965 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8966 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8967 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8968 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8969 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8970 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8971 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8972 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8973 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8974 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8975 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8976 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8977 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8978 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8979 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8980 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8981 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8982 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8983 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8984 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8985 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8986 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8987 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8988 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8989 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8990 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8991 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8992
8993 /* SPE load and stores */
8994 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8995 {
8996 target_ulong uimm = rB(ctx->opcode);
8997
8998 if (rA(ctx->opcode) == 0) {
8999 tcg_gen_movi_tl(EA, uimm << sh);
9000 } else {
9001 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9002 if (NARROW_MODE(ctx)) {
9003 tcg_gen_ext32u_tl(EA, EA);
9004 }
9005 }
9006 }
9007
9008 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9009 {
9010 TCGv_i64 t0 = tcg_temp_new_i64();
9011 gen_qemu_ld64(ctx, t0, addr);
9012 gen_store_gpr64(rD(ctx->opcode), t0);
9013 tcg_temp_free_i64(t0);
9014 }
9015
9016 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9017 {
9018 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9019 gen_addr_add(ctx, addr, addr, 4);
9020 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9021 }
9022
9023 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9024 {
9025 TCGv t0 = tcg_temp_new();
9026 gen_qemu_ld16u(ctx, t0, addr);
9027 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9028 gen_addr_add(ctx, addr, addr, 2);
9029 gen_qemu_ld16u(ctx, t0, addr);
9030 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9031 gen_addr_add(ctx, addr, addr, 2);
9032 gen_qemu_ld16u(ctx, t0, addr);
9033 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9034 gen_addr_add(ctx, addr, addr, 2);
9035 gen_qemu_ld16u(ctx, t0, addr);
9036 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9037 tcg_temp_free(t0);
9038 }
9039
9040 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9041 {
9042 TCGv t0 = tcg_temp_new();
9043 gen_qemu_ld16u(ctx, t0, addr);
9044 tcg_gen_shli_tl(t0, t0, 16);
9045 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9046 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9047 tcg_temp_free(t0);
9048 }
9049
9050 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9051 {
9052 TCGv t0 = tcg_temp_new();
9053 gen_qemu_ld16u(ctx, t0, addr);
9054 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9055 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9056 tcg_temp_free(t0);
9057 }
9058
9059 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9060 {
9061 TCGv t0 = tcg_temp_new();
9062 gen_qemu_ld16s(ctx, t0, addr);
9063 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9064 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9065 tcg_temp_free(t0);
9066 }
9067
9068 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9069 {
9070 TCGv t0 = tcg_temp_new();
9071 gen_qemu_ld16u(ctx, t0, addr);
9072 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9073 gen_addr_add(ctx, addr, addr, 2);
9074 gen_qemu_ld16u(ctx, t0, addr);
9075 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9076 tcg_temp_free(t0);
9077 }
9078
9079 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9080 {
9081 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9082 gen_addr_add(ctx, addr, addr, 2);
9083 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9084 }
9085
9086 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9087 {
9088 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9089 gen_addr_add(ctx, addr, addr, 2);
9090 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9091 }
9092
9093 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9094 {
9095 TCGv t0 = tcg_temp_new();
9096 gen_qemu_ld32u(ctx, t0, addr);
9097 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9098 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9099 tcg_temp_free(t0);
9100 }
9101
9102 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9103 {
9104 TCGv t0 = tcg_temp_new();
9105 gen_qemu_ld16u(ctx, t0, addr);
9106 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9107 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9108 gen_addr_add(ctx, addr, addr, 2);
9109 gen_qemu_ld16u(ctx, t0, addr);
9110 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9111 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9112 tcg_temp_free(t0);
9113 }
9114
9115 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9116 {
9117 TCGv_i64 t0 = tcg_temp_new_i64();
9118 gen_load_gpr64(t0, rS(ctx->opcode));
9119 gen_qemu_st64(ctx, t0, addr);
9120 tcg_temp_free_i64(t0);
9121 }
9122
9123 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9124 {
9125 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9126 gen_addr_add(ctx, addr, addr, 4);
9127 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9128 }
9129
9130 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9131 {
9132 TCGv t0 = tcg_temp_new();
9133 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9134 gen_qemu_st16(ctx, t0, addr);
9135 gen_addr_add(ctx, addr, addr, 2);
9136 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9137 gen_addr_add(ctx, addr, addr, 2);
9138 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9139 gen_qemu_st16(ctx, t0, addr);
9140 tcg_temp_free(t0);
9141 gen_addr_add(ctx, addr, addr, 2);
9142 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9143 }
9144
9145 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9146 {
9147 TCGv t0 = tcg_temp_new();
9148 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9149 gen_qemu_st16(ctx, t0, addr);
9150 gen_addr_add(ctx, addr, addr, 2);
9151 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9152 gen_qemu_st16(ctx, t0, addr);
9153 tcg_temp_free(t0);
9154 }
9155
9156 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9157 {
9158 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9159 gen_addr_add(ctx, addr, addr, 2);
9160 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9161 }
9162
9163 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9164 {
9165 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9166 }
9167
9168 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9169 {
9170 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9171 }
9172
9173 #define GEN_SPEOP_LDST(name, opc2, sh) \
9174 static void glue(gen_, name)(DisasContext *ctx) \
9175 { \
9176 TCGv t0; \
9177 if (unlikely(!ctx->spe_enabled)) { \
9178 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9179 return; \
9180 } \
9181 gen_set_access_type(ctx, ACCESS_INT); \
9182 t0 = tcg_temp_new(); \
9183 if (Rc(ctx->opcode)) { \
9184 gen_addr_spe_imm_index(ctx, t0, sh); \
9185 } else { \
9186 gen_addr_reg_index(ctx, t0); \
9187 } \
9188 gen_op_##name(ctx, t0); \
9189 tcg_temp_free(t0); \
9190 }
9191
9192 GEN_SPEOP_LDST(evldd, 0x00, 3);
9193 GEN_SPEOP_LDST(evldw, 0x01, 3);
9194 GEN_SPEOP_LDST(evldh, 0x02, 3);
9195 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9196 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9197 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9198 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9199 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9200 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9201 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9202 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9203
9204 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9205 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9206 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9207 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9208 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9209 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9210 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9211
9212 /* Multiply and add - TODO */
9213 #if 0
9214 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9215 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9216 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9217 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9218 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9219 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9220 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9221 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9222 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9223 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9224 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9225 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9226
9227 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9228 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9229 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9230 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9231 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9232 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9233 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9234 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9235 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9236 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9237 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9238 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9239
9240 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9241 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9242 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9243 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9244 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9245
9246 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9247 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9248 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9249 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9250 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9251 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9252 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9253 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9254 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9255 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9256 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9257 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9258
9259 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9260 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9261 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9262 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9263
9264 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9265 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9266 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9267 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9268 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9269 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9270 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9271 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9272 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9273 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276
9277 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9278 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9281 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282 #endif
9283
9284 /*** SPE floating-point extension ***/
9285 #define GEN_SPEFPUOP_CONV_32_32(name) \
9286 static inline void gen_##name(DisasContext *ctx) \
9287 { \
9288 TCGv_i32 t0 = tcg_temp_new_i32(); \
9289 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9290 gen_helper_##name(t0, cpu_env, t0); \
9291 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9292 tcg_temp_free_i32(t0); \
9293 }
9294 #define GEN_SPEFPUOP_CONV_32_64(name) \
9295 static inline void gen_##name(DisasContext *ctx) \
9296 { \
9297 TCGv_i64 t0 = tcg_temp_new_i64(); \
9298 TCGv_i32 t1 = tcg_temp_new_i32(); \
9299 gen_load_gpr64(t0, rB(ctx->opcode)); \
9300 gen_helper_##name(t1, cpu_env, t0); \
9301 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9302 tcg_temp_free_i64(t0); \
9303 tcg_temp_free_i32(t1); \
9304 }
9305 #define GEN_SPEFPUOP_CONV_64_32(name) \
9306 static inline void gen_##name(DisasContext *ctx) \
9307 { \
9308 TCGv_i64 t0 = tcg_temp_new_i64(); \
9309 TCGv_i32 t1 = tcg_temp_new_i32(); \
9310 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9311 gen_helper_##name(t0, cpu_env, t1); \
9312 gen_store_gpr64(rD(ctx->opcode), t0); \
9313 tcg_temp_free_i64(t0); \
9314 tcg_temp_free_i32(t1); \
9315 }
9316 #define GEN_SPEFPUOP_CONV_64_64(name) \
9317 static inline void gen_##name(DisasContext *ctx) \
9318 { \
9319 TCGv_i64 t0 = tcg_temp_new_i64(); \
9320 gen_load_gpr64(t0, rB(ctx->opcode)); \
9321 gen_helper_##name(t0, cpu_env, t0); \
9322 gen_store_gpr64(rD(ctx->opcode), t0); \
9323 tcg_temp_free_i64(t0); \
9324 }
9325 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9326 static inline void gen_##name(DisasContext *ctx) \
9327 { \
9328 TCGv_i32 t0, t1; \
9329 if (unlikely(!ctx->spe_enabled)) { \
9330 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9331 return; \
9332 } \
9333 t0 = tcg_temp_new_i32(); \
9334 t1 = tcg_temp_new_i32(); \
9335 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9336 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9337 gen_helper_##name(t0, cpu_env, t0, t1); \
9338 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9339 \
9340 tcg_temp_free_i32(t0); \
9341 tcg_temp_free_i32(t1); \
9342 }
9343 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9344 static inline void gen_##name(DisasContext *ctx) \
9345 { \
9346 TCGv_i64 t0, t1; \
9347 if (unlikely(!ctx->spe_enabled)) { \
9348 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9349 return; \
9350 } \
9351 t0 = tcg_temp_new_i64(); \
9352 t1 = tcg_temp_new_i64(); \
9353 gen_load_gpr64(t0, rA(ctx->opcode)); \
9354 gen_load_gpr64(t1, rB(ctx->opcode)); \
9355 gen_helper_##name(t0, cpu_env, t0, t1); \
9356 gen_store_gpr64(rD(ctx->opcode), t0); \
9357 tcg_temp_free_i64(t0); \
9358 tcg_temp_free_i64(t1); \
9359 }
9360 #define GEN_SPEFPUOP_COMP_32(name) \
9361 static inline void gen_##name(DisasContext *ctx) \
9362 { \
9363 TCGv_i32 t0, t1; \
9364 if (unlikely(!ctx->spe_enabled)) { \
9365 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9366 return; \
9367 } \
9368 t0 = tcg_temp_new_i32(); \
9369 t1 = tcg_temp_new_i32(); \
9370 \
9371 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9372 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9373 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9374 \
9375 tcg_temp_free_i32(t0); \
9376 tcg_temp_free_i32(t1); \
9377 }
9378 #define GEN_SPEFPUOP_COMP_64(name) \
9379 static inline void gen_##name(DisasContext *ctx) \
9380 { \
9381 TCGv_i64 t0, t1; \
9382 if (unlikely(!ctx->spe_enabled)) { \
9383 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9384 return; \
9385 } \
9386 t0 = tcg_temp_new_i64(); \
9387 t1 = tcg_temp_new_i64(); \
9388 gen_load_gpr64(t0, rA(ctx->opcode)); \
9389 gen_load_gpr64(t1, rB(ctx->opcode)); \
9390 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9391 tcg_temp_free_i64(t0); \
9392 tcg_temp_free_i64(t1); \
9393 }
9394
9395 /* Single precision floating-point vectors operations */
9396 /* Arithmetic */
9397 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9398 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9399 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9400 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9401 static inline void gen_evfsabs(DisasContext *ctx)
9402 {
9403 if (unlikely(!ctx->spe_enabled)) {
9404 gen_exception(ctx, POWERPC_EXCP_SPEU);
9405 return;
9406 }
9407 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9408 ~0x80000000);
9409 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9410 ~0x80000000);
9411 }
9412 static inline void gen_evfsnabs(DisasContext *ctx)
9413 {
9414 if (unlikely(!ctx->spe_enabled)) {
9415 gen_exception(ctx, POWERPC_EXCP_SPEU);
9416 return;
9417 }
9418 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9419 0x80000000);
9420 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9421 0x80000000);
9422 }
9423 static inline void gen_evfsneg(DisasContext *ctx)
9424 {
9425 if (unlikely(!ctx->spe_enabled)) {
9426 gen_exception(ctx, POWERPC_EXCP_SPEU);
9427 return;
9428 }
9429 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9430 0x80000000);
9431 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9432 0x80000000);
9433 }
9434
9435 /* Conversion */
9436 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9437 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9438 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9439 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9440 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9441 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9442 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9443 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9444 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9445 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9446
9447 /* Comparison */
9448 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9449 GEN_SPEFPUOP_COMP_64(evfscmplt);
9450 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9451 GEN_SPEFPUOP_COMP_64(evfststgt);
9452 GEN_SPEFPUOP_COMP_64(evfststlt);
9453 GEN_SPEFPUOP_COMP_64(evfststeq);
9454
9455 /* Opcodes definitions */
9456 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9457 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9458 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9459 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9460 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9461 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9462 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9463 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9464 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9465 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9466 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9467 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9468 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9469 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9470
9471 /* Single precision floating-point operations */
9472 /* Arithmetic */
9473 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9474 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9475 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9476 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9477 static inline void gen_efsabs(DisasContext *ctx)
9478 {
9479 if (unlikely(!ctx->spe_enabled)) {
9480 gen_exception(ctx, POWERPC_EXCP_SPEU);
9481 return;
9482 }
9483 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9484 }
9485 static inline void gen_efsnabs(DisasContext *ctx)
9486 {
9487 if (unlikely(!ctx->spe_enabled)) {
9488 gen_exception(ctx, POWERPC_EXCP_SPEU);
9489 return;
9490 }
9491 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9492 }
9493 static inline void gen_efsneg(DisasContext *ctx)
9494 {
9495 if (unlikely(!ctx->spe_enabled)) {
9496 gen_exception(ctx, POWERPC_EXCP_SPEU);
9497 return;
9498 }
9499 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9500 }
9501
9502 /* Conversion */
9503 GEN_SPEFPUOP_CONV_32_32(efscfui);
9504 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9505 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9506 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9507 GEN_SPEFPUOP_CONV_32_32(efsctui);
9508 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9509 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9510 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9511 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9512 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9513 GEN_SPEFPUOP_CONV_32_64(efscfd);
9514
9515 /* Comparison */
9516 GEN_SPEFPUOP_COMP_32(efscmpgt);
9517 GEN_SPEFPUOP_COMP_32(efscmplt);
9518 GEN_SPEFPUOP_COMP_32(efscmpeq);
9519 GEN_SPEFPUOP_COMP_32(efststgt);
9520 GEN_SPEFPUOP_COMP_32(efststlt);
9521 GEN_SPEFPUOP_COMP_32(efststeq);
9522
9523 /* Opcodes definitions */
9524 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9525 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9526 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9527 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9528 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9529 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9530 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9531 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9532 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9533 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9534 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9535 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9536 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9537 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9538
9539 /* Double precision floating-point operations */
9540 /* Arithmetic */
9541 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9542 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9543 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9544 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9545 static inline void gen_efdabs(DisasContext *ctx)
9546 {
9547 if (unlikely(!ctx->spe_enabled)) {
9548 gen_exception(ctx, POWERPC_EXCP_SPEU);
9549 return;
9550 }
9551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9552 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9553 ~0x80000000);
9554 }
9555 static inline void gen_efdnabs(DisasContext *ctx)
9556 {
9557 if (unlikely(!ctx->spe_enabled)) {
9558 gen_exception(ctx, POWERPC_EXCP_SPEU);
9559 return;
9560 }
9561 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9562 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9563 0x80000000);
9564 }
9565 static inline void gen_efdneg(DisasContext *ctx)
9566 {
9567 if (unlikely(!ctx->spe_enabled)) {
9568 gen_exception(ctx, POWERPC_EXCP_SPEU);
9569 return;
9570 }
9571 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9572 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9573 0x80000000);
9574 }
9575
9576 /* Conversion */
9577 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9578 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9579 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9580 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9581 GEN_SPEFPUOP_CONV_32_64(efdctui);
9582 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9583 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9584 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9585 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9586 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9587 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9588 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9589 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9590 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9591 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9592
9593 /* Comparison */
9594 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9595 GEN_SPEFPUOP_COMP_64(efdcmplt);
9596 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9597 GEN_SPEFPUOP_COMP_64(efdtstgt);
9598 GEN_SPEFPUOP_COMP_64(efdtstlt);
9599 GEN_SPEFPUOP_COMP_64(efdtsteq);
9600
9601 /* Opcodes definitions */
9602 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9603 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9604 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9605 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9606 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9607 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9608 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9609 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9610 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9611 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9612 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9613 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9614 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9615 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9616 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9617 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9618
9619 static opcode_t opcodes[] = {
9620 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9621 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9622 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9623 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9624 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9625 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9626 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9627 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9628 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9629 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9630 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9631 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9632 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9633 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9634 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9635 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9636 #if defined(TARGET_PPC64)
9637 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9638 #endif
9639 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9640 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9641 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9642 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9643 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9644 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9645 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9646 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9647 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9648 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9649 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9650 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9651 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9652 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9653 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9654 #if defined(TARGET_PPC64)
9655 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9656 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9657 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9658 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9659 #endif
9660 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9661 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9662 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9663 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9664 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9665 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9666 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9667 #if defined(TARGET_PPC64)
9668 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9669 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9670 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9671 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9672 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9673 #endif
9674 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9675 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9676 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9677 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9678 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9679 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9680 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9681 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9682 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9683 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9684 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9685 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9686 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9687 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9688 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9689 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9690 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9691 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9692 #if defined(TARGET_PPC64)
9693 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9694 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9695 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9696 #endif
9697 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9698 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9699 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9700 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9701 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9702 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9703 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9704 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9705 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9706 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9707 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9708 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9709 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9710 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9711 #if defined(TARGET_PPC64)
9712 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9713 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9714 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9715 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9716 #endif
9717 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9718 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9719 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9720 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9721 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9722 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9723 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9724 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9725 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9726 #if defined(TARGET_PPC64)
9727 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9728 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9729 #endif
9730 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9731 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9732 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9733 #if defined(TARGET_PPC64)
9734 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9735 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9736 #endif
9737 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9738 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9739 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9740 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9741 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9742 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9743 #if defined(TARGET_PPC64)
9744 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9745 #endif
9746 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9747 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9748 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9749 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9750 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9751 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9752 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9753 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9754 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9755 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9756 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9757 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9758 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9759 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9760 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9761 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9762 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9763 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9764 #if defined(TARGET_PPC64)
9765 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9766 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9767 PPC_SEGMENT_64B),
9768 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9769 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9770 PPC_SEGMENT_64B),
9771 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9772 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9773 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9774 #endif
9775 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9776 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9777 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9778 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9779 #if defined(TARGET_PPC64)
9780 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9781 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9782 #endif
9783 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9784 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9785 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9786 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9787 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9788 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9789 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9790 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9791 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9792 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9793 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9794 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9795 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9796 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9797 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9798 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9799 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9800 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9801 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9802 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9803 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9804 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9805 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9806 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9807 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9808 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9809 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9810 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9811 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9812 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9813 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9814 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9815 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9816 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9817 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9818 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9819 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9820 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9821 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9822 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9823 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9824 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9825 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9826 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9827 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9828 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9829 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9830 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9831 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9832 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9833 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9834 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9835 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9836 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9837 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9838 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9839 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9840 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9841 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9842 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9843 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9844 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9845 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9846 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9847 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9848 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9849 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9850 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9851 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9852 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9853 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9854 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9855 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9856 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9857 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9858 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9859 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9860 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9861 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9862 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9863 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9864 PPC_NONE, PPC2_BOOKE206),
9865 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9866 PPC_NONE, PPC2_BOOKE206),
9867 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9868 PPC_NONE, PPC2_BOOKE206),
9869 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9870 PPC_NONE, PPC2_BOOKE206),
9871 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9872 PPC_NONE, PPC2_BOOKE206),
9873 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9874 PPC_NONE, PPC2_PRCNTL),
9875 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9876 PPC_NONE, PPC2_PRCNTL),
9877 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9878 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9879 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9880 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9881 PPC_BOOKE, PPC2_BOOKE206),
9882 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9883 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9884 PPC_BOOKE, PPC2_BOOKE206),
9885 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9886 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9887 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9888 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9889 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9890 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9891 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9892 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9893 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9894
9895 #undef GEN_INT_ARITH_ADD
9896 #undef GEN_INT_ARITH_ADD_CONST
9897 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9898 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9899 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9900 add_ca, compute_ca, compute_ov) \
9901 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9902 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9903 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9904 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9905 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9906 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9907 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9908 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9909 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9910 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9911 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9912
9913 #undef GEN_INT_ARITH_DIVW
9914 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9915 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9916 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9917 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9918 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9919 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9920 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9921 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9922 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9923 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9924
9925 #if defined(TARGET_PPC64)
9926 #undef GEN_INT_ARITH_DIVD
9927 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9928 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9929 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9930 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9931 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9932 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9933
9934 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9935 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9936 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9937 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9938
9939 #undef GEN_INT_ARITH_MUL_HELPER
9940 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9941 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9942 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9943 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9944 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9945 #endif
9946
9947 #undef GEN_INT_ARITH_SUBF
9948 #undef GEN_INT_ARITH_SUBF_CONST
9949 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9950 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9951 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9952 add_ca, compute_ca, compute_ov) \
9953 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9954 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9955 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9956 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9957 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9958 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9959 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9960 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9961 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9962 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9963 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9964
9965 #undef GEN_LOGICAL1
9966 #undef GEN_LOGICAL2
9967 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9968 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9969 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9970 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9971 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9972 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9973 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9974 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9975 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9976 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9977 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9978 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9979 #if defined(TARGET_PPC64)
9980 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9981 #endif
9982
9983 #if defined(TARGET_PPC64)
9984 #undef GEN_PPC64_R2
9985 #undef GEN_PPC64_R4
9986 #define GEN_PPC64_R2(name, opc1, opc2) \
9987 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9988 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9989 PPC_64B)
9990 #define GEN_PPC64_R4(name, opc1, opc2) \
9991 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9992 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9993 PPC_64B), \
9994 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9995 PPC_64B), \
9996 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9997 PPC_64B)
9998 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9999 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10000 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10001 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10002 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10003 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10004 #endif
10005
10006 #undef _GEN_FLOAT_ACB
10007 #undef GEN_FLOAT_ACB
10008 #undef _GEN_FLOAT_AB
10009 #undef GEN_FLOAT_AB
10010 #undef _GEN_FLOAT_AC
10011 #undef GEN_FLOAT_AC
10012 #undef GEN_FLOAT_B
10013 #undef GEN_FLOAT_BS
10014 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10015 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10016 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10017 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10018 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10019 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10020 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10021 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10022 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10023 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10024 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10025 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10026 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10027 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10028 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10029 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10030 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10031 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10032 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10033
10034 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10035 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10036 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10037 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10038 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10039 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10040 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10041 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10042 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10043 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10044 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10045 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10046 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10047 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10048 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10049 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10050 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10051 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10052 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10053 #if defined(TARGET_PPC64)
10054 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10055 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10056 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10057 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10058 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10059 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10060 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10061 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10062 #endif
10063 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10064 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10065 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10066 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10067
10068 #undef GEN_LD
10069 #undef GEN_LDU
10070 #undef GEN_LDUX
10071 #undef GEN_LDX_E
10072 #undef GEN_LDS
10073 #define GEN_LD(name, ldop, opc, type) \
10074 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10075 #define GEN_LDU(name, ldop, opc, type) \
10076 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10077 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10078 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10079 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10080 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10081 #define GEN_LDS(name, ldop, op, type) \
10082 GEN_LD(name, ldop, op | 0x20, type) \
10083 GEN_LDU(name, ldop, op | 0x21, type) \
10084 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10085 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10086
10087 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10088 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10089 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10090 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10091 #if defined(TARGET_PPC64)
10092 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10093 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10094 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10095 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10096 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10097 #endif
10098 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10099 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10100
10101 #undef GEN_ST
10102 #undef GEN_STU
10103 #undef GEN_STUX
10104 #undef GEN_STX_E
10105 #undef GEN_STS
10106 #define GEN_ST(name, stop, opc, type) \
10107 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10108 #define GEN_STU(name, stop, opc, type) \
10109 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10110 #define GEN_STUX(name, stop, opc2, opc3, type) \
10111 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10112 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10113 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10114 #define GEN_STS(name, stop, op, type) \
10115 GEN_ST(name, stop, op | 0x20, type) \
10116 GEN_STU(name, stop, op | 0x21, type) \
10117 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10118 GEN_STX(name, stop, 0x17, op | 0x00, type)
10119
10120 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10121 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10122 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10123 #if defined(TARGET_PPC64)
10124 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10125 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10126 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10127 #endif
10128 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10129 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10130
10131 #undef GEN_LDF
10132 #undef GEN_LDUF
10133 #undef GEN_LDUXF
10134 #undef GEN_LDXF
10135 #undef GEN_LDFS
10136 #define GEN_LDF(name, ldop, opc, type) \
10137 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10138 #define GEN_LDUF(name, ldop, opc, type) \
10139 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10140 #define GEN_LDUXF(name, ldop, opc, type) \
10141 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10142 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10143 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10144 #define GEN_LDFS(name, ldop, op, type) \
10145 GEN_LDF(name, ldop, op | 0x20, type) \
10146 GEN_LDUF(name, ldop, op | 0x21, type) \
10147 GEN_LDUXF(name, ldop, op | 0x01, type) \
10148 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10149
10150 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10151 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10152 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10153 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10154 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10155 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10156
10157 #undef GEN_STF
10158 #undef GEN_STUF
10159 #undef GEN_STUXF
10160 #undef GEN_STXF
10161 #undef GEN_STFS
10162 #define GEN_STF(name, stop, opc, type) \
10163 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10164 #define GEN_STUF(name, stop, opc, type) \
10165 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10166 #define GEN_STUXF(name, stop, opc, type) \
10167 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10168 #define GEN_STXF(name, stop, opc2, opc3, type) \
10169 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10170 #define GEN_STFS(name, stop, op, type) \
10171 GEN_STF(name, stop, op | 0x20, type) \
10172 GEN_STUF(name, stop, op | 0x21, type) \
10173 GEN_STUXF(name, stop, op | 0x01, type) \
10174 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10175
10176 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10177 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10178 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10179 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10180 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10181
10182 #undef GEN_CRLOGIC
10183 #define GEN_CRLOGIC(name, tcg_op, opc) \
10184 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10185 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10186 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10187 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10188 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10189 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10190 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10191 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10192 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10193
10194 #undef GEN_MAC_HANDLER
10195 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10196 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10197 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10198 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10199 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10200 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10201 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10202 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10203 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10204 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10205 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10206 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10207 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10208 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10209 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10210 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10211 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10212 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10213 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10214 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10215 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10216 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10217 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10218 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10219 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10220 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10221 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10222 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10223 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10224 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10225 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10226 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10227 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10228 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10229 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10230 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10231 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10232 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10233 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10234 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10235 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10236 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10237 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10238 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10239
10240 #undef GEN_VR_LDX
10241 #undef GEN_VR_STX
10242 #undef GEN_VR_LVE
10243 #undef GEN_VR_STVE
10244 #define GEN_VR_LDX(name, opc2, opc3) \
10245 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10246 #define GEN_VR_STX(name, opc2, opc3) \
10247 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10248 #define GEN_VR_LVE(name, opc2, opc3) \
10249 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10250 #define GEN_VR_STVE(name, opc2, opc3) \
10251 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10252 GEN_VR_LDX(lvx, 0x07, 0x03),
10253 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10254 GEN_VR_LVE(bx, 0x07, 0x00),
10255 GEN_VR_LVE(hx, 0x07, 0x01),
10256 GEN_VR_LVE(wx, 0x07, 0x02),
10257 GEN_VR_STX(svx, 0x07, 0x07),
10258 GEN_VR_STX(svxl, 0x07, 0x0F),
10259 GEN_VR_STVE(bx, 0x07, 0x04),
10260 GEN_VR_STVE(hx, 0x07, 0x05),
10261 GEN_VR_STVE(wx, 0x07, 0x06),
10262
10263 #undef GEN_VX_LOGICAL
10264 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10265 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10266
10267 #undef GEN_VX_LOGICAL_207
10268 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10269 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10270
10271 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10272 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10273 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10274 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10275 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10276 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10277 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10278 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10279
10280 #undef GEN_VXFORM
10281 #define GEN_VXFORM(name, opc2, opc3) \
10282 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10283
10284 #undef GEN_VXFORM_207
10285 #define GEN_VXFORM_207(name, opc2, opc3) \
10286 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10287
10288 #undef GEN_VXFORM_DUAL
10289 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10290 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10291
10292 #undef GEN_VXRFORM_DUAL
10293 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10294 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10295 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10296
10297 GEN_VXFORM(vaddubm, 0, 0),
10298 GEN_VXFORM(vadduhm, 0, 1),
10299 GEN_VXFORM(vadduwm, 0, 2),
10300 GEN_VXFORM_207(vaddudm, 0, 3),
10301 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10302 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10303 GEN_VXFORM(vsubuwm, 0, 18),
10304 GEN_VXFORM_207(vsubudm, 0, 19),
10305 GEN_VXFORM(vmaxub, 1, 0),
10306 GEN_VXFORM(vmaxuh, 1, 1),
10307 GEN_VXFORM(vmaxuw, 1, 2),
10308 GEN_VXFORM_207(vmaxud, 1, 3),
10309 GEN_VXFORM(vmaxsb, 1, 4),
10310 GEN_VXFORM(vmaxsh, 1, 5),
10311 GEN_VXFORM(vmaxsw, 1, 6),
10312 GEN_VXFORM_207(vmaxsd, 1, 7),
10313 GEN_VXFORM(vminub, 1, 8),
10314 GEN_VXFORM(vminuh, 1, 9),
10315 GEN_VXFORM(vminuw, 1, 10),
10316 GEN_VXFORM_207(vminud, 1, 11),
10317 GEN_VXFORM(vminsb, 1, 12),
10318 GEN_VXFORM(vminsh, 1, 13),
10319 GEN_VXFORM(vminsw, 1, 14),
10320 GEN_VXFORM_207(vminsd, 1, 15),
10321 GEN_VXFORM(vavgub, 1, 16),
10322 GEN_VXFORM(vavguh, 1, 17),
10323 GEN_VXFORM(vavguw, 1, 18),
10324 GEN_VXFORM(vavgsb, 1, 20),
10325 GEN_VXFORM(vavgsh, 1, 21),
10326 GEN_VXFORM(vavgsw, 1, 22),
10327 GEN_VXFORM(vmrghb, 6, 0),
10328 GEN_VXFORM(vmrghh, 6, 1),
10329 GEN_VXFORM(vmrghw, 6, 2),
10330 GEN_VXFORM(vmrglb, 6, 4),
10331 GEN_VXFORM(vmrglh, 6, 5),
10332 GEN_VXFORM(vmrglw, 6, 6),
10333 GEN_VXFORM_207(vmrgew, 6, 30),
10334 GEN_VXFORM_207(vmrgow, 6, 26),
10335 GEN_VXFORM(vmuloub, 4, 0),
10336 GEN_VXFORM(vmulouh, 4, 1),
10337 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10338 GEN_VXFORM(vmulosb, 4, 4),
10339 GEN_VXFORM(vmulosh, 4, 5),
10340 GEN_VXFORM_207(vmulosw, 4, 6),
10341 GEN_VXFORM(vmuleub, 4, 8),
10342 GEN_VXFORM(vmuleuh, 4, 9),
10343 GEN_VXFORM_207(vmuleuw, 4, 10),
10344 GEN_VXFORM(vmulesb, 4, 12),
10345 GEN_VXFORM(vmulesh, 4, 13),
10346 GEN_VXFORM_207(vmulesw, 4, 14),
10347 GEN_VXFORM(vslb, 2, 4),
10348 GEN_VXFORM(vslh, 2, 5),
10349 GEN_VXFORM(vslw, 2, 6),
10350 GEN_VXFORM_207(vsld, 2, 23),
10351 GEN_VXFORM(vsrb, 2, 8),
10352 GEN_VXFORM(vsrh, 2, 9),
10353 GEN_VXFORM(vsrw, 2, 10),
10354 GEN_VXFORM_207(vsrd, 2, 27),
10355 GEN_VXFORM(vsrab, 2, 12),
10356 GEN_VXFORM(vsrah, 2, 13),
10357 GEN_VXFORM(vsraw, 2, 14),
10358 GEN_VXFORM_207(vsrad, 2, 15),
10359 GEN_VXFORM(vslo, 6, 16),
10360 GEN_VXFORM(vsro, 6, 17),
10361 GEN_VXFORM(vaddcuw, 0, 6),
10362 GEN_VXFORM(vsubcuw, 0, 22),
10363 GEN_VXFORM(vaddubs, 0, 8),
10364 GEN_VXFORM(vadduhs, 0, 9),
10365 GEN_VXFORM(vadduws, 0, 10),
10366 GEN_VXFORM(vaddsbs, 0, 12),
10367 GEN_VXFORM(vaddshs, 0, 13),
10368 GEN_VXFORM(vaddsws, 0, 14),
10369 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10370 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10371 GEN_VXFORM(vsubuws, 0, 26),
10372 GEN_VXFORM(vsubsbs, 0, 28),
10373 GEN_VXFORM(vsubshs, 0, 29),
10374 GEN_VXFORM(vsubsws, 0, 30),
10375 GEN_VXFORM_207(vadduqm, 0, 4),
10376 GEN_VXFORM_207(vaddcuq, 0, 5),
10377 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10378 GEN_VXFORM_207(vsubuqm, 0, 20),
10379 GEN_VXFORM_207(vsubcuq, 0, 21),
10380 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10381 GEN_VXFORM(vrlb, 2, 0),
10382 GEN_VXFORM(vrlh, 2, 1),
10383 GEN_VXFORM(vrlw, 2, 2),
10384 GEN_VXFORM_207(vrld, 2, 3),
10385 GEN_VXFORM(vsl, 2, 7),
10386 GEN_VXFORM(vsr, 2, 11),
10387 GEN_VXFORM(vpkuhum, 7, 0),
10388 GEN_VXFORM(vpkuwum, 7, 1),
10389 GEN_VXFORM_207(vpkudum, 7, 17),
10390 GEN_VXFORM(vpkuhus, 7, 2),
10391 GEN_VXFORM(vpkuwus, 7, 3),
10392 GEN_VXFORM_207(vpkudus, 7, 19),
10393 GEN_VXFORM(vpkshus, 7, 4),
10394 GEN_VXFORM(vpkswus, 7, 5),
10395 GEN_VXFORM_207(vpksdus, 7, 21),
10396 GEN_VXFORM(vpkshss, 7, 6),
10397 GEN_VXFORM(vpkswss, 7, 7),
10398 GEN_VXFORM_207(vpksdss, 7, 23),
10399 GEN_VXFORM(vpkpx, 7, 12),
10400 GEN_VXFORM(vsum4ubs, 4, 24),
10401 GEN_VXFORM(vsum4sbs, 4, 28),
10402 GEN_VXFORM(vsum4shs, 4, 25),
10403 GEN_VXFORM(vsum2sws, 4, 26),
10404 GEN_VXFORM(vsumsws, 4, 30),
10405 GEN_VXFORM(vaddfp, 5, 0),
10406 GEN_VXFORM(vsubfp, 5, 1),
10407 GEN_VXFORM(vmaxfp, 5, 16),
10408 GEN_VXFORM(vminfp, 5, 17),
10409
10410 #undef GEN_VXRFORM1
10411 #undef GEN_VXRFORM
10412 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10413 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10414 #define GEN_VXRFORM(name, opc2, opc3) \
10415 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10416 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10417 GEN_VXRFORM(vcmpequb, 3, 0)
10418 GEN_VXRFORM(vcmpequh, 3, 1)
10419 GEN_VXRFORM(vcmpequw, 3, 2)
10420 GEN_VXRFORM(vcmpgtsb, 3, 12)
10421 GEN_VXRFORM(vcmpgtsh, 3, 13)
10422 GEN_VXRFORM(vcmpgtsw, 3, 14)
10423 GEN_VXRFORM(vcmpgtub, 3, 8)
10424 GEN_VXRFORM(vcmpgtuh, 3, 9)
10425 GEN_VXRFORM(vcmpgtuw, 3, 10)
10426 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10427 GEN_VXRFORM(vcmpgefp, 3, 7)
10428 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10429 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10430
10431 #undef GEN_VXFORM_SIMM
10432 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10433 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10434 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10435 GEN_VXFORM_SIMM(vspltish, 6, 13),
10436 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10437
10438 #undef GEN_VXFORM_NOA
10439 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10440 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10441 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10442 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10443 GEN_VXFORM_207(vupkhsw, 7, 25),
10444 GEN_VXFORM_NOA(vupklsb, 7, 10),
10445 GEN_VXFORM_NOA(vupklsh, 7, 11),
10446 GEN_VXFORM_207(vupklsw, 7, 27),
10447 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10448 GEN_VXFORM_NOA(vupklpx, 7, 15),
10449 GEN_VXFORM_NOA(vrefp, 5, 4),
10450 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10451 GEN_VXFORM_NOA(vexptefp, 5, 6),
10452 GEN_VXFORM_NOA(vlogefp, 5, 7),
10453 GEN_VXFORM_NOA(vrfim, 5, 8),
10454 GEN_VXFORM_NOA(vrfin, 5, 9),
10455 GEN_VXFORM_NOA(vrfip, 5, 10),
10456 GEN_VXFORM_NOA(vrfiz, 5, 11),
10457
10458 #undef GEN_VXFORM_UIMM
10459 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10460 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10461 GEN_VXFORM_UIMM(vspltb, 6, 8),
10462 GEN_VXFORM_UIMM(vsplth, 6, 9),
10463 GEN_VXFORM_UIMM(vspltw, 6, 10),
10464 GEN_VXFORM_UIMM(vcfux, 5, 12),
10465 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10466 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10467 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10468
10469 #undef GEN_VAFORM_PAIRED
10470 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10471 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10472 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10473 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10474 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10475 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10476 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10477 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10478
10479 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10480 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10481 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10482 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10483
10484 GEN_VXFORM_207(vbpermq, 6, 21),
10485 GEN_VXFORM_207(vgbbd, 6, 20),
10486 GEN_VXFORM_207(vpmsumb, 4, 16),
10487 GEN_VXFORM_207(vpmsumh, 4, 17),
10488 GEN_VXFORM_207(vpmsumw, 4, 18),
10489 GEN_VXFORM_207(vpmsumd, 4, 19),
10490
10491 GEN_VXFORM_207(vsbox, 4, 23),
10492
10493 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10494 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10495
10496 GEN_VXFORM_207(vshasigmaw, 1, 26),
10497 GEN_VXFORM_207(vshasigmad, 1, 27),
10498
10499 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10500
10501 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10502 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10503 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10504 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10505 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10506 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10507 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10508
10509 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10510 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10511 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10512 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10513 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10514
10515 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10516 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10517 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10518 #if defined(TARGET_PPC64)
10519 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10520 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10521 #endif
10522
10523 #undef GEN_XX2FORM
10524 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10525 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10526 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10527
10528 #undef GEN_XX3FORM
10529 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10530 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10531 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10532 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10533 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10534
10535 #undef GEN_XX3_RC_FORM
10536 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10537 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10538 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10539 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10540 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10541 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10542 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10543 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10544 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10545
10546 #undef GEN_XX3FORM_DM
10547 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10548 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10549 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10550 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10551 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10552 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10553 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10554 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10555 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10556 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10557 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10558 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10559 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10560 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10561 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10562 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10563 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10564
10565 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10566 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10567 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10568 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10569
10570 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10571 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10572 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10573 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10574 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10575 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10576 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10577 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10578
10579 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10580 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10581 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10582 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10583 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10584 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10585 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10586 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10587 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10588 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10589 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10590 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10591 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10592 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10593 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10594 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10595 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10596 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10597 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10598 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10599 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10600 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10601 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10602 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10603 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10604 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10605 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10606 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10607 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10608 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10609 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10610 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10611 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10612 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10613 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10614 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10615
10616 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10617 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10618 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10619 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10620 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10621 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10622 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10623 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10624 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10625 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10626 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10627 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10628 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10629 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10630 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10631 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10632 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10633 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10634
10635 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10636 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10637 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10638 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10639 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10640 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10641 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10642 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10643 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10644 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10645 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10646 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10647 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10648 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10649 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10650 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10651 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10652 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10653 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10654 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10655 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10656 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10657 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10658 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10659 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10660 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10661 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10662 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10663 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10664 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10665 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10666 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10667 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10668 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10669 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10670 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10671
10672 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10673 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10674 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10675 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10676 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10677 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10678 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10679 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10680 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10681 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10682 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10683 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10684 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10685 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10686 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10687 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10688 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10689 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10690 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10691 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10692 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10693 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10694 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10695 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10696 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10697 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10698 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10699 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10700 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10701 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10702 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10703 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10704 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10705 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10706 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10707 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10708
10709 #undef VSX_LOGICAL
10710 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10711 GEN_XX3FORM(name, opc2, opc3, fl2)
10712
10713 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10714 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10715 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10716 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10717 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10718 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10719 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10720 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10721 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10722 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10723 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10724 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10725
10726 #define GEN_XXSEL_ROW(opc3) \
10727 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10728 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10729 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10730 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10731 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10732 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10733 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10734 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10735
10736 GEN_XXSEL_ROW(0x00)
10737 GEN_XXSEL_ROW(0x01)
10738 GEN_XXSEL_ROW(0x02)
10739 GEN_XXSEL_ROW(0x03)
10740 GEN_XXSEL_ROW(0x04)
10741 GEN_XXSEL_ROW(0x05)
10742 GEN_XXSEL_ROW(0x06)
10743 GEN_XXSEL_ROW(0x07)
10744 GEN_XXSEL_ROW(0x08)
10745 GEN_XXSEL_ROW(0x09)
10746 GEN_XXSEL_ROW(0x0A)
10747 GEN_XXSEL_ROW(0x0B)
10748 GEN_XXSEL_ROW(0x0C)
10749 GEN_XXSEL_ROW(0x0D)
10750 GEN_XXSEL_ROW(0x0E)
10751 GEN_XXSEL_ROW(0x0F)
10752 GEN_XXSEL_ROW(0x10)
10753 GEN_XXSEL_ROW(0x11)
10754 GEN_XXSEL_ROW(0x12)
10755 GEN_XXSEL_ROW(0x13)
10756 GEN_XXSEL_ROW(0x14)
10757 GEN_XXSEL_ROW(0x15)
10758 GEN_XXSEL_ROW(0x16)
10759 GEN_XXSEL_ROW(0x17)
10760 GEN_XXSEL_ROW(0x18)
10761 GEN_XXSEL_ROW(0x19)
10762 GEN_XXSEL_ROW(0x1A)
10763 GEN_XXSEL_ROW(0x1B)
10764 GEN_XXSEL_ROW(0x1C)
10765 GEN_XXSEL_ROW(0x1D)
10766 GEN_XXSEL_ROW(0x1E)
10767 GEN_XXSEL_ROW(0x1F)
10768
10769 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10770
10771 #undef GEN_DFP_T_A_B_Rc
10772 #undef GEN_DFP_BF_A_B
10773 #undef GEN_DFP_BF_A_DCM
10774 #undef GEN_DFP_T_B_U32_U32_Rc
10775 #undef GEN_DFP_T_A_B_I32_Rc
10776 #undef GEN_DFP_T_B_Rc
10777 #undef GEN_DFP_T_FPR_I32_Rc
10778
10779 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10780 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10781
10782 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10783 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10784 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10785
10786 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10787 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10788 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10789 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10790 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10791
10792 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10793 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10794
10795 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10796 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10797 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10798
10799 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10800 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10801 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10802 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10803 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10804
10805 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10806 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10807
10808 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10809 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10810
10811 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10812 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10813
10814 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10815 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10816
10817 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10818 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10819
10820 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10821 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10822
10823 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10824 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10825
10826 #define GEN_DFP_BF_A_B(name, op1, op2) \
10827 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10828
10829 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10830 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10831
10832 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10833 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10834
10835 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10836 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10837
10838 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10839 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10840
10841 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10842 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10843
10844 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10845 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10846
10847 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10848 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10849
10850 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10851 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10852
10853 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10854 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10855
10856 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10857 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10858
10859 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10860 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10861
10862 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10863 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10864
10865 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10866 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10867
10868 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10869 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10870
10871 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10872 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10873
10874 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10875 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10876
10877 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10878 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10879
10880 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10881 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10882 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10883 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10884 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10885 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10886 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10887 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10888 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10889 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10890 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10891 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10892 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10893 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10894 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10895 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10896 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10897 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10898 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10899 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10900 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10901 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10902 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10903 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10904 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10905 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10906 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10907 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10908 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10909 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10910 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10911 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10912 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10913 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10914 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10915 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10916 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10917 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10918 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10919 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10920 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10921 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10922 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10923 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10924 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10925 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10926 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10927 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10928 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10929 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10930
10931 #undef GEN_SPE
10932 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10933 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10934 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10935 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10936 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10937 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10938 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10939 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10940 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10941 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10942 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10943 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10944 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10945 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10946 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10947 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10948 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10949 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10950 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10951 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10952 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10953 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10954 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10955 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10956 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10957 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10958 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10959 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10960 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10961 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10962 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10963
10964 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10965 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10966 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10967 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10968 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10969 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10970 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10971 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10972 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10973 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10974 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10975 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10976 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10977 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10978
10979 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10980 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10981 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10982 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10983 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10984 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10985 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10986 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10987 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10988 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10989 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10990 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10991 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10992 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10993
10994 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10995 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10996 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10997 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10998 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10999 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11000 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11001 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11002 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11003 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11004 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11005 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11006 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11007 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11008 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11009 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11010
11011 #undef GEN_SPEOP_LDST
11012 #define GEN_SPEOP_LDST(name, opc2, sh) \
11013 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11014 GEN_SPEOP_LDST(evldd, 0x00, 3),
11015 GEN_SPEOP_LDST(evldw, 0x01, 3),
11016 GEN_SPEOP_LDST(evldh, 0x02, 3),
11017 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11018 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11019 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11020 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11021 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11022 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11023 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11024 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11025
11026 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11027 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11028 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11029 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11030 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11031 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11032 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11033 };
11034
11035 #include "helper_regs.h"
11036 #include "translate_init.c"
11037
11038 /*****************************************************************************/
11039 /* Misc PowerPC helpers */
11040 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11041 int flags)
11042 {
11043 #define RGPL 4
11044 #define RFPL 4
11045
11046 PowerPCCPU *cpu = POWERPC_CPU(cs);
11047 CPUPPCState *env = &cpu->env;
11048 int i;
11049
11050 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11051 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11052 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11053 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11054 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11055 env->hflags, env->mmu_idx);
11056 #if !defined(NO_TIMER_DUMP)
11057 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11058 #if !defined(CONFIG_USER_ONLY)
11059 " DECR %08" PRIu32
11060 #endif
11061 "\n",
11062 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11063 #if !defined(CONFIG_USER_ONLY)
11064 , cpu_ppc_load_decr(env)
11065 #endif
11066 );
11067 #endif
11068 for (i = 0; i < 32; i++) {
11069 if ((i & (RGPL - 1)) == 0)
11070 cpu_fprintf(f, "GPR%02d", i);
11071 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11072 if ((i & (RGPL - 1)) == (RGPL - 1))
11073 cpu_fprintf(f, "\n");
11074 }
11075 cpu_fprintf(f, "CR ");
11076 for (i = 0; i < 8; i++)
11077 cpu_fprintf(f, "%01x", env->crf[i]);
11078 cpu_fprintf(f, " [");
11079 for (i = 0; i < 8; i++) {
11080 char a = '-';
11081 if (env->crf[i] & 0x08)
11082 a = 'L';
11083 else if (env->crf[i] & 0x04)
11084 a = 'G';
11085 else if (env->crf[i] & 0x02)
11086 a = 'E';
11087 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11088 }
11089 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11090 env->reserve_addr);
11091 for (i = 0; i < 32; i++) {
11092 if ((i & (RFPL - 1)) == 0)
11093 cpu_fprintf(f, "FPR%02d", i);
11094 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11095 if ((i & (RFPL - 1)) == (RFPL - 1))
11096 cpu_fprintf(f, "\n");
11097 }
11098 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11099 #if !defined(CONFIG_USER_ONLY)
11100 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11101 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11102 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11103 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11104
11105 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11106 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11107 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11108 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11109
11110 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11111 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11112 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11113 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11114
11115 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11116 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11117 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11118 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11119 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11120
11121 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11122 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11123 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11124 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11125
11126 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11127 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11128 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11129 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11130
11131 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11132 " EPR " TARGET_FMT_lx "\n",
11133 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11134 env->spr[SPR_BOOKE_EPR]);
11135
11136 /* FSL-specific */
11137 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11138 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11139 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11140 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11141
11142 /*
11143 * IVORs are left out as they are large and do not change often --
11144 * they can be read with "p $ivor0", "p $ivor1", etc.
11145 */
11146 }
11147
11148 #if defined(TARGET_PPC64)
11149 if (env->flags & POWERPC_FLAG_CFAR) {
11150 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11151 }
11152 #endif
11153
11154 switch (env->mmu_model) {
11155 case POWERPC_MMU_32B:
11156 case POWERPC_MMU_601:
11157 case POWERPC_MMU_SOFT_6xx:
11158 case POWERPC_MMU_SOFT_74xx:
11159 #if defined(TARGET_PPC64)
11160 case POWERPC_MMU_64B:
11161 case POWERPC_MMU_2_06:
11162 case POWERPC_MMU_2_06a:
11163 case POWERPC_MMU_2_06d:
11164 #endif
11165 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11166 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11167 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11168 break;
11169 case POWERPC_MMU_BOOKE206:
11170 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11171 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11172 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11173 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11174
11175 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11176 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11177 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11178 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11179
11180 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11181 " TLB1CFG " TARGET_FMT_lx "\n",
11182 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11183 env->spr[SPR_BOOKE_TLB1CFG]);
11184 break;
11185 default:
11186 break;
11187 }
11188 #endif
11189
11190 #undef RGPL
11191 #undef RFPL
11192 }
11193
11194 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11195 fprintf_function cpu_fprintf, int flags)
11196 {
11197 #if defined(DO_PPC_STATISTICS)
11198 PowerPCCPU *cpu = POWERPC_CPU(cs);
11199 opc_handler_t **t1, **t2, **t3, *handler;
11200 int op1, op2, op3;
11201
11202 t1 = cpu->env.opcodes;
11203 for (op1 = 0; op1 < 64; op1++) {
11204 handler = t1[op1];
11205 if (is_indirect_opcode(handler)) {
11206 t2 = ind_table(handler);
11207 for (op2 = 0; op2 < 32; op2++) {
11208 handler = t2[op2];
11209 if (is_indirect_opcode(handler)) {
11210 t3 = ind_table(handler);
11211 for (op3 = 0; op3 < 32; op3++) {
11212 handler = t3[op3];
11213 if (handler->count == 0)
11214 continue;
11215 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11216 "%016" PRIx64 " %" PRId64 "\n",
11217 op1, op2, op3, op1, (op3 << 5) | op2,
11218 handler->oname,
11219 handler->count, handler->count);
11220 }
11221 } else {
11222 if (handler->count == 0)
11223 continue;
11224 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11225 "%016" PRIx64 " %" PRId64 "\n",
11226 op1, op2, op1, op2, handler->oname,
11227 handler->count, handler->count);
11228 }
11229 }
11230 } else {
11231 if (handler->count == 0)
11232 continue;
11233 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11234 " %" PRId64 "\n",
11235 op1, op1, handler->oname,
11236 handler->count, handler->count);
11237 }
11238 }
11239 #endif
11240 }
11241
11242 /*****************************************************************************/
11243 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11244 TranslationBlock *tb,
11245 bool search_pc)
11246 {
11247 CPUState *cs = CPU(cpu);
11248 CPUPPCState *env = &cpu->env;
11249 DisasContext ctx, *ctxp = &ctx;
11250 opc_handler_t **table, *handler;
11251 target_ulong pc_start;
11252 uint16_t *gen_opc_end;
11253 CPUBreakpoint *bp;
11254 int j, lj = -1;
11255 int num_insns;
11256 int max_insns;
11257
11258 pc_start = tb->pc;
11259 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11260 ctx.nip = pc_start;
11261 ctx.tb = tb;
11262 ctx.exception = POWERPC_EXCP_NONE;
11263 ctx.spr_cb = env->spr_cb;
11264 ctx.mem_idx = env->mmu_idx;
11265 ctx.insns_flags = env->insns_flags;
11266 ctx.insns_flags2 = env->insns_flags2;
11267 ctx.access_type = -1;
11268 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11269 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11270 #if defined(TARGET_PPC64)
11271 ctx.sf_mode = msr_is_64bit(env, env->msr);
11272 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11273 #endif
11274 ctx.fpu_enabled = msr_fp;
11275 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11276 ctx.spe_enabled = msr_spe;
11277 else
11278 ctx.spe_enabled = 0;
11279 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11280 ctx.altivec_enabled = msr_vr;
11281 else
11282 ctx.altivec_enabled = 0;
11283 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11284 ctx.vsx_enabled = msr_vsx;
11285 } else {
11286 ctx.vsx_enabled = 0;
11287 }
11288 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11289 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11290 else
11291 ctx.singlestep_enabled = 0;
11292 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11293 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11294 if (unlikely(cs->singlestep_enabled)) {
11295 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11296 }
11297 #if defined (DO_SINGLE_STEP) && 0
11298 /* Single step trace mode */
11299 msr_se = 1;
11300 #endif
11301 num_insns = 0;
11302 max_insns = tb->cflags & CF_COUNT_MASK;
11303 if (max_insns == 0)
11304 max_insns = CF_COUNT_MASK;
11305
11306 gen_tb_start();
11307 tcg_clear_temp_count();
11308 /* Set env in case of segfault during code fetch */
11309 while (ctx.exception == POWERPC_EXCP_NONE
11310 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11311 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11312 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11313 if (bp->pc == ctx.nip) {
11314 gen_debug_exception(ctxp);
11315 break;
11316 }
11317 }
11318 }
11319 if (unlikely(search_pc)) {
11320 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11321 if (lj < j) {
11322 lj++;
11323 while (lj < j)
11324 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11325 }
11326 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11327 tcg_ctx.gen_opc_instr_start[lj] = 1;
11328 tcg_ctx.gen_opc_icount[lj] = num_insns;
11329 }
11330 LOG_DISAS("----------------\n");
11331 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11332 ctx.nip, ctx.mem_idx, (int)msr_ir);
11333 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11334 gen_io_start();
11335 if (unlikely(need_byteswap(&ctx))) {
11336 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11337 } else {
11338 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11339 }
11340 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11341 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11342 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11343 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11344 tcg_gen_debug_insn_start(ctx.nip);
11345 }
11346 ctx.nip += 4;
11347 table = env->opcodes;
11348 num_insns++;
11349 handler = table[opc1(ctx.opcode)];
11350 if (is_indirect_opcode(handler)) {
11351 table = ind_table(handler);
11352 handler = table[opc2(ctx.opcode)];
11353 if (is_indirect_opcode(handler)) {
11354 table = ind_table(handler);
11355 handler = table[opc3(ctx.opcode)];
11356 }
11357 }
11358 /* Is opcode *REALLY* valid ? */
11359 if (unlikely(handler->handler == &gen_invalid)) {
11360 if (qemu_log_enabled()) {
11361 qemu_log("invalid/unsupported opcode: "
11362 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11363 opc1(ctx.opcode), opc2(ctx.opcode),
11364 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11365 }
11366 } else {
11367 uint32_t inval;
11368
11369 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11370 inval = handler->inval2;
11371 } else {
11372 inval = handler->inval1;
11373 }
11374
11375 if (unlikely((ctx.opcode & inval) != 0)) {
11376 if (qemu_log_enabled()) {
11377 qemu_log("invalid bits: %08x for opcode: "
11378 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11379 ctx.opcode & inval, opc1(ctx.opcode),
11380 opc2(ctx.opcode), opc3(ctx.opcode),
11381 ctx.opcode, ctx.nip - 4);
11382 }
11383 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11384 break;
11385 }
11386 }
11387 (*(handler->handler))(&ctx);
11388 #if defined(DO_PPC_STATISTICS)
11389 handler->count++;
11390 #endif
11391 /* Check trace mode exceptions */
11392 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11393 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11394 ctx.exception != POWERPC_SYSCALL &&
11395 ctx.exception != POWERPC_EXCP_TRAP &&
11396 ctx.exception != POWERPC_EXCP_BRANCH)) {
11397 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11398 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11399 (cs->singlestep_enabled) ||
11400 singlestep ||
11401 num_insns >= max_insns)) {
11402 /* if we reach a page boundary or are single stepping, stop
11403 * generation
11404 */
11405 break;
11406 }
11407 if (tcg_check_temp_count()) {
11408 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11409 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11410 ctx.opcode);
11411 exit(1);
11412 }
11413 }
11414 if (tb->cflags & CF_LAST_IO)
11415 gen_io_end();
11416 if (ctx.exception == POWERPC_EXCP_NONE) {
11417 gen_goto_tb(&ctx, 0, ctx.nip);
11418 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11419 if (unlikely(cs->singlestep_enabled)) {
11420 gen_debug_exception(ctxp);
11421 }
11422 /* Generate the return instruction */
11423 tcg_gen_exit_tb(0);
11424 }
11425 gen_tb_end(tb, num_insns);
11426 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11427 if (unlikely(search_pc)) {
11428 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11429 lj++;
11430 while (lj <= j)
11431 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11432 } else {
11433 tb->size = ctx.nip - pc_start;
11434 tb->icount = num_insns;
11435 }
11436 #if defined(DEBUG_DISAS)
11437 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11438 int flags;
11439 flags = env->bfd_mach;
11440 flags |= ctx.le_mode << 16;
11441 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11442 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11443 qemu_log("\n");
11444 }
11445 #endif
11446 }
11447
11448 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11449 {
11450 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11451 }
11452
11453 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11454 {
11455 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11456 }
11457
11458 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11459 {
11460 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11461 }
AR7 emulation for QEMU