1 #if !defined (__MIPS_CPU_H__)
8 #define ELF_MACHINE EM_MIPS
10 #define CPUArchState struct CPUMIPSState
13 #include "qemu-common.h"
14 #include "mips-defs.h"
15 #include "exec/cpu-defs.h"
16 #include "fpu/softfloat.h"
20 typedef struct r4k_tlb_t r4k_tlb_t
;
36 uint_fast16_t EHINV
:1;
40 #if !defined(CONFIG_USER_ONLY)
41 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
42 struct CPUMIPSTLBContext
{
45 int (*map_address
) (struct CPUMIPSState
*env
, hwaddr
*physical
, int *prot
, target_ulong address
, int rw
, int access_type
);
46 void (*helper_tlbwi
)(struct CPUMIPSState
*env
);
47 void (*helper_tlbwr
)(struct CPUMIPSState
*env
);
48 void (*helper_tlbp
)(struct CPUMIPSState
*env
);
49 void (*helper_tlbr
)(struct CPUMIPSState
*env
);
50 void (*helper_tlbinv
)(struct CPUMIPSState
*env
);
51 void (*helper_tlbinvf
)(struct CPUMIPSState
*env
);
54 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
61 #define MSA_WRLEN (128)
63 enum CPUMIPSMSADataFormat
{
70 typedef union wr_t wr_t
;
72 int8_t b
[MSA_WRLEN
/8];
73 int16_t h
[MSA_WRLEN
/16];
74 int32_t w
[MSA_WRLEN
/32];
75 int64_t d
[MSA_WRLEN
/64];
78 typedef union fpr_t fpr_t
;
80 float64 fd
; /* ieee double precision */
81 float32 fs
[2];/* ieee single precision */
82 uint64_t d
; /* binary double fixed-point */
83 uint32_t w
[2]; /* binary single fixed-point */
84 /* FPU/MSA register mapping is not tested on big-endian hosts. */
85 wr_t wr
; /* vector data */
87 /* define FP_ENDIAN_IDX to access the same location
88 * in the fpr_t union regardless of the host endianness
90 #if defined(HOST_WORDS_BIGENDIAN)
91 # define FP_ENDIAN_IDX 1
93 # define FP_ENDIAN_IDX 0
96 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
97 struct CPUMIPSFPUContext
{
98 /* Floating point registers */
100 float_status fp_status
;
101 /* fpu implementation/revision register (fir) */
116 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
117 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
118 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
119 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
120 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
121 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
122 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
123 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
124 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
125 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
127 #define FP_UNDERFLOW 2
128 #define FP_OVERFLOW 4
130 #define FP_INVALID 16
131 #define FP_UNIMPLEMENTED 32
134 #define NB_MMU_MODES 3
136 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
137 struct CPUMIPSMVPContext
{
138 int32_t CP0_MVPControl
;
139 #define CP0MVPCo_CPA 3
140 #define CP0MVPCo_STLB 2
141 #define CP0MVPCo_VPC 1
142 #define CP0MVPCo_EVP 0
143 int32_t CP0_MVPConf0
;
144 #define CP0MVPC0_M 31
145 #define CP0MVPC0_TLBS 29
146 #define CP0MVPC0_GS 28
147 #define CP0MVPC0_PCP 27
148 #define CP0MVPC0_PTLBE 16
149 #define CP0MVPC0_TCA 15
150 #define CP0MVPC0_PVPE 10
151 #define CP0MVPC0_PTC 0
152 int32_t CP0_MVPConf1
;
153 #define CP0MVPC1_CIM 31
154 #define CP0MVPC1_CIF 30
155 #define CP0MVPC1_PCX 20
156 #define CP0MVPC1_PCP2 10
157 #define CP0MVPC1_PCP1 0
160 typedef struct mips_def_t mips_def_t
;
162 #define MIPS_SHADOW_SET_MAX 16
163 #define MIPS_TC_MAX 5
164 #define MIPS_FPU_MAX 1
165 #define MIPS_DSP_ACC 4
166 #define MIPS_KSCRATCH_NUM 6
168 typedef struct TCState TCState
;
170 target_ulong gpr
[32];
172 target_ulong HI
[MIPS_DSP_ACC
];
173 target_ulong LO
[MIPS_DSP_ACC
];
174 target_ulong ACX
[MIPS_DSP_ACC
];
175 target_ulong DSPControl
;
176 int32_t CP0_TCStatus
;
177 #define CP0TCSt_TCU3 31
178 #define CP0TCSt_TCU2 30
179 #define CP0TCSt_TCU1 29
180 #define CP0TCSt_TCU0 28
181 #define CP0TCSt_TMX 27
182 #define CP0TCSt_RNST 23
183 #define CP0TCSt_TDS 21
184 #define CP0TCSt_DT 20
185 #define CP0TCSt_DA 15
187 #define CP0TCSt_TKSU 11
188 #define CP0TCSt_IXMT 10
189 #define CP0TCSt_TASID 0
191 #define CP0TCBd_CurTC 21
192 #define CP0TCBd_TBE 17
193 #define CP0TCBd_CurVPE 0
194 target_ulong CP0_TCHalt
;
195 target_ulong CP0_TCContext
;
196 target_ulong CP0_TCSchedule
;
197 target_ulong CP0_TCScheFBack
;
198 int32_t CP0_Debug_tcstatus
;
199 target_ulong CP0_UserLocal
;
204 #define MSACSR_FS_MASK (1 << MSACSR_FS)
206 #define MSACSR_NX_MASK (1 << MSACSR_NX)
208 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
210 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
211 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
214 float_status msa_fp_status
;
217 typedef struct CPUMIPSState CPUMIPSState
;
218 struct CPUMIPSState
{
220 CPUMIPSFPUContext active_fpu
;
223 uint32_t current_fpu
;
227 target_ulong SEGMask
;
231 #define MSAIR_ProcID 8
235 /* CP0_MVP* are per MVP registers. */
237 int32_t CP0_VPEControl
;
238 #define CP0VPECo_YSI 21
239 #define CP0VPECo_GSI 20
240 #define CP0VPECo_EXCPT 16
241 #define CP0VPECo_TE 15
242 #define CP0VPECo_TargTC 0
243 int32_t CP0_VPEConf0
;
244 #define CP0VPEC0_M 31
245 #define CP0VPEC0_XTC 21
246 #define CP0VPEC0_TCS 19
247 #define CP0VPEC0_SCS 18
248 #define CP0VPEC0_DSC 17
249 #define CP0VPEC0_ICS 16
250 #define CP0VPEC0_MVP 1
251 #define CP0VPEC0_VPA 0
252 int32_t CP0_VPEConf1
;
253 #define CP0VPEC1_NCX 20
254 #define CP0VPEC1_NCP2 10
255 #define CP0VPEC1_NCP1 0
256 target_ulong CP0_YQMask
;
257 target_ulong CP0_VPESchedule
;
258 target_ulong CP0_VPEScheFBack
;
260 #define CP0VPEOpt_IWX7 15
261 #define CP0VPEOpt_IWX6 14
262 #define CP0VPEOpt_IWX5 13
263 #define CP0VPEOpt_IWX4 12
264 #define CP0VPEOpt_IWX3 11
265 #define CP0VPEOpt_IWX2 10
266 #define CP0VPEOpt_IWX1 9
267 #define CP0VPEOpt_IWX0 8
268 #define CP0VPEOpt_DWX7 7
269 #define CP0VPEOpt_DWX6 6
270 #define CP0VPEOpt_DWX5 5
271 #define CP0VPEOpt_DWX4 4
272 #define CP0VPEOpt_DWX3 3
273 #define CP0VPEOpt_DWX2 2
274 #define CP0VPEOpt_DWX1 1
275 #define CP0VPEOpt_DWX0 0
276 target_ulong CP0_EntryLo0
;
277 target_ulong CP0_EntryLo1
;
278 #if defined(TARGET_MIPS64)
279 # define CP0EnLo_RI 63
280 # define CP0EnLo_XI 62
282 # define CP0EnLo_RI 31
283 # define CP0EnLo_XI 30
285 target_ulong CP0_Context
;
286 target_ulong CP0_KScratch
[MIPS_KSCRATCH_NUM
];
287 int32_t CP0_PageMask
;
288 int32_t CP0_PageGrain_rw_bitmask
;
289 int32_t CP0_PageGrain
;
294 int32_t CP0_SRSConf0_rw_bitmask
;
295 int32_t CP0_SRSConf0
;
296 #define CP0SRSC0_M 31
297 #define CP0SRSC0_SRS3 20
298 #define CP0SRSC0_SRS2 10
299 #define CP0SRSC0_SRS1 0
300 int32_t CP0_SRSConf1_rw_bitmask
;
301 int32_t CP0_SRSConf1
;
302 #define CP0SRSC1_M 31
303 #define CP0SRSC1_SRS6 20
304 #define CP0SRSC1_SRS5 10
305 #define CP0SRSC1_SRS4 0
306 int32_t CP0_SRSConf2_rw_bitmask
;
307 int32_t CP0_SRSConf2
;
308 #define CP0SRSC2_M 31
309 #define CP0SRSC2_SRS9 20
310 #define CP0SRSC2_SRS8 10
311 #define CP0SRSC2_SRS7 0
312 int32_t CP0_SRSConf3_rw_bitmask
;
313 int32_t CP0_SRSConf3
;
314 #define CP0SRSC3_M 31
315 #define CP0SRSC3_SRS12 20
316 #define CP0SRSC3_SRS11 10
317 #define CP0SRSC3_SRS10 0
318 int32_t CP0_SRSConf4_rw_bitmask
;
319 int32_t CP0_SRSConf4
;
320 #define CP0SRSC4_SRS15 20
321 #define CP0SRSC4_SRS14 10
322 #define CP0SRSC4_SRS13 0
324 target_ulong CP0_BadVAddr
;
325 uint32_t CP0_BadInstr
;
326 uint32_t CP0_BadInstrP
;
328 target_ulong CP0_EntryHi
;
329 #define CP0EnHi_EHINV 10
354 #define CP0IntCtl_IPTI 29
355 #define CP0IntCtl_IPPC1 26
356 #define CP0IntCtl_VS 5
358 #define CP0SRSCtl_HSS 26
359 #define CP0SRSCtl_EICSS 18
360 #define CP0SRSCtl_ESS 12
361 #define CP0SRSCtl_PSS 6
362 #define CP0SRSCtl_CSS 0
364 #define CP0SRSMap_SSV7 28
365 #define CP0SRSMap_SSV6 24
366 #define CP0SRSMap_SSV5 20
367 #define CP0SRSMap_SSV4 16
368 #define CP0SRSMap_SSV3 12
369 #define CP0SRSMap_SSV2 8
370 #define CP0SRSMap_SSV1 4
371 #define CP0SRSMap_SSV0 0
381 #define CP0Ca_IP_mask 0x0000FF00
383 target_ulong CP0_EPC
;
428 #define CP0C3_CMCGR 29
429 #define CP0C3_MSAP 28
432 #define CP0C3_IPLW 21
433 #define CP0C3_MMAR 18
435 #define CP0C3_ISA_ON_EXC 16
437 #define CP0C3_ULRI 13
439 #define CP0C3_DSP2P 11
440 #define CP0C3_DSPP 10
450 int32_t CP0_Config4_rw_bitmask
;
453 #define CP0C4_KScrExist 16
454 #define CP0C4_MMUExtDef 14
455 #define CP0C4_FTLBPageSize 8
456 #define CP0C4_FTLBWays 4
457 #define CP0C4_FTLBSets 0
458 #define CP0C4_MMUSizeExt 0
460 int32_t CP0_Config5_rw_bitmask
;
465 #define CP0C5_MSAEn 27
471 #define CP0C5_NFExists 0
474 /* XXX: Maybe make LLAddr per-TC? */
477 target_ulong llnewval
;
479 target_ulong CP0_LLAddr_rw_bitmask
;
480 int CP0_LLAddr_shift
;
481 target_ulong CP0_WatchLo
[8];
482 int32_t CP0_WatchHi
[8];
483 target_ulong CP0_XContext
;
484 int32_t CP0_Framemask
;
488 #define CP0DB_LSNM 28
489 #define CP0DB_Doze 27
490 #define CP0DB_Halt 26
492 #define CP0DB_IBEP 24
493 #define CP0DB_DBEP 21
494 #define CP0DB_IEXI 20
504 target_ulong CP0_DEPC
;
505 int32_t CP0_Performance0
;
510 target_ulong CP0_ErrorEPC
;
512 /* We waste some space so we can handle shadow registers like TCs. */
513 TCState tcs
[MIPS_SHADOW_SET_MAX
];
514 CPUMIPSFPUContext fpus
[MIPS_FPU_MAX
];
517 #define EXCP_TLB_NOMATCH 0x1
518 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
519 uint32_t hflags
; /* CPU State */
520 /* TMASK defines different execution modes */
521 #define MIPS_HFLAG_TMASK 0x35807FF
522 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
523 /* The KSU flags must be the lowest bits in hflags. The flag order
524 must be the same as defined for CP0 Status. This allows to use
525 the bits as the value of mmu_idx. */
526 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
527 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
528 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
529 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
530 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
531 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
532 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
533 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
534 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
535 /* True if the MIPS IV COP1X instructions can be used. This also
536 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
538 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
539 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
540 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
541 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
542 #define MIPS_HFLAG_M16_SHIFT 10
543 /* If translation is interrupted between the branch instruction and
544 * the delay slot, record what type of branch it is so that we can
545 * resume translation properly. It might be possible to reduce
546 * this from three bits to two. */
547 #define MIPS_HFLAG_BMASK_BASE 0x803800
548 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
549 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
550 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
551 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
552 /* Extra flags about the current pending branch. */
553 #define MIPS_HFLAG_BMASK_EXT 0x7C000
554 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
555 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
556 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
557 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
558 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
559 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
560 /* MIPS DSP resources access. */
561 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
562 #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
563 /* Extra flag about HWREna register. */
564 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
565 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
566 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
567 #define MIPS_HFLAG_MSA 0x1000000
568 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
569 target_ulong btarget
; /* Jump / branch target */
570 target_ulong bcond
; /* Branch condition (if needed) */
572 int SYNCI_Step
; /* Address step size for SYNCI */
573 int CCRes
; /* Cycle count resolution/divisor */
574 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
575 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
576 int insn_flags
; /* Supported instruction set */
580 /* Fields from here on are preserved across CPU reset. */
581 CPUMIPSMVPContext
*mvp
;
582 #if !defined(CONFIG_USER_ONLY)
583 CPUMIPSTLBContext
*tlb
;
586 const mips_def_t
*cpu_model
;
588 QEMUTimer
*timer
; /* Internal timer */
593 #if !defined(CONFIG_USER_ONLY)
594 int no_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
595 target_ulong address
, int rw
, int access_type
);
596 int fixed_mmu_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
597 target_ulong address
, int rw
, int access_type
);
598 int r4k_map_address (CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
599 target_ulong address
, int rw
, int access_type
);
600 void r4k_helper_tlbwi(CPUMIPSState
*env
);
601 void r4k_helper_tlbwr(CPUMIPSState
*env
);
602 void r4k_helper_tlbp(CPUMIPSState
*env
);
603 void r4k_helper_tlbr(CPUMIPSState
*env
);
604 void r4k_helper_tlbinv(CPUMIPSState
*env
);
605 void r4k_helper_tlbinvf(CPUMIPSState
*env
);
607 void mips_cpu_unassigned_access(CPUState
*cpu
, hwaddr addr
,
608 bool is_write
, bool is_exec
, int unused
,
612 void mips_cpu_list (FILE *f
, fprintf_function cpu_fprintf
);
614 #define cpu_exec cpu_mips_exec
615 #define cpu_gen_code cpu_mips_gen_code
616 #define cpu_signal_handler cpu_mips_signal_handler
617 #define cpu_list mips_cpu_list
619 extern void cpu_wrdsp(uint32_t rs
, uint32_t mask_num
, CPUMIPSState
*env
);
620 extern uint32_t cpu_rddsp(uint32_t mask_num
, CPUMIPSState
*env
);
622 /* MMU modes definitions. We carefully match the indices with our
624 #define MMU_MODE0_SUFFIX _kernel
625 #define MMU_MODE1_SUFFIX _super
626 #define MMU_MODE2_SUFFIX _user
627 #define MMU_USER_IDX 2
628 static inline int cpu_mmu_index (CPUMIPSState
*env
)
630 return env
->hflags
& MIPS_HFLAG_KSU
;
633 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
639 if (!(env
->CP0_Status
& (1 << CP0St_IE
)) ||
640 (env
->CP0_Status
& (1 << CP0St_EXL
)) ||
641 (env
->CP0_Status
& (1 << CP0St_ERL
)) ||
642 /* Note that the TCStatus IXMT field is initialized to zero,
643 and only MT capable cores can set it to one. So we don't
644 need to check for MT capabilities here. */
645 (env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
)) ||
646 (env
->hflags
& MIPS_HFLAG_DM
)) {
647 /* Interrupts are disabled */
651 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
652 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
654 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
655 /* A MIPS configured with a vectorizing external interrupt controller
656 will feed a vector into the Cause pending lines. The core treats
657 the status lines as a vector level, not as indiviual masks. */
658 r
= pending
> status
;
660 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
661 treats the pending lines as individual interrupt lines, the status
662 lines are individual masks. */
663 r
= pending
& status
;
668 #include "exec/cpu-all.h"
670 /* Memory access type :
671 * may be needed for precise access rights control and precise exceptions.
674 /* 1 bit to define user level / supervisor access */
677 /* 1 bit to indicate direction */
679 /* Type of instruction that generated the access */
680 ACCESS_CODE
= 0x10, /* Code fetch access */
681 ACCESS_INT
= 0x20, /* Integer load/store access */
682 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
696 EXCP_EXT_INTERRUPT
, /* 8 */
712 EXCP_DWATCH
, /* 24 */
727 EXCP_LAST
= EXCP_TLBRI
,
729 /* Dummy exception for conditional stores. */
730 #define EXCP_SC 0x100
733 * This is an interrnally generated WAKE request line.
734 * It is driven by the CPU itself. Raised when the MT
735 * block wants to wake a VPE from an inactive state and
736 * cleared when VPE goes from active to inactive.
738 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
740 int cpu_mips_exec(CPUMIPSState
*s
);
741 void mips_tcg_init(void);
742 MIPSCPU
*cpu_mips_init(const char *cpu_model
);
743 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
745 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
747 /* TODO QOM'ify CPU reset and remove */
748 void cpu_state_reset(CPUMIPSState
*s
);
751 uint32_t cpu_mips_get_random (CPUMIPSState
*env
);
752 uint32_t cpu_mips_get_count (CPUMIPSState
*env
);
753 void cpu_mips_store_count (CPUMIPSState
*env
, uint32_t value
);
754 void cpu_mips_store_compare (CPUMIPSState
*env
, uint32_t value
);
755 void cpu_mips_start_count(CPUMIPSState
*env
);
756 void cpu_mips_stop_count(CPUMIPSState
*env
);
759 void cpu_mips_soft_irq(CPUMIPSState
*env
, int irq
, int level
);
762 int mips_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
764 #if !defined(CONFIG_USER_ONLY)
765 void r4k_invalidate_tlb (CPUMIPSState
*env
, int idx
, int use_extra
);
766 hwaddr
cpu_mips_translate_address (CPUMIPSState
*env
, target_ulong address
,
769 target_ulong
exception_resume_pc (CPUMIPSState
*env
);
772 extern unsigned int ieee_rm
[];
773 int ieee_ex_to_mips(int xcpt
);
775 static inline void restore_rounding_mode(CPUMIPSState
*env
)
777 set_float_rounding_mode(ieee_rm
[env
->active_fpu
.fcr31
& 3],
778 &env
->active_fpu
.fp_status
);
781 static inline void restore_flush_mode(CPUMIPSState
*env
)
783 set_flush_to_zero((env
->active_fpu
.fcr31
& (1 << 24)) != 0,
784 &env
->active_fpu
.fp_status
);
787 static inline void restore_fp_status(CPUMIPSState
*env
)
789 restore_rounding_mode(env
);
790 restore_flush_mode(env
);
793 static inline void restore_msa_fp_status(CPUMIPSState
*env
)
795 float_status
*status
= &env
->active_tc
.msa_fp_status
;
796 int rounding_mode
= (env
->active_tc
.msacsr
& MSACSR_RM_MASK
) >> MSACSR_RM
;
797 bool flush_to_zero
= (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0;
799 set_float_rounding_mode(ieee_rm
[rounding_mode
], status
);
800 set_flush_to_zero(flush_to_zero
, status
);
801 set_flush_inputs_to_zero(flush_to_zero
, status
);
804 static inline void cpu_get_tb_cpu_state(CPUMIPSState
*env
, target_ulong
*pc
,
805 target_ulong
*cs_base
, int *flags
)
807 *pc
= env
->active_tc
.PC
;
809 *flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
|
810 MIPS_HFLAG_HWRENA_ULR
);
813 static inline int mips_vpe_active(CPUMIPSState
*env
)
817 /* Check that the VPE is enabled. */
818 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
821 /* Check that the VPE is activated. */
822 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
826 /* Now verify that there are active thread contexts in the VPE.
828 This assumes the CPU model will internally reschedule threads
829 if the active one goes to sleep. If there are no threads available
830 the active one will be in a sleeping state, and we can turn off
832 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
833 /* TC is not activated. */
836 if (env
->active_tc
.CP0_TCHalt
& 1) {
837 /* TC is in halt state. */
844 #include "exec/exec-all.h"
846 static inline void compute_hflags(CPUMIPSState
*env
)
848 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
849 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
850 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSPR2
|
851 MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
| MIPS_HFLAG_FRE
);
852 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
853 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
854 !(env
->hflags
& MIPS_HFLAG_DM
)) {
855 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) & MIPS_HFLAG_KSU
;
857 #if defined(TARGET_MIPS64)
858 if ((env
->insn_flags
& ISA_MIPS3
) &&
859 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
860 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
861 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
862 env
->hflags
|= MIPS_HFLAG_64
;
865 if (!(env
->insn_flags
& ISA_MIPS3
)) {
866 env
->hflags
|= MIPS_HFLAG_AWRAP
;
867 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
868 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
869 env
->hflags
|= MIPS_HFLAG_AWRAP
;
870 } else if (env
->insn_flags
& ISA_MIPS64R6
) {
871 /* Address wrapping for Supervisor and Kernel is specified in R6 */
872 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
873 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
874 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
875 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
876 env
->hflags
|= MIPS_HFLAG_AWRAP
;
880 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
881 !(env
->insn_flags
& ISA_MIPS32R6
)) ||
882 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
883 env
->hflags
|= MIPS_HFLAG_CP0
;
885 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
886 env
->hflags
|= MIPS_HFLAG_FPU
;
888 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
889 env
->hflags
|= MIPS_HFLAG_F64
;
891 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
892 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
893 env
->hflags
|= MIPS_HFLAG_SBRI
;
895 if (env
->insn_flags
& ASE_DSPR2
) {
896 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
897 so enable to access DSPR2 resources. */
898 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
899 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSPR2
;
902 } else if (env
->insn_flags
& ASE_DSP
) {
903 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
904 so enable to access DSP resources. */
905 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
906 env
->hflags
|= MIPS_HFLAG_DSP
;
910 if (env
->insn_flags
& ISA_MIPS32R2
) {
911 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
912 env
->hflags
|= MIPS_HFLAG_COP1X
;
914 } else if (env
->insn_flags
& ISA_MIPS32
) {
915 if (env
->hflags
& MIPS_HFLAG_64
) {
916 env
->hflags
|= MIPS_HFLAG_COP1X
;
918 } else if (env
->insn_flags
& ISA_MIPS4
) {
919 /* All supported MIPS IV CPUs use the XX (CU3) to enable
920 and disable the MIPS IV extensions to the MIPS III ISA.
921 Some other MIPS IV CPUs ignore the bit, so the check here
922 would be too restrictive for them. */
923 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
924 env
->hflags
|= MIPS_HFLAG_COP1X
;
927 if (env
->insn_flags
& ASE_MSA
) {
928 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
929 env
->hflags
|= MIPS_HFLAG_MSA
;
932 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
933 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
934 env
->hflags
|= MIPS_HFLAG_FRE
;
939 #ifndef CONFIG_USER_ONLY
940 /* Called for updates to CP0_Status. */
941 static inline void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
)
943 int32_t tcstatus
, *tcst
;
944 uint32_t v
= cpu
->CP0_Status
;
945 uint32_t cu
, mx
, asid
, ksu
;
946 uint32_t mask
= ((1 << CP0TCSt_TCU3
)
947 | (1 << CP0TCSt_TCU2
)
948 | (1 << CP0TCSt_TCU1
)
949 | (1 << CP0TCSt_TCU0
)
951 | (3 << CP0TCSt_TKSU
)
952 | (0xff << CP0TCSt_TASID
));
954 cu
= (v
>> CP0St_CU0
) & 0xf;
955 mx
= (v
>> CP0St_MX
) & 0x1;
956 ksu
= (v
>> CP0St_KSU
) & 0x3;
957 asid
= env
->CP0_EntryHi
& 0xff;
959 tcstatus
= cu
<< CP0TCSt_TCU0
;
960 tcstatus
|= mx
<< CP0TCSt_TMX
;
961 tcstatus
|= ksu
<< CP0TCSt_TKSU
;
964 if (tc
== cpu
->current_tc
) {
965 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
967 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
975 static inline void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
)
977 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
979 if (env
->insn_flags
& ISA_MIPS32R6
) {
980 bool has_supervisor
= extract32(mask
, CP0St_KSU
, 2) == 0x3;
982 if (has_supervisor
&& extract32(val
, CP0St_KSU
, 2) == 0x3) {
983 mask
&= ~(3 << CP0St_KSU
);
985 mask
&= ~(((1 << CP0St_SR
) | (1 << CP0St_NMI
)) & val
);
988 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | (val
& mask
);
989 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
990 sync_c0_status(env
, env
, env
->current_tc
);
996 static inline void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
)
998 uint32_t mask
= 0x00C00300;
999 uint32_t old
= env
->CP0_Cause
;
1002 if (env
->insn_flags
& ISA_MIPS32R2
) {
1003 mask
|= 1 << CP0Ca_DC
;
1005 if (env
->insn_flags
& ISA_MIPS32R6
) {
1006 mask
&= ~((1 << CP0Ca_WP
) & val
);
1009 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (val
& mask
);
1011 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
1012 if (env
->CP0_Cause
& (1 << CP0Ca_DC
)) {
1013 cpu_mips_stop_count(env
);
1015 cpu_mips_start_count(env
);
1019 /* Set/reset software interrupts */
1020 for (i
= 0 ; i
< 2 ; i
++) {
1021 if ((old
^ env
->CP0_Cause
) & (1 << (CP0Ca_IP
+ i
))) {
1022 cpu_mips_soft_irq(env
, i
, env
->CP0_Cause
& (1 << (CP0Ca_IP
+ i
)));
1028 #endif /* !defined (__MIPS_CPU_H__) */