5 #include "exec/cpu-defs.h"
6 #include "fpu/softfloat-types.h"
10 #define TCG_GUEST_DEFAULT_MO (0)
12 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
15 #define MSA_WRLEN (128)
17 typedef union wr_t wr_t
;
19 int8_t b
[MSA_WRLEN
/ 8];
20 int16_t h
[MSA_WRLEN
/ 16];
21 int32_t w
[MSA_WRLEN
/ 32];
22 int64_t d
[MSA_WRLEN
/ 64];
25 typedef union fpr_t fpr_t
;
27 float64 fd
; /* ieee double precision */
28 float32 fs
[2];/* ieee single precision */
29 uint64_t d
; /* binary double fixed-point */
30 uint32_t w
[2]; /* binary single fixed-point */
31 /* FPU/MSA register mapping is not tested on big-endian hosts. */
32 wr_t wr
; /* vector data */
35 *define FP_ENDIAN_IDX to access the same location
36 * in the fpr_t union regardless of the host endianness
38 #if defined(HOST_WORDS_BIGENDIAN)
39 # define FP_ENDIAN_IDX 1
41 # define FP_ENDIAN_IDX 0
44 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
45 struct CPUMIPSFPUContext
{
46 /* Floating point registers */
48 float_status fp_status
;
49 /* fpu implementation/revision register (fir) */
53 #define FCR0_HAS2008 23
64 uint32_t fcr31_rw_bitmask
;
67 #define FCR31_ABS2008 19
68 #define FCR31_NAN2008 18
69 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \
70 ((num) ? (1 << ((num) + 24)) : \
73 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
74 ~((num) ? (1 << ((num) + 24)) : \
77 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
78 (((env).fcr31 >> 23) & 0x1))
79 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
80 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
81 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
82 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
85 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
88 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
91 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
93 #define FP_UNDERFLOW 2
97 #define FP_UNIMPLEMENTED 32
100 #define TARGET_INSN_START_EXTRA_WORDS 2
102 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
103 struct CPUMIPSMVPContext
{
104 int32_t CP0_MVPControl
;
105 #define CP0MVPCo_CPA 3
106 #define CP0MVPCo_STLB 2
107 #define CP0MVPCo_VPC 1
108 #define CP0MVPCo_EVP 0
109 int32_t CP0_MVPConf0
;
110 #define CP0MVPC0_M 31
111 #define CP0MVPC0_TLBS 29
112 #define CP0MVPC0_GS 28
113 #define CP0MVPC0_PCP 27
114 #define CP0MVPC0_PTLBE 16
115 #define CP0MVPC0_TCA 15
116 #define CP0MVPC0_PVPE 10
117 #define CP0MVPC0_PTC 0
118 int32_t CP0_MVPConf1
;
119 #define CP0MVPC1_CIM 31
120 #define CP0MVPC1_CIF 30
121 #define CP0MVPC1_PCX 20
122 #define CP0MVPC1_PCP2 10
123 #define CP0MVPC1_PCP1 0
126 typedef struct mips_def_t mips_def_t
;
128 #define MIPS_SHADOW_SET_MAX 16
129 #define MIPS_TC_MAX 5
130 #define MIPS_FPU_MAX 1
131 #define MIPS_DSP_ACC 4
132 #define MIPS_KSCRATCH_NUM 6
133 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
137 * Summary of CP0 registers
138 * ========================
141 * Register 0 Register 1 Register 2 Register 3
142 * ---------- ---------- ---------- ----------
144 * 0 Index Random EntryLo0 EntryLo1
145 * 1 MVPControl VPEControl TCStatus GlobalNumber
146 * 2 MVPConf0 VPEConf0 TCBind
147 * 3 MVPConf1 VPEConf1 TCRestart
148 * 4 VPControl YQMask TCHalt
149 * 5 VPESchedule TCContext
150 * 6 VPEScheFBack TCSchedule
151 * 7 VPEOpt TCScheFBack TCOpt
154 * Register 4 Register 5 Register 6 Register 7
155 * ---------- ---------- ---------- ----------
157 * 0 Context PageMask Wired HWREna
158 * 1 ContextConfig PageGrain SRSConf0
159 * 2 UserLocal SegCtl0 SRSConf1
160 * 3 XContextConfig SegCtl1 SRSConf2
161 * 4 DebugContextID SegCtl2 SRSConf3
162 * 5 MemoryMapID PWBase SRSConf4
167 * Register 8 Register 9 Register 10 Register 11
168 * ---------- ---------- ----------- -----------
170 * 0 BadVAddr Count EntryHi Compare
174 * 4 GuestCtl1 GuestCtl0Ext
180 * Register 12 Register 13 Register 14 Register 15
181 * ----------- ----------- ----------- -----------
183 * 0 Status Cause EPC PRId
185 * 2 SRSCtl NestedEPC CDMMBase
187 * 4 View_IPL View_RIPL BEVVA
188 * 5 SRSMap2 NestedExc
193 * Register 16 Register 17 Register 18 Register 19
194 * ----------- ----------- ----------- -----------
196 * 0 Config LLAddr WatchLo0 WatchHi
197 * 1 Config1 MAAR WatchLo1 WatchHi
198 * 2 Config2 MAARI WatchLo2 WatchHi
199 * 3 Config3 WatchLo3 WatchHi
200 * 4 Config4 WatchLo4 WatchHi
201 * 5 Config5 WatchLo5 WatchHi
202 * 6 Config6 WatchLo6 WatchHi
203 * 7 Config7 WatchLo7 WatchHi
206 * Register 20 Register 21 Register 22 Register 23
207 * ----------- ----------- ----------- -----------
219 * Register 24 Register 25 Register 26 Register 27
220 * ----------- ----------- ----------- -----------
222 * 0 DEPC PerfCnt ErrCtl CacheErr
224 * 2 TraceControl3 PerfCnt
225 * 3 UserTraceData2 PerfCnt
232 * Register 28 Register 29 Register 30 Register 31
233 * ----------- ----------- ----------- -----------
235 * 0 DataLo DataHi ErrorEPC DESAVE
237 * 2 DataLo1 DataHi1 KScratch<n>
238 * 3 TagLo1 TagHi1 KScratch<n>
239 * 4 DataLo2 DataHi2 KScratch<n>
240 * 5 TagLo2 TagHi2 KScratch<n>
241 * 6 DataLo3 DataHi3 KScratch<n>
242 * 7 TagLo3 TagHi3 KScratch<n>
245 #define CP0_REGISTER_00 0
246 #define CP0_REGISTER_01 1
247 #define CP0_REGISTER_02 2
248 #define CP0_REGISTER_03 3
249 #define CP0_REGISTER_04 4
250 #define CP0_REGISTER_05 5
251 #define CP0_REGISTER_06 6
252 #define CP0_REGISTER_07 7
253 #define CP0_REGISTER_08 8
254 #define CP0_REGISTER_09 9
255 #define CP0_REGISTER_10 10
256 #define CP0_REGISTER_11 11
257 #define CP0_REGISTER_12 12
258 #define CP0_REGISTER_13 13
259 #define CP0_REGISTER_14 14
260 #define CP0_REGISTER_15 15
261 #define CP0_REGISTER_16 16
262 #define CP0_REGISTER_17 17
263 #define CP0_REGISTER_18 18
264 #define CP0_REGISTER_19 19
265 #define CP0_REGISTER_20 20
266 #define CP0_REGISTER_21 21
267 #define CP0_REGISTER_22 22
268 #define CP0_REGISTER_23 23
269 #define CP0_REGISTER_24 24
270 #define CP0_REGISTER_25 25
271 #define CP0_REGISTER_26 26
272 #define CP0_REGISTER_27 27
273 #define CP0_REGISTER_28 28
274 #define CP0_REGISTER_29 29
275 #define CP0_REGISTER_30 30
276 #define CP0_REGISTER_31 31
279 /* CP0 Register 00 */
280 #define CP0_REG00__INDEX 0
281 #define CP0_REG00__MVPCONTROL 1
282 #define CP0_REG00__MVPCONF0 2
283 #define CP0_REG00__MVPCONF1 3
284 #define CP0_REG00__VPCONTROL 4
285 /* CP0 Register 01 */
286 #define CP0_REG01__RANDOM 0
287 #define CP0_REG01__VPECONTROL 1
288 #define CP0_REG01__VPECONF0 2
289 #define CP0_REG01__VPECONF1 3
290 #define CP0_REG01__YQMASK 4
291 #define CP0_REG01__VPESCHEDULE 5
292 #define CP0_REG01__VPESCHEFBACK 6
293 #define CP0_REG01__VPEOPT 7
294 /* CP0 Register 02 */
295 #define CP0_REG02__ENTRYLO0 0
296 #define CP0_REG02__TCSTATUS 1
297 #define CP0_REG02__TCBIND 2
298 #define CP0_REG02__TCRESTART 3
299 #define CP0_REG02__TCHALT 4
300 #define CP0_REG02__TCCONTEXT 5
301 #define CP0_REG02__TCSCHEDULE 6
302 #define CP0_REG02__TCSCHEFBACK 7
303 /* CP0 Register 03 */
304 #define CP0_REG03__ENTRYLO1 0
305 #define CP0_REG03__GLOBALNUM 1
306 #define CP0_REG03__TCOPT 7
307 /* CP0 Register 04 */
308 #define CP0_REG04__CONTEXT 0
309 #define CP0_REG04__CONTEXTCONFIG 1
310 #define CP0_REG04__USERLOCAL 2
311 #define CP0_REG04__XCONTEXTCONFIG 3
312 #define CP0_REG04__DBGCONTEXTID 4
313 #define CP0_REG04__MMID 5
314 /* CP0 Register 05 */
315 #define CP0_REG05__PAGEMASK 0
316 #define CP0_REG05__PAGEGRAIN 1
317 #define CP0_REG05__SEGCTL0 2
318 #define CP0_REG05__SEGCTL1 3
319 #define CP0_REG05__SEGCTL2 4
320 #define CP0_REG05__PWBASE 5
321 #define CP0_REG05__PWFIELD 6
322 #define CP0_REG05__PWSIZE 7
323 /* CP0 Register 06 */
324 #define CP0_REG06__WIRED 0
325 #define CP0_REG06__SRSCONF0 1
326 #define CP0_REG06__SRSCONF1 2
327 #define CP0_REG06__SRSCONF2 3
328 #define CP0_REG06__SRSCONF3 4
329 #define CP0_REG06__SRSCONF4 5
330 #define CP0_REG06__PWCTL 6
331 /* CP0 Register 07 */
332 #define CP0_REG07__HWRENA 0
333 /* CP0 Register 08 */
334 #define CP0_REG08__BADVADDR 0
335 #define CP0_REG08__BADINSTR 1
336 #define CP0_REG08__BADINSTRP 2
337 #define CP0_REG08__BADINSTRX 3
338 /* CP0 Register 09 */
339 #define CP0_REG09__COUNT 0
340 #define CP0_REG09__SAARI 6
341 #define CP0_REG09__SAAR 7
342 /* CP0 Register 10 */
343 #define CP0_REG10__ENTRYHI 0
344 #define CP0_REG10__GUESTCTL1 4
345 #define CP0_REG10__GUESTCTL2 5
346 #define CP0_REG10__GUESTCTL3 6
347 /* CP0 Register 11 */
348 #define CP0_REG11__COMPARE 0
349 #define CP0_REG11__GUESTCTL0EXT 4
350 /* CP0 Register 12 */
351 #define CP0_REG12__STATUS 0
352 #define CP0_REG12__INTCTL 1
353 #define CP0_REG12__SRSCTL 2
354 #define CP0_REG12__SRSMAP 3
355 #define CP0_REG12__VIEW_IPL 4
356 #define CP0_REG12__SRSMAP2 5
357 #define CP0_REG12__GUESTCTL0 6
358 #define CP0_REG12__GTOFFSET 7
359 /* CP0 Register 13 */
360 #define CP0_REG13__CAUSE 0
361 #define CP0_REG13__VIEW_RIPL 4
362 #define CP0_REG13__NESTEDEXC 5
363 /* CP0 Register 14 */
364 #define CP0_REG14__EPC 0
365 #define CP0_REG14__NESTEDEPC 2
366 /* CP0 Register 15 */
367 #define CP0_REG15__PRID 0
368 #define CP0_REG15__EBASE 1
369 #define CP0_REG15__CDMMBASE 2
370 #define CP0_REG15__CMGCRBASE 3
371 #define CP0_REG15__BEVVA 4
372 /* CP0 Register 16 */
373 #define CP0_REG16__CONFIG 0
374 #define CP0_REG16__CONFIG1 1
375 #define CP0_REG16__CONFIG2 2
376 #define CP0_REG16__CONFIG3 3
377 #define CP0_REG16__CONFIG4 4
378 #define CP0_REG16__CONFIG5 5
379 #define CP0_REG16__CONFIG6 6
380 #define CP0_REG16__CONFIG7 7
381 /* CP0 Register 17 */
382 #define CP0_REG17__LLADDR 0
383 #define CP0_REG17__MAAR 1
384 #define CP0_REG17__MAARI 2
385 /* CP0 Register 18 */
386 #define CP0_REG18__WATCHLO0 0
387 #define CP0_REG18__WATCHLO1 1
388 #define CP0_REG18__WATCHLO2 2
389 #define CP0_REG18__WATCHLO3 3
390 #define CP0_REG18__WATCHLO4 4
391 #define CP0_REG18__WATCHLO5 5
392 #define CP0_REG18__WATCHLO6 6
393 #define CP0_REG18__WATCHLO7 7
394 /* CP0 Register 19 */
395 #define CP0_REG19__WATCHHI0 0
396 #define CP0_REG19__WATCHHI1 1
397 #define CP0_REG19__WATCHHI2 2
398 #define CP0_REG19__WATCHHI3 3
399 #define CP0_REG19__WATCHHI4 4
400 #define CP0_REG19__WATCHHI5 5
401 #define CP0_REG19__WATCHHI6 6
402 #define CP0_REG19__WATCHHI7 7
403 /* CP0 Register 20 */
404 #define CP0_REG20__XCONTEXT 0
405 /* CP0 Register 21 */
406 /* CP0 Register 22 */
407 /* CP0 Register 23 */
408 #define CP0_REG23__DEBUG 0
409 #define CP0_REG23__TRACECONTROL 1
410 #define CP0_REG23__TRACECONTROL2 2
411 #define CP0_REG23__USERTRACEDATA1 3
412 #define CP0_REG23__TRACEIBPC 4
413 #define CP0_REG23__TRACEDBPC 5
414 #define CP0_REG23__DEBUG2 6
415 /* CP0 Register 24 */
416 #define CP0_REG24__DEPC 0
417 /* CP0 Register 25 */
418 #define CP0_REG25__PERFCTL0 0
419 #define CP0_REG25__PERFCNT0 1
420 #define CP0_REG25__PERFCTL1 2
421 #define CP0_REG25__PERFCNT1 3
422 #define CP0_REG25__PERFCTL2 4
423 #define CP0_REG25__PERFCNT2 5
424 #define CP0_REG25__PERFCTL3 6
425 #define CP0_REG25__PERFCNT3 7
426 /* CP0 Register 26 */
427 #define CP0_REG26__ERRCTL 0
428 /* CP0 Register 27 */
429 #define CP0_REG27__CACHERR 0
430 /* CP0 Register 28 */
431 #define CP0_REG28__TAGLO 0
432 #define CP0_REG28__DATALO 1
433 #define CP0_REG28__TAGLO1 2
434 #define CP0_REG28__DATALO1 3
435 #define CP0_REG28__TAGLO2 4
436 #define CP0_REG28__DATALO2 5
437 #define CP0_REG28__TAGLO3 6
438 #define CP0_REG28__DATALO3 7
439 /* CP0 Register 29 */
440 #define CP0_REG29__TAGHI 0
441 #define CP0_REG29__DATAHI 1
442 #define CP0_REG29__TAGHI1 2
443 #define CP0_REG29__DATAHI1 3
444 #define CP0_REG29__TAGHI2 4
445 #define CP0_REG29__DATAHI2 5
446 #define CP0_REG29__TAGHI3 6
447 #define CP0_REG29__DATAHI3 7
448 /* CP0 Register 30 */
449 #define CP0_REG30__ERROREPC 0
450 /* CP0 Register 31 */
451 #define CP0_REG31__DESAVE 0
452 #define CP0_REG31__KSCRATCH1 2
453 #define CP0_REG31__KSCRATCH2 3
454 #define CP0_REG31__KSCRATCH3 4
455 #define CP0_REG31__KSCRATCH4 5
456 #define CP0_REG31__KSCRATCH5 6
457 #define CP0_REG31__KSCRATCH6 7
460 typedef struct TCState TCState
;
462 target_ulong gpr
[32];
464 target_ulong HI
[MIPS_DSP_ACC
];
465 target_ulong LO
[MIPS_DSP_ACC
];
466 target_ulong ACX
[MIPS_DSP_ACC
];
467 target_ulong DSPControl
;
468 int32_t CP0_TCStatus
;
469 #define CP0TCSt_TCU3 31
470 #define CP0TCSt_TCU2 30
471 #define CP0TCSt_TCU1 29
472 #define CP0TCSt_TCU0 28
473 #define CP0TCSt_TMX 27
474 #define CP0TCSt_RNST 23
475 #define CP0TCSt_TDS 21
476 #define CP0TCSt_DT 20
477 #define CP0TCSt_DA 15
479 #define CP0TCSt_TKSU 11
480 #define CP0TCSt_IXMT 10
481 #define CP0TCSt_TASID 0
483 #define CP0TCBd_CurTC 21
484 #define CP0TCBd_TBE 17
485 #define CP0TCBd_CurVPE 0
486 target_ulong CP0_TCHalt
;
487 target_ulong CP0_TCContext
;
488 target_ulong CP0_TCSchedule
;
489 target_ulong CP0_TCScheFBack
;
490 int32_t CP0_Debug_tcstatus
;
491 target_ulong CP0_UserLocal
;
496 #define MSACSR_FS_MASK (1 << MSACSR_FS)
498 #define MSACSR_NX_MASK (1 << MSACSR_NX)
500 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
502 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
503 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
506 float_status msa_fp_status
;
508 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
511 #define NUMBER_OF_MXU_REGISTERS 16
512 target_ulong mxu_gpr
[NUMBER_OF_MXU_REGISTERS
- 1];
516 #define MXU_CR_BIAS 2
517 #define MXU_CR_RD_EN 1
518 #define MXU_CR_MXU_EN 0
523 typedef struct CPUMIPSState CPUMIPSState
;
524 struct CPUMIPSState
{
526 CPUMIPSFPUContext active_fpu
;
529 uint32_t current_fpu
;
533 #if defined(TARGET_MIPS64)
534 # define PABITS_BASE 36
536 # define PABITS_BASE 32
538 target_ulong SEGMask
;
540 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
543 #define MSAIR_ProcID 8
550 /* CP0_MVP* are per MVP registers. */
551 int32_t CP0_VPControl
;
552 #define CP0VPCtl_DIS 0
557 int32_t CP0_VPEControl
;
558 #define CP0VPECo_YSI 21
559 #define CP0VPECo_GSI 20
560 #define CP0VPECo_EXCPT 16
561 #define CP0VPECo_TE 15
562 #define CP0VPECo_TargTC 0
563 int32_t CP0_VPEConf0
;
564 #define CP0VPEC0_M 31
565 #define CP0VPEC0_XTC 21
566 #define CP0VPEC0_TCS 19
567 #define CP0VPEC0_SCS 18
568 #define CP0VPEC0_DSC 17
569 #define CP0VPEC0_ICS 16
570 #define CP0VPEC0_MVP 1
571 #define CP0VPEC0_VPA 0
572 int32_t CP0_VPEConf1
;
573 #define CP0VPEC1_NCX 20
574 #define CP0VPEC1_NCP2 10
575 #define CP0VPEC1_NCP1 0
576 target_ulong CP0_YQMask
;
577 target_ulong CP0_VPESchedule
;
578 target_ulong CP0_VPEScheFBack
;
580 #define CP0VPEOpt_IWX7 15
581 #define CP0VPEOpt_IWX6 14
582 #define CP0VPEOpt_IWX5 13
583 #define CP0VPEOpt_IWX4 12
584 #define CP0VPEOpt_IWX3 11
585 #define CP0VPEOpt_IWX2 10
586 #define CP0VPEOpt_IWX1 9
587 #define CP0VPEOpt_IWX0 8
588 #define CP0VPEOpt_DWX7 7
589 #define CP0VPEOpt_DWX6 6
590 #define CP0VPEOpt_DWX5 5
591 #define CP0VPEOpt_DWX4 4
592 #define CP0VPEOpt_DWX3 3
593 #define CP0VPEOpt_DWX2 2
594 #define CP0VPEOpt_DWX1 1
595 #define CP0VPEOpt_DWX0 0
599 uint64_t CP0_EntryLo0
;
603 uint64_t CP0_EntryLo1
;
604 #if defined(TARGET_MIPS64)
605 # define CP0EnLo_RI 63
606 # define CP0EnLo_XI 62
608 # define CP0EnLo_RI 31
609 # define CP0EnLo_XI 30
611 int32_t CP0_GlobalNumber
;
616 target_ulong CP0_Context
;
617 int32_t CP0_MemoryMapID
;
621 int32_t CP0_PageMask
;
622 #define CP0PM_MASK 13
623 int32_t CP0_PageGrain_rw_bitmask
;
624 int32_t CP0_PageGrain
;
627 #define CP0PG_ELPA 29
629 target_ulong CP0_SegCtl0
;
630 target_ulong CP0_SegCtl1
;
631 target_ulong CP0_SegCtl2
;
633 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
634 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
636 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
637 #define CP0SC_AM_UK 0ULL
638 #define CP0SC_AM_MK 1ULL
639 #define CP0SC_AM_MSK 2ULL
640 #define CP0SC_AM_MUSK 3ULL
641 #define CP0SC_AM_MUSUK 4ULL
642 #define CP0SC_AM_USK 5ULL
643 #define CP0SC_AM_UUSK 7ULL
645 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
647 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
648 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
650 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
652 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
653 #define CP0SC1_XAM 59
654 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
655 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
657 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
658 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
659 target_ulong CP0_PWBase
;
660 target_ulong CP0_PWField
;
661 #if defined(TARGET_MIPS64)
662 #define CP0PF_BDI 32 /* 37..32 */
663 #define CP0PF_GDI 24 /* 29..24 */
664 #define CP0PF_UDI 18 /* 23..18 */
665 #define CP0PF_MDI 12 /* 17..12 */
666 #define CP0PF_PTI 6 /* 11..6 */
667 #define CP0PF_PTEI 0 /* 5..0 */
669 #define CP0PF_GDW 24 /* 29..24 */
670 #define CP0PF_UDW 18 /* 23..18 */
671 #define CP0PF_MDW 12 /* 17..12 */
672 #define CP0PF_PTW 6 /* 11..6 */
673 #define CP0PF_PTEW 0 /* 5..0 */
675 target_ulong CP0_PWSize
;
676 #if defined(TARGET_MIPS64)
677 #define CP0PS_BDW 32 /* 37..32 */
680 #define CP0PS_GDW 24 /* 29..24 */
681 #define CP0PS_UDW 18 /* 23..18 */
682 #define CP0PS_MDW 12 /* 17..12 */
683 #define CP0PS_PTW 6 /* 11..6 */
684 #define CP0PS_PTEW 0 /* 5..0 */
690 #define CP0PC_PWEN 31
691 #if defined(TARGET_MIPS64)
692 #define CP0PC_PWDIREXT 30
698 #define CP0PC_HUGEPG 6
699 #define CP0PC_PSN 0 /* 5..0 */
700 int32_t CP0_SRSConf0_rw_bitmask
;
701 int32_t CP0_SRSConf0
;
702 #define CP0SRSC0_M 31
703 #define CP0SRSC0_SRS3 20
704 #define CP0SRSC0_SRS2 10
705 #define CP0SRSC0_SRS1 0
706 int32_t CP0_SRSConf1_rw_bitmask
;
707 int32_t CP0_SRSConf1
;
708 #define CP0SRSC1_M 31
709 #define CP0SRSC1_SRS6 20
710 #define CP0SRSC1_SRS5 10
711 #define CP0SRSC1_SRS4 0
712 int32_t CP0_SRSConf2_rw_bitmask
;
713 int32_t CP0_SRSConf2
;
714 #define CP0SRSC2_M 31
715 #define CP0SRSC2_SRS9 20
716 #define CP0SRSC2_SRS8 10
717 #define CP0SRSC2_SRS7 0
718 int32_t CP0_SRSConf3_rw_bitmask
;
719 int32_t CP0_SRSConf3
;
720 #define CP0SRSC3_M 31
721 #define CP0SRSC3_SRS12 20
722 #define CP0SRSC3_SRS11 10
723 #define CP0SRSC3_SRS10 0
724 int32_t CP0_SRSConf4_rw_bitmask
;
725 int32_t CP0_SRSConf4
;
726 #define CP0SRSC4_SRS15 20
727 #define CP0SRSC4_SRS14 10
728 #define CP0SRSC4_SRS13 0
736 target_ulong CP0_BadVAddr
;
737 uint32_t CP0_BadInstr
;
738 uint32_t CP0_BadInstrP
;
739 uint32_t CP0_BadInstrX
;
745 #define CP0SAARI_TARGET 0 /* 5..0 */
746 uint64_t CP0_SAAR
[2];
747 #define CP0SAAR_BASE 12 /* 43..12 */
748 #define CP0SAAR_SIZE 1 /* 5..1 */
753 target_ulong CP0_EntryHi
;
754 #define CP0EnHi_EHINV 10
755 target_ulong CP0_EntryHi_ASID_mask
;
786 #define CP0IntCtl_IPTI 29
787 #define CP0IntCtl_IPPCI 26
788 #define CP0IntCtl_VS 5
790 #define CP0SRSCtl_HSS 26
791 #define CP0SRSCtl_EICSS 18
792 #define CP0SRSCtl_ESS 12
793 #define CP0SRSCtl_PSS 6
794 #define CP0SRSCtl_CSS 0
796 #define CP0SRSMap_SSV7 28
797 #define CP0SRSMap_SSV6 24
798 #define CP0SRSMap_SSV5 20
799 #define CP0SRSMap_SSV4 16
800 #define CP0SRSMap_SSV3 12
801 #define CP0SRSMap_SSV2 8
802 #define CP0SRSMap_SSV1 4
803 #define CP0SRSMap_SSV0 0
816 #define CP0Ca_IP_mask 0x0000FF00
821 target_ulong CP0_EPC
;
826 target_ulong CP0_EBase
;
827 target_ulong CP0_EBaseWG_rw_bitmask
;
828 #define CP0EBase_WG 11
829 target_ulong CP0_CMGCRBase
;
831 * CP0 Register 16 (after Release 1)
835 #define CP0C0_K23 28 /* 30..28 */
836 #define CP0C0_KU 25 /* 27..25 */
840 #define CP0C0_Impl 16 /* 24..16 */
842 #define CP0C0_AT 13 /* 14..13 */
843 #define CP0C0_AR 10 /* 12..10 */
844 #define CP0C0_MT 7 /* 9..7 */
846 #define CP0C0_K0 0 /* 2..0 */
847 #define CP0C0_AR_LENGTH 3
849 * CP0 Register 16 (before Release 1)
851 #define CP0C0_Impl 16 /* 24..16 */
852 #define CP0C0_IC 9 /* 11..9 */
853 #define CP0C0_DC 6 /* 8..6 */
858 #define CP0C1_MMU 25 /* 30..25 */
859 #define CP0C1_IS 22 /* 24..22 */
860 #define CP0C1_IL 19 /* 21..19 */
861 #define CP0C1_IA 16 /* 18..16 */
862 #define CP0C1_DS 13 /* 15..13 */
863 #define CP0C1_DL 10 /* 12..10 */
864 #define CP0C1_DA 7 /* 9..7 */
874 #define CP0C2_TU 28 /* 30..28 */
875 #define CP0C2_TS 24 /* 27..24 */
876 #define CP0C2_TL 20 /* 23..20 */
877 #define CP0C2_TA 16 /* 19..16 */
878 #define CP0C2_SU 12 /* 15..12 */
879 #define CP0C2_SS 8 /* 11..8 */
880 #define CP0C2_SL 4 /* 7..4 */
881 #define CP0C2_SA 0 /* 3..0 */
885 #define CP0C3_CMGCR 29
886 #define CP0C3_MSAP 28
892 #define CP0C3_IPLV 21 /* 22..21 */
893 #define CP0C3_MMAR 18 /* 20..18 */
895 #define CP0C3_ISA_ON_EXC 16
896 #define CP0C3_ISA 14 /* 15..14 */
897 #define CP0C3_ULRI 13
899 #define CP0C3_DSP2P 11
900 #define CP0C3_DSPP 10
901 #define CP0C3_CTXTC 9
912 int32_t CP0_Config4_rw_bitmask
;
914 #define CP0C4_IE 29 /* 30..29 */
916 #define CP0C4_VTLBSizeExt 24 /* 27..24 */
917 #define CP0C4_KScrExist 16
918 #define CP0C4_MMUExtDef 14
919 #define CP0C4_FTLBPageSize 8 /* 12..8 */
920 /* bit layout if MMUExtDef=1 */
921 #define CP0C4_MMUSizeExt 0 /* 7..0 */
922 /* bit layout if MMUExtDef=2 */
923 #define CP0C4_FTLBWays 4 /* 7..4 */
924 #define CP0C4_FTLBSets 0 /* 3..0 */
926 int32_t CP0_Config5_rw_bitmask
;
931 #define CP0C5_MSAEn 27
932 #define CP0C5_PMJ 23 /* 25..23 */
937 #define CP0C5_CRCP 18
939 #define CP0C5_GI 15 /* 16..15 */
952 #define CP0C5_NFExists 0
954 int32_t CP0_Config6_rw_bitmask
;
955 #define CP0C6_BPPASS 31
956 #define CP0C6_KPOS 24
958 #define CP0C6_VTLBONLY 22
959 #define CP0C6_LASX 21
960 #define CP0C6_SSEN 20
961 #define CP0C6_DISDRTIME 19
962 #define CP0C6_PIXNUEN 18
963 #define CP0C6_SCRAND 17
964 #define CP0C6_LLEXCEN 16
965 #define CP0C6_DISVC 15
966 #define CP0C6_VCLRU 14
967 #define CP0C6_DCLRU 13
968 #define CP0C6_PIXUEN 12
969 #define CP0C6_DISBLKLYEN 11
970 #define CP0C6_UMEMUALEN 10
971 #define CP0C6_SFBEN 8
972 #define CP0C6_FLTINT 7
973 #define CP0C6_VLTINT 6
974 #define CP0C6_DISBTB 5
975 #define CP0C6_STPREFCTL 2
976 #define CP0C6_INSTPREF 1
977 #define CP0C6_DATAPREF 0
979 int64_t CP0_Config7_rw_bitmask
;
980 #define CP0C7_NAPCGEN 2
981 #define CP0C7_UNIMUEN 1
982 #define CP0C7_VFPUCGEN 0
984 uint64_t CP0_MAAR
[MIPS_MAAR_MAX
];
986 /* XXX: Maybe make LLAddr per-TC? */
990 target_ulong lladdr
; /* LL virtual address compared against SC */
993 uint32_t llnewval_wp
;
994 uint64_t CP0_LLAddr_rw_bitmask
;
995 int CP0_LLAddr_shift
;
999 target_ulong CP0_WatchLo
[8];
1003 uint64_t CP0_WatchHi
[8];
1004 #define CP0WH_ASID 16
1008 target_ulong CP0_XContext
;
1009 int32_t CP0_Framemask
;
1014 #define CP0DB_DBD 31
1016 #define CP0DB_LSNM 28
1017 #define CP0DB_Doze 27
1018 #define CP0DB_Halt 26
1019 #define CP0DB_CNT 25
1020 #define CP0DB_IBEP 24
1021 #define CP0DB_DBEP 21
1022 #define CP0DB_IEXI 20
1023 #define CP0DB_VER 15
1024 #define CP0DB_DEC 10
1026 #define CP0DB_DINT 5
1028 #define CP0DB_DDBS 3
1029 #define CP0DB_DDBL 2
1035 target_ulong CP0_DEPC
;
1039 int32_t CP0_Performance0
;
1044 #define CP0EC_WST 29
1045 #define CP0EC_SPR 28
1046 #define CP0EC_ITC 26
1060 target_ulong CP0_ErrorEPC
;
1065 target_ulong CP0_KScratch
[MIPS_KSCRATCH_NUM
];
1067 /* We waste some space so we can handle shadow registers like TCs. */
1068 TCState tcs
[MIPS_SHADOW_SET_MAX
];
1069 CPUMIPSFPUContext fpus
[MIPS_FPU_MAX
];
1072 #define EXCP_TLB_NOMATCH 0x1
1073 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1074 uint32_t hflags
; /* CPU State */
1075 /* TMASK defines different execution modes */
1076 #define MIPS_HFLAG_TMASK 0x1F5807FF
1077 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
1079 * The KSU flags must be the lowest bits in hflags. The flag order
1080 * must be the same as defined for CP0 Status. This allows to use
1081 * the bits as the value of mmu_idx.
1083 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
1084 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
1085 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
1086 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
1087 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
1088 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
1089 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
1090 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
1091 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
1093 * True if the MIPS IV COP1X instructions can be used. This also
1094 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1097 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
1098 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
1099 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
1100 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
1101 #define MIPS_HFLAG_M16_SHIFT 10
1103 * If translation is interrupted between the branch instruction and
1104 * the delay slot, record what type of branch it is so that we can
1105 * resume translation properly. It might be possible to reduce
1106 * this from three bits to two.
1108 #define MIPS_HFLAG_BMASK_BASE 0x803800
1109 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
1110 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
1111 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
1112 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
1113 /* Extra flags about the current pending branch. */
1114 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1115 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
1116 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
1117 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
1118 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
1119 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
1120 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1121 /* MIPS DSP resources access. */
1122 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
1123 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
1124 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1125 /* Extra flag about HWREna register. */
1126 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1127 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1128 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
1129 #define MIPS_HFLAG_MSA 0x1000000
1130 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
1131 #define MIPS_HFLAG_ELPA 0x4000000
1132 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
1133 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
1134 target_ulong btarget
; /* Jump / branch target */
1135 target_ulong bcond
; /* Branch condition (if needed) */
1137 int SYNCI_Step
; /* Address step size for SYNCI */
1138 int CCRes
; /* Cycle count resolution/divisor */
1139 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
1140 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
1141 uint64_t insn_flags
; /* Supported instruction set */
1144 /* Fields up to this point are cleared by a CPU reset */
1145 struct {} end_reset_fields
;
1147 /* Fields from here on are preserved across CPU reset. */
1148 CPUMIPSMVPContext
*mvp
;
1149 #if !defined(CONFIG_USER_ONLY)
1150 CPUMIPSTLBContext
*tlb
;
1153 const mips_def_t
*cpu_model
;
1155 QEMUTimer
*timer
; /* Internal timer */
1156 struct MIPSITUState
*itu
;
1157 MemoryRegion
*itc_tag
; /* ITC Configuration Tags */
1158 target_ulong exception_base
; /* ExceptionBase input to the core */
1159 uint64_t cp0_count_ns
; /* CP0_Count clock period (in nanoseconds) */
1164 * @env: #CPUMIPSState
1165 * @clock: this CPU input clock (may be connected
1166 * to an output clock from another device).
1167 * @cp0_count_rate: rate at which the coprocessor 0 counter increments
1173 CPUState parent_obj
;
1177 CPUNegativeOffsetState neg
;
1180 * The Count register acts as a timer, incrementing at a constant rate,
1181 * whether or not an instruction is executed, retired, or any forward
1182 * progress is made through the pipeline. The rate at which the counter
1183 * increments is implementation dependent, and is a function of the
1184 * pipeline clock of the processor, not the issue width of the processor.
1186 unsigned cp0_count_rate
;
1190 void mips_cpu_list(void);
1192 #define cpu_signal_handler cpu_mips_signal_handler
1193 #define cpu_list mips_cpu_list
1195 extern void cpu_wrdsp(uint32_t rs
, uint32_t mask_num
, CPUMIPSState
*env
);
1196 extern uint32_t cpu_rddsp(uint32_t mask_num
, CPUMIPSState
*env
);
1199 * MMU modes definitions. We carefully match the indices with our
1202 #define MMU_USER_IDX 2
1204 static inline int hflags_mmu_index(uint32_t hflags
)
1206 if (hflags
& MIPS_HFLAG_ERL
) {
1209 return hflags
& MIPS_HFLAG_KSU
;
1213 static inline int cpu_mmu_index(CPUMIPSState
*env
, bool ifetch
)
1215 return hflags_mmu_index(env
->hflags
);
1218 typedef CPUMIPSState CPUArchState
;
1219 typedef MIPSCPU ArchCPU
;
1221 #include "exec/cpu-all.h"
1224 * Memory access type :
1225 * may be needed for precise access rights control and precise exceptions.
1228 /* 1 bit to define user level / supervisor access */
1230 ACCESS_SUPER
= 0x01,
1231 /* 1 bit to indicate direction */
1232 ACCESS_STORE
= 0x02,
1233 /* Type of instruction that generated the access */
1234 ACCESS_CODE
= 0x10, /* Code fetch access */
1235 ACCESS_INT
= 0x20, /* Integer load/store access */
1236 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
1250 EXCP_EXT_INTERRUPT
, /* 8 */
1266 EXCP_DWATCH
, /* 24 */
1274 EXCP_CACHE
, /* 32 */
1281 EXCP_LAST
= EXCP_TLBRI
,
1285 * This is an internally generated WAKE request line.
1286 * It is driven by the CPU itself. Raised when the MT
1287 * block wants to wake a VPE from an inactive state and
1288 * cleared when VPE goes from active to inactive.
1290 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1292 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
1294 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1295 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1296 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1298 bool cpu_type_supports_cps_smp(const char *cpu_type
);
1299 bool cpu_supports_isa(const CPUMIPSState
*env
, uint64_t isa_mask
);
1300 bool cpu_type_supports_isa(const char *cpu_type
, uint64_t isa
);
1302 /* Check presence of MSA implementation */
1303 static inline bool ase_msa_available(CPUMIPSState
*env
)
1305 return env
->CP0_Config3
& (1 << CP0C3_MSAP
);
1308 /* Check presence of multi-threading ASE implementation */
1309 static inline bool ase_mt_available(CPUMIPSState
*env
)
1311 return env
->CP0_Config3
& (1 << CP0C3_MT
);
1314 static inline bool cpu_type_is_64bit(const char *cpu_type
)
1316 return cpu_type_supports_isa(cpu_type
, CPU_MIPS64
);
1319 void cpu_set_exception_base(int vp_index
, target_ulong address
);
1322 uint64_t cpu_mips_kseg0_to_phys(void *opaque
, uint64_t addr
);
1323 uint64_t cpu_mips_phys_to_kseg0(void *opaque
, uint64_t addr
);
1325 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque
, uint64_t addr
);
1326 uint64_t cpu_mips_kseg1_to_phys(void *opaque
, uint64_t addr
);
1327 uint64_t cpu_mips_phys_to_kseg1(void *opaque
, uint64_t addr
);
1328 bool mips_um_ksegs_enabled(void);
1329 void mips_um_ksegs_enable(void);
1332 void cpu_mips_soft_irq(CPUMIPSState
*env
, int irq
, int level
);
1335 void itc_reconfigure(struct MIPSITUState
*tag
);
1338 target_ulong
exception_resume_pc(CPUMIPSState
*env
);
1340 static inline void cpu_get_tb_cpu_state(CPUMIPSState
*env
, target_ulong
*pc
,
1341 target_ulong
*cs_base
, uint32_t *flags
)
1343 *pc
= env
->active_tc
.PC
;
1345 *flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
|
1346 MIPS_HFLAG_HWRENA_ULR
);
1350 * mips_cpu_create_with_clock:
1351 * @typename: a MIPS CPU type.
1352 * @cpu_refclk: this cpu input clock (an output clock of another device)
1354 * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
1355 * then realizes the CPU.
1357 * Returns: A #CPUState or %NULL if an error occurred.
1359 MIPSCPU
*mips_cpu_create_with_clock(const char *cpu_type
, Clock
*cpu_refclk
);
1361 #endif /* MIPS_CPU_H */