2 * RISC-V Vector Extension Helpers for QEMU.
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/memop.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "fpu/softfloat.h"
25 #include "tcg/tcg-gvec-desc.h"
26 #include "internals.h"
29 target_ulong
HELPER(vsetvl
)(CPURISCVState
*env
, target_ulong s1
,
33 RISCVCPU
*cpu
= env_archcpu(env
);
34 uint16_t sew
= 8 << FIELD_EX64(s2
, VTYPE
, VSEW
);
35 uint8_t ediv
= FIELD_EX64(s2
, VTYPE
, VEDIV
);
36 bool vill
= FIELD_EX64(s2
, VTYPE
, VILL
);
37 target_ulong reserved
= FIELD_EX64(s2
, VTYPE
, RESERVED
);
39 if ((sew
> cpu
->cfg
.elen
) || vill
|| (ediv
!= 0) || (reserved
!= 0)) {
40 /* only set vill bit. */
41 env
->vtype
= FIELD_DP64(0, VTYPE
, VILL
, 1);
47 vlmax
= vext_get_vlmax(cpu
, s2
);
60 * Note that vector data is stored in host-endian 64-bit chunks,
61 * so addressing units smaller than that needs a host-endian fixup.
63 #ifdef HOST_WORDS_BIGENDIAN
64 #define H1(x) ((x) ^ 7)
65 #define H1_2(x) ((x) ^ 6)
66 #define H1_4(x) ((x) ^ 4)
67 #define H2(x) ((x) ^ 3)
68 #define H4(x) ((x) ^ 1)
79 static inline uint32_t vext_nf(uint32_t desc
)
81 return FIELD_EX32(simd_data(desc
), VDATA
, NF
);
84 static inline uint32_t vext_mlen(uint32_t desc
)
86 return FIELD_EX32(simd_data(desc
), VDATA
, MLEN
);
89 static inline uint32_t vext_vm(uint32_t desc
)
91 return FIELD_EX32(simd_data(desc
), VDATA
, VM
);
94 static inline uint32_t vext_lmul(uint32_t desc
)
96 return FIELD_EX32(simd_data(desc
), VDATA
, LMUL
);
99 static uint32_t vext_wd(uint32_t desc
)
101 return (simd_data(desc
) >> 11) & 0x1;
105 * Get vector group length in bytes. Its range is [64, 2048].
107 * As simd_desc support at most 256, the max vlen is 512 bits.
108 * So vlen in bytes is encoded as maxsz.
110 static inline uint32_t vext_maxsz(uint32_t desc
)
112 return simd_maxsz(desc
) << vext_lmul(desc
);
116 * This function checks watchpoint before real load operation.
118 * In softmmu mode, the TLB API probe_access is enough for watchpoint check.
119 * In user mode, there is no watchpoint support now.
121 * It will trigger an exception if there is no mapping in TLB
122 * and page table walk can't fill the TLB entry. Then the guest
123 * software can return here after process the exception or never return.
125 static void probe_pages(CPURISCVState
*env
, target_ulong addr
,
126 target_ulong len
, uintptr_t ra
,
127 MMUAccessType access_type
)
129 target_ulong pagelen
= -(addr
| TARGET_PAGE_MASK
);
130 target_ulong curlen
= MIN(pagelen
, len
);
132 probe_access(env
, addr
, curlen
, access_type
,
133 cpu_mmu_index(env
, false), ra
);
136 curlen
= len
- curlen
;
137 probe_access(env
, addr
, curlen
, access_type
,
138 cpu_mmu_index(env
, false), ra
);
142 #ifdef HOST_WORDS_BIGENDIAN
143 static void vext_clear(void *tail
, uint32_t cnt
, uint32_t tot
)
146 * Split the remaining range to two parts.
147 * The first part is in the last uint64_t unit.
148 * The second part start from the next uint64_t unit.
150 int part1
= 0, part2
= tot
- cnt
;
152 part1
= 8 - (cnt
% 8);
153 part2
= tot
- cnt
- part1
;
154 memset((void *)((uintptr_t)tail
& ~(7ULL)), 0, part1
);
155 memset((void *)(((uintptr_t)tail
+ 8) & ~(7ULL)), 0, part2
);
157 memset(tail
, 0, part2
);
161 static void vext_clear(void *tail
, uint32_t cnt
, uint32_t tot
)
163 memset(tail
, 0, tot
- cnt
);
167 static void clearb(void *vd
, uint32_t idx
, uint32_t cnt
, uint32_t tot
)
169 int8_t *cur
= ((int8_t *)vd
+ H1(idx
));
170 vext_clear(cur
, cnt
, tot
);
173 static void clearh(void *vd
, uint32_t idx
, uint32_t cnt
, uint32_t tot
)
175 int16_t *cur
= ((int16_t *)vd
+ H2(idx
));
176 vext_clear(cur
, cnt
, tot
);
179 static void clearl(void *vd
, uint32_t idx
, uint32_t cnt
, uint32_t tot
)
181 int32_t *cur
= ((int32_t *)vd
+ H4(idx
));
182 vext_clear(cur
, cnt
, tot
);
185 static void clearq(void *vd
, uint32_t idx
, uint32_t cnt
, uint32_t tot
)
187 int64_t *cur
= (int64_t *)vd
+ idx
;
188 vext_clear(cur
, cnt
, tot
);
191 static inline void vext_set_elem_mask(void *v0
, int mlen
, int index
,
194 int idx
= (index
* mlen
) / 64;
195 int pos
= (index
* mlen
) % 64;
196 uint64_t old
= ((uint64_t *)v0
)[idx
];
197 ((uint64_t *)v0
)[idx
] = deposit64(old
, pos
, mlen
, value
);
200 static inline int vext_elem_mask(void *v0
, int mlen
, int index
)
202 int idx
= (index
* mlen
) / 64;
203 int pos
= (index
* mlen
) % 64;
204 return (((uint64_t *)v0
)[idx
] >> pos
) & 1;
207 /* elements operations for load and store */
208 typedef void vext_ldst_elem_fn(CPURISCVState
*env
, target_ulong addr
,
209 uint32_t idx
, void *vd
, uintptr_t retaddr
);
210 typedef void clear_fn(void *vd
, uint32_t idx
, uint32_t cnt
, uint32_t tot
);
212 #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
213 static void NAME(CPURISCVState *env, abi_ptr addr, \
214 uint32_t idx, void *vd, uintptr_t retaddr)\
217 ETYPE *cur = ((ETYPE *)vd + H(idx)); \
218 data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
222 GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
223 GEN_VEXT_LD_ELEM(ldb_h
, int8_t, int16_t, H2
, ldsb
)
224 GEN_VEXT_LD_ELEM(ldb_w
, int8_t, int32_t, H4
, ldsb
)
225 GEN_VEXT_LD_ELEM(ldb_d
, int8_t, int64_t, H8
, ldsb
)
226 GEN_VEXT_LD_ELEM(ldh_h
, int16_t, int16_t, H2
, ldsw
)
227 GEN_VEXT_LD_ELEM(ldh_w
, int16_t, int32_t, H4
, ldsw
)
228 GEN_VEXT_LD_ELEM(ldh_d
, int16_t, int64_t, H8
, ldsw
)
229 GEN_VEXT_LD_ELEM(ldw_w
, int32_t, int32_t, H4
, ldl
)
230 GEN_VEXT_LD_ELEM(ldw_d
, int32_t, int64_t, H8
, ldl
)
231 GEN_VEXT_LD_ELEM(lde_b
, int8_t, int8_t, H1
, ldsb
)
232 GEN_VEXT_LD_ELEM(lde_h
, int16_t, int16_t, H2
, ldsw
)
233 GEN_VEXT_LD_ELEM(lde_w
, int32_t, int32_t, H4
, ldl
)
234 GEN_VEXT_LD_ELEM(lde_d
, int64_t, int64_t, H8
, ldq
)
235 GEN_VEXT_LD_ELEM(ldbu_b
, uint8_t, uint8_t, H1
, ldub
)
236 GEN_VEXT_LD_ELEM(ldbu_h
, uint8_t, uint16_t, H2
, ldub
)
237 GEN_VEXT_LD_ELEM(ldbu_w
, uint8_t, uint32_t, H4
, ldub
)
238 GEN_VEXT_LD_ELEM(ldbu_d
, uint8_t, uint64_t, H8
, ldub
)
239 GEN_VEXT_LD_ELEM(ldhu_h
, uint16_t, uint16_t, H2
, lduw
)
240 GEN_VEXT_LD_ELEM(ldhu_w
, uint16_t, uint32_t, H4
, lduw
)
241 GEN_VEXT_LD_ELEM(ldhu_d
, uint16_t, uint64_t, H8
, lduw
)
242 GEN_VEXT_LD_ELEM(ldwu_w
, uint32_t, uint32_t, H4
, ldl
)
243 GEN_VEXT_LD_ELEM(ldwu_d
, uint32_t, uint64_t, H8
, ldl
)
245 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
246 static void NAME(CPURISCVState *env, abi_ptr addr, \
247 uint32_t idx, void *vd, uintptr_t retaddr)\
249 ETYPE data = *((ETYPE *)vd + H(idx)); \
250 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
253 GEN_VEXT_ST_ELEM(stb_b
, int8_t, H1
, stb
)
254 GEN_VEXT_ST_ELEM(stb_h
, int16_t, H2
, stb
)
255 GEN_VEXT_ST_ELEM(stb_w
, int32_t, H4
, stb
)
256 GEN_VEXT_ST_ELEM(stb_d
, int64_t, H8
, stb
)
257 GEN_VEXT_ST_ELEM(sth_h
, int16_t, H2
, stw
)
258 GEN_VEXT_ST_ELEM(sth_w
, int32_t, H4
, stw
)
259 GEN_VEXT_ST_ELEM(sth_d
, int64_t, H8
, stw
)
260 GEN_VEXT_ST_ELEM(stw_w
, int32_t, H4
, stl
)
261 GEN_VEXT_ST_ELEM(stw_d
, int64_t, H8
, stl
)
262 GEN_VEXT_ST_ELEM(ste_b
, int8_t, H1
, stb
)
263 GEN_VEXT_ST_ELEM(ste_h
, int16_t, H2
, stw
)
264 GEN_VEXT_ST_ELEM(ste_w
, int32_t, H4
, stl
)
265 GEN_VEXT_ST_ELEM(ste_d
, int64_t, H8
, stq
)
268 *** stride: access vector element from strided memory
271 vext_ldst_stride(void *vd
, void *v0
, target_ulong base
,
272 target_ulong stride
, CPURISCVState
*env
,
273 uint32_t desc
, uint32_t vm
,
274 vext_ldst_elem_fn
*ldst_elem
, clear_fn
*clear_elem
,
275 uint32_t esz
, uint32_t msz
, uintptr_t ra
,
276 MMUAccessType access_type
)
279 uint32_t nf
= vext_nf(desc
);
280 uint32_t mlen
= vext_mlen(desc
);
281 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
283 /* probe every access*/
284 for (i
= 0; i
< env
->vl
; i
++) {
285 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
288 probe_pages(env
, base
+ stride
* i
, nf
* msz
, ra
, access_type
);
291 for (i
= 0; i
< env
->vl
; i
++) {
293 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
297 target_ulong addr
= base
+ stride
* i
+ k
* msz
;
298 ldst_elem(env
, addr
, i
+ k
* vlmax
, vd
, ra
);
302 /* clear tail elements */
304 for (k
= 0; k
< nf
; k
++) {
305 clear_elem(vd
, env
->vl
+ k
* vlmax
, env
->vl
* esz
, vlmax
* esz
);
310 #define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
311 void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
312 target_ulong stride, CPURISCVState *env, \
315 uint32_t vm = vext_vm(desc); \
316 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
317 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
318 GETPC(), MMU_DATA_LOAD); \
321 GEN_VEXT_LD_STRIDE(vlsb_v_b
, int8_t, int8_t, ldb_b
, clearb
)
322 GEN_VEXT_LD_STRIDE(vlsb_v_h
, int8_t, int16_t, ldb_h
, clearh
)
323 GEN_VEXT_LD_STRIDE(vlsb_v_w
, int8_t, int32_t, ldb_w
, clearl
)
324 GEN_VEXT_LD_STRIDE(vlsb_v_d
, int8_t, int64_t, ldb_d
, clearq
)
325 GEN_VEXT_LD_STRIDE(vlsh_v_h
, int16_t, int16_t, ldh_h
, clearh
)
326 GEN_VEXT_LD_STRIDE(vlsh_v_w
, int16_t, int32_t, ldh_w
, clearl
)
327 GEN_VEXT_LD_STRIDE(vlsh_v_d
, int16_t, int64_t, ldh_d
, clearq
)
328 GEN_VEXT_LD_STRIDE(vlsw_v_w
, int32_t, int32_t, ldw_w
, clearl
)
329 GEN_VEXT_LD_STRIDE(vlsw_v_d
, int32_t, int64_t, ldw_d
, clearq
)
330 GEN_VEXT_LD_STRIDE(vlse_v_b
, int8_t, int8_t, lde_b
, clearb
)
331 GEN_VEXT_LD_STRIDE(vlse_v_h
, int16_t, int16_t, lde_h
, clearh
)
332 GEN_VEXT_LD_STRIDE(vlse_v_w
, int32_t, int32_t, lde_w
, clearl
)
333 GEN_VEXT_LD_STRIDE(vlse_v_d
, int64_t, int64_t, lde_d
, clearq
)
334 GEN_VEXT_LD_STRIDE(vlsbu_v_b
, uint8_t, uint8_t, ldbu_b
, clearb
)
335 GEN_VEXT_LD_STRIDE(vlsbu_v_h
, uint8_t, uint16_t, ldbu_h
, clearh
)
336 GEN_VEXT_LD_STRIDE(vlsbu_v_w
, uint8_t, uint32_t, ldbu_w
, clearl
)
337 GEN_VEXT_LD_STRIDE(vlsbu_v_d
, uint8_t, uint64_t, ldbu_d
, clearq
)
338 GEN_VEXT_LD_STRIDE(vlshu_v_h
, uint16_t, uint16_t, ldhu_h
, clearh
)
339 GEN_VEXT_LD_STRIDE(vlshu_v_w
, uint16_t, uint32_t, ldhu_w
, clearl
)
340 GEN_VEXT_LD_STRIDE(vlshu_v_d
, uint16_t, uint64_t, ldhu_d
, clearq
)
341 GEN_VEXT_LD_STRIDE(vlswu_v_w
, uint32_t, uint32_t, ldwu_w
, clearl
)
342 GEN_VEXT_LD_STRIDE(vlswu_v_d
, uint32_t, uint64_t, ldwu_d
, clearq
)
344 #define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
345 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
346 target_ulong stride, CPURISCVState *env, \
349 uint32_t vm = vext_vm(desc); \
350 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
351 NULL, sizeof(ETYPE), sizeof(MTYPE), \
352 GETPC(), MMU_DATA_STORE); \
355 GEN_VEXT_ST_STRIDE(vssb_v_b
, int8_t, int8_t, stb_b
)
356 GEN_VEXT_ST_STRIDE(vssb_v_h
, int8_t, int16_t, stb_h
)
357 GEN_VEXT_ST_STRIDE(vssb_v_w
, int8_t, int32_t, stb_w
)
358 GEN_VEXT_ST_STRIDE(vssb_v_d
, int8_t, int64_t, stb_d
)
359 GEN_VEXT_ST_STRIDE(vssh_v_h
, int16_t, int16_t, sth_h
)
360 GEN_VEXT_ST_STRIDE(vssh_v_w
, int16_t, int32_t, sth_w
)
361 GEN_VEXT_ST_STRIDE(vssh_v_d
, int16_t, int64_t, sth_d
)
362 GEN_VEXT_ST_STRIDE(vssw_v_w
, int32_t, int32_t, stw_w
)
363 GEN_VEXT_ST_STRIDE(vssw_v_d
, int32_t, int64_t, stw_d
)
364 GEN_VEXT_ST_STRIDE(vsse_v_b
, int8_t, int8_t, ste_b
)
365 GEN_VEXT_ST_STRIDE(vsse_v_h
, int16_t, int16_t, ste_h
)
366 GEN_VEXT_ST_STRIDE(vsse_v_w
, int32_t, int32_t, ste_w
)
367 GEN_VEXT_ST_STRIDE(vsse_v_d
, int64_t, int64_t, ste_d
)
370 *** unit-stride: access elements stored contiguously in memory
373 /* unmasked unit-stride load and store operation*/
375 vext_ldst_us(void *vd
, target_ulong base
, CPURISCVState
*env
, uint32_t desc
,
376 vext_ldst_elem_fn
*ldst_elem
, clear_fn
*clear_elem
,
377 uint32_t esz
, uint32_t msz
, uintptr_t ra
,
378 MMUAccessType access_type
)
381 uint32_t nf
= vext_nf(desc
);
382 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
384 /* probe every access */
385 probe_pages(env
, base
, env
->vl
* nf
* msz
, ra
, access_type
);
386 /* load bytes from guest memory */
387 for (i
= 0; i
< env
->vl
; i
++) {
390 target_ulong addr
= base
+ (i
* nf
+ k
) * msz
;
391 ldst_elem(env
, addr
, i
+ k
* vlmax
, vd
, ra
);
395 /* clear tail elements */
397 for (k
= 0; k
< nf
; k
++) {
398 clear_elem(vd
, env
->vl
+ k
* vlmax
, env
->vl
* esz
, vlmax
* esz
);
404 * masked unit-stride load and store operation will be a special case of stride,
405 * stride = NF * sizeof (MTYPE)
408 #define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
409 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
410 CPURISCVState *env, uint32_t desc) \
412 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
413 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
414 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
415 GETPC(), MMU_DATA_LOAD); \
418 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
419 CPURISCVState *env, uint32_t desc) \
421 vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
422 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
425 GEN_VEXT_LD_US(vlb_v_b
, int8_t, int8_t, ldb_b
, clearb
)
426 GEN_VEXT_LD_US(vlb_v_h
, int8_t, int16_t, ldb_h
, clearh
)
427 GEN_VEXT_LD_US(vlb_v_w
, int8_t, int32_t, ldb_w
, clearl
)
428 GEN_VEXT_LD_US(vlb_v_d
, int8_t, int64_t, ldb_d
, clearq
)
429 GEN_VEXT_LD_US(vlh_v_h
, int16_t, int16_t, ldh_h
, clearh
)
430 GEN_VEXT_LD_US(vlh_v_w
, int16_t, int32_t, ldh_w
, clearl
)
431 GEN_VEXT_LD_US(vlh_v_d
, int16_t, int64_t, ldh_d
, clearq
)
432 GEN_VEXT_LD_US(vlw_v_w
, int32_t, int32_t, ldw_w
, clearl
)
433 GEN_VEXT_LD_US(vlw_v_d
, int32_t, int64_t, ldw_d
, clearq
)
434 GEN_VEXT_LD_US(vle_v_b
, int8_t, int8_t, lde_b
, clearb
)
435 GEN_VEXT_LD_US(vle_v_h
, int16_t, int16_t, lde_h
, clearh
)
436 GEN_VEXT_LD_US(vle_v_w
, int32_t, int32_t, lde_w
, clearl
)
437 GEN_VEXT_LD_US(vle_v_d
, int64_t, int64_t, lde_d
, clearq
)
438 GEN_VEXT_LD_US(vlbu_v_b
, uint8_t, uint8_t, ldbu_b
, clearb
)
439 GEN_VEXT_LD_US(vlbu_v_h
, uint8_t, uint16_t, ldbu_h
, clearh
)
440 GEN_VEXT_LD_US(vlbu_v_w
, uint8_t, uint32_t, ldbu_w
, clearl
)
441 GEN_VEXT_LD_US(vlbu_v_d
, uint8_t, uint64_t, ldbu_d
, clearq
)
442 GEN_VEXT_LD_US(vlhu_v_h
, uint16_t, uint16_t, ldhu_h
, clearh
)
443 GEN_VEXT_LD_US(vlhu_v_w
, uint16_t, uint32_t, ldhu_w
, clearl
)
444 GEN_VEXT_LD_US(vlhu_v_d
, uint16_t, uint64_t, ldhu_d
, clearq
)
445 GEN_VEXT_LD_US(vlwu_v_w
, uint32_t, uint32_t, ldwu_w
, clearl
)
446 GEN_VEXT_LD_US(vlwu_v_d
, uint32_t, uint64_t, ldwu_d
, clearq
)
448 #define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
449 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
450 CPURISCVState *env, uint32_t desc) \
452 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
453 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
454 NULL, sizeof(ETYPE), sizeof(MTYPE), \
455 GETPC(), MMU_DATA_STORE); \
458 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
459 CPURISCVState *env, uint32_t desc) \
461 vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
462 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
465 GEN_VEXT_ST_US(vsb_v_b
, int8_t, int8_t , stb_b
)
466 GEN_VEXT_ST_US(vsb_v_h
, int8_t, int16_t, stb_h
)
467 GEN_VEXT_ST_US(vsb_v_w
, int8_t, int32_t, stb_w
)
468 GEN_VEXT_ST_US(vsb_v_d
, int8_t, int64_t, stb_d
)
469 GEN_VEXT_ST_US(vsh_v_h
, int16_t, int16_t, sth_h
)
470 GEN_VEXT_ST_US(vsh_v_w
, int16_t, int32_t, sth_w
)
471 GEN_VEXT_ST_US(vsh_v_d
, int16_t, int64_t, sth_d
)
472 GEN_VEXT_ST_US(vsw_v_w
, int32_t, int32_t, stw_w
)
473 GEN_VEXT_ST_US(vsw_v_d
, int32_t, int64_t, stw_d
)
474 GEN_VEXT_ST_US(vse_v_b
, int8_t, int8_t , ste_b
)
475 GEN_VEXT_ST_US(vse_v_h
, int16_t, int16_t, ste_h
)
476 GEN_VEXT_ST_US(vse_v_w
, int32_t, int32_t, ste_w
)
477 GEN_VEXT_ST_US(vse_v_d
, int64_t, int64_t, ste_d
)
480 *** index: access vector element from indexed memory
482 typedef target_ulong
vext_get_index_addr(target_ulong base
,
483 uint32_t idx
, void *vs2
);
485 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \
486 static target_ulong NAME(target_ulong base, \
487 uint32_t idx, void *vs2) \
489 return (base + *((ETYPE *)vs2 + H(idx))); \
492 GEN_VEXT_GET_INDEX_ADDR(idx_b
, int8_t, H1
)
493 GEN_VEXT_GET_INDEX_ADDR(idx_h
, int16_t, H2
)
494 GEN_VEXT_GET_INDEX_ADDR(idx_w
, int32_t, H4
)
495 GEN_VEXT_GET_INDEX_ADDR(idx_d
, int64_t, H8
)
498 vext_ldst_index(void *vd
, void *v0
, target_ulong base
,
499 void *vs2
, CPURISCVState
*env
, uint32_t desc
,
500 vext_get_index_addr get_index_addr
,
501 vext_ldst_elem_fn
*ldst_elem
,
502 clear_fn
*clear_elem
,
503 uint32_t esz
, uint32_t msz
, uintptr_t ra
,
504 MMUAccessType access_type
)
507 uint32_t nf
= vext_nf(desc
);
508 uint32_t vm
= vext_vm(desc
);
509 uint32_t mlen
= vext_mlen(desc
);
510 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
512 /* probe every access*/
513 for (i
= 0; i
< env
->vl
; i
++) {
514 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
517 probe_pages(env
, get_index_addr(base
, i
, vs2
), nf
* msz
, ra
,
520 /* load bytes from guest memory */
521 for (i
= 0; i
< env
->vl
; i
++) {
523 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
527 abi_ptr addr
= get_index_addr(base
, i
, vs2
) + k
* msz
;
528 ldst_elem(env
, addr
, i
+ k
* vlmax
, vd
, ra
);
532 /* clear tail elements */
534 for (k
= 0; k
< nf
; k
++) {
535 clear_elem(vd
, env
->vl
+ k
* vlmax
, env
->vl
* esz
, vlmax
* esz
);
540 #define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
541 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
542 void *vs2, CPURISCVState *env, uint32_t desc) \
544 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
545 LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
546 GETPC(), MMU_DATA_LOAD); \
549 GEN_VEXT_LD_INDEX(vlxb_v_b
, int8_t, int8_t, idx_b
, ldb_b
, clearb
)
550 GEN_VEXT_LD_INDEX(vlxb_v_h
, int8_t, int16_t, idx_h
, ldb_h
, clearh
)
551 GEN_VEXT_LD_INDEX(vlxb_v_w
, int8_t, int32_t, idx_w
, ldb_w
, clearl
)
552 GEN_VEXT_LD_INDEX(vlxb_v_d
, int8_t, int64_t, idx_d
, ldb_d
, clearq
)
553 GEN_VEXT_LD_INDEX(vlxh_v_h
, int16_t, int16_t, idx_h
, ldh_h
, clearh
)
554 GEN_VEXT_LD_INDEX(vlxh_v_w
, int16_t, int32_t, idx_w
, ldh_w
, clearl
)
555 GEN_VEXT_LD_INDEX(vlxh_v_d
, int16_t, int64_t, idx_d
, ldh_d
, clearq
)
556 GEN_VEXT_LD_INDEX(vlxw_v_w
, int32_t, int32_t, idx_w
, ldw_w
, clearl
)
557 GEN_VEXT_LD_INDEX(vlxw_v_d
, int32_t, int64_t, idx_d
, ldw_d
, clearq
)
558 GEN_VEXT_LD_INDEX(vlxe_v_b
, int8_t, int8_t, idx_b
, lde_b
, clearb
)
559 GEN_VEXT_LD_INDEX(vlxe_v_h
, int16_t, int16_t, idx_h
, lde_h
, clearh
)
560 GEN_VEXT_LD_INDEX(vlxe_v_w
, int32_t, int32_t, idx_w
, lde_w
, clearl
)
561 GEN_VEXT_LD_INDEX(vlxe_v_d
, int64_t, int64_t, idx_d
, lde_d
, clearq
)
562 GEN_VEXT_LD_INDEX(vlxbu_v_b
, uint8_t, uint8_t, idx_b
, ldbu_b
, clearb
)
563 GEN_VEXT_LD_INDEX(vlxbu_v_h
, uint8_t, uint16_t, idx_h
, ldbu_h
, clearh
)
564 GEN_VEXT_LD_INDEX(vlxbu_v_w
, uint8_t, uint32_t, idx_w
, ldbu_w
, clearl
)
565 GEN_VEXT_LD_INDEX(vlxbu_v_d
, uint8_t, uint64_t, idx_d
, ldbu_d
, clearq
)
566 GEN_VEXT_LD_INDEX(vlxhu_v_h
, uint16_t, uint16_t, idx_h
, ldhu_h
, clearh
)
567 GEN_VEXT_LD_INDEX(vlxhu_v_w
, uint16_t, uint32_t, idx_w
, ldhu_w
, clearl
)
568 GEN_VEXT_LD_INDEX(vlxhu_v_d
, uint16_t, uint64_t, idx_d
, ldhu_d
, clearq
)
569 GEN_VEXT_LD_INDEX(vlxwu_v_w
, uint32_t, uint32_t, idx_w
, ldwu_w
, clearl
)
570 GEN_VEXT_LD_INDEX(vlxwu_v_d
, uint32_t, uint64_t, idx_d
, ldwu_d
, clearq
)
572 #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
573 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
574 void *vs2, CPURISCVState *env, uint32_t desc) \
576 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
577 STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
578 GETPC(), MMU_DATA_STORE); \
581 GEN_VEXT_ST_INDEX(vsxb_v_b
, int8_t, int8_t, idx_b
, stb_b
)
582 GEN_VEXT_ST_INDEX(vsxb_v_h
, int8_t, int16_t, idx_h
, stb_h
)
583 GEN_VEXT_ST_INDEX(vsxb_v_w
, int8_t, int32_t, idx_w
, stb_w
)
584 GEN_VEXT_ST_INDEX(vsxb_v_d
, int8_t, int64_t, idx_d
, stb_d
)
585 GEN_VEXT_ST_INDEX(vsxh_v_h
, int16_t, int16_t, idx_h
, sth_h
)
586 GEN_VEXT_ST_INDEX(vsxh_v_w
, int16_t, int32_t, idx_w
, sth_w
)
587 GEN_VEXT_ST_INDEX(vsxh_v_d
, int16_t, int64_t, idx_d
, sth_d
)
588 GEN_VEXT_ST_INDEX(vsxw_v_w
, int32_t, int32_t, idx_w
, stw_w
)
589 GEN_VEXT_ST_INDEX(vsxw_v_d
, int32_t, int64_t, idx_d
, stw_d
)
590 GEN_VEXT_ST_INDEX(vsxe_v_b
, int8_t, int8_t, idx_b
, ste_b
)
591 GEN_VEXT_ST_INDEX(vsxe_v_h
, int16_t, int16_t, idx_h
, ste_h
)
592 GEN_VEXT_ST_INDEX(vsxe_v_w
, int32_t, int32_t, idx_w
, ste_w
)
593 GEN_VEXT_ST_INDEX(vsxe_v_d
, int64_t, int64_t, idx_d
, ste_d
)
596 *** unit-stride fault-only-fisrt load instructions
599 vext_ldff(void *vd
, void *v0
, target_ulong base
,
600 CPURISCVState
*env
, uint32_t desc
,
601 vext_ldst_elem_fn
*ldst_elem
,
602 clear_fn
*clear_elem
,
603 uint32_t esz
, uint32_t msz
, uintptr_t ra
)
606 uint32_t i
, k
, vl
= 0;
607 uint32_t mlen
= vext_mlen(desc
);
608 uint32_t nf
= vext_nf(desc
);
609 uint32_t vm
= vext_vm(desc
);
610 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
611 target_ulong addr
, offset
, remain
;
613 /* probe every access*/
614 for (i
= 0; i
< env
->vl
; i
++) {
615 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
618 addr
= base
+ nf
* i
* msz
;
620 probe_pages(env
, addr
, nf
* msz
, ra
, MMU_DATA_LOAD
);
622 /* if it triggers an exception, no need to check watchpoint */
625 offset
= -(addr
| TARGET_PAGE_MASK
);
626 host
= tlb_vaddr_to_host(env
, addr
, MMU_DATA_LOAD
,
627 cpu_mmu_index(env
, false));
629 #ifdef CONFIG_USER_ONLY
630 if (page_check_range(addr
, nf
* msz
, PAGE_READ
) < 0) {
635 probe_pages(env
, addr
, nf
* msz
, ra
, MMU_DATA_LOAD
);
641 if (remain
<= offset
) {
650 /* load bytes from guest memory */
654 for (i
= 0; i
< env
->vl
; i
++) {
656 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
660 target_ulong addr
= base
+ (i
* nf
+ k
) * msz
;
661 ldst_elem(env
, addr
, i
+ k
* vlmax
, vd
, ra
);
665 /* clear tail elements */
669 for (k
= 0; k
< nf
; k
++) {
670 clear_elem(vd
, env
->vl
+ k
* vlmax
, env
->vl
* esz
, vlmax
* esz
);
674 #define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
675 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
676 CPURISCVState *env, uint32_t desc) \
678 vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
679 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
682 GEN_VEXT_LDFF(vlbff_v_b
, int8_t, int8_t, ldb_b
, clearb
)
683 GEN_VEXT_LDFF(vlbff_v_h
, int8_t, int16_t, ldb_h
, clearh
)
684 GEN_VEXT_LDFF(vlbff_v_w
, int8_t, int32_t, ldb_w
, clearl
)
685 GEN_VEXT_LDFF(vlbff_v_d
, int8_t, int64_t, ldb_d
, clearq
)
686 GEN_VEXT_LDFF(vlhff_v_h
, int16_t, int16_t, ldh_h
, clearh
)
687 GEN_VEXT_LDFF(vlhff_v_w
, int16_t, int32_t, ldh_w
, clearl
)
688 GEN_VEXT_LDFF(vlhff_v_d
, int16_t, int64_t, ldh_d
, clearq
)
689 GEN_VEXT_LDFF(vlwff_v_w
, int32_t, int32_t, ldw_w
, clearl
)
690 GEN_VEXT_LDFF(vlwff_v_d
, int32_t, int64_t, ldw_d
, clearq
)
691 GEN_VEXT_LDFF(vleff_v_b
, int8_t, int8_t, lde_b
, clearb
)
692 GEN_VEXT_LDFF(vleff_v_h
, int16_t, int16_t, lde_h
, clearh
)
693 GEN_VEXT_LDFF(vleff_v_w
, int32_t, int32_t, lde_w
, clearl
)
694 GEN_VEXT_LDFF(vleff_v_d
, int64_t, int64_t, lde_d
, clearq
)
695 GEN_VEXT_LDFF(vlbuff_v_b
, uint8_t, uint8_t, ldbu_b
, clearb
)
696 GEN_VEXT_LDFF(vlbuff_v_h
, uint8_t, uint16_t, ldbu_h
, clearh
)
697 GEN_VEXT_LDFF(vlbuff_v_w
, uint8_t, uint32_t, ldbu_w
, clearl
)
698 GEN_VEXT_LDFF(vlbuff_v_d
, uint8_t, uint64_t, ldbu_d
, clearq
)
699 GEN_VEXT_LDFF(vlhuff_v_h
, uint16_t, uint16_t, ldhu_h
, clearh
)
700 GEN_VEXT_LDFF(vlhuff_v_w
, uint16_t, uint32_t, ldhu_w
, clearl
)
701 GEN_VEXT_LDFF(vlhuff_v_d
, uint16_t, uint64_t, ldhu_d
, clearq
)
702 GEN_VEXT_LDFF(vlwuff_v_w
, uint32_t, uint32_t, ldwu_w
, clearl
)
703 GEN_VEXT_LDFF(vlwuff_v_d
, uint32_t, uint64_t, ldwu_d
, clearq
)
706 *** Vector AMO Operations (Zvamo)
708 typedef void vext_amo_noatomic_fn(void *vs3
, target_ulong addr
,
709 uint32_t wd
, uint32_t idx
, CPURISCVState
*env
,
712 /* no atomic opreation for vector atomic insructions */
713 #define DO_SWAP(N, M) (M)
714 #define DO_AND(N, M) (N & M)
715 #define DO_XOR(N, M) (N ^ M)
716 #define DO_OR(N, M) (N | M)
717 #define DO_ADD(N, M) (N + M)
719 #define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
721 vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
722 uint32_t wd, uint32_t idx, \
723 CPURISCVState *env, uintptr_t retaddr)\
725 typedef int##ESZ##_t ETYPE; \
726 typedef int##MSZ##_t MTYPE; \
727 typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
728 ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
729 MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
731 cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
738 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
739 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
741 /* Unsigned min/max */
742 #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
743 #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
745 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w
, 32, 32, H4
, DO_SWAP
, l
)
746 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w
, 32, 32, H4
, DO_ADD
, l
)
747 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w
, 32, 32, H4
, DO_XOR
, l
)
748 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w
, 32, 32, H4
, DO_AND
, l
)
749 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w
, 32, 32, H4
, DO_OR
, l
)
750 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w
, 32, 32, H4
, DO_MIN
, l
)
751 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w
, 32, 32, H4
, DO_MAX
, l
)
752 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w
, 32, 32, H4
, DO_MINU
, l
)
753 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w
, 32, 32, H4
, DO_MAXU
, l
)
754 #ifdef TARGET_RISCV64
755 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d
, 64, 32, H8
, DO_SWAP
, l
)
756 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d
, 64, 64, H8
, DO_SWAP
, q
)
757 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d
, 64, 32, H8
, DO_ADD
, l
)
758 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d
, 64, 64, H8
, DO_ADD
, q
)
759 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d
, 64, 32, H8
, DO_XOR
, l
)
760 GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d
, 64, 64, H8
, DO_XOR
, q
)
761 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d
, 64, 32, H8
, DO_AND
, l
)
762 GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d
, 64, 64, H8
, DO_AND
, q
)
763 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d
, 64, 32, H8
, DO_OR
, l
)
764 GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d
, 64, 64, H8
, DO_OR
, q
)
765 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d
, 64, 32, H8
, DO_MIN
, l
)
766 GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d
, 64, 64, H8
, DO_MIN
, q
)
767 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d
, 64, 32, H8
, DO_MAX
, l
)
768 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d
, 64, 64, H8
, DO_MAX
, q
)
769 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d
, 64, 32, H8
, DO_MINU
, l
)
770 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d
, 64, 64, H8
, DO_MINU
, q
)
771 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d
, 64, 32, H8
, DO_MAXU
, l
)
772 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d
, 64, 64, H8
, DO_MAXU
, q
)
776 vext_amo_noatomic(void *vs3
, void *v0
, target_ulong base
,
777 void *vs2
, CPURISCVState
*env
, uint32_t desc
,
778 vext_get_index_addr get_index_addr
,
779 vext_amo_noatomic_fn
*noatomic_op
,
780 clear_fn
*clear_elem
,
781 uint32_t esz
, uint32_t msz
, uintptr_t ra
)
785 uint32_t wd
= vext_wd(desc
);
786 uint32_t vm
= vext_vm(desc
);
787 uint32_t mlen
= vext_mlen(desc
);
788 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
790 for (i
= 0; i
< env
->vl
; i
++) {
791 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
794 probe_pages(env
, get_index_addr(base
, i
, vs2
), msz
, ra
, MMU_DATA_LOAD
);
795 probe_pages(env
, get_index_addr(base
, i
, vs2
), msz
, ra
, MMU_DATA_STORE
);
797 for (i
= 0; i
< env
->vl
; i
++) {
798 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
801 addr
= get_index_addr(base
, i
, vs2
);
802 noatomic_op(vs3
, addr
, wd
, i
, env
, ra
);
804 clear_elem(vs3
, env
->vl
, env
->vl
* esz
, vlmax
* esz
);
807 #define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
808 void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
809 void *vs2, CPURISCVState *env, uint32_t desc) \
811 vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
812 INDEX_FN, vext_##NAME##_noatomic_op, \
813 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
817 #ifdef TARGET_RISCV64
818 GEN_VEXT_AMO(vamoswapw_v_d
, int32_t, int64_t, idx_d
, clearq
)
819 GEN_VEXT_AMO(vamoswapd_v_d
, int64_t, int64_t, idx_d
, clearq
)
820 GEN_VEXT_AMO(vamoaddw_v_d
, int32_t, int64_t, idx_d
, clearq
)
821 GEN_VEXT_AMO(vamoaddd_v_d
, int64_t, int64_t, idx_d
, clearq
)
822 GEN_VEXT_AMO(vamoxorw_v_d
, int32_t, int64_t, idx_d
, clearq
)
823 GEN_VEXT_AMO(vamoxord_v_d
, int64_t, int64_t, idx_d
, clearq
)
824 GEN_VEXT_AMO(vamoandw_v_d
, int32_t, int64_t, idx_d
, clearq
)
825 GEN_VEXT_AMO(vamoandd_v_d
, int64_t, int64_t, idx_d
, clearq
)
826 GEN_VEXT_AMO(vamoorw_v_d
, int32_t, int64_t, idx_d
, clearq
)
827 GEN_VEXT_AMO(vamoord_v_d
, int64_t, int64_t, idx_d
, clearq
)
828 GEN_VEXT_AMO(vamominw_v_d
, int32_t, int64_t, idx_d
, clearq
)
829 GEN_VEXT_AMO(vamomind_v_d
, int64_t, int64_t, idx_d
, clearq
)
830 GEN_VEXT_AMO(vamomaxw_v_d
, int32_t, int64_t, idx_d
, clearq
)
831 GEN_VEXT_AMO(vamomaxd_v_d
, int64_t, int64_t, idx_d
, clearq
)
832 GEN_VEXT_AMO(vamominuw_v_d
, uint32_t, uint64_t, idx_d
, clearq
)
833 GEN_VEXT_AMO(vamominud_v_d
, uint64_t, uint64_t, idx_d
, clearq
)
834 GEN_VEXT_AMO(vamomaxuw_v_d
, uint32_t, uint64_t, idx_d
, clearq
)
835 GEN_VEXT_AMO(vamomaxud_v_d
, uint64_t, uint64_t, idx_d
, clearq
)
837 GEN_VEXT_AMO(vamoswapw_v_w
, int32_t, int32_t, idx_w
, clearl
)
838 GEN_VEXT_AMO(vamoaddw_v_w
, int32_t, int32_t, idx_w
, clearl
)
839 GEN_VEXT_AMO(vamoxorw_v_w
, int32_t, int32_t, idx_w
, clearl
)
840 GEN_VEXT_AMO(vamoandw_v_w
, int32_t, int32_t, idx_w
, clearl
)
841 GEN_VEXT_AMO(vamoorw_v_w
, int32_t, int32_t, idx_w
, clearl
)
842 GEN_VEXT_AMO(vamominw_v_w
, int32_t, int32_t, idx_w
, clearl
)
843 GEN_VEXT_AMO(vamomaxw_v_w
, int32_t, int32_t, idx_w
, clearl
)
844 GEN_VEXT_AMO(vamominuw_v_w
, uint32_t, uint32_t, idx_w
, clearl
)
845 GEN_VEXT_AMO(vamomaxuw_v_w
, uint32_t, uint32_t, idx_w
, clearl
)
848 *** Vector Integer Arithmetic Instructions
851 /* expand macro args before macro */
852 #define RVVCALL(macro, ...) macro(__VA_ARGS__)
854 /* (TD, T1, T2, TX1, TX2) */
855 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
856 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
857 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
858 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
859 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
860 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
861 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
862 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
863 #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
864 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
865 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
866 #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
867 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
868 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
869 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
870 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
871 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
872 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
873 #define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
874 #define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
875 #define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
876 #define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
877 #define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
878 #define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
879 #define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
880 #define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
881 #define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
882 #define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t
883 #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
884 #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
886 /* operation of two vector elements */
887 typedef void opivv2_fn(void *vd
, void *vs1
, void *vs2
, int i
);
889 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
890 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
892 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
893 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
894 *((TD *)vd + HD(i)) = OP(s2, s1); \
896 #define DO_SUB(N, M) (N - M)
897 #define DO_RSUB(N, M) (M - N)
899 RVVCALL(OPIVV2
, vadd_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_ADD
)
900 RVVCALL(OPIVV2
, vadd_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_ADD
)
901 RVVCALL(OPIVV2
, vadd_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_ADD
)
902 RVVCALL(OPIVV2
, vadd_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_ADD
)
903 RVVCALL(OPIVV2
, vsub_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_SUB
)
904 RVVCALL(OPIVV2
, vsub_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_SUB
)
905 RVVCALL(OPIVV2
, vsub_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_SUB
)
906 RVVCALL(OPIVV2
, vsub_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_SUB
)
908 static void do_vext_vv(void *vd
, void *v0
, void *vs1
, void *vs2
,
909 CPURISCVState
*env
, uint32_t desc
,
910 uint32_t esz
, uint32_t dsz
,
911 opivv2_fn
*fn
, clear_fn
*clearfn
)
913 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
914 uint32_t mlen
= vext_mlen(desc
);
915 uint32_t vm
= vext_vm(desc
);
916 uint32_t vl
= env
->vl
;
919 for (i
= 0; i
< vl
; i
++) {
920 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
925 clearfn(vd
, vl
, vl
* dsz
, vlmax
* dsz
);
928 /* generate the helpers for OPIVV */
929 #define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \
930 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
931 void *vs2, CPURISCVState *env, \
934 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
935 do_##NAME, CLEAR_FN); \
938 GEN_VEXT_VV(vadd_vv_b
, 1, 1, clearb
)
939 GEN_VEXT_VV(vadd_vv_h
, 2, 2, clearh
)
940 GEN_VEXT_VV(vadd_vv_w
, 4, 4, clearl
)
941 GEN_VEXT_VV(vadd_vv_d
, 8, 8, clearq
)
942 GEN_VEXT_VV(vsub_vv_b
, 1, 1, clearb
)
943 GEN_VEXT_VV(vsub_vv_h
, 2, 2, clearh
)
944 GEN_VEXT_VV(vsub_vv_w
, 4, 4, clearl
)
945 GEN_VEXT_VV(vsub_vv_d
, 8, 8, clearq
)
947 typedef void opivx2_fn(void *vd
, target_long s1
, void *vs2
, int i
);
950 * (T1)s1 gives the real operator type.
951 * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
953 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
954 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
956 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
957 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
960 RVVCALL(OPIVX2
, vadd_vx_b
, OP_SSS_B
, H1
, H1
, DO_ADD
)
961 RVVCALL(OPIVX2
, vadd_vx_h
, OP_SSS_H
, H2
, H2
, DO_ADD
)
962 RVVCALL(OPIVX2
, vadd_vx_w
, OP_SSS_W
, H4
, H4
, DO_ADD
)
963 RVVCALL(OPIVX2
, vadd_vx_d
, OP_SSS_D
, H8
, H8
, DO_ADD
)
964 RVVCALL(OPIVX2
, vsub_vx_b
, OP_SSS_B
, H1
, H1
, DO_SUB
)
965 RVVCALL(OPIVX2
, vsub_vx_h
, OP_SSS_H
, H2
, H2
, DO_SUB
)
966 RVVCALL(OPIVX2
, vsub_vx_w
, OP_SSS_W
, H4
, H4
, DO_SUB
)
967 RVVCALL(OPIVX2
, vsub_vx_d
, OP_SSS_D
, H8
, H8
, DO_SUB
)
968 RVVCALL(OPIVX2
, vrsub_vx_b
, OP_SSS_B
, H1
, H1
, DO_RSUB
)
969 RVVCALL(OPIVX2
, vrsub_vx_h
, OP_SSS_H
, H2
, H2
, DO_RSUB
)
970 RVVCALL(OPIVX2
, vrsub_vx_w
, OP_SSS_W
, H4
, H4
, DO_RSUB
)
971 RVVCALL(OPIVX2
, vrsub_vx_d
, OP_SSS_D
, H8
, H8
, DO_RSUB
)
973 static void do_vext_vx(void *vd
, void *v0
, target_long s1
, void *vs2
,
974 CPURISCVState
*env
, uint32_t desc
,
975 uint32_t esz
, uint32_t dsz
,
976 opivx2_fn fn
, clear_fn
*clearfn
)
978 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
979 uint32_t mlen
= vext_mlen(desc
);
980 uint32_t vm
= vext_vm(desc
);
981 uint32_t vl
= env
->vl
;
984 for (i
= 0; i
< vl
; i
++) {
985 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
990 clearfn(vd
, vl
, vl
* dsz
, vlmax
* dsz
);
993 /* generate the helpers for OPIVX */
994 #define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \
995 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
996 void *vs2, CPURISCVState *env, \
999 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
1000 do_##NAME, CLEAR_FN); \
1003 GEN_VEXT_VX(vadd_vx_b
, 1, 1, clearb
)
1004 GEN_VEXT_VX(vadd_vx_h
, 2, 2, clearh
)
1005 GEN_VEXT_VX(vadd_vx_w
, 4, 4, clearl
)
1006 GEN_VEXT_VX(vadd_vx_d
, 8, 8, clearq
)
1007 GEN_VEXT_VX(vsub_vx_b
, 1, 1, clearb
)
1008 GEN_VEXT_VX(vsub_vx_h
, 2, 2, clearh
)
1009 GEN_VEXT_VX(vsub_vx_w
, 4, 4, clearl
)
1010 GEN_VEXT_VX(vsub_vx_d
, 8, 8, clearq
)
1011 GEN_VEXT_VX(vrsub_vx_b
, 1, 1, clearb
)
1012 GEN_VEXT_VX(vrsub_vx_h
, 2, 2, clearh
)
1013 GEN_VEXT_VX(vrsub_vx_w
, 4, 4, clearl
)
1014 GEN_VEXT_VX(vrsub_vx_d
, 8, 8, clearq
)
1016 void HELPER(vec_rsubs8
)(void *d
, void *a
, uint64_t b
, uint32_t desc
)
1018 intptr_t oprsz
= simd_oprsz(desc
);
1021 for (i
= 0; i
< oprsz
; i
+= sizeof(uint8_t)) {
1022 *(uint8_t *)(d
+ i
) = (uint8_t)b
- *(uint8_t *)(a
+ i
);
1026 void HELPER(vec_rsubs16
)(void *d
, void *a
, uint64_t b
, uint32_t desc
)
1028 intptr_t oprsz
= simd_oprsz(desc
);
1031 for (i
= 0; i
< oprsz
; i
+= sizeof(uint16_t)) {
1032 *(uint16_t *)(d
+ i
) = (uint16_t)b
- *(uint16_t *)(a
+ i
);
1036 void HELPER(vec_rsubs32
)(void *d
, void *a
, uint64_t b
, uint32_t desc
)
1038 intptr_t oprsz
= simd_oprsz(desc
);
1041 for (i
= 0; i
< oprsz
; i
+= sizeof(uint32_t)) {
1042 *(uint32_t *)(d
+ i
) = (uint32_t)b
- *(uint32_t *)(a
+ i
);
1046 void HELPER(vec_rsubs64
)(void *d
, void *a
, uint64_t b
, uint32_t desc
)
1048 intptr_t oprsz
= simd_oprsz(desc
);
1051 for (i
= 0; i
< oprsz
; i
+= sizeof(uint64_t)) {
1052 *(uint64_t *)(d
+ i
) = b
- *(uint64_t *)(a
+ i
);
1056 /* Vector Widening Integer Add/Subtract */
1057 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
1058 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
1059 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
1060 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
1061 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
1062 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
1063 #define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t
1064 #define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t
1065 #define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t
1066 #define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
1067 #define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
1068 #define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
1069 RVVCALL(OPIVV2
, vwaddu_vv_b
, WOP_UUU_B
, H2
, H1
, H1
, DO_ADD
)
1070 RVVCALL(OPIVV2
, vwaddu_vv_h
, WOP_UUU_H
, H4
, H2
, H2
, DO_ADD
)
1071 RVVCALL(OPIVV2
, vwaddu_vv_w
, WOP_UUU_W
, H8
, H4
, H4
, DO_ADD
)
1072 RVVCALL(OPIVV2
, vwsubu_vv_b
, WOP_UUU_B
, H2
, H1
, H1
, DO_SUB
)
1073 RVVCALL(OPIVV2
, vwsubu_vv_h
, WOP_UUU_H
, H4
, H2
, H2
, DO_SUB
)
1074 RVVCALL(OPIVV2
, vwsubu_vv_w
, WOP_UUU_W
, H8
, H4
, H4
, DO_SUB
)
1075 RVVCALL(OPIVV2
, vwadd_vv_b
, WOP_SSS_B
, H2
, H1
, H1
, DO_ADD
)
1076 RVVCALL(OPIVV2
, vwadd_vv_h
, WOP_SSS_H
, H4
, H2
, H2
, DO_ADD
)
1077 RVVCALL(OPIVV2
, vwadd_vv_w
, WOP_SSS_W
, H8
, H4
, H4
, DO_ADD
)
1078 RVVCALL(OPIVV2
, vwsub_vv_b
, WOP_SSS_B
, H2
, H1
, H1
, DO_SUB
)
1079 RVVCALL(OPIVV2
, vwsub_vv_h
, WOP_SSS_H
, H4
, H2
, H2
, DO_SUB
)
1080 RVVCALL(OPIVV2
, vwsub_vv_w
, WOP_SSS_W
, H8
, H4
, H4
, DO_SUB
)
1081 RVVCALL(OPIVV2
, vwaddu_wv_b
, WOP_WUUU_B
, H2
, H1
, H1
, DO_ADD
)
1082 RVVCALL(OPIVV2
, vwaddu_wv_h
, WOP_WUUU_H
, H4
, H2
, H2
, DO_ADD
)
1083 RVVCALL(OPIVV2
, vwaddu_wv_w
, WOP_WUUU_W
, H8
, H4
, H4
, DO_ADD
)
1084 RVVCALL(OPIVV2
, vwsubu_wv_b
, WOP_WUUU_B
, H2
, H1
, H1
, DO_SUB
)
1085 RVVCALL(OPIVV2
, vwsubu_wv_h
, WOP_WUUU_H
, H4
, H2
, H2
, DO_SUB
)
1086 RVVCALL(OPIVV2
, vwsubu_wv_w
, WOP_WUUU_W
, H8
, H4
, H4
, DO_SUB
)
1087 RVVCALL(OPIVV2
, vwadd_wv_b
, WOP_WSSS_B
, H2
, H1
, H1
, DO_ADD
)
1088 RVVCALL(OPIVV2
, vwadd_wv_h
, WOP_WSSS_H
, H4
, H2
, H2
, DO_ADD
)
1089 RVVCALL(OPIVV2
, vwadd_wv_w
, WOP_WSSS_W
, H8
, H4
, H4
, DO_ADD
)
1090 RVVCALL(OPIVV2
, vwsub_wv_b
, WOP_WSSS_B
, H2
, H1
, H1
, DO_SUB
)
1091 RVVCALL(OPIVV2
, vwsub_wv_h
, WOP_WSSS_H
, H4
, H2
, H2
, DO_SUB
)
1092 RVVCALL(OPIVV2
, vwsub_wv_w
, WOP_WSSS_W
, H8
, H4
, H4
, DO_SUB
)
1093 GEN_VEXT_VV(vwaddu_vv_b
, 1, 2, clearh
)
1094 GEN_VEXT_VV(vwaddu_vv_h
, 2, 4, clearl
)
1095 GEN_VEXT_VV(vwaddu_vv_w
, 4, 8, clearq
)
1096 GEN_VEXT_VV(vwsubu_vv_b
, 1, 2, clearh
)
1097 GEN_VEXT_VV(vwsubu_vv_h
, 2, 4, clearl
)
1098 GEN_VEXT_VV(vwsubu_vv_w
, 4, 8, clearq
)
1099 GEN_VEXT_VV(vwadd_vv_b
, 1, 2, clearh
)
1100 GEN_VEXT_VV(vwadd_vv_h
, 2, 4, clearl
)
1101 GEN_VEXT_VV(vwadd_vv_w
, 4, 8, clearq
)
1102 GEN_VEXT_VV(vwsub_vv_b
, 1, 2, clearh
)
1103 GEN_VEXT_VV(vwsub_vv_h
, 2, 4, clearl
)
1104 GEN_VEXT_VV(vwsub_vv_w
, 4, 8, clearq
)
1105 GEN_VEXT_VV(vwaddu_wv_b
, 1, 2, clearh
)
1106 GEN_VEXT_VV(vwaddu_wv_h
, 2, 4, clearl
)
1107 GEN_VEXT_VV(vwaddu_wv_w
, 4, 8, clearq
)
1108 GEN_VEXT_VV(vwsubu_wv_b
, 1, 2, clearh
)
1109 GEN_VEXT_VV(vwsubu_wv_h
, 2, 4, clearl
)
1110 GEN_VEXT_VV(vwsubu_wv_w
, 4, 8, clearq
)
1111 GEN_VEXT_VV(vwadd_wv_b
, 1, 2, clearh
)
1112 GEN_VEXT_VV(vwadd_wv_h
, 2, 4, clearl
)
1113 GEN_VEXT_VV(vwadd_wv_w
, 4, 8, clearq
)
1114 GEN_VEXT_VV(vwsub_wv_b
, 1, 2, clearh
)
1115 GEN_VEXT_VV(vwsub_wv_h
, 2, 4, clearl
)
1116 GEN_VEXT_VV(vwsub_wv_w
, 4, 8, clearq
)
1118 RVVCALL(OPIVX2
, vwaddu_vx_b
, WOP_UUU_B
, H2
, H1
, DO_ADD
)
1119 RVVCALL(OPIVX2
, vwaddu_vx_h
, WOP_UUU_H
, H4
, H2
, DO_ADD
)
1120 RVVCALL(OPIVX2
, vwaddu_vx_w
, WOP_UUU_W
, H8
, H4
, DO_ADD
)
1121 RVVCALL(OPIVX2
, vwsubu_vx_b
, WOP_UUU_B
, H2
, H1
, DO_SUB
)
1122 RVVCALL(OPIVX2
, vwsubu_vx_h
, WOP_UUU_H
, H4
, H2
, DO_SUB
)
1123 RVVCALL(OPIVX2
, vwsubu_vx_w
, WOP_UUU_W
, H8
, H4
, DO_SUB
)
1124 RVVCALL(OPIVX2
, vwadd_vx_b
, WOP_SSS_B
, H2
, H1
, DO_ADD
)
1125 RVVCALL(OPIVX2
, vwadd_vx_h
, WOP_SSS_H
, H4
, H2
, DO_ADD
)
1126 RVVCALL(OPIVX2
, vwadd_vx_w
, WOP_SSS_W
, H8
, H4
, DO_ADD
)
1127 RVVCALL(OPIVX2
, vwsub_vx_b
, WOP_SSS_B
, H2
, H1
, DO_SUB
)
1128 RVVCALL(OPIVX2
, vwsub_vx_h
, WOP_SSS_H
, H4
, H2
, DO_SUB
)
1129 RVVCALL(OPIVX2
, vwsub_vx_w
, WOP_SSS_W
, H8
, H4
, DO_SUB
)
1130 RVVCALL(OPIVX2
, vwaddu_wx_b
, WOP_WUUU_B
, H2
, H1
, DO_ADD
)
1131 RVVCALL(OPIVX2
, vwaddu_wx_h
, WOP_WUUU_H
, H4
, H2
, DO_ADD
)
1132 RVVCALL(OPIVX2
, vwaddu_wx_w
, WOP_WUUU_W
, H8
, H4
, DO_ADD
)
1133 RVVCALL(OPIVX2
, vwsubu_wx_b
, WOP_WUUU_B
, H2
, H1
, DO_SUB
)
1134 RVVCALL(OPIVX2
, vwsubu_wx_h
, WOP_WUUU_H
, H4
, H2
, DO_SUB
)
1135 RVVCALL(OPIVX2
, vwsubu_wx_w
, WOP_WUUU_W
, H8
, H4
, DO_SUB
)
1136 RVVCALL(OPIVX2
, vwadd_wx_b
, WOP_WSSS_B
, H2
, H1
, DO_ADD
)
1137 RVVCALL(OPIVX2
, vwadd_wx_h
, WOP_WSSS_H
, H4
, H2
, DO_ADD
)
1138 RVVCALL(OPIVX2
, vwadd_wx_w
, WOP_WSSS_W
, H8
, H4
, DO_ADD
)
1139 RVVCALL(OPIVX2
, vwsub_wx_b
, WOP_WSSS_B
, H2
, H1
, DO_SUB
)
1140 RVVCALL(OPIVX2
, vwsub_wx_h
, WOP_WSSS_H
, H4
, H2
, DO_SUB
)
1141 RVVCALL(OPIVX2
, vwsub_wx_w
, WOP_WSSS_W
, H8
, H4
, DO_SUB
)
1142 GEN_VEXT_VX(vwaddu_vx_b
, 1, 2, clearh
)
1143 GEN_VEXT_VX(vwaddu_vx_h
, 2, 4, clearl
)
1144 GEN_VEXT_VX(vwaddu_vx_w
, 4, 8, clearq
)
1145 GEN_VEXT_VX(vwsubu_vx_b
, 1, 2, clearh
)
1146 GEN_VEXT_VX(vwsubu_vx_h
, 2, 4, clearl
)
1147 GEN_VEXT_VX(vwsubu_vx_w
, 4, 8, clearq
)
1148 GEN_VEXT_VX(vwadd_vx_b
, 1, 2, clearh
)
1149 GEN_VEXT_VX(vwadd_vx_h
, 2, 4, clearl
)
1150 GEN_VEXT_VX(vwadd_vx_w
, 4, 8, clearq
)
1151 GEN_VEXT_VX(vwsub_vx_b
, 1, 2, clearh
)
1152 GEN_VEXT_VX(vwsub_vx_h
, 2, 4, clearl
)
1153 GEN_VEXT_VX(vwsub_vx_w
, 4, 8, clearq
)
1154 GEN_VEXT_VX(vwaddu_wx_b
, 1, 2, clearh
)
1155 GEN_VEXT_VX(vwaddu_wx_h
, 2, 4, clearl
)
1156 GEN_VEXT_VX(vwaddu_wx_w
, 4, 8, clearq
)
1157 GEN_VEXT_VX(vwsubu_wx_b
, 1, 2, clearh
)
1158 GEN_VEXT_VX(vwsubu_wx_h
, 2, 4, clearl
)
1159 GEN_VEXT_VX(vwsubu_wx_w
, 4, 8, clearq
)
1160 GEN_VEXT_VX(vwadd_wx_b
, 1, 2, clearh
)
1161 GEN_VEXT_VX(vwadd_wx_h
, 2, 4, clearl
)
1162 GEN_VEXT_VX(vwadd_wx_w
, 4, 8, clearq
)
1163 GEN_VEXT_VX(vwsub_wx_b
, 1, 2, clearh
)
1164 GEN_VEXT_VX(vwsub_wx_h
, 2, 4, clearl
)
1165 GEN_VEXT_VX(vwsub_wx_w
, 4, 8, clearq
)
1167 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1168 #define DO_VADC(N, M, C) (N + M + C)
1169 #define DO_VSBC(N, M, C) (N - M - C)
1171 #define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1172 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1173 CPURISCVState *env, uint32_t desc) \
1175 uint32_t mlen = vext_mlen(desc); \
1176 uint32_t vl = env->vl; \
1177 uint32_t esz = sizeof(ETYPE); \
1178 uint32_t vlmax = vext_maxsz(desc) / esz; \
1181 for (i = 0; i < vl; i++) { \
1182 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1183 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1184 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1186 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
1188 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1191 GEN_VEXT_VADC_VVM(vadc_vvm_b
, uint8_t, H1
, DO_VADC
, clearb
)
1192 GEN_VEXT_VADC_VVM(vadc_vvm_h
, uint16_t, H2
, DO_VADC
, clearh
)
1193 GEN_VEXT_VADC_VVM(vadc_vvm_w
, uint32_t, H4
, DO_VADC
, clearl
)
1194 GEN_VEXT_VADC_VVM(vadc_vvm_d
, uint64_t, H8
, DO_VADC
, clearq
)
1196 GEN_VEXT_VADC_VVM(vsbc_vvm_b
, uint8_t, H1
, DO_VSBC
, clearb
)
1197 GEN_VEXT_VADC_VVM(vsbc_vvm_h
, uint16_t, H2
, DO_VSBC
, clearh
)
1198 GEN_VEXT_VADC_VVM(vsbc_vvm_w
, uint32_t, H4
, DO_VSBC
, clearl
)
1199 GEN_VEXT_VADC_VVM(vsbc_vvm_d
, uint64_t, H8
, DO_VSBC
, clearq
)
1201 #define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1202 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1203 CPURISCVState *env, uint32_t desc) \
1205 uint32_t mlen = vext_mlen(desc); \
1206 uint32_t vl = env->vl; \
1207 uint32_t esz = sizeof(ETYPE); \
1208 uint32_t vlmax = vext_maxsz(desc) / esz; \
1211 for (i = 0; i < vl; i++) { \
1212 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1213 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1215 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
1217 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1220 GEN_VEXT_VADC_VXM(vadc_vxm_b
, uint8_t, H1
, DO_VADC
, clearb
)
1221 GEN_VEXT_VADC_VXM(vadc_vxm_h
, uint16_t, H2
, DO_VADC
, clearh
)
1222 GEN_VEXT_VADC_VXM(vadc_vxm_w
, uint32_t, H4
, DO_VADC
, clearl
)
1223 GEN_VEXT_VADC_VXM(vadc_vxm_d
, uint64_t, H8
, DO_VADC
, clearq
)
1225 GEN_VEXT_VADC_VXM(vsbc_vxm_b
, uint8_t, H1
, DO_VSBC
, clearb
)
1226 GEN_VEXT_VADC_VXM(vsbc_vxm_h
, uint16_t, H2
, DO_VSBC
, clearh
)
1227 GEN_VEXT_VADC_VXM(vsbc_vxm_w
, uint32_t, H4
, DO_VSBC
, clearl
)
1228 GEN_VEXT_VADC_VXM(vsbc_vxm_d
, uint64_t, H8
, DO_VSBC
, clearq
)
1230 #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \
1231 (__typeof(N))(N + M) < N)
1232 #define DO_MSBC(N, M, C) (C ? N <= M : N < M)
1234 #define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
1235 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1236 CPURISCVState *env, uint32_t desc) \
1238 uint32_t mlen = vext_mlen(desc); \
1239 uint32_t vl = env->vl; \
1240 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1243 for (i = 0; i < vl; i++) { \
1244 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1245 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1246 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1248 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
1250 for (; i < vlmax; i++) { \
1251 vext_set_elem_mask(vd, mlen, i, 0); \
1255 GEN_VEXT_VMADC_VVM(vmadc_vvm_b
, uint8_t, H1
, DO_MADC
)
1256 GEN_VEXT_VMADC_VVM(vmadc_vvm_h
, uint16_t, H2
, DO_MADC
)
1257 GEN_VEXT_VMADC_VVM(vmadc_vvm_w
, uint32_t, H4
, DO_MADC
)
1258 GEN_VEXT_VMADC_VVM(vmadc_vvm_d
, uint64_t, H8
, DO_MADC
)
1260 GEN_VEXT_VMADC_VVM(vmsbc_vvm_b
, uint8_t, H1
, DO_MSBC
)
1261 GEN_VEXT_VMADC_VVM(vmsbc_vvm_h
, uint16_t, H2
, DO_MSBC
)
1262 GEN_VEXT_VMADC_VVM(vmsbc_vvm_w
, uint32_t, H4
, DO_MSBC
)
1263 GEN_VEXT_VMADC_VVM(vmsbc_vvm_d
, uint64_t, H8
, DO_MSBC
)
1265 #define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \
1266 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1267 void *vs2, CPURISCVState *env, uint32_t desc) \
1269 uint32_t mlen = vext_mlen(desc); \
1270 uint32_t vl = env->vl; \
1271 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1274 for (i = 0; i < vl; i++) { \
1275 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1276 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1278 vext_set_elem_mask(vd, mlen, i, \
1279 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
1281 for (; i < vlmax; i++) { \
1282 vext_set_elem_mask(vd, mlen, i, 0); \
1286 GEN_VEXT_VMADC_VXM(vmadc_vxm_b
, uint8_t, H1
, DO_MADC
)
1287 GEN_VEXT_VMADC_VXM(vmadc_vxm_h
, uint16_t, H2
, DO_MADC
)
1288 GEN_VEXT_VMADC_VXM(vmadc_vxm_w
, uint32_t, H4
, DO_MADC
)
1289 GEN_VEXT_VMADC_VXM(vmadc_vxm_d
, uint64_t, H8
, DO_MADC
)
1291 GEN_VEXT_VMADC_VXM(vmsbc_vxm_b
, uint8_t, H1
, DO_MSBC
)
1292 GEN_VEXT_VMADC_VXM(vmsbc_vxm_h
, uint16_t, H2
, DO_MSBC
)
1293 GEN_VEXT_VMADC_VXM(vmsbc_vxm_w
, uint32_t, H4
, DO_MSBC
)
1294 GEN_VEXT_VMADC_VXM(vmsbc_vxm_d
, uint64_t, H8
, DO_MSBC
)
1296 /* Vector Bitwise Logical Instructions */
1297 RVVCALL(OPIVV2
, vand_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_AND
)
1298 RVVCALL(OPIVV2
, vand_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_AND
)
1299 RVVCALL(OPIVV2
, vand_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_AND
)
1300 RVVCALL(OPIVV2
, vand_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_AND
)
1301 RVVCALL(OPIVV2
, vor_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_OR
)
1302 RVVCALL(OPIVV2
, vor_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_OR
)
1303 RVVCALL(OPIVV2
, vor_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_OR
)
1304 RVVCALL(OPIVV2
, vor_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_OR
)
1305 RVVCALL(OPIVV2
, vxor_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_XOR
)
1306 RVVCALL(OPIVV2
, vxor_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_XOR
)
1307 RVVCALL(OPIVV2
, vxor_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_XOR
)
1308 RVVCALL(OPIVV2
, vxor_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_XOR
)
1309 GEN_VEXT_VV(vand_vv_b
, 1, 1, clearb
)
1310 GEN_VEXT_VV(vand_vv_h
, 2, 2, clearh
)
1311 GEN_VEXT_VV(vand_vv_w
, 4, 4, clearl
)
1312 GEN_VEXT_VV(vand_vv_d
, 8, 8, clearq
)
1313 GEN_VEXT_VV(vor_vv_b
, 1, 1, clearb
)
1314 GEN_VEXT_VV(vor_vv_h
, 2, 2, clearh
)
1315 GEN_VEXT_VV(vor_vv_w
, 4, 4, clearl
)
1316 GEN_VEXT_VV(vor_vv_d
, 8, 8, clearq
)
1317 GEN_VEXT_VV(vxor_vv_b
, 1, 1, clearb
)
1318 GEN_VEXT_VV(vxor_vv_h
, 2, 2, clearh
)
1319 GEN_VEXT_VV(vxor_vv_w
, 4, 4, clearl
)
1320 GEN_VEXT_VV(vxor_vv_d
, 8, 8, clearq
)
1322 RVVCALL(OPIVX2
, vand_vx_b
, OP_SSS_B
, H1
, H1
, DO_AND
)
1323 RVVCALL(OPIVX2
, vand_vx_h
, OP_SSS_H
, H2
, H2
, DO_AND
)
1324 RVVCALL(OPIVX2
, vand_vx_w
, OP_SSS_W
, H4
, H4
, DO_AND
)
1325 RVVCALL(OPIVX2
, vand_vx_d
, OP_SSS_D
, H8
, H8
, DO_AND
)
1326 RVVCALL(OPIVX2
, vor_vx_b
, OP_SSS_B
, H1
, H1
, DO_OR
)
1327 RVVCALL(OPIVX2
, vor_vx_h
, OP_SSS_H
, H2
, H2
, DO_OR
)
1328 RVVCALL(OPIVX2
, vor_vx_w
, OP_SSS_W
, H4
, H4
, DO_OR
)
1329 RVVCALL(OPIVX2
, vor_vx_d
, OP_SSS_D
, H8
, H8
, DO_OR
)
1330 RVVCALL(OPIVX2
, vxor_vx_b
, OP_SSS_B
, H1
, H1
, DO_XOR
)
1331 RVVCALL(OPIVX2
, vxor_vx_h
, OP_SSS_H
, H2
, H2
, DO_XOR
)
1332 RVVCALL(OPIVX2
, vxor_vx_w
, OP_SSS_W
, H4
, H4
, DO_XOR
)
1333 RVVCALL(OPIVX2
, vxor_vx_d
, OP_SSS_D
, H8
, H8
, DO_XOR
)
1334 GEN_VEXT_VX(vand_vx_b
, 1, 1, clearb
)
1335 GEN_VEXT_VX(vand_vx_h
, 2, 2, clearh
)
1336 GEN_VEXT_VX(vand_vx_w
, 4, 4, clearl
)
1337 GEN_VEXT_VX(vand_vx_d
, 8, 8, clearq
)
1338 GEN_VEXT_VX(vor_vx_b
, 1, 1, clearb
)
1339 GEN_VEXT_VX(vor_vx_h
, 2, 2, clearh
)
1340 GEN_VEXT_VX(vor_vx_w
, 4, 4, clearl
)
1341 GEN_VEXT_VX(vor_vx_d
, 8, 8, clearq
)
1342 GEN_VEXT_VX(vxor_vx_b
, 1, 1, clearb
)
1343 GEN_VEXT_VX(vxor_vx_h
, 2, 2, clearh
)
1344 GEN_VEXT_VX(vxor_vx_w
, 4, 4, clearl
)
1345 GEN_VEXT_VX(vxor_vx_d
, 8, 8, clearq
)
1347 /* Vector Single-Width Bit Shift Instructions */
1348 #define DO_SLL(N, M) (N << (M))
1349 #define DO_SRL(N, M) (N >> (M))
1351 /* generate the helpers for shift instructions with two vector operators */
1352 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
1353 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1354 void *vs2, CPURISCVState *env, uint32_t desc) \
1356 uint32_t mlen = vext_mlen(desc); \
1357 uint32_t vm = vext_vm(desc); \
1358 uint32_t vl = env->vl; \
1359 uint32_t esz = sizeof(TS1); \
1360 uint32_t vlmax = vext_maxsz(desc) / esz; \
1363 for (i = 0; i < vl; i++) { \
1364 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1367 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1368 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1369 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
1371 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1374 GEN_VEXT_SHIFT_VV(vsll_vv_b
, uint8_t, uint8_t, H1
, H1
, DO_SLL
, 0x7, clearb
)
1375 GEN_VEXT_SHIFT_VV(vsll_vv_h
, uint16_t, uint16_t, H2
, H2
, DO_SLL
, 0xf, clearh
)
1376 GEN_VEXT_SHIFT_VV(vsll_vv_w
, uint32_t, uint32_t, H4
, H4
, DO_SLL
, 0x1f, clearl
)
1377 GEN_VEXT_SHIFT_VV(vsll_vv_d
, uint64_t, uint64_t, H8
, H8
, DO_SLL
, 0x3f, clearq
)
1379 GEN_VEXT_SHIFT_VV(vsrl_vv_b
, uint8_t, uint8_t, H1
, H1
, DO_SRL
, 0x7, clearb
)
1380 GEN_VEXT_SHIFT_VV(vsrl_vv_h
, uint16_t, uint16_t, H2
, H2
, DO_SRL
, 0xf, clearh
)
1381 GEN_VEXT_SHIFT_VV(vsrl_vv_w
, uint32_t, uint32_t, H4
, H4
, DO_SRL
, 0x1f, clearl
)
1382 GEN_VEXT_SHIFT_VV(vsrl_vv_d
, uint64_t, uint64_t, H8
, H8
, DO_SRL
, 0x3f, clearq
)
1384 GEN_VEXT_SHIFT_VV(vsra_vv_b
, uint8_t, int8_t, H1
, H1
, DO_SRL
, 0x7, clearb
)
1385 GEN_VEXT_SHIFT_VV(vsra_vv_h
, uint16_t, int16_t, H2
, H2
, DO_SRL
, 0xf, clearh
)
1386 GEN_VEXT_SHIFT_VV(vsra_vv_w
, uint32_t, int32_t, H4
, H4
, DO_SRL
, 0x1f, clearl
)
1387 GEN_VEXT_SHIFT_VV(vsra_vv_d
, uint64_t, int64_t, H8
, H8
, DO_SRL
, 0x3f, clearq
)
1389 /* generate the helpers for shift instructions with one vector and one scalar */
1390 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
1391 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1392 void *vs2, CPURISCVState *env, uint32_t desc) \
1394 uint32_t mlen = vext_mlen(desc); \
1395 uint32_t vm = vext_vm(desc); \
1396 uint32_t vl = env->vl; \
1397 uint32_t esz = sizeof(TD); \
1398 uint32_t vlmax = vext_maxsz(desc) / esz; \
1401 for (i = 0; i < vl; i++) { \
1402 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1405 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1406 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
1408 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1411 GEN_VEXT_SHIFT_VX(vsll_vx_b
, uint8_t, int8_t, H1
, H1
, DO_SLL
, 0x7, clearb
)
1412 GEN_VEXT_SHIFT_VX(vsll_vx_h
, uint16_t, int16_t, H2
, H2
, DO_SLL
, 0xf, clearh
)
1413 GEN_VEXT_SHIFT_VX(vsll_vx_w
, uint32_t, int32_t, H4
, H4
, DO_SLL
, 0x1f, clearl
)
1414 GEN_VEXT_SHIFT_VX(vsll_vx_d
, uint64_t, int64_t, H8
, H8
, DO_SLL
, 0x3f, clearq
)
1416 GEN_VEXT_SHIFT_VX(vsrl_vx_b
, uint8_t, uint8_t, H1
, H1
, DO_SRL
, 0x7, clearb
)
1417 GEN_VEXT_SHIFT_VX(vsrl_vx_h
, uint16_t, uint16_t, H2
, H2
, DO_SRL
, 0xf, clearh
)
1418 GEN_VEXT_SHIFT_VX(vsrl_vx_w
, uint32_t, uint32_t, H4
, H4
, DO_SRL
, 0x1f, clearl
)
1419 GEN_VEXT_SHIFT_VX(vsrl_vx_d
, uint64_t, uint64_t, H8
, H8
, DO_SRL
, 0x3f, clearq
)
1421 GEN_VEXT_SHIFT_VX(vsra_vx_b
, int8_t, int8_t, H1
, H1
, DO_SRL
, 0x7, clearb
)
1422 GEN_VEXT_SHIFT_VX(vsra_vx_h
, int16_t, int16_t, H2
, H2
, DO_SRL
, 0xf, clearh
)
1423 GEN_VEXT_SHIFT_VX(vsra_vx_w
, int32_t, int32_t, H4
, H4
, DO_SRL
, 0x1f, clearl
)
1424 GEN_VEXT_SHIFT_VX(vsra_vx_d
, int64_t, int64_t, H8
, H8
, DO_SRL
, 0x3f, clearq
)
1426 /* Vector Narrowing Integer Right Shift Instructions */
1427 GEN_VEXT_SHIFT_VV(vnsrl_vv_b
, uint8_t, uint16_t, H1
, H2
, DO_SRL
, 0xf, clearb
)
1428 GEN_VEXT_SHIFT_VV(vnsrl_vv_h
, uint16_t, uint32_t, H2
, H4
, DO_SRL
, 0x1f, clearh
)
1429 GEN_VEXT_SHIFT_VV(vnsrl_vv_w
, uint32_t, uint64_t, H4
, H8
, DO_SRL
, 0x3f, clearl
)
1430 GEN_VEXT_SHIFT_VV(vnsra_vv_b
, uint8_t, int16_t, H1
, H2
, DO_SRL
, 0xf, clearb
)
1431 GEN_VEXT_SHIFT_VV(vnsra_vv_h
, uint16_t, int32_t, H2
, H4
, DO_SRL
, 0x1f, clearh
)
1432 GEN_VEXT_SHIFT_VV(vnsra_vv_w
, uint32_t, int64_t, H4
, H8
, DO_SRL
, 0x3f, clearl
)
1433 GEN_VEXT_SHIFT_VX(vnsrl_vx_b
, uint8_t, uint16_t, H1
, H2
, DO_SRL
, 0xf, clearb
)
1434 GEN_VEXT_SHIFT_VX(vnsrl_vx_h
, uint16_t, uint32_t, H2
, H4
, DO_SRL
, 0x1f, clearh
)
1435 GEN_VEXT_SHIFT_VX(vnsrl_vx_w
, uint32_t, uint64_t, H4
, H8
, DO_SRL
, 0x3f, clearl
)
1436 GEN_VEXT_SHIFT_VX(vnsra_vx_b
, int8_t, int16_t, H1
, H2
, DO_SRL
, 0xf, clearb
)
1437 GEN_VEXT_SHIFT_VX(vnsra_vx_h
, int16_t, int32_t, H2
, H4
, DO_SRL
, 0x1f, clearh
)
1438 GEN_VEXT_SHIFT_VX(vnsra_vx_w
, int32_t, int64_t, H4
, H8
, DO_SRL
, 0x3f, clearl
)
1440 /* Vector Integer Comparison Instructions */
1441 #define DO_MSEQ(N, M) (N == M)
1442 #define DO_MSNE(N, M) (N != M)
1443 #define DO_MSLT(N, M) (N < M)
1444 #define DO_MSLE(N, M) (N <= M)
1445 #define DO_MSGT(N, M) (N > M)
1447 #define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
1448 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1449 CPURISCVState *env, uint32_t desc) \
1451 uint32_t mlen = vext_mlen(desc); \
1452 uint32_t vm = vext_vm(desc); \
1453 uint32_t vl = env->vl; \
1454 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1457 for (i = 0; i < vl; i++) { \
1458 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1459 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1460 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1463 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
1465 for (; i < vlmax; i++) { \
1466 vext_set_elem_mask(vd, mlen, i, 0); \
1470 GEN_VEXT_CMP_VV(vmseq_vv_b
, uint8_t, H1
, DO_MSEQ
)
1471 GEN_VEXT_CMP_VV(vmseq_vv_h
, uint16_t, H2
, DO_MSEQ
)
1472 GEN_VEXT_CMP_VV(vmseq_vv_w
, uint32_t, H4
, DO_MSEQ
)
1473 GEN_VEXT_CMP_VV(vmseq_vv_d
, uint64_t, H8
, DO_MSEQ
)
1475 GEN_VEXT_CMP_VV(vmsne_vv_b
, uint8_t, H1
, DO_MSNE
)
1476 GEN_VEXT_CMP_VV(vmsne_vv_h
, uint16_t, H2
, DO_MSNE
)
1477 GEN_VEXT_CMP_VV(vmsne_vv_w
, uint32_t, H4
, DO_MSNE
)
1478 GEN_VEXT_CMP_VV(vmsne_vv_d
, uint64_t, H8
, DO_MSNE
)
1480 GEN_VEXT_CMP_VV(vmsltu_vv_b
, uint8_t, H1
, DO_MSLT
)
1481 GEN_VEXT_CMP_VV(vmsltu_vv_h
, uint16_t, H2
, DO_MSLT
)
1482 GEN_VEXT_CMP_VV(vmsltu_vv_w
, uint32_t, H4
, DO_MSLT
)
1483 GEN_VEXT_CMP_VV(vmsltu_vv_d
, uint64_t, H8
, DO_MSLT
)
1485 GEN_VEXT_CMP_VV(vmslt_vv_b
, int8_t, H1
, DO_MSLT
)
1486 GEN_VEXT_CMP_VV(vmslt_vv_h
, int16_t, H2
, DO_MSLT
)
1487 GEN_VEXT_CMP_VV(vmslt_vv_w
, int32_t, H4
, DO_MSLT
)
1488 GEN_VEXT_CMP_VV(vmslt_vv_d
, int64_t, H8
, DO_MSLT
)
1490 GEN_VEXT_CMP_VV(vmsleu_vv_b
, uint8_t, H1
, DO_MSLE
)
1491 GEN_VEXT_CMP_VV(vmsleu_vv_h
, uint16_t, H2
, DO_MSLE
)
1492 GEN_VEXT_CMP_VV(vmsleu_vv_w
, uint32_t, H4
, DO_MSLE
)
1493 GEN_VEXT_CMP_VV(vmsleu_vv_d
, uint64_t, H8
, DO_MSLE
)
1495 GEN_VEXT_CMP_VV(vmsle_vv_b
, int8_t, H1
, DO_MSLE
)
1496 GEN_VEXT_CMP_VV(vmsle_vv_h
, int16_t, H2
, DO_MSLE
)
1497 GEN_VEXT_CMP_VV(vmsle_vv_w
, int32_t, H4
, DO_MSLE
)
1498 GEN_VEXT_CMP_VV(vmsle_vv_d
, int64_t, H8
, DO_MSLE
)
1500 #define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
1501 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1502 CPURISCVState *env, uint32_t desc) \
1504 uint32_t mlen = vext_mlen(desc); \
1505 uint32_t vm = vext_vm(desc); \
1506 uint32_t vl = env->vl; \
1507 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1510 for (i = 0; i < vl; i++) { \
1511 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1512 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1515 vext_set_elem_mask(vd, mlen, i, \
1516 DO_OP(s2, (ETYPE)(target_long)s1)); \
1518 for (; i < vlmax; i++) { \
1519 vext_set_elem_mask(vd, mlen, i, 0); \
1523 GEN_VEXT_CMP_VX(vmseq_vx_b
, uint8_t, H1
, DO_MSEQ
)
1524 GEN_VEXT_CMP_VX(vmseq_vx_h
, uint16_t, H2
, DO_MSEQ
)
1525 GEN_VEXT_CMP_VX(vmseq_vx_w
, uint32_t, H4
, DO_MSEQ
)
1526 GEN_VEXT_CMP_VX(vmseq_vx_d
, uint64_t, H8
, DO_MSEQ
)
1528 GEN_VEXT_CMP_VX(vmsne_vx_b
, uint8_t, H1
, DO_MSNE
)
1529 GEN_VEXT_CMP_VX(vmsne_vx_h
, uint16_t, H2
, DO_MSNE
)
1530 GEN_VEXT_CMP_VX(vmsne_vx_w
, uint32_t, H4
, DO_MSNE
)
1531 GEN_VEXT_CMP_VX(vmsne_vx_d
, uint64_t, H8
, DO_MSNE
)
1533 GEN_VEXT_CMP_VX(vmsltu_vx_b
, uint8_t, H1
, DO_MSLT
)
1534 GEN_VEXT_CMP_VX(vmsltu_vx_h
, uint16_t, H2
, DO_MSLT
)
1535 GEN_VEXT_CMP_VX(vmsltu_vx_w
, uint32_t, H4
, DO_MSLT
)
1536 GEN_VEXT_CMP_VX(vmsltu_vx_d
, uint64_t, H8
, DO_MSLT
)
1538 GEN_VEXT_CMP_VX(vmslt_vx_b
, int8_t, H1
, DO_MSLT
)
1539 GEN_VEXT_CMP_VX(vmslt_vx_h
, int16_t, H2
, DO_MSLT
)
1540 GEN_VEXT_CMP_VX(vmslt_vx_w
, int32_t, H4
, DO_MSLT
)
1541 GEN_VEXT_CMP_VX(vmslt_vx_d
, int64_t, H8
, DO_MSLT
)
1543 GEN_VEXT_CMP_VX(vmsleu_vx_b
, uint8_t, H1
, DO_MSLE
)
1544 GEN_VEXT_CMP_VX(vmsleu_vx_h
, uint16_t, H2
, DO_MSLE
)
1545 GEN_VEXT_CMP_VX(vmsleu_vx_w
, uint32_t, H4
, DO_MSLE
)
1546 GEN_VEXT_CMP_VX(vmsleu_vx_d
, uint64_t, H8
, DO_MSLE
)
1548 GEN_VEXT_CMP_VX(vmsle_vx_b
, int8_t, H1
, DO_MSLE
)
1549 GEN_VEXT_CMP_VX(vmsle_vx_h
, int16_t, H2
, DO_MSLE
)
1550 GEN_VEXT_CMP_VX(vmsle_vx_w
, int32_t, H4
, DO_MSLE
)
1551 GEN_VEXT_CMP_VX(vmsle_vx_d
, int64_t, H8
, DO_MSLE
)
1553 GEN_VEXT_CMP_VX(vmsgtu_vx_b
, uint8_t, H1
, DO_MSGT
)
1554 GEN_VEXT_CMP_VX(vmsgtu_vx_h
, uint16_t, H2
, DO_MSGT
)
1555 GEN_VEXT_CMP_VX(vmsgtu_vx_w
, uint32_t, H4
, DO_MSGT
)
1556 GEN_VEXT_CMP_VX(vmsgtu_vx_d
, uint64_t, H8
, DO_MSGT
)
1558 GEN_VEXT_CMP_VX(vmsgt_vx_b
, int8_t, H1
, DO_MSGT
)
1559 GEN_VEXT_CMP_VX(vmsgt_vx_h
, int16_t, H2
, DO_MSGT
)
1560 GEN_VEXT_CMP_VX(vmsgt_vx_w
, int32_t, H4
, DO_MSGT
)
1561 GEN_VEXT_CMP_VX(vmsgt_vx_d
, int64_t, H8
, DO_MSGT
)
1563 /* Vector Integer Min/Max Instructions */
1564 RVVCALL(OPIVV2
, vminu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, DO_MIN
)
1565 RVVCALL(OPIVV2
, vminu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, DO_MIN
)
1566 RVVCALL(OPIVV2
, vminu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, DO_MIN
)
1567 RVVCALL(OPIVV2
, vminu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, DO_MIN
)
1568 RVVCALL(OPIVV2
, vmin_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_MIN
)
1569 RVVCALL(OPIVV2
, vmin_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_MIN
)
1570 RVVCALL(OPIVV2
, vmin_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_MIN
)
1571 RVVCALL(OPIVV2
, vmin_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_MIN
)
1572 RVVCALL(OPIVV2
, vmaxu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, DO_MAX
)
1573 RVVCALL(OPIVV2
, vmaxu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, DO_MAX
)
1574 RVVCALL(OPIVV2
, vmaxu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, DO_MAX
)
1575 RVVCALL(OPIVV2
, vmaxu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, DO_MAX
)
1576 RVVCALL(OPIVV2
, vmax_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_MAX
)
1577 RVVCALL(OPIVV2
, vmax_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_MAX
)
1578 RVVCALL(OPIVV2
, vmax_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_MAX
)
1579 RVVCALL(OPIVV2
, vmax_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_MAX
)
1580 GEN_VEXT_VV(vminu_vv_b
, 1, 1, clearb
)
1581 GEN_VEXT_VV(vminu_vv_h
, 2, 2, clearh
)
1582 GEN_VEXT_VV(vminu_vv_w
, 4, 4, clearl
)
1583 GEN_VEXT_VV(vminu_vv_d
, 8, 8, clearq
)
1584 GEN_VEXT_VV(vmin_vv_b
, 1, 1, clearb
)
1585 GEN_VEXT_VV(vmin_vv_h
, 2, 2, clearh
)
1586 GEN_VEXT_VV(vmin_vv_w
, 4, 4, clearl
)
1587 GEN_VEXT_VV(vmin_vv_d
, 8, 8, clearq
)
1588 GEN_VEXT_VV(vmaxu_vv_b
, 1, 1, clearb
)
1589 GEN_VEXT_VV(vmaxu_vv_h
, 2, 2, clearh
)
1590 GEN_VEXT_VV(vmaxu_vv_w
, 4, 4, clearl
)
1591 GEN_VEXT_VV(vmaxu_vv_d
, 8, 8, clearq
)
1592 GEN_VEXT_VV(vmax_vv_b
, 1, 1, clearb
)
1593 GEN_VEXT_VV(vmax_vv_h
, 2, 2, clearh
)
1594 GEN_VEXT_VV(vmax_vv_w
, 4, 4, clearl
)
1595 GEN_VEXT_VV(vmax_vv_d
, 8, 8, clearq
)
1597 RVVCALL(OPIVX2
, vminu_vx_b
, OP_UUU_B
, H1
, H1
, DO_MIN
)
1598 RVVCALL(OPIVX2
, vminu_vx_h
, OP_UUU_H
, H2
, H2
, DO_MIN
)
1599 RVVCALL(OPIVX2
, vminu_vx_w
, OP_UUU_W
, H4
, H4
, DO_MIN
)
1600 RVVCALL(OPIVX2
, vminu_vx_d
, OP_UUU_D
, H8
, H8
, DO_MIN
)
1601 RVVCALL(OPIVX2
, vmin_vx_b
, OP_SSS_B
, H1
, H1
, DO_MIN
)
1602 RVVCALL(OPIVX2
, vmin_vx_h
, OP_SSS_H
, H2
, H2
, DO_MIN
)
1603 RVVCALL(OPIVX2
, vmin_vx_w
, OP_SSS_W
, H4
, H4
, DO_MIN
)
1604 RVVCALL(OPIVX2
, vmin_vx_d
, OP_SSS_D
, H8
, H8
, DO_MIN
)
1605 RVVCALL(OPIVX2
, vmaxu_vx_b
, OP_UUU_B
, H1
, H1
, DO_MAX
)
1606 RVVCALL(OPIVX2
, vmaxu_vx_h
, OP_UUU_H
, H2
, H2
, DO_MAX
)
1607 RVVCALL(OPIVX2
, vmaxu_vx_w
, OP_UUU_W
, H4
, H4
, DO_MAX
)
1608 RVVCALL(OPIVX2
, vmaxu_vx_d
, OP_UUU_D
, H8
, H8
, DO_MAX
)
1609 RVVCALL(OPIVX2
, vmax_vx_b
, OP_SSS_B
, H1
, H1
, DO_MAX
)
1610 RVVCALL(OPIVX2
, vmax_vx_h
, OP_SSS_H
, H2
, H2
, DO_MAX
)
1611 RVVCALL(OPIVX2
, vmax_vx_w
, OP_SSS_W
, H4
, H4
, DO_MAX
)
1612 RVVCALL(OPIVX2
, vmax_vx_d
, OP_SSS_D
, H8
, H8
, DO_MAX
)
1613 GEN_VEXT_VX(vminu_vx_b
, 1, 1, clearb
)
1614 GEN_VEXT_VX(vminu_vx_h
, 2, 2, clearh
)
1615 GEN_VEXT_VX(vminu_vx_w
, 4, 4, clearl
)
1616 GEN_VEXT_VX(vminu_vx_d
, 8, 8, clearq
)
1617 GEN_VEXT_VX(vmin_vx_b
, 1, 1, clearb
)
1618 GEN_VEXT_VX(vmin_vx_h
, 2, 2, clearh
)
1619 GEN_VEXT_VX(vmin_vx_w
, 4, 4, clearl
)
1620 GEN_VEXT_VX(vmin_vx_d
, 8, 8, clearq
)
1621 GEN_VEXT_VX(vmaxu_vx_b
, 1, 1, clearb
)
1622 GEN_VEXT_VX(vmaxu_vx_h
, 2, 2, clearh
)
1623 GEN_VEXT_VX(vmaxu_vx_w
, 4, 4, clearl
)
1624 GEN_VEXT_VX(vmaxu_vx_d
, 8, 8, clearq
)
1625 GEN_VEXT_VX(vmax_vx_b
, 1, 1, clearb
)
1626 GEN_VEXT_VX(vmax_vx_h
, 2, 2, clearh
)
1627 GEN_VEXT_VX(vmax_vx_w
, 4, 4, clearl
)
1628 GEN_VEXT_VX(vmax_vx_d
, 8, 8, clearq
)
1630 /* Vector Single-Width Integer Multiply Instructions */
1631 #define DO_MUL(N, M) (N * M)
1632 RVVCALL(OPIVV2
, vmul_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_MUL
)
1633 RVVCALL(OPIVV2
, vmul_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_MUL
)
1634 RVVCALL(OPIVV2
, vmul_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_MUL
)
1635 RVVCALL(OPIVV2
, vmul_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_MUL
)
1636 GEN_VEXT_VV(vmul_vv_b
, 1, 1, clearb
)
1637 GEN_VEXT_VV(vmul_vv_h
, 2, 2, clearh
)
1638 GEN_VEXT_VV(vmul_vv_w
, 4, 4, clearl
)
1639 GEN_VEXT_VV(vmul_vv_d
, 8, 8, clearq
)
1641 static int8_t do_mulh_b(int8_t s2
, int8_t s1
)
1643 return (int16_t)s2
* (int16_t)s1
>> 8;
1646 static int16_t do_mulh_h(int16_t s2
, int16_t s1
)
1648 return (int32_t)s2
* (int32_t)s1
>> 16;
1651 static int32_t do_mulh_w(int32_t s2
, int32_t s1
)
1653 return (int64_t)s2
* (int64_t)s1
>> 32;
1656 static int64_t do_mulh_d(int64_t s2
, int64_t s1
)
1658 uint64_t hi_64
, lo_64
;
1660 muls64(&lo_64
, &hi_64
, s1
, s2
);
1664 static uint8_t do_mulhu_b(uint8_t s2
, uint8_t s1
)
1666 return (uint16_t)s2
* (uint16_t)s1
>> 8;
1669 static uint16_t do_mulhu_h(uint16_t s2
, uint16_t s1
)
1671 return (uint32_t)s2
* (uint32_t)s1
>> 16;
1674 static uint32_t do_mulhu_w(uint32_t s2
, uint32_t s1
)
1676 return (uint64_t)s2
* (uint64_t)s1
>> 32;
1679 static uint64_t do_mulhu_d(uint64_t s2
, uint64_t s1
)
1681 uint64_t hi_64
, lo_64
;
1683 mulu64(&lo_64
, &hi_64
, s2
, s1
);
1687 static int8_t do_mulhsu_b(int8_t s2
, uint8_t s1
)
1689 return (int16_t)s2
* (uint16_t)s1
>> 8;
1692 static int16_t do_mulhsu_h(int16_t s2
, uint16_t s1
)
1694 return (int32_t)s2
* (uint32_t)s1
>> 16;
1697 static int32_t do_mulhsu_w(int32_t s2
, uint32_t s1
)
1699 return (int64_t)s2
* (uint64_t)s1
>> 32;
1703 * Let A = signed operand,
1704 * B = unsigned operand
1705 * P = mulu64(A, B), unsigned product
1707 * LET X = 2 ** 64 - A, 2's complement of A
1708 * SP = signed product
1712 * = -(2 ** 64 - A) * B
1713 * = A * B - 2 ** 64 * B
1718 * HI_P -= (A < 0 ? B : 0)
1721 static int64_t do_mulhsu_d(int64_t s2
, uint64_t s1
)
1723 uint64_t hi_64
, lo_64
;
1725 mulu64(&lo_64
, &hi_64
, s2
, s1
);
1727 hi_64
-= s2
< 0 ? s1
: 0;
1731 RVVCALL(OPIVV2
, vmulh_vv_b
, OP_SSS_B
, H1
, H1
, H1
, do_mulh_b
)
1732 RVVCALL(OPIVV2
, vmulh_vv_h
, OP_SSS_H
, H2
, H2
, H2
, do_mulh_h
)
1733 RVVCALL(OPIVV2
, vmulh_vv_w
, OP_SSS_W
, H4
, H4
, H4
, do_mulh_w
)
1734 RVVCALL(OPIVV2
, vmulh_vv_d
, OP_SSS_D
, H8
, H8
, H8
, do_mulh_d
)
1735 RVVCALL(OPIVV2
, vmulhu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, do_mulhu_b
)
1736 RVVCALL(OPIVV2
, vmulhu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, do_mulhu_h
)
1737 RVVCALL(OPIVV2
, vmulhu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, do_mulhu_w
)
1738 RVVCALL(OPIVV2
, vmulhu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, do_mulhu_d
)
1739 RVVCALL(OPIVV2
, vmulhsu_vv_b
, OP_SUS_B
, H1
, H1
, H1
, do_mulhsu_b
)
1740 RVVCALL(OPIVV2
, vmulhsu_vv_h
, OP_SUS_H
, H2
, H2
, H2
, do_mulhsu_h
)
1741 RVVCALL(OPIVV2
, vmulhsu_vv_w
, OP_SUS_W
, H4
, H4
, H4
, do_mulhsu_w
)
1742 RVVCALL(OPIVV2
, vmulhsu_vv_d
, OP_SUS_D
, H8
, H8
, H8
, do_mulhsu_d
)
1743 GEN_VEXT_VV(vmulh_vv_b
, 1, 1, clearb
)
1744 GEN_VEXT_VV(vmulh_vv_h
, 2, 2, clearh
)
1745 GEN_VEXT_VV(vmulh_vv_w
, 4, 4, clearl
)
1746 GEN_VEXT_VV(vmulh_vv_d
, 8, 8, clearq
)
1747 GEN_VEXT_VV(vmulhu_vv_b
, 1, 1, clearb
)
1748 GEN_VEXT_VV(vmulhu_vv_h
, 2, 2, clearh
)
1749 GEN_VEXT_VV(vmulhu_vv_w
, 4, 4, clearl
)
1750 GEN_VEXT_VV(vmulhu_vv_d
, 8, 8, clearq
)
1751 GEN_VEXT_VV(vmulhsu_vv_b
, 1, 1, clearb
)
1752 GEN_VEXT_VV(vmulhsu_vv_h
, 2, 2, clearh
)
1753 GEN_VEXT_VV(vmulhsu_vv_w
, 4, 4, clearl
)
1754 GEN_VEXT_VV(vmulhsu_vv_d
, 8, 8, clearq
)
1756 RVVCALL(OPIVX2
, vmul_vx_b
, OP_SSS_B
, H1
, H1
, DO_MUL
)
1757 RVVCALL(OPIVX2
, vmul_vx_h
, OP_SSS_H
, H2
, H2
, DO_MUL
)
1758 RVVCALL(OPIVX2
, vmul_vx_w
, OP_SSS_W
, H4
, H4
, DO_MUL
)
1759 RVVCALL(OPIVX2
, vmul_vx_d
, OP_SSS_D
, H8
, H8
, DO_MUL
)
1760 RVVCALL(OPIVX2
, vmulh_vx_b
, OP_SSS_B
, H1
, H1
, do_mulh_b
)
1761 RVVCALL(OPIVX2
, vmulh_vx_h
, OP_SSS_H
, H2
, H2
, do_mulh_h
)
1762 RVVCALL(OPIVX2
, vmulh_vx_w
, OP_SSS_W
, H4
, H4
, do_mulh_w
)
1763 RVVCALL(OPIVX2
, vmulh_vx_d
, OP_SSS_D
, H8
, H8
, do_mulh_d
)
1764 RVVCALL(OPIVX2
, vmulhu_vx_b
, OP_UUU_B
, H1
, H1
, do_mulhu_b
)
1765 RVVCALL(OPIVX2
, vmulhu_vx_h
, OP_UUU_H
, H2
, H2
, do_mulhu_h
)
1766 RVVCALL(OPIVX2
, vmulhu_vx_w
, OP_UUU_W
, H4
, H4
, do_mulhu_w
)
1767 RVVCALL(OPIVX2
, vmulhu_vx_d
, OP_UUU_D
, H8
, H8
, do_mulhu_d
)
1768 RVVCALL(OPIVX2
, vmulhsu_vx_b
, OP_SUS_B
, H1
, H1
, do_mulhsu_b
)
1769 RVVCALL(OPIVX2
, vmulhsu_vx_h
, OP_SUS_H
, H2
, H2
, do_mulhsu_h
)
1770 RVVCALL(OPIVX2
, vmulhsu_vx_w
, OP_SUS_W
, H4
, H4
, do_mulhsu_w
)
1771 RVVCALL(OPIVX2
, vmulhsu_vx_d
, OP_SUS_D
, H8
, H8
, do_mulhsu_d
)
1772 GEN_VEXT_VX(vmul_vx_b
, 1, 1, clearb
)
1773 GEN_VEXT_VX(vmul_vx_h
, 2, 2, clearh
)
1774 GEN_VEXT_VX(vmul_vx_w
, 4, 4, clearl
)
1775 GEN_VEXT_VX(vmul_vx_d
, 8, 8, clearq
)
1776 GEN_VEXT_VX(vmulh_vx_b
, 1, 1, clearb
)
1777 GEN_VEXT_VX(vmulh_vx_h
, 2, 2, clearh
)
1778 GEN_VEXT_VX(vmulh_vx_w
, 4, 4, clearl
)
1779 GEN_VEXT_VX(vmulh_vx_d
, 8, 8, clearq
)
1780 GEN_VEXT_VX(vmulhu_vx_b
, 1, 1, clearb
)
1781 GEN_VEXT_VX(vmulhu_vx_h
, 2, 2, clearh
)
1782 GEN_VEXT_VX(vmulhu_vx_w
, 4, 4, clearl
)
1783 GEN_VEXT_VX(vmulhu_vx_d
, 8, 8, clearq
)
1784 GEN_VEXT_VX(vmulhsu_vx_b
, 1, 1, clearb
)
1785 GEN_VEXT_VX(vmulhsu_vx_h
, 2, 2, clearh
)
1786 GEN_VEXT_VX(vmulhsu_vx_w
, 4, 4, clearl
)
1787 GEN_VEXT_VX(vmulhsu_vx_d
, 8, 8, clearq
)
1789 /* Vector Integer Divide Instructions */
1790 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
1791 #define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
1792 #define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
1793 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
1794 #define DO_REM(N, M) (unlikely(M == 0) ? N :\
1795 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
1797 RVVCALL(OPIVV2
, vdivu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, DO_DIVU
)
1798 RVVCALL(OPIVV2
, vdivu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, DO_DIVU
)
1799 RVVCALL(OPIVV2
, vdivu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, DO_DIVU
)
1800 RVVCALL(OPIVV2
, vdivu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, DO_DIVU
)
1801 RVVCALL(OPIVV2
, vdiv_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_DIV
)
1802 RVVCALL(OPIVV2
, vdiv_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_DIV
)
1803 RVVCALL(OPIVV2
, vdiv_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_DIV
)
1804 RVVCALL(OPIVV2
, vdiv_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_DIV
)
1805 RVVCALL(OPIVV2
, vremu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, DO_REMU
)
1806 RVVCALL(OPIVV2
, vremu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, DO_REMU
)
1807 RVVCALL(OPIVV2
, vremu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, DO_REMU
)
1808 RVVCALL(OPIVV2
, vremu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, DO_REMU
)
1809 RVVCALL(OPIVV2
, vrem_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_REM
)
1810 RVVCALL(OPIVV2
, vrem_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_REM
)
1811 RVVCALL(OPIVV2
, vrem_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_REM
)
1812 RVVCALL(OPIVV2
, vrem_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_REM
)
1813 GEN_VEXT_VV(vdivu_vv_b
, 1, 1, clearb
)
1814 GEN_VEXT_VV(vdivu_vv_h
, 2, 2, clearh
)
1815 GEN_VEXT_VV(vdivu_vv_w
, 4, 4, clearl
)
1816 GEN_VEXT_VV(vdivu_vv_d
, 8, 8, clearq
)
1817 GEN_VEXT_VV(vdiv_vv_b
, 1, 1, clearb
)
1818 GEN_VEXT_VV(vdiv_vv_h
, 2, 2, clearh
)
1819 GEN_VEXT_VV(vdiv_vv_w
, 4, 4, clearl
)
1820 GEN_VEXT_VV(vdiv_vv_d
, 8, 8, clearq
)
1821 GEN_VEXT_VV(vremu_vv_b
, 1, 1, clearb
)
1822 GEN_VEXT_VV(vremu_vv_h
, 2, 2, clearh
)
1823 GEN_VEXT_VV(vremu_vv_w
, 4, 4, clearl
)
1824 GEN_VEXT_VV(vremu_vv_d
, 8, 8, clearq
)
1825 GEN_VEXT_VV(vrem_vv_b
, 1, 1, clearb
)
1826 GEN_VEXT_VV(vrem_vv_h
, 2, 2, clearh
)
1827 GEN_VEXT_VV(vrem_vv_w
, 4, 4, clearl
)
1828 GEN_VEXT_VV(vrem_vv_d
, 8, 8, clearq
)
1830 RVVCALL(OPIVX2
, vdivu_vx_b
, OP_UUU_B
, H1
, H1
, DO_DIVU
)
1831 RVVCALL(OPIVX2
, vdivu_vx_h
, OP_UUU_H
, H2
, H2
, DO_DIVU
)
1832 RVVCALL(OPIVX2
, vdivu_vx_w
, OP_UUU_W
, H4
, H4
, DO_DIVU
)
1833 RVVCALL(OPIVX2
, vdivu_vx_d
, OP_UUU_D
, H8
, H8
, DO_DIVU
)
1834 RVVCALL(OPIVX2
, vdiv_vx_b
, OP_SSS_B
, H1
, H1
, DO_DIV
)
1835 RVVCALL(OPIVX2
, vdiv_vx_h
, OP_SSS_H
, H2
, H2
, DO_DIV
)
1836 RVVCALL(OPIVX2
, vdiv_vx_w
, OP_SSS_W
, H4
, H4
, DO_DIV
)
1837 RVVCALL(OPIVX2
, vdiv_vx_d
, OP_SSS_D
, H8
, H8
, DO_DIV
)
1838 RVVCALL(OPIVX2
, vremu_vx_b
, OP_UUU_B
, H1
, H1
, DO_REMU
)
1839 RVVCALL(OPIVX2
, vremu_vx_h
, OP_UUU_H
, H2
, H2
, DO_REMU
)
1840 RVVCALL(OPIVX2
, vremu_vx_w
, OP_UUU_W
, H4
, H4
, DO_REMU
)
1841 RVVCALL(OPIVX2
, vremu_vx_d
, OP_UUU_D
, H8
, H8
, DO_REMU
)
1842 RVVCALL(OPIVX2
, vrem_vx_b
, OP_SSS_B
, H1
, H1
, DO_REM
)
1843 RVVCALL(OPIVX2
, vrem_vx_h
, OP_SSS_H
, H2
, H2
, DO_REM
)
1844 RVVCALL(OPIVX2
, vrem_vx_w
, OP_SSS_W
, H4
, H4
, DO_REM
)
1845 RVVCALL(OPIVX2
, vrem_vx_d
, OP_SSS_D
, H8
, H8
, DO_REM
)
1846 GEN_VEXT_VX(vdivu_vx_b
, 1, 1, clearb
)
1847 GEN_VEXT_VX(vdivu_vx_h
, 2, 2, clearh
)
1848 GEN_VEXT_VX(vdivu_vx_w
, 4, 4, clearl
)
1849 GEN_VEXT_VX(vdivu_vx_d
, 8, 8, clearq
)
1850 GEN_VEXT_VX(vdiv_vx_b
, 1, 1, clearb
)
1851 GEN_VEXT_VX(vdiv_vx_h
, 2, 2, clearh
)
1852 GEN_VEXT_VX(vdiv_vx_w
, 4, 4, clearl
)
1853 GEN_VEXT_VX(vdiv_vx_d
, 8, 8, clearq
)
1854 GEN_VEXT_VX(vremu_vx_b
, 1, 1, clearb
)
1855 GEN_VEXT_VX(vremu_vx_h
, 2, 2, clearh
)
1856 GEN_VEXT_VX(vremu_vx_w
, 4, 4, clearl
)
1857 GEN_VEXT_VX(vremu_vx_d
, 8, 8, clearq
)
1858 GEN_VEXT_VX(vrem_vx_b
, 1, 1, clearb
)
1859 GEN_VEXT_VX(vrem_vx_h
, 2, 2, clearh
)
1860 GEN_VEXT_VX(vrem_vx_w
, 4, 4, clearl
)
1861 GEN_VEXT_VX(vrem_vx_d
, 8, 8, clearq
)
1863 /* Vector Widening Integer Multiply Instructions */
1864 RVVCALL(OPIVV2
, vwmul_vv_b
, WOP_SSS_B
, H2
, H1
, H1
, DO_MUL
)
1865 RVVCALL(OPIVV2
, vwmul_vv_h
, WOP_SSS_H
, H4
, H2
, H2
, DO_MUL
)
1866 RVVCALL(OPIVV2
, vwmul_vv_w
, WOP_SSS_W
, H8
, H4
, H4
, DO_MUL
)
1867 RVVCALL(OPIVV2
, vwmulu_vv_b
, WOP_UUU_B
, H2
, H1
, H1
, DO_MUL
)
1868 RVVCALL(OPIVV2
, vwmulu_vv_h
, WOP_UUU_H
, H4
, H2
, H2
, DO_MUL
)
1869 RVVCALL(OPIVV2
, vwmulu_vv_w
, WOP_UUU_W
, H8
, H4
, H4
, DO_MUL
)
1870 RVVCALL(OPIVV2
, vwmulsu_vv_b
, WOP_SUS_B
, H2
, H1
, H1
, DO_MUL
)
1871 RVVCALL(OPIVV2
, vwmulsu_vv_h
, WOP_SUS_H
, H4
, H2
, H2
, DO_MUL
)
1872 RVVCALL(OPIVV2
, vwmulsu_vv_w
, WOP_SUS_W
, H8
, H4
, H4
, DO_MUL
)
1873 GEN_VEXT_VV(vwmul_vv_b
, 1, 2, clearh
)
1874 GEN_VEXT_VV(vwmul_vv_h
, 2, 4, clearl
)
1875 GEN_VEXT_VV(vwmul_vv_w
, 4, 8, clearq
)
1876 GEN_VEXT_VV(vwmulu_vv_b
, 1, 2, clearh
)
1877 GEN_VEXT_VV(vwmulu_vv_h
, 2, 4, clearl
)
1878 GEN_VEXT_VV(vwmulu_vv_w
, 4, 8, clearq
)
1879 GEN_VEXT_VV(vwmulsu_vv_b
, 1, 2, clearh
)
1880 GEN_VEXT_VV(vwmulsu_vv_h
, 2, 4, clearl
)
1881 GEN_VEXT_VV(vwmulsu_vv_w
, 4, 8, clearq
)
1883 RVVCALL(OPIVX2
, vwmul_vx_b
, WOP_SSS_B
, H2
, H1
, DO_MUL
)
1884 RVVCALL(OPIVX2
, vwmul_vx_h
, WOP_SSS_H
, H4
, H2
, DO_MUL
)
1885 RVVCALL(OPIVX2
, vwmul_vx_w
, WOP_SSS_W
, H8
, H4
, DO_MUL
)
1886 RVVCALL(OPIVX2
, vwmulu_vx_b
, WOP_UUU_B
, H2
, H1
, DO_MUL
)
1887 RVVCALL(OPIVX2
, vwmulu_vx_h
, WOP_UUU_H
, H4
, H2
, DO_MUL
)
1888 RVVCALL(OPIVX2
, vwmulu_vx_w
, WOP_UUU_W
, H8
, H4
, DO_MUL
)
1889 RVVCALL(OPIVX2
, vwmulsu_vx_b
, WOP_SUS_B
, H2
, H1
, DO_MUL
)
1890 RVVCALL(OPIVX2
, vwmulsu_vx_h
, WOP_SUS_H
, H4
, H2
, DO_MUL
)
1891 RVVCALL(OPIVX2
, vwmulsu_vx_w
, WOP_SUS_W
, H8
, H4
, DO_MUL
)
1892 GEN_VEXT_VX(vwmul_vx_b
, 1, 2, clearh
)
1893 GEN_VEXT_VX(vwmul_vx_h
, 2, 4, clearl
)
1894 GEN_VEXT_VX(vwmul_vx_w
, 4, 8, clearq
)
1895 GEN_VEXT_VX(vwmulu_vx_b
, 1, 2, clearh
)
1896 GEN_VEXT_VX(vwmulu_vx_h
, 2, 4, clearl
)
1897 GEN_VEXT_VX(vwmulu_vx_w
, 4, 8, clearq
)
1898 GEN_VEXT_VX(vwmulsu_vx_b
, 1, 2, clearh
)
1899 GEN_VEXT_VX(vwmulsu_vx_h
, 2, 4, clearl
)
1900 GEN_VEXT_VX(vwmulsu_vx_w
, 4, 8, clearq
)
1902 /* Vector Single-Width Integer Multiply-Add Instructions */
1903 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
1904 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
1906 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
1907 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1908 TD d = *((TD *)vd + HD(i)); \
1909 *((TD *)vd + HD(i)) = OP(s2, s1, d); \
1912 #define DO_MACC(N, M, D) (M * N + D)
1913 #define DO_NMSAC(N, M, D) (-(M * N) + D)
1914 #define DO_MADD(N, M, D) (M * D + N)
1915 #define DO_NMSUB(N, M, D) (-(M * D) + N)
1916 RVVCALL(OPIVV3
, vmacc_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_MACC
)
1917 RVVCALL(OPIVV3
, vmacc_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_MACC
)
1918 RVVCALL(OPIVV3
, vmacc_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_MACC
)
1919 RVVCALL(OPIVV3
, vmacc_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_MACC
)
1920 RVVCALL(OPIVV3
, vnmsac_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_NMSAC
)
1921 RVVCALL(OPIVV3
, vnmsac_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_NMSAC
)
1922 RVVCALL(OPIVV3
, vnmsac_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_NMSAC
)
1923 RVVCALL(OPIVV3
, vnmsac_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_NMSAC
)
1924 RVVCALL(OPIVV3
, vmadd_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_MADD
)
1925 RVVCALL(OPIVV3
, vmadd_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_MADD
)
1926 RVVCALL(OPIVV3
, vmadd_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_MADD
)
1927 RVVCALL(OPIVV3
, vmadd_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_MADD
)
1928 RVVCALL(OPIVV3
, vnmsub_vv_b
, OP_SSS_B
, H1
, H1
, H1
, DO_NMSUB
)
1929 RVVCALL(OPIVV3
, vnmsub_vv_h
, OP_SSS_H
, H2
, H2
, H2
, DO_NMSUB
)
1930 RVVCALL(OPIVV3
, vnmsub_vv_w
, OP_SSS_W
, H4
, H4
, H4
, DO_NMSUB
)
1931 RVVCALL(OPIVV3
, vnmsub_vv_d
, OP_SSS_D
, H8
, H8
, H8
, DO_NMSUB
)
1932 GEN_VEXT_VV(vmacc_vv_b
, 1, 1, clearb
)
1933 GEN_VEXT_VV(vmacc_vv_h
, 2, 2, clearh
)
1934 GEN_VEXT_VV(vmacc_vv_w
, 4, 4, clearl
)
1935 GEN_VEXT_VV(vmacc_vv_d
, 8, 8, clearq
)
1936 GEN_VEXT_VV(vnmsac_vv_b
, 1, 1, clearb
)
1937 GEN_VEXT_VV(vnmsac_vv_h
, 2, 2, clearh
)
1938 GEN_VEXT_VV(vnmsac_vv_w
, 4, 4, clearl
)
1939 GEN_VEXT_VV(vnmsac_vv_d
, 8, 8, clearq
)
1940 GEN_VEXT_VV(vmadd_vv_b
, 1, 1, clearb
)
1941 GEN_VEXT_VV(vmadd_vv_h
, 2, 2, clearh
)
1942 GEN_VEXT_VV(vmadd_vv_w
, 4, 4, clearl
)
1943 GEN_VEXT_VV(vmadd_vv_d
, 8, 8, clearq
)
1944 GEN_VEXT_VV(vnmsub_vv_b
, 1, 1, clearb
)
1945 GEN_VEXT_VV(vnmsub_vv_h
, 2, 2, clearh
)
1946 GEN_VEXT_VV(vnmsub_vv_w
, 4, 4, clearl
)
1947 GEN_VEXT_VV(vnmsub_vv_d
, 8, 8, clearq
)
1949 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
1950 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
1952 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1953 TD d = *((TD *)vd + HD(i)); \
1954 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \
1957 RVVCALL(OPIVX3
, vmacc_vx_b
, OP_SSS_B
, H1
, H1
, DO_MACC
)
1958 RVVCALL(OPIVX3
, vmacc_vx_h
, OP_SSS_H
, H2
, H2
, DO_MACC
)
1959 RVVCALL(OPIVX3
, vmacc_vx_w
, OP_SSS_W
, H4
, H4
, DO_MACC
)
1960 RVVCALL(OPIVX3
, vmacc_vx_d
, OP_SSS_D
, H8
, H8
, DO_MACC
)
1961 RVVCALL(OPIVX3
, vnmsac_vx_b
, OP_SSS_B
, H1
, H1
, DO_NMSAC
)
1962 RVVCALL(OPIVX3
, vnmsac_vx_h
, OP_SSS_H
, H2
, H2
, DO_NMSAC
)
1963 RVVCALL(OPIVX3
, vnmsac_vx_w
, OP_SSS_W
, H4
, H4
, DO_NMSAC
)
1964 RVVCALL(OPIVX3
, vnmsac_vx_d
, OP_SSS_D
, H8
, H8
, DO_NMSAC
)
1965 RVVCALL(OPIVX3
, vmadd_vx_b
, OP_SSS_B
, H1
, H1
, DO_MADD
)
1966 RVVCALL(OPIVX3
, vmadd_vx_h
, OP_SSS_H
, H2
, H2
, DO_MADD
)
1967 RVVCALL(OPIVX3
, vmadd_vx_w
, OP_SSS_W
, H4
, H4
, DO_MADD
)
1968 RVVCALL(OPIVX3
, vmadd_vx_d
, OP_SSS_D
, H8
, H8
, DO_MADD
)
1969 RVVCALL(OPIVX3
, vnmsub_vx_b
, OP_SSS_B
, H1
, H1
, DO_NMSUB
)
1970 RVVCALL(OPIVX3
, vnmsub_vx_h
, OP_SSS_H
, H2
, H2
, DO_NMSUB
)
1971 RVVCALL(OPIVX3
, vnmsub_vx_w
, OP_SSS_W
, H4
, H4
, DO_NMSUB
)
1972 RVVCALL(OPIVX3
, vnmsub_vx_d
, OP_SSS_D
, H8
, H8
, DO_NMSUB
)
1973 GEN_VEXT_VX(vmacc_vx_b
, 1, 1, clearb
)
1974 GEN_VEXT_VX(vmacc_vx_h
, 2, 2, clearh
)
1975 GEN_VEXT_VX(vmacc_vx_w
, 4, 4, clearl
)
1976 GEN_VEXT_VX(vmacc_vx_d
, 8, 8, clearq
)
1977 GEN_VEXT_VX(vnmsac_vx_b
, 1, 1, clearb
)
1978 GEN_VEXT_VX(vnmsac_vx_h
, 2, 2, clearh
)
1979 GEN_VEXT_VX(vnmsac_vx_w
, 4, 4, clearl
)
1980 GEN_VEXT_VX(vnmsac_vx_d
, 8, 8, clearq
)
1981 GEN_VEXT_VX(vmadd_vx_b
, 1, 1, clearb
)
1982 GEN_VEXT_VX(vmadd_vx_h
, 2, 2, clearh
)
1983 GEN_VEXT_VX(vmadd_vx_w
, 4, 4, clearl
)
1984 GEN_VEXT_VX(vmadd_vx_d
, 8, 8, clearq
)
1985 GEN_VEXT_VX(vnmsub_vx_b
, 1, 1, clearb
)
1986 GEN_VEXT_VX(vnmsub_vx_h
, 2, 2, clearh
)
1987 GEN_VEXT_VX(vnmsub_vx_w
, 4, 4, clearl
)
1988 GEN_VEXT_VX(vnmsub_vx_d
, 8, 8, clearq
)
1990 /* Vector Widening Integer Multiply-Add Instructions */
1991 RVVCALL(OPIVV3
, vwmaccu_vv_b
, WOP_UUU_B
, H2
, H1
, H1
, DO_MACC
)
1992 RVVCALL(OPIVV3
, vwmaccu_vv_h
, WOP_UUU_H
, H4
, H2
, H2
, DO_MACC
)
1993 RVVCALL(OPIVV3
, vwmaccu_vv_w
, WOP_UUU_W
, H8
, H4
, H4
, DO_MACC
)
1994 RVVCALL(OPIVV3
, vwmacc_vv_b
, WOP_SSS_B
, H2
, H1
, H1
, DO_MACC
)
1995 RVVCALL(OPIVV3
, vwmacc_vv_h
, WOP_SSS_H
, H4
, H2
, H2
, DO_MACC
)
1996 RVVCALL(OPIVV3
, vwmacc_vv_w
, WOP_SSS_W
, H8
, H4
, H4
, DO_MACC
)
1997 RVVCALL(OPIVV3
, vwmaccsu_vv_b
, WOP_SSU_B
, H2
, H1
, H1
, DO_MACC
)
1998 RVVCALL(OPIVV3
, vwmaccsu_vv_h
, WOP_SSU_H
, H4
, H2
, H2
, DO_MACC
)
1999 RVVCALL(OPIVV3
, vwmaccsu_vv_w
, WOP_SSU_W
, H8
, H4
, H4
, DO_MACC
)
2000 GEN_VEXT_VV(vwmaccu_vv_b
, 1, 2, clearh
)
2001 GEN_VEXT_VV(vwmaccu_vv_h
, 2, 4, clearl
)
2002 GEN_VEXT_VV(vwmaccu_vv_w
, 4, 8, clearq
)
2003 GEN_VEXT_VV(vwmacc_vv_b
, 1, 2, clearh
)
2004 GEN_VEXT_VV(vwmacc_vv_h
, 2, 4, clearl
)
2005 GEN_VEXT_VV(vwmacc_vv_w
, 4, 8, clearq
)
2006 GEN_VEXT_VV(vwmaccsu_vv_b
, 1, 2, clearh
)
2007 GEN_VEXT_VV(vwmaccsu_vv_h
, 2, 4, clearl
)
2008 GEN_VEXT_VV(vwmaccsu_vv_w
, 4, 8, clearq
)
2010 RVVCALL(OPIVX3
, vwmaccu_vx_b
, WOP_UUU_B
, H2
, H1
, DO_MACC
)
2011 RVVCALL(OPIVX3
, vwmaccu_vx_h
, WOP_UUU_H
, H4
, H2
, DO_MACC
)
2012 RVVCALL(OPIVX3
, vwmaccu_vx_w
, WOP_UUU_W
, H8
, H4
, DO_MACC
)
2013 RVVCALL(OPIVX3
, vwmacc_vx_b
, WOP_SSS_B
, H2
, H1
, DO_MACC
)
2014 RVVCALL(OPIVX3
, vwmacc_vx_h
, WOP_SSS_H
, H4
, H2
, DO_MACC
)
2015 RVVCALL(OPIVX3
, vwmacc_vx_w
, WOP_SSS_W
, H8
, H4
, DO_MACC
)
2016 RVVCALL(OPIVX3
, vwmaccsu_vx_b
, WOP_SSU_B
, H2
, H1
, DO_MACC
)
2017 RVVCALL(OPIVX3
, vwmaccsu_vx_h
, WOP_SSU_H
, H4
, H2
, DO_MACC
)
2018 RVVCALL(OPIVX3
, vwmaccsu_vx_w
, WOP_SSU_W
, H8
, H4
, DO_MACC
)
2019 RVVCALL(OPIVX3
, vwmaccus_vx_b
, WOP_SUS_B
, H2
, H1
, DO_MACC
)
2020 RVVCALL(OPIVX3
, vwmaccus_vx_h
, WOP_SUS_H
, H4
, H2
, DO_MACC
)
2021 RVVCALL(OPIVX3
, vwmaccus_vx_w
, WOP_SUS_W
, H8
, H4
, DO_MACC
)
2022 GEN_VEXT_VX(vwmaccu_vx_b
, 1, 2, clearh
)
2023 GEN_VEXT_VX(vwmaccu_vx_h
, 2, 4, clearl
)
2024 GEN_VEXT_VX(vwmaccu_vx_w
, 4, 8, clearq
)
2025 GEN_VEXT_VX(vwmacc_vx_b
, 1, 2, clearh
)
2026 GEN_VEXT_VX(vwmacc_vx_h
, 2, 4, clearl
)
2027 GEN_VEXT_VX(vwmacc_vx_w
, 4, 8, clearq
)
2028 GEN_VEXT_VX(vwmaccsu_vx_b
, 1, 2, clearh
)
2029 GEN_VEXT_VX(vwmaccsu_vx_h
, 2, 4, clearl
)
2030 GEN_VEXT_VX(vwmaccsu_vx_w
, 4, 8, clearq
)
2031 GEN_VEXT_VX(vwmaccus_vx_b
, 1, 2, clearh
)
2032 GEN_VEXT_VX(vwmaccus_vx_h
, 2, 4, clearl
)
2033 GEN_VEXT_VX(vwmaccus_vx_w
, 4, 8, clearq
)
2035 /* Vector Integer Merge and Move Instructions */
2036 #define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
2037 void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
2040 uint32_t vl = env->vl; \
2041 uint32_t esz = sizeof(ETYPE); \
2042 uint32_t vlmax = vext_maxsz(desc) / esz; \
2045 for (i = 0; i < vl; i++) { \
2046 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
2047 *((ETYPE *)vd + H(i)) = s1; \
2049 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2052 GEN_VEXT_VMV_VV(vmv_v_v_b
, int8_t, H1
, clearb
)
2053 GEN_VEXT_VMV_VV(vmv_v_v_h
, int16_t, H2
, clearh
)
2054 GEN_VEXT_VMV_VV(vmv_v_v_w
, int32_t, H4
, clearl
)
2055 GEN_VEXT_VMV_VV(vmv_v_v_d
, int64_t, H8
, clearq
)
2057 #define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \
2058 void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
2061 uint32_t vl = env->vl; \
2062 uint32_t esz = sizeof(ETYPE); \
2063 uint32_t vlmax = vext_maxsz(desc) / esz; \
2066 for (i = 0; i < vl; i++) { \
2067 *((ETYPE *)vd + H(i)) = (ETYPE)s1; \
2069 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2072 GEN_VEXT_VMV_VX(vmv_v_x_b
, int8_t, H1
, clearb
)
2073 GEN_VEXT_VMV_VX(vmv_v_x_h
, int16_t, H2
, clearh
)
2074 GEN_VEXT_VMV_VX(vmv_v_x_w
, int32_t, H4
, clearl
)
2075 GEN_VEXT_VMV_VX(vmv_v_x_d
, int64_t, H8
, clearq
)
2077 #define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \
2078 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2079 CPURISCVState *env, uint32_t desc) \
2081 uint32_t mlen = vext_mlen(desc); \
2082 uint32_t vl = env->vl; \
2083 uint32_t esz = sizeof(ETYPE); \
2084 uint32_t vlmax = vext_maxsz(desc) / esz; \
2087 for (i = 0; i < vl; i++) { \
2088 ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
2089 *((ETYPE *)vd + H(i)) = *(vt + H(i)); \
2091 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2094 GEN_VEXT_VMERGE_VV(vmerge_vvm_b
, int8_t, H1
, clearb
)
2095 GEN_VEXT_VMERGE_VV(vmerge_vvm_h
, int16_t, H2
, clearh
)
2096 GEN_VEXT_VMERGE_VV(vmerge_vvm_w
, int32_t, H4
, clearl
)
2097 GEN_VEXT_VMERGE_VV(vmerge_vvm_d
, int64_t, H8
, clearq
)
2099 #define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \
2100 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2101 void *vs2, CPURISCVState *env, uint32_t desc) \
2103 uint32_t mlen = vext_mlen(desc); \
2104 uint32_t vl = env->vl; \
2105 uint32_t esz = sizeof(ETYPE); \
2106 uint32_t vlmax = vext_maxsz(desc) / esz; \
2109 for (i = 0; i < vl; i++) { \
2110 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
2111 ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
2112 (ETYPE)(target_long)s1); \
2113 *((ETYPE *)vd + H(i)) = d; \
2115 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2118 GEN_VEXT_VMERGE_VX(vmerge_vxm_b
, int8_t, H1
, clearb
)
2119 GEN_VEXT_VMERGE_VX(vmerge_vxm_h
, int16_t, H2
, clearh
)
2120 GEN_VEXT_VMERGE_VX(vmerge_vxm_w
, int32_t, H4
, clearl
)
2121 GEN_VEXT_VMERGE_VX(vmerge_vxm_d
, int64_t, H8
, clearq
)
2124 *** Vector Fixed-Point Arithmetic Instructions
2127 /* Vector Single-Width Saturating Add and Subtract */
2130 * As fixed point instructions probably have round mode and saturation,
2131 * define common macros for fixed point here.
2133 typedef void opivv2_rm_fn(void *vd
, void *vs1
, void *vs2
, int i
,
2134 CPURISCVState
*env
, int vxrm
);
2136 #define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
2137 static inline void \
2138 do_##NAME(void *vd, void *vs1, void *vs2, int i, \
2139 CPURISCVState *env, int vxrm) \
2141 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
2142 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2143 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1); \
2147 vext_vv_rm_1(void *vd
, void *v0
, void *vs1
, void *vs2
,
2149 uint32_t vl
, uint32_t vm
, uint32_t mlen
, int vxrm
,
2152 for (uint32_t i
= 0; i
< vl
; i
++) {
2153 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
2156 fn(vd
, vs1
, vs2
, i
, env
, vxrm
);
2161 vext_vv_rm_2(void *vd
, void *v0
, void *vs1
, void *vs2
,
2163 uint32_t desc
, uint32_t esz
, uint32_t dsz
,
2164 opivv2_rm_fn
*fn
, clear_fn
*clearfn
)
2166 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
2167 uint32_t mlen
= vext_mlen(desc
);
2168 uint32_t vm
= vext_vm(desc
);
2169 uint32_t vl
= env
->vl
;
2171 switch (env
->vxrm
) {
2173 vext_vv_rm_1(vd
, v0
, vs1
, vs2
,
2174 env
, vl
, vm
, mlen
, 0, fn
);
2177 vext_vv_rm_1(vd
, v0
, vs1
, vs2
,
2178 env
, vl
, vm
, mlen
, 1, fn
);
2181 vext_vv_rm_1(vd
, v0
, vs1
, vs2
,
2182 env
, vl
, vm
, mlen
, 2, fn
);
2185 vext_vv_rm_1(vd
, v0
, vs1
, vs2
,
2186 env
, vl
, vm
, mlen
, 3, fn
);
2190 clearfn(vd
, vl
, vl
* dsz
, vlmax
* dsz
);
2193 /* generate helpers for fixed point instructions with OPIVV format */
2194 #define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2195 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2196 CPURISCVState *env, uint32_t desc) \
2198 vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
2199 do_##NAME, CLEAR_FN); \
2202 static inline uint8_t saddu8(CPURISCVState
*env
, int vxrm
, uint8_t a
, uint8_t b
)
2204 uint8_t res
= a
+ b
;
2212 static inline uint16_t saddu16(CPURISCVState
*env
, int vxrm
, uint16_t a
,
2215 uint16_t res
= a
+ b
;
2223 static inline uint32_t saddu32(CPURISCVState
*env
, int vxrm
, uint32_t a
,
2226 uint32_t res
= a
+ b
;
2234 static inline uint64_t saddu64(CPURISCVState
*env
, int vxrm
, uint64_t a
,
2237 uint64_t res
= a
+ b
;
2245 RVVCALL(OPIVV2_RM
, vsaddu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, saddu8
)
2246 RVVCALL(OPIVV2_RM
, vsaddu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, saddu16
)
2247 RVVCALL(OPIVV2_RM
, vsaddu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, saddu32
)
2248 RVVCALL(OPIVV2_RM
, vsaddu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, saddu64
)
2249 GEN_VEXT_VV_RM(vsaddu_vv_b
, 1, 1, clearb
)
2250 GEN_VEXT_VV_RM(vsaddu_vv_h
, 2, 2, clearh
)
2251 GEN_VEXT_VV_RM(vsaddu_vv_w
, 4, 4, clearl
)
2252 GEN_VEXT_VV_RM(vsaddu_vv_d
, 8, 8, clearq
)
2254 typedef void opivx2_rm_fn(void *vd
, target_long s1
, void *vs2
, int i
,
2255 CPURISCVState
*env
, int vxrm
);
2257 #define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
2258 static inline void \
2259 do_##NAME(void *vd, target_long s1, void *vs2, int i, \
2260 CPURISCVState *env, int vxrm) \
2262 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2263 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1); \
2267 vext_vx_rm_1(void *vd
, void *v0
, target_long s1
, void *vs2
,
2269 uint32_t vl
, uint32_t vm
, uint32_t mlen
, int vxrm
,
2272 for (uint32_t i
= 0; i
< vl
; i
++) {
2273 if (!vm
&& !vext_elem_mask(v0
, mlen
, i
)) {
2276 fn(vd
, s1
, vs2
, i
, env
, vxrm
);
2281 vext_vx_rm_2(void *vd
, void *v0
, target_long s1
, void *vs2
,
2283 uint32_t desc
, uint32_t esz
, uint32_t dsz
,
2284 opivx2_rm_fn
*fn
, clear_fn
*clearfn
)
2286 uint32_t vlmax
= vext_maxsz(desc
) / esz
;
2287 uint32_t mlen
= vext_mlen(desc
);
2288 uint32_t vm
= vext_vm(desc
);
2289 uint32_t vl
= env
->vl
;
2291 switch (env
->vxrm
) {
2293 vext_vx_rm_1(vd
, v0
, s1
, vs2
,
2294 env
, vl
, vm
, mlen
, 0, fn
);
2297 vext_vx_rm_1(vd
, v0
, s1
, vs2
,
2298 env
, vl
, vm
, mlen
, 1, fn
);
2301 vext_vx_rm_1(vd
, v0
, s1
, vs2
,
2302 env
, vl
, vm
, mlen
, 2, fn
);
2305 vext_vx_rm_1(vd
, v0
, s1
, vs2
,
2306 env
, vl
, vm
, mlen
, 3, fn
);
2310 clearfn(vd
, vl
, vl
* dsz
, vlmax
* dsz
);
2313 /* generate helpers for fixed point instructions with OPIVX format */
2314 #define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2315 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2316 void *vs2, CPURISCVState *env, uint32_t desc) \
2318 vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
2319 do_##NAME, CLEAR_FN); \
2322 RVVCALL(OPIVX2_RM
, vsaddu_vx_b
, OP_UUU_B
, H1
, H1
, saddu8
)
2323 RVVCALL(OPIVX2_RM
, vsaddu_vx_h
, OP_UUU_H
, H2
, H2
, saddu16
)
2324 RVVCALL(OPIVX2_RM
, vsaddu_vx_w
, OP_UUU_W
, H4
, H4
, saddu32
)
2325 RVVCALL(OPIVX2_RM
, vsaddu_vx_d
, OP_UUU_D
, H8
, H8
, saddu64
)
2326 GEN_VEXT_VX_RM(vsaddu_vx_b
, 1, 1, clearb
)
2327 GEN_VEXT_VX_RM(vsaddu_vx_h
, 2, 2, clearh
)
2328 GEN_VEXT_VX_RM(vsaddu_vx_w
, 4, 4, clearl
)
2329 GEN_VEXT_VX_RM(vsaddu_vx_d
, 8, 8, clearq
)
2331 static inline int8_t sadd8(CPURISCVState
*env
, int vxrm
, int8_t a
, int8_t b
)
2334 if ((res
^ a
) & (res
^ b
) & INT8_MIN
) {
2335 res
= a
> 0 ? INT8_MAX
: INT8_MIN
;
2341 static inline int16_t sadd16(CPURISCVState
*env
, int vxrm
, int16_t a
, int16_t b
)
2343 int16_t res
= a
+ b
;
2344 if ((res
^ a
) & (res
^ b
) & INT16_MIN
) {
2345 res
= a
> 0 ? INT16_MAX
: INT16_MIN
;
2351 static inline int32_t sadd32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
2353 int32_t res
= a
+ b
;
2354 if ((res
^ a
) & (res
^ b
) & INT32_MIN
) {
2355 res
= a
> 0 ? INT32_MAX
: INT32_MIN
;
2361 static inline int64_t sadd64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
2363 int64_t res
= a
+ b
;
2364 if ((res
^ a
) & (res
^ b
) & INT64_MIN
) {
2365 res
= a
> 0 ? INT64_MAX
: INT64_MIN
;
2371 RVVCALL(OPIVV2_RM
, vsadd_vv_b
, OP_SSS_B
, H1
, H1
, H1
, sadd8
)
2372 RVVCALL(OPIVV2_RM
, vsadd_vv_h
, OP_SSS_H
, H2
, H2
, H2
, sadd16
)
2373 RVVCALL(OPIVV2_RM
, vsadd_vv_w
, OP_SSS_W
, H4
, H4
, H4
, sadd32
)
2374 RVVCALL(OPIVV2_RM
, vsadd_vv_d
, OP_SSS_D
, H8
, H8
, H8
, sadd64
)
2375 GEN_VEXT_VV_RM(vsadd_vv_b
, 1, 1, clearb
)
2376 GEN_VEXT_VV_RM(vsadd_vv_h
, 2, 2, clearh
)
2377 GEN_VEXT_VV_RM(vsadd_vv_w
, 4, 4, clearl
)
2378 GEN_VEXT_VV_RM(vsadd_vv_d
, 8, 8, clearq
)
2380 RVVCALL(OPIVX2_RM
, vsadd_vx_b
, OP_SSS_B
, H1
, H1
, sadd8
)
2381 RVVCALL(OPIVX2_RM
, vsadd_vx_h
, OP_SSS_H
, H2
, H2
, sadd16
)
2382 RVVCALL(OPIVX2_RM
, vsadd_vx_w
, OP_SSS_W
, H4
, H4
, sadd32
)
2383 RVVCALL(OPIVX2_RM
, vsadd_vx_d
, OP_SSS_D
, H8
, H8
, sadd64
)
2384 GEN_VEXT_VX_RM(vsadd_vx_b
, 1, 1, clearb
)
2385 GEN_VEXT_VX_RM(vsadd_vx_h
, 2, 2, clearh
)
2386 GEN_VEXT_VX_RM(vsadd_vx_w
, 4, 4, clearl
)
2387 GEN_VEXT_VX_RM(vsadd_vx_d
, 8, 8, clearq
)
2389 static inline uint8_t ssubu8(CPURISCVState
*env
, int vxrm
, uint8_t a
, uint8_t b
)
2391 uint8_t res
= a
- b
;
2399 static inline uint16_t ssubu16(CPURISCVState
*env
, int vxrm
, uint16_t a
,
2402 uint16_t res
= a
- b
;
2410 static inline uint32_t ssubu32(CPURISCVState
*env
, int vxrm
, uint32_t a
,
2413 uint32_t res
= a
- b
;
2421 static inline uint64_t ssubu64(CPURISCVState
*env
, int vxrm
, uint64_t a
,
2424 uint64_t res
= a
- b
;
2432 RVVCALL(OPIVV2_RM
, vssubu_vv_b
, OP_UUU_B
, H1
, H1
, H1
, ssubu8
)
2433 RVVCALL(OPIVV2_RM
, vssubu_vv_h
, OP_UUU_H
, H2
, H2
, H2
, ssubu16
)
2434 RVVCALL(OPIVV2_RM
, vssubu_vv_w
, OP_UUU_W
, H4
, H4
, H4
, ssubu32
)
2435 RVVCALL(OPIVV2_RM
, vssubu_vv_d
, OP_UUU_D
, H8
, H8
, H8
, ssubu64
)
2436 GEN_VEXT_VV_RM(vssubu_vv_b
, 1, 1, clearb
)
2437 GEN_VEXT_VV_RM(vssubu_vv_h
, 2, 2, clearh
)
2438 GEN_VEXT_VV_RM(vssubu_vv_w
, 4, 4, clearl
)
2439 GEN_VEXT_VV_RM(vssubu_vv_d
, 8, 8, clearq
)
2441 RVVCALL(OPIVX2_RM
, vssubu_vx_b
, OP_UUU_B
, H1
, H1
, ssubu8
)
2442 RVVCALL(OPIVX2_RM
, vssubu_vx_h
, OP_UUU_H
, H2
, H2
, ssubu16
)
2443 RVVCALL(OPIVX2_RM
, vssubu_vx_w
, OP_UUU_W
, H4
, H4
, ssubu32
)
2444 RVVCALL(OPIVX2_RM
, vssubu_vx_d
, OP_UUU_D
, H8
, H8
, ssubu64
)
2445 GEN_VEXT_VX_RM(vssubu_vx_b
, 1, 1, clearb
)
2446 GEN_VEXT_VX_RM(vssubu_vx_h
, 2, 2, clearh
)
2447 GEN_VEXT_VX_RM(vssubu_vx_w
, 4, 4, clearl
)
2448 GEN_VEXT_VX_RM(vssubu_vx_d
, 8, 8, clearq
)
2450 static inline int8_t ssub8(CPURISCVState
*env
, int vxrm
, int8_t a
, int8_t b
)
2453 if ((res
^ a
) & (a
^ b
) & INT8_MIN
) {
2454 res
= a
> 0 ? INT8_MAX
: INT8_MIN
;
2460 static inline int16_t ssub16(CPURISCVState
*env
, int vxrm
, int16_t a
, int16_t b
)
2462 int16_t res
= a
- b
;
2463 if ((res
^ a
) & (a
^ b
) & INT16_MIN
) {
2464 res
= a
> 0 ? INT16_MAX
: INT16_MIN
;
2470 static inline int32_t ssub32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
2472 int32_t res
= a
- b
;
2473 if ((res
^ a
) & (a
^ b
) & INT32_MIN
) {
2474 res
= a
> 0 ? INT32_MAX
: INT32_MIN
;
2480 static inline int64_t ssub64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
2482 int64_t res
= a
- b
;
2483 if ((res
^ a
) & (a
^ b
) & INT64_MIN
) {
2484 res
= a
> 0 ? INT64_MAX
: INT64_MIN
;
2490 RVVCALL(OPIVV2_RM
, vssub_vv_b
, OP_SSS_B
, H1
, H1
, H1
, ssub8
)
2491 RVVCALL(OPIVV2_RM
, vssub_vv_h
, OP_SSS_H
, H2
, H2
, H2
, ssub16
)
2492 RVVCALL(OPIVV2_RM
, vssub_vv_w
, OP_SSS_W
, H4
, H4
, H4
, ssub32
)
2493 RVVCALL(OPIVV2_RM
, vssub_vv_d
, OP_SSS_D
, H8
, H8
, H8
, ssub64
)
2494 GEN_VEXT_VV_RM(vssub_vv_b
, 1, 1, clearb
)
2495 GEN_VEXT_VV_RM(vssub_vv_h
, 2, 2, clearh
)
2496 GEN_VEXT_VV_RM(vssub_vv_w
, 4, 4, clearl
)
2497 GEN_VEXT_VV_RM(vssub_vv_d
, 8, 8, clearq
)
2499 RVVCALL(OPIVX2_RM
, vssub_vx_b
, OP_SSS_B
, H1
, H1
, ssub8
)
2500 RVVCALL(OPIVX2_RM
, vssub_vx_h
, OP_SSS_H
, H2
, H2
, ssub16
)
2501 RVVCALL(OPIVX2_RM
, vssub_vx_w
, OP_SSS_W
, H4
, H4
, ssub32
)
2502 RVVCALL(OPIVX2_RM
, vssub_vx_d
, OP_SSS_D
, H8
, H8
, ssub64
)
2503 GEN_VEXT_VX_RM(vssub_vx_b
, 1, 1, clearb
)
2504 GEN_VEXT_VX_RM(vssub_vx_h
, 2, 2, clearh
)
2505 GEN_VEXT_VX_RM(vssub_vx_w
, 4, 4, clearl
)
2506 GEN_VEXT_VX_RM(vssub_vx_d
, 8, 8, clearq
)
2508 /* Vector Single-Width Averaging Add and Subtract */
2509 static inline uint8_t get_round(int vxrm
, uint64_t v
, uint8_t shift
)
2511 uint8_t d
= extract64(v
, shift
, 1);
2515 if (shift
== 0 || shift
> 64) {
2519 d1
= extract64(v
, shift
- 1, 1);
2520 D1
= extract64(v
, 0, shift
);
2521 if (vxrm
== 0) { /* round-to-nearest-up (add +0.5 LSB) */
2523 } else if (vxrm
== 1) { /* round-to-nearest-even */
2525 D2
= extract64(v
, 0, shift
- 1);
2526 return d1
& ((D2
!= 0) | d
);
2530 } else if (vxrm
== 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
2531 return !d
& (D1
!= 0);
2533 return 0; /* round-down (truncate) */
2536 static inline int32_t aadd32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
2538 int64_t res
= (int64_t)a
+ b
;
2539 uint8_t round
= get_round(vxrm
, res
, 1);
2541 return (res
>> 1) + round
;
2544 static inline int64_t aadd64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
2546 int64_t res
= a
+ b
;
2547 uint8_t round
= get_round(vxrm
, res
, 1);
2548 int64_t over
= (res
^ a
) & (res
^ b
) & INT64_MIN
;
2550 /* With signed overflow, bit 64 is inverse of bit 63. */
2551 return ((res
>> 1) ^ over
) + round
;
2554 RVVCALL(OPIVV2_RM
, vaadd_vv_b
, OP_SSS_B
, H1
, H1
, H1
, aadd32
)
2555 RVVCALL(OPIVV2_RM
, vaadd_vv_h
, OP_SSS_H
, H2
, H2
, H2
, aadd32
)
2556 RVVCALL(OPIVV2_RM
, vaadd_vv_w
, OP_SSS_W
, H4
, H4
, H4
, aadd32
)
2557 RVVCALL(OPIVV2_RM
, vaadd_vv_d
, OP_SSS_D
, H8
, H8
, H8
, aadd64
)
2558 GEN_VEXT_VV_RM(vaadd_vv_b
, 1, 1, clearb
)
2559 GEN_VEXT_VV_RM(vaadd_vv_h
, 2, 2, clearh
)
2560 GEN_VEXT_VV_RM(vaadd_vv_w
, 4, 4, clearl
)
2561 GEN_VEXT_VV_RM(vaadd_vv_d
, 8, 8, clearq
)
2563 RVVCALL(OPIVX2_RM
, vaadd_vx_b
, OP_SSS_B
, H1
, H1
, aadd32
)
2564 RVVCALL(OPIVX2_RM
, vaadd_vx_h
, OP_SSS_H
, H2
, H2
, aadd32
)
2565 RVVCALL(OPIVX2_RM
, vaadd_vx_w
, OP_SSS_W
, H4
, H4
, aadd32
)
2566 RVVCALL(OPIVX2_RM
, vaadd_vx_d
, OP_SSS_D
, H8
, H8
, aadd64
)
2567 GEN_VEXT_VX_RM(vaadd_vx_b
, 1, 1, clearb
)
2568 GEN_VEXT_VX_RM(vaadd_vx_h
, 2, 2, clearh
)
2569 GEN_VEXT_VX_RM(vaadd_vx_w
, 4, 4, clearl
)
2570 GEN_VEXT_VX_RM(vaadd_vx_d
, 8, 8, clearq
)
2572 static inline int32_t asub32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
2574 int64_t res
= (int64_t)a
- b
;
2575 uint8_t round
= get_round(vxrm
, res
, 1);
2577 return (res
>> 1) + round
;
2580 static inline int64_t asub64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
2582 int64_t res
= (int64_t)a
- b
;
2583 uint8_t round
= get_round(vxrm
, res
, 1);
2584 int64_t over
= (res
^ a
) & (a
^ b
) & INT64_MIN
;
2586 /* With signed overflow, bit 64 is inverse of bit 63. */
2587 return ((res
>> 1) ^ over
) + round
;
2590 RVVCALL(OPIVV2_RM
, vasub_vv_b
, OP_SSS_B
, H1
, H1
, H1
, asub32
)
2591 RVVCALL(OPIVV2_RM
, vasub_vv_h
, OP_SSS_H
, H2
, H2
, H2
, asub32
)
2592 RVVCALL(OPIVV2_RM
, vasub_vv_w
, OP_SSS_W
, H4
, H4
, H4
, asub32
)
2593 RVVCALL(OPIVV2_RM
, vasub_vv_d
, OP_SSS_D
, H8
, H8
, H8
, asub64
)
2594 GEN_VEXT_VV_RM(vasub_vv_b
, 1, 1, clearb
)
2595 GEN_VEXT_VV_RM(vasub_vv_h
, 2, 2, clearh
)
2596 GEN_VEXT_VV_RM(vasub_vv_w
, 4, 4, clearl
)
2597 GEN_VEXT_VV_RM(vasub_vv_d
, 8, 8, clearq
)
2599 RVVCALL(OPIVX2_RM
, vasub_vx_b
, OP_SSS_B
, H1
, H1
, asub32
)
2600 RVVCALL(OPIVX2_RM
, vasub_vx_h
, OP_SSS_H
, H2
, H2
, asub32
)
2601 RVVCALL(OPIVX2_RM
, vasub_vx_w
, OP_SSS_W
, H4
, H4
, asub32
)
2602 RVVCALL(OPIVX2_RM
, vasub_vx_d
, OP_SSS_D
, H8
, H8
, asub64
)
2603 GEN_VEXT_VX_RM(vasub_vx_b
, 1, 1, clearb
)
2604 GEN_VEXT_VX_RM(vasub_vx_h
, 2, 2, clearh
)
2605 GEN_VEXT_VX_RM(vasub_vx_w
, 4, 4, clearl
)
2606 GEN_VEXT_VX_RM(vasub_vx_d
, 8, 8, clearq
)
2608 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
2609 static inline int8_t vsmul8(CPURISCVState
*env
, int vxrm
, int8_t a
, int8_t b
)
2614 res
= (int16_t)a
* (int16_t)b
;
2615 round
= get_round(vxrm
, res
, 7);
2616 res
= (res
>> 7) + round
;
2618 if (res
> INT8_MAX
) {
2621 } else if (res
< INT8_MIN
) {
2629 static int16_t vsmul16(CPURISCVState
*env
, int vxrm
, int16_t a
, int16_t b
)
2634 res
= (int32_t)a
* (int32_t)b
;
2635 round
= get_round(vxrm
, res
, 15);
2636 res
= (res
>> 15) + round
;
2638 if (res
> INT16_MAX
) {
2641 } else if (res
< INT16_MIN
) {
2649 static int32_t vsmul32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
2654 res
= (int64_t)a
* (int64_t)b
;
2655 round
= get_round(vxrm
, res
, 31);
2656 res
= (res
>> 31) + round
;
2658 if (res
> INT32_MAX
) {
2661 } else if (res
< INT32_MIN
) {
2669 static int64_t vsmul64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
2672 uint64_t hi_64
, lo_64
;
2675 if (a
== INT64_MIN
&& b
== INT64_MIN
) {
2680 muls64(&lo_64
, &hi_64
, a
, b
);
2681 round
= get_round(vxrm
, lo_64
, 63);
2683 * Cannot overflow, as there are always
2684 * 2 sign bits after multiply.
2686 res
= (hi_64
<< 1) | (lo_64
>> 63);
2688 if (res
== INT64_MAX
) {
2697 RVVCALL(OPIVV2_RM
, vsmul_vv_b
, OP_SSS_B
, H1
, H1
, H1
, vsmul8
)
2698 RVVCALL(OPIVV2_RM
, vsmul_vv_h
, OP_SSS_H
, H2
, H2
, H2
, vsmul16
)
2699 RVVCALL(OPIVV2_RM
, vsmul_vv_w
, OP_SSS_W
, H4
, H4
, H4
, vsmul32
)
2700 RVVCALL(OPIVV2_RM
, vsmul_vv_d
, OP_SSS_D
, H8
, H8
, H8
, vsmul64
)
2701 GEN_VEXT_VV_RM(vsmul_vv_b
, 1, 1, clearb
)
2702 GEN_VEXT_VV_RM(vsmul_vv_h
, 2, 2, clearh
)
2703 GEN_VEXT_VV_RM(vsmul_vv_w
, 4, 4, clearl
)
2704 GEN_VEXT_VV_RM(vsmul_vv_d
, 8, 8, clearq
)
2706 RVVCALL(OPIVX2_RM
, vsmul_vx_b
, OP_SSS_B
, H1
, H1
, vsmul8
)
2707 RVVCALL(OPIVX2_RM
, vsmul_vx_h
, OP_SSS_H
, H2
, H2
, vsmul16
)
2708 RVVCALL(OPIVX2_RM
, vsmul_vx_w
, OP_SSS_W
, H4
, H4
, vsmul32
)
2709 RVVCALL(OPIVX2_RM
, vsmul_vx_d
, OP_SSS_D
, H8
, H8
, vsmul64
)
2710 GEN_VEXT_VX_RM(vsmul_vx_b
, 1, 1, clearb
)
2711 GEN_VEXT_VX_RM(vsmul_vx_h
, 2, 2, clearh
)
2712 GEN_VEXT_VX_RM(vsmul_vx_w
, 4, 4, clearl
)
2713 GEN_VEXT_VX_RM(vsmul_vx_d
, 8, 8, clearq
)
2715 /* Vector Widening Saturating Scaled Multiply-Add */
2716 static inline uint16_t
2717 vwsmaccu8(CPURISCVState
*env
, int vxrm
, uint8_t a
, uint8_t b
,
2721 uint16_t res
= (uint16_t)a
* b
;
2723 round
= get_round(vxrm
, res
, 4);
2724 res
= (res
>> 4) + round
;
2725 return saddu16(env
, vxrm
, c
, res
);
2728 static inline uint32_t
2729 vwsmaccu16(CPURISCVState
*env
, int vxrm
, uint16_t a
, uint16_t b
,
2733 uint32_t res
= (uint32_t)a
* b
;
2735 round
= get_round(vxrm
, res
, 8);
2736 res
= (res
>> 8) + round
;
2737 return saddu32(env
, vxrm
, c
, res
);
2740 static inline uint64_t
2741 vwsmaccu32(CPURISCVState
*env
, int vxrm
, uint32_t a
, uint32_t b
,
2745 uint64_t res
= (uint64_t)a
* b
;
2747 round
= get_round(vxrm
, res
, 16);
2748 res
= (res
>> 16) + round
;
2749 return saddu64(env
, vxrm
, c
, res
);
2752 #define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
2753 static inline void \
2754 do_##NAME(void *vd, void *vs1, void *vs2, int i, \
2755 CPURISCVState *env, int vxrm) \
2757 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
2758 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2759 TD d = *((TD *)vd + HD(i)); \
2760 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
2763 RVVCALL(OPIVV3_RM
, vwsmaccu_vv_b
, WOP_UUU_B
, H2
, H1
, H1
, vwsmaccu8
)
2764 RVVCALL(OPIVV3_RM
, vwsmaccu_vv_h
, WOP_UUU_H
, H4
, H2
, H2
, vwsmaccu16
)
2765 RVVCALL(OPIVV3_RM
, vwsmaccu_vv_w
, WOP_UUU_W
, H8
, H4
, H4
, vwsmaccu32
)
2766 GEN_VEXT_VV_RM(vwsmaccu_vv_b
, 1, 2, clearh
)
2767 GEN_VEXT_VV_RM(vwsmaccu_vv_h
, 2, 4, clearl
)
2768 GEN_VEXT_VV_RM(vwsmaccu_vv_w
, 4, 8, clearq
)
2770 #define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
2771 static inline void \
2772 do_##NAME(void *vd, target_long s1, void *vs2, int i, \
2773 CPURISCVState *env, int vxrm) \
2775 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2776 TD d = *((TD *)vd + HD(i)); \
2777 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
2780 RVVCALL(OPIVX3_RM
, vwsmaccu_vx_b
, WOP_UUU_B
, H2
, H1
, vwsmaccu8
)
2781 RVVCALL(OPIVX3_RM
, vwsmaccu_vx_h
, WOP_UUU_H
, H4
, H2
, vwsmaccu16
)
2782 RVVCALL(OPIVX3_RM
, vwsmaccu_vx_w
, WOP_UUU_W
, H8
, H4
, vwsmaccu32
)
2783 GEN_VEXT_VX_RM(vwsmaccu_vx_b
, 1, 2, clearh
)
2784 GEN_VEXT_VX_RM(vwsmaccu_vx_h
, 2, 4, clearl
)
2785 GEN_VEXT_VX_RM(vwsmaccu_vx_w
, 4, 8, clearq
)
2787 static inline int16_t
2788 vwsmacc8(CPURISCVState
*env
, int vxrm
, int8_t a
, int8_t b
, int16_t c
)
2791 int16_t res
= (int16_t)a
* b
;
2793 round
= get_round(vxrm
, res
, 4);
2794 res
= (res
>> 4) + round
;
2795 return sadd16(env
, vxrm
, c
, res
);
2798 static inline int32_t
2799 vwsmacc16(CPURISCVState
*env
, int vxrm
, int16_t a
, int16_t b
, int32_t c
)
2802 int32_t res
= (int32_t)a
* b
;
2804 round
= get_round(vxrm
, res
, 8);
2805 res
= (res
>> 8) + round
;
2806 return sadd32(env
, vxrm
, c
, res
);
2810 static inline int64_t
2811 vwsmacc32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
, int64_t c
)
2814 int64_t res
= (int64_t)a
* b
;
2816 round
= get_round(vxrm
, res
, 16);
2817 res
= (res
>> 16) + round
;
2818 return sadd64(env
, vxrm
, c
, res
);
2821 RVVCALL(OPIVV3_RM
, vwsmacc_vv_b
, WOP_SSS_B
, H2
, H1
, H1
, vwsmacc8
)
2822 RVVCALL(OPIVV3_RM
, vwsmacc_vv_h
, WOP_SSS_H
, H4
, H2
, H2
, vwsmacc16
)
2823 RVVCALL(OPIVV3_RM
, vwsmacc_vv_w
, WOP_SSS_W
, H8
, H4
, H4
, vwsmacc32
)
2824 GEN_VEXT_VV_RM(vwsmacc_vv_b
, 1, 2, clearh
)
2825 GEN_VEXT_VV_RM(vwsmacc_vv_h
, 2, 4, clearl
)
2826 GEN_VEXT_VV_RM(vwsmacc_vv_w
, 4, 8, clearq
)
2827 RVVCALL(OPIVX3_RM
, vwsmacc_vx_b
, WOP_SSS_B
, H2
, H1
, vwsmacc8
)
2828 RVVCALL(OPIVX3_RM
, vwsmacc_vx_h
, WOP_SSS_H
, H4
, H2
, vwsmacc16
)
2829 RVVCALL(OPIVX3_RM
, vwsmacc_vx_w
, WOP_SSS_W
, H8
, H4
, vwsmacc32
)
2830 GEN_VEXT_VX_RM(vwsmacc_vx_b
, 1, 2, clearh
)
2831 GEN_VEXT_VX_RM(vwsmacc_vx_h
, 2, 4, clearl
)
2832 GEN_VEXT_VX_RM(vwsmacc_vx_w
, 4, 8, clearq
)
2834 static inline int16_t
2835 vwsmaccsu8(CPURISCVState
*env
, int vxrm
, uint8_t a
, int8_t b
, int16_t c
)
2838 int16_t res
= a
* (int16_t)b
;
2840 round
= get_round(vxrm
, res
, 4);
2841 res
= (res
>> 4) + round
;
2842 return ssub16(env
, vxrm
, c
, res
);
2845 static inline int32_t
2846 vwsmaccsu16(CPURISCVState
*env
, int vxrm
, uint16_t a
, int16_t b
, uint32_t c
)
2849 int32_t res
= a
* (int32_t)b
;
2851 round
= get_round(vxrm
, res
, 8);
2852 res
= (res
>> 8) + round
;
2853 return ssub32(env
, vxrm
, c
, res
);
2856 static inline int64_t
2857 vwsmaccsu32(CPURISCVState
*env
, int vxrm
, uint32_t a
, int32_t b
, int64_t c
)
2860 int64_t res
= a
* (int64_t)b
;
2862 round
= get_round(vxrm
, res
, 16);
2863 res
= (res
>> 16) + round
;
2864 return ssub64(env
, vxrm
, c
, res
);
2867 RVVCALL(OPIVV3_RM
, vwsmaccsu_vv_b
, WOP_SSU_B
, H2
, H1
, H1
, vwsmaccsu8
)
2868 RVVCALL(OPIVV3_RM
, vwsmaccsu_vv_h
, WOP_SSU_H
, H4
, H2
, H2
, vwsmaccsu16
)
2869 RVVCALL(OPIVV3_RM
, vwsmaccsu_vv_w
, WOP_SSU_W
, H8
, H4
, H4
, vwsmaccsu32
)
2870 GEN_VEXT_VV_RM(vwsmaccsu_vv_b
, 1, 2, clearh
)
2871 GEN_VEXT_VV_RM(vwsmaccsu_vv_h
, 2, 4, clearl
)
2872 GEN_VEXT_VV_RM(vwsmaccsu_vv_w
, 4, 8, clearq
)
2873 RVVCALL(OPIVX3_RM
, vwsmaccsu_vx_b
, WOP_SSU_B
, H2
, H1
, vwsmaccsu8
)
2874 RVVCALL(OPIVX3_RM
, vwsmaccsu_vx_h
, WOP_SSU_H
, H4
, H2
, vwsmaccsu16
)
2875 RVVCALL(OPIVX3_RM
, vwsmaccsu_vx_w
, WOP_SSU_W
, H8
, H4
, vwsmaccsu32
)
2876 GEN_VEXT_VX_RM(vwsmaccsu_vx_b
, 1, 2, clearh
)
2877 GEN_VEXT_VX_RM(vwsmaccsu_vx_h
, 2, 4, clearl
)
2878 GEN_VEXT_VX_RM(vwsmaccsu_vx_w
, 4, 8, clearq
)
2880 static inline int16_t
2881 vwsmaccus8(CPURISCVState
*env
, int vxrm
, int8_t a
, uint8_t b
, int16_t c
)
2884 int16_t res
= (int16_t)a
* b
;
2886 round
= get_round(vxrm
, res
, 4);
2887 res
= (res
>> 4) + round
;
2888 return ssub16(env
, vxrm
, c
, res
);
2891 static inline int32_t
2892 vwsmaccus16(CPURISCVState
*env
, int vxrm
, int16_t a
, uint16_t b
, int32_t c
)
2895 int32_t res
= (int32_t)a
* b
;
2897 round
= get_round(vxrm
, res
, 8);
2898 res
= (res
>> 8) + round
;
2899 return ssub32(env
, vxrm
, c
, res
);
2902 static inline int64_t
2903 vwsmaccus32(CPURISCVState
*env
, int vxrm
, int32_t a
, uint32_t b
, int64_t c
)
2906 int64_t res
= (int64_t)a
* b
;
2908 round
= get_round(vxrm
, res
, 16);
2909 res
= (res
>> 16) + round
;
2910 return ssub64(env
, vxrm
, c
, res
);
2913 RVVCALL(OPIVX3_RM
, vwsmaccus_vx_b
, WOP_SUS_B
, H2
, H1
, vwsmaccus8
)
2914 RVVCALL(OPIVX3_RM
, vwsmaccus_vx_h
, WOP_SUS_H
, H4
, H2
, vwsmaccus16
)
2915 RVVCALL(OPIVX3_RM
, vwsmaccus_vx_w
, WOP_SUS_W
, H8
, H4
, vwsmaccus32
)
2916 GEN_VEXT_VX_RM(vwsmaccus_vx_b
, 1, 2, clearh
)
2917 GEN_VEXT_VX_RM(vwsmaccus_vx_h
, 2, 4, clearl
)
2918 GEN_VEXT_VX_RM(vwsmaccus_vx_w
, 4, 8, clearq
)
2920 /* Vector Single-Width Scaling Shift Instructions */
2921 static inline uint8_t
2922 vssrl8(CPURISCVState
*env
, int vxrm
, uint8_t a
, uint8_t b
)
2924 uint8_t round
, shift
= b
& 0x7;
2927 round
= get_round(vxrm
, a
, shift
);
2928 res
= (a
>> shift
) + round
;
2931 static inline uint16_t
2932 vssrl16(CPURISCVState
*env
, int vxrm
, uint16_t a
, uint16_t b
)
2934 uint8_t round
, shift
= b
& 0xf;
2937 round
= get_round(vxrm
, a
, shift
);
2938 res
= (a
>> shift
) + round
;
2941 static inline uint32_t
2942 vssrl32(CPURISCVState
*env
, int vxrm
, uint32_t a
, uint32_t b
)
2944 uint8_t round
, shift
= b
& 0x1f;
2947 round
= get_round(vxrm
, a
, shift
);
2948 res
= (a
>> shift
) + round
;
2951 static inline uint64_t
2952 vssrl64(CPURISCVState
*env
, int vxrm
, uint64_t a
, uint64_t b
)
2954 uint8_t round
, shift
= b
& 0x3f;
2957 round
= get_round(vxrm
, a
, shift
);
2958 res
= (a
>> shift
) + round
;
2961 RVVCALL(OPIVV2_RM
, vssrl_vv_b
, OP_UUU_B
, H1
, H1
, H1
, vssrl8
)
2962 RVVCALL(OPIVV2_RM
, vssrl_vv_h
, OP_UUU_H
, H2
, H2
, H2
, vssrl16
)
2963 RVVCALL(OPIVV2_RM
, vssrl_vv_w
, OP_UUU_W
, H4
, H4
, H4
, vssrl32
)
2964 RVVCALL(OPIVV2_RM
, vssrl_vv_d
, OP_UUU_D
, H8
, H8
, H8
, vssrl64
)
2965 GEN_VEXT_VV_RM(vssrl_vv_b
, 1, 1, clearb
)
2966 GEN_VEXT_VV_RM(vssrl_vv_h
, 2, 2, clearh
)
2967 GEN_VEXT_VV_RM(vssrl_vv_w
, 4, 4, clearl
)
2968 GEN_VEXT_VV_RM(vssrl_vv_d
, 8, 8, clearq
)
2970 RVVCALL(OPIVX2_RM
, vssrl_vx_b
, OP_UUU_B
, H1
, H1
, vssrl8
)
2971 RVVCALL(OPIVX2_RM
, vssrl_vx_h
, OP_UUU_H
, H2
, H2
, vssrl16
)
2972 RVVCALL(OPIVX2_RM
, vssrl_vx_w
, OP_UUU_W
, H4
, H4
, vssrl32
)
2973 RVVCALL(OPIVX2_RM
, vssrl_vx_d
, OP_UUU_D
, H8
, H8
, vssrl64
)
2974 GEN_VEXT_VX_RM(vssrl_vx_b
, 1, 1, clearb
)
2975 GEN_VEXT_VX_RM(vssrl_vx_h
, 2, 2, clearh
)
2976 GEN_VEXT_VX_RM(vssrl_vx_w
, 4, 4, clearl
)
2977 GEN_VEXT_VX_RM(vssrl_vx_d
, 8, 8, clearq
)
2979 static inline int8_t
2980 vssra8(CPURISCVState
*env
, int vxrm
, int8_t a
, int8_t b
)
2982 uint8_t round
, shift
= b
& 0x7;
2985 round
= get_round(vxrm
, a
, shift
);
2986 res
= (a
>> shift
) + round
;
2989 static inline int16_t
2990 vssra16(CPURISCVState
*env
, int vxrm
, int16_t a
, int16_t b
)
2992 uint8_t round
, shift
= b
& 0xf;
2995 round
= get_round(vxrm
, a
, shift
);
2996 res
= (a
>> shift
) + round
;
2999 static inline int32_t
3000 vssra32(CPURISCVState
*env
, int vxrm
, int32_t a
, int32_t b
)
3002 uint8_t round
, shift
= b
& 0x1f;
3005 round
= get_round(vxrm
, a
, shift
);
3006 res
= (a
>> shift
) + round
;
3009 static inline int64_t
3010 vssra64(CPURISCVState
*env
, int vxrm
, int64_t a
, int64_t b
)
3012 uint8_t round
, shift
= b
& 0x3f;
3015 round
= get_round(vxrm
, a
, shift
);
3016 res
= (a
>> shift
) + round
;
3020 RVVCALL(OPIVV2_RM
, vssra_vv_b
, OP_SSS_B
, H1
, H1
, H1
, vssra8
)
3021 RVVCALL(OPIVV2_RM
, vssra_vv_h
, OP_SSS_H
, H2
, H2
, H2
, vssra16
)
3022 RVVCALL(OPIVV2_RM
, vssra_vv_w
, OP_SSS_W
, H4
, H4
, H4
, vssra32
)
3023 RVVCALL(OPIVV2_RM
, vssra_vv_d
, OP_SSS_D
, H8
, H8
, H8
, vssra64
)
3024 GEN_VEXT_VV_RM(vssra_vv_b
, 1, 1, clearb
)
3025 GEN_VEXT_VV_RM(vssra_vv_h
, 2, 2, clearh
)
3026 GEN_VEXT_VV_RM(vssra_vv_w
, 4, 4, clearl
)
3027 GEN_VEXT_VV_RM(vssra_vv_d
, 8, 8, clearq
)
3029 RVVCALL(OPIVX2_RM
, vssra_vx_b
, OP_SSS_B
, H1
, H1
, vssra8
)
3030 RVVCALL(OPIVX2_RM
, vssra_vx_h
, OP_SSS_H
, H2
, H2
, vssra16
)
3031 RVVCALL(OPIVX2_RM
, vssra_vx_w
, OP_SSS_W
, H4
, H4
, vssra32
)
3032 RVVCALL(OPIVX2_RM
, vssra_vx_d
, OP_SSS_D
, H8
, H8
, vssra64
)
3033 GEN_VEXT_VX_RM(vssra_vx_b
, 1, 1, clearb
)
3034 GEN_VEXT_VX_RM(vssra_vx_h
, 2, 2, clearh
)
3035 GEN_VEXT_VX_RM(vssra_vx_w
, 4, 4, clearl
)
3036 GEN_VEXT_VX_RM(vssra_vx_d
, 8, 8, clearq
)
3038 /* Vector Narrowing Fixed-Point Clip Instructions */
3039 static inline int8_t
3040 vnclip8(CPURISCVState
*env
, int vxrm
, int16_t a
, int8_t b
)
3042 uint8_t round
, shift
= b
& 0xf;
3045 round
= get_round(vxrm
, a
, shift
);
3046 res
= (a
>> shift
) + round
;
3047 if (res
> INT8_MAX
) {
3050 } else if (res
< INT8_MIN
) {
3058 static inline int16_t
3059 vnclip16(CPURISCVState
*env
, int vxrm
, int32_t a
, int16_t b
)
3061 uint8_t round
, shift
= b
& 0x1f;
3064 round
= get_round(vxrm
, a
, shift
);
3065 res
= (a
>> shift
) + round
;
3066 if (res
> INT16_MAX
) {
3069 } else if (res
< INT16_MIN
) {
3077 static inline int32_t
3078 vnclip32(CPURISCVState
*env
, int vxrm
, int64_t a
, int32_t b
)
3080 uint8_t round
, shift
= b
& 0x3f;
3083 round
= get_round(vxrm
, a
, shift
);
3084 res
= (a
>> shift
) + round
;
3085 if (res
> INT32_MAX
) {
3088 } else if (res
< INT32_MIN
) {
3096 RVVCALL(OPIVV2_RM
, vnclip_vv_b
, NOP_SSS_B
, H1
, H2
, H1
, vnclip8
)
3097 RVVCALL(OPIVV2_RM
, vnclip_vv_h
, NOP_SSS_H
, H2
, H4
, H2
, vnclip16
)
3098 RVVCALL(OPIVV2_RM
, vnclip_vv_w
, NOP_SSS_W
, H4
, H8
, H4
, vnclip32
)
3099 GEN_VEXT_VV_RM(vnclip_vv_b
, 1, 1, clearb
)
3100 GEN_VEXT_VV_RM(vnclip_vv_h
, 2, 2, clearh
)
3101 GEN_VEXT_VV_RM(vnclip_vv_w
, 4, 4, clearl
)
3103 RVVCALL(OPIVX2_RM
, vnclip_vx_b
, NOP_SSS_B
, H1
, H2
, vnclip8
)
3104 RVVCALL(OPIVX2_RM
, vnclip_vx_h
, NOP_SSS_H
, H2
, H4
, vnclip16
)
3105 RVVCALL(OPIVX2_RM
, vnclip_vx_w
, NOP_SSS_W
, H4
, H8
, vnclip32
)
3106 GEN_VEXT_VX_RM(vnclip_vx_b
, 1, 1, clearb
)
3107 GEN_VEXT_VX_RM(vnclip_vx_h
, 2, 2, clearh
)
3108 GEN_VEXT_VX_RM(vnclip_vx_w
, 4, 4, clearl
)
3110 static inline uint8_t
3111 vnclipu8(CPURISCVState
*env
, int vxrm
, uint16_t a
, uint8_t b
)
3113 uint8_t round
, shift
= b
& 0xf;
3116 round
= get_round(vxrm
, a
, shift
);
3117 res
= (a
>> shift
) + round
;
3118 if (res
> UINT8_MAX
) {
3126 static inline uint16_t
3127 vnclipu16(CPURISCVState
*env
, int vxrm
, uint32_t a
, uint16_t b
)
3129 uint8_t round
, shift
= b
& 0x1f;
3132 round
= get_round(vxrm
, a
, shift
);
3133 res
= (a
>> shift
) + round
;
3134 if (res
> UINT16_MAX
) {
3142 static inline uint32_t
3143 vnclipu32(CPURISCVState
*env
, int vxrm
, uint64_t a
, uint32_t b
)
3145 uint8_t round
, shift
= b
& 0x3f;
3148 round
= get_round(vxrm
, a
, shift
);
3149 res
= (a
>> shift
) + round
;
3150 if (res
> UINT32_MAX
) {
3158 RVVCALL(OPIVV2_RM
, vnclipu_vv_b
, NOP_UUU_B
, H1
, H2
, H1
, vnclipu8
)
3159 RVVCALL(OPIVV2_RM
, vnclipu_vv_h
, NOP_UUU_H
, H2
, H4
, H2
, vnclipu16
)
3160 RVVCALL(OPIVV2_RM
, vnclipu_vv_w
, NOP_UUU_W
, H4
, H8
, H4
, vnclipu32
)
3161 GEN_VEXT_VV_RM(vnclipu_vv_b
, 1, 1, clearb
)
3162 GEN_VEXT_VV_RM(vnclipu_vv_h
, 2, 2, clearh
)
3163 GEN_VEXT_VV_RM(vnclipu_vv_w
, 4, 4, clearl
)
3165 RVVCALL(OPIVX2_RM
, vnclipu_vx_b
, NOP_UUU_B
, H1
, H2
, vnclipu8
)
3166 RVVCALL(OPIVX2_RM
, vnclipu_vx_h
, NOP_UUU_H
, H2
, H4
, vnclipu16
)
3167 RVVCALL(OPIVX2_RM
, vnclipu_vx_w
, NOP_UUU_W
, H4
, H8
, vnclipu32
)
3168 GEN_VEXT_VX_RM(vnclipu_vx_b
, 1, 1, clearb
)
3169 GEN_VEXT_VX_RM(vnclipu_vx_h
, 2, 2, clearh
)
3170 GEN_VEXT_VX_RM(vnclipu_vx_w
, 4, 4, clearl
)
3173 *** Vector Float Point Arithmetic Instructions
3175 /* Vector Single-Width Floating-Point Add/Subtract Instructions */
3176 #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
3177 static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
3178 CPURISCVState *env) \
3180 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
3181 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
3182 *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \
3185 #define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
3186 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
3187 void *vs2, CPURISCVState *env, \
3190 uint32_t vlmax = vext_maxsz(desc) / ESZ; \
3191 uint32_t mlen = vext_mlen(desc); \
3192 uint32_t vm = vext_vm(desc); \
3193 uint32_t vl = env->vl; \
3196 for (i = 0; i < vl; i++) { \
3197 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
3200 do_##NAME(vd, vs1, vs2, i, env); \
3202 CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
3205 RVVCALL(OPFVV2
, vfadd_vv_h
, OP_UUU_H
, H2
, H2
, H2
, float16_add
)
3206 RVVCALL(OPFVV2
, vfadd_vv_w
, OP_UUU_W
, H4
, H4
, H4
, float32_add
)
3207 RVVCALL(OPFVV2
, vfadd_vv_d
, OP_UUU_D
, H8
, H8
, H8
, float64_add
)
3208 GEN_VEXT_VV_ENV(vfadd_vv_h
, 2, 2, clearh
)
3209 GEN_VEXT_VV_ENV(vfadd_vv_w
, 4, 4, clearl
)
3210 GEN_VEXT_VV_ENV(vfadd_vv_d
, 8, 8, clearq
)
3212 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
3213 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
3214 CPURISCVState *env) \
3216 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
3217 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
3220 #define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN) \
3221 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
3222 void *vs2, CPURISCVState *env, \
3225 uint32_t vlmax = vext_maxsz(desc) / ESZ; \
3226 uint32_t mlen = vext_mlen(desc); \
3227 uint32_t vm = vext_vm(desc); \
3228 uint32_t vl = env->vl; \
3231 for (i = 0; i < vl; i++) { \
3232 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
3235 do_##NAME(vd, s1, vs2, i, env); \
3237 CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
3240 RVVCALL(OPFVF2
, vfadd_vf_h
, OP_UUU_H
, H2
, H2
, float16_add
)
3241 RVVCALL(OPFVF2
, vfadd_vf_w
, OP_UUU_W
, H4
, H4
, float32_add
)
3242 RVVCALL(OPFVF2
, vfadd_vf_d
, OP_UUU_D
, H8
, H8
, float64_add
)
3243 GEN_VEXT_VF(vfadd_vf_h
, 2, 2, clearh
)
3244 GEN_VEXT_VF(vfadd_vf_w
, 4, 4, clearl
)
3245 GEN_VEXT_VF(vfadd_vf_d
, 8, 8, clearq
)
3247 RVVCALL(OPFVV2
, vfsub_vv_h
, OP_UUU_H
, H2
, H2
, H2
, float16_sub
)
3248 RVVCALL(OPFVV2
, vfsub_vv_w
, OP_UUU_W
, H4
, H4
, H4
, float32_sub
)
3249 RVVCALL(OPFVV2
, vfsub_vv_d
, OP_UUU_D
, H8
, H8
, H8
, float64_sub
)
3250 GEN_VEXT_VV_ENV(vfsub_vv_h
, 2, 2, clearh
)
3251 GEN_VEXT_VV_ENV(vfsub_vv_w
, 4, 4, clearl
)
3252 GEN_VEXT_VV_ENV(vfsub_vv_d
, 8, 8, clearq
)
3253 RVVCALL(OPFVF2
, vfsub_vf_h
, OP_UUU_H
, H2
, H2
, float16_sub
)
3254 RVVCALL(OPFVF2
, vfsub_vf_w
, OP_UUU_W
, H4
, H4
, float32_sub
)
3255 RVVCALL(OPFVF2
, vfsub_vf_d
, OP_UUU_D
, H8
, H8
, float64_sub
)
3256 GEN_VEXT_VF(vfsub_vf_h
, 2, 2, clearh
)
3257 GEN_VEXT_VF(vfsub_vf_w
, 4, 4, clearl
)
3258 GEN_VEXT_VF(vfsub_vf_d
, 8, 8, clearq
)
3260 static uint16_t float16_rsub(uint16_t a
, uint16_t b
, float_status
*s
)
3262 return float16_sub(b
, a
, s
);
3265 static uint32_t float32_rsub(uint32_t a
, uint32_t b
, float_status
*s
)
3267 return float32_sub(b
, a
, s
);
3270 static uint64_t float64_rsub(uint64_t a
, uint64_t b
, float_status
*s
)
3272 return float64_sub(b
, a
, s
);
3275 RVVCALL(OPFVF2
, vfrsub_vf_h
, OP_UUU_H
, H2
, H2
, float16_rsub
)
3276 RVVCALL(OPFVF2
, vfrsub_vf_w
, OP_UUU_W
, H4
, H4
, float32_rsub
)
3277 RVVCALL(OPFVF2
, vfrsub_vf_d
, OP_UUU_D
, H8
, H8
, float64_rsub
)
3278 GEN_VEXT_VF(vfrsub_vf_h
, 2, 2, clearh
)
3279 GEN_VEXT_VF(vfrsub_vf_w
, 4, 4, clearl
)
3280 GEN_VEXT_VF(vfrsub_vf_d
, 8, 8, clearq
)