2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/msi.h"
30 #include "hw/pci/msix.h"
31 #include "hw/pci/pci_host.h"
32 #include "hw/ppc/spapr.h"
33 #include "hw/pci-host/spapr.h"
34 #include "exec/address-spaces.h"
37 #include "qemu/error-report.h"
38 #include "qapi/qmp/qerror.h"
40 #include "hw/pci/pci_bridge.h"
41 #include "hw/pci/pci_bus.h"
42 #include "hw/ppc/spapr_drc.h"
43 #include "sysemu/device_tree.h"
45 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
46 #define RTAS_QUERY_FN 0
47 #define RTAS_CHANGE_FN 1
48 #define RTAS_RESET_FN 2
49 #define RTAS_CHANGE_MSI_FN 3
50 #define RTAS_CHANGE_MSIX_FN 4
52 /* Interrupt types to return on RTAS_CHANGE_* */
53 #define RTAS_TYPE_MSI 1
54 #define RTAS_TYPE_MSIX 2
56 #define FDT_NAME_MAX 128
66 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
)
70 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
71 if (sphb
->buid
!= buid
) {
80 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
83 sPAPRPHBState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
84 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
85 int bus_num
= (config_addr
>> 16) & 0xFF;
86 int devfn
= (config_addr
>> 8) & 0xFF;
92 return pci_find_device(phb
->bus
, bus_num
, devfn
);
95 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
97 /* This handles the encoding of extended config space addresses */
98 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
101 static void finish_read_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
102 uint32_t addr
, uint32_t size
,
108 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
109 /* access must be 1, 2 or 4 bytes */
110 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
114 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
115 addr
= rtas_pci_cfgaddr(addr
);
117 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
118 /* Access must be to a valid device, within bounds and
119 * naturally aligned */
120 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
124 val
= pci_host_config_read_common(pci_dev
, addr
,
125 pci_config_size(pci_dev
), size
);
127 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
128 rtas_st(rets
, 1, val
);
131 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
132 uint32_t token
, uint32_t nargs
,
134 uint32_t nret
, target_ulong rets
)
139 if ((nargs
!= 4) || (nret
!= 2)) {
140 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
144 buid
= rtas_ldq(args
, 1);
145 size
= rtas_ld(args
, 3);
146 addr
= rtas_ld(args
, 0);
148 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
151 static void rtas_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
152 uint32_t token
, uint32_t nargs
,
154 uint32_t nret
, target_ulong rets
)
158 if ((nargs
!= 2) || (nret
!= 2)) {
159 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
163 size
= rtas_ld(args
, 1);
164 addr
= rtas_ld(args
, 0);
166 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
169 static void finish_write_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
170 uint32_t addr
, uint32_t size
,
171 uint32_t val
, target_ulong rets
)
175 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
176 /* access must be 1, 2 or 4 bytes */
177 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
181 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
182 addr
= rtas_pci_cfgaddr(addr
);
184 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
185 /* Access must be to a valid device, within bounds and
186 * naturally aligned */
187 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
191 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
194 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
197 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
198 uint32_t token
, uint32_t nargs
,
200 uint32_t nret
, target_ulong rets
)
203 uint32_t val
, size
, addr
;
205 if ((nargs
!= 5) || (nret
!= 1)) {
206 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
210 buid
= rtas_ldq(args
, 1);
211 val
= rtas_ld(args
, 4);
212 size
= rtas_ld(args
, 3);
213 addr
= rtas_ld(args
, 0);
215 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
218 static void rtas_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
219 uint32_t token
, uint32_t nargs
,
221 uint32_t nret
, target_ulong rets
)
223 uint32_t val
, size
, addr
;
225 if ((nargs
!= 3) || (nret
!= 1)) {
226 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
231 val
= rtas_ld(args
, 2);
232 size
= rtas_ld(args
, 1);
233 addr
= rtas_ld(args
, 0);
235 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
239 * Set MSI/MSIX message data.
240 * This is required for msi_notify()/msix_notify() which
241 * will write at the addresses via spapr_msi_write().
243 * If hwaddr == 0, all entries will have .data == first_irq i.e.
244 * table will be reset.
246 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
247 unsigned first_irq
, unsigned req_num
)
250 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
253 msi_set_message(pdev
, msg
);
254 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
258 for (i
= 0; i
< req_num
; ++i
) {
259 msix_set_message(pdev
, i
, msg
);
260 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
267 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
268 uint32_t token
, uint32_t nargs
,
269 target_ulong args
, uint32_t nret
,
272 uint32_t config_addr
= rtas_ld(args
, 0);
273 uint64_t buid
= rtas_ldq(args
, 1);
274 unsigned int func
= rtas_ld(args
, 3);
275 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
276 unsigned int seq_num
= rtas_ld(args
, 5);
277 unsigned int ret_intr_type
;
278 unsigned int irq
, max_irqs
= 0;
279 sPAPRPHBState
*phb
= NULL
;
280 PCIDevice
*pdev
= NULL
;
282 int *config_addr_key
;
285 case RTAS_CHANGE_MSI_FN
:
287 ret_intr_type
= RTAS_TYPE_MSI
;
289 case RTAS_CHANGE_MSIX_FN
:
290 ret_intr_type
= RTAS_TYPE_MSIX
;
293 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
294 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
298 /* Fins sPAPRPHBState */
299 phb
= spapr_pci_find_phb(spapr
, buid
);
301 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
304 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
308 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
313 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
314 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
318 xics_free(spapr
->icp
, msi
->first_irq
, msi
->num
);
319 if (msi_present(pdev
)) {
320 spapr_msi_setmsg(pdev
, 0, false, 0, 0);
322 if (msix_present(pdev
)) {
323 spapr_msi_setmsg(pdev
, 0, true, 0, 0);
325 g_hash_table_remove(phb
->msi
, &config_addr
);
327 trace_spapr_pci_msi("Released MSIs", config_addr
);
328 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
335 /* Check if the device supports as many IRQs as requested */
336 if (ret_intr_type
== RTAS_TYPE_MSI
) {
337 max_irqs
= msi_nr_vectors_allocated(pdev
);
338 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
339 max_irqs
= pdev
->msix_entries_nr
;
342 error_report("Requested interrupt type %d is not enabled for device %x",
343 ret_intr_type
, config_addr
);
344 rtas_st(rets
, 0, -1); /* Hardware error */
347 /* Correct the number if the guest asked for too many */
348 if (req_num
> max_irqs
) {
349 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
351 irq
= 0; /* to avoid misleading trace */
356 irq
= xics_alloc_block(spapr
->icp
, 0, req_num
, false,
357 ret_intr_type
== RTAS_TYPE_MSI
);
359 error_report("Cannot allocate MSIs for device %x", config_addr
);
360 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
364 /* Release previous MSIs */
366 xics_free(spapr
->icp
, msi
->first_irq
, msi
->num
);
367 g_hash_table_remove(phb
->msi
, &config_addr
);
370 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
371 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
374 /* Add MSI device to cache */
375 msi
= g_new(spapr_pci_msi
, 1);
376 msi
->first_irq
= irq
;
378 config_addr_key
= g_new(int, 1);
379 *config_addr_key
= config_addr
;
380 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
383 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
384 rtas_st(rets
, 1, req_num
);
385 rtas_st(rets
, 2, ++seq_num
);
387 rtas_st(rets
, 3, ret_intr_type
);
390 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
393 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
394 sPAPRMachineState
*spapr
,
401 uint32_t config_addr
= rtas_ld(args
, 0);
402 uint64_t buid
= rtas_ldq(args
, 1);
403 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
404 sPAPRPHBState
*phb
= NULL
;
405 PCIDevice
*pdev
= NULL
;
408 /* Find sPAPRPHBState */
409 phb
= spapr_pci_find_phb(spapr
, buid
);
411 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
414 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
418 /* Find device descriptor and start IRQ */
419 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
420 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
421 trace_spapr_pci_msi("Failed to return vector", config_addr
);
422 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
425 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
426 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
429 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
430 rtas_st(rets
, 1, intr_src_num
);
431 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
434 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
435 sPAPRMachineState
*spapr
,
436 uint32_t token
, uint32_t nargs
,
437 target_ulong args
, uint32_t nret
,
442 uint32_t addr
, option
;
446 if ((nargs
!= 4) || (nret
!= 1)) {
447 goto param_error_exit
;
450 buid
= rtas_ldq(args
, 1);
451 addr
= rtas_ld(args
, 0);
452 option
= rtas_ld(args
, 3);
454 sphb
= spapr_pci_find_phb(spapr
, buid
);
456 goto param_error_exit
;
459 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
460 if (!spc
->eeh_set_option
) {
461 goto param_error_exit
;
464 ret
= spc
->eeh_set_option(sphb
, addr
, option
);
465 rtas_st(rets
, 0, ret
);
469 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
472 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
473 sPAPRMachineState
*spapr
,
474 uint32_t token
, uint32_t nargs
,
475 target_ulong args
, uint32_t nret
,
481 uint32_t addr
, option
;
484 if ((nargs
!= 4) || (nret
!= 2)) {
485 goto param_error_exit
;
488 buid
= rtas_ldq(args
, 1);
489 sphb
= spapr_pci_find_phb(spapr
, buid
);
491 goto param_error_exit
;
494 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
495 if (!spc
->eeh_set_option
) {
496 goto param_error_exit
;
500 * We always have PE address of form "00BB0001". "BB"
501 * represents the bus number of PE's primary bus.
503 option
= rtas_ld(args
, 3);
505 case RTAS_GET_PE_ADDR
:
506 addr
= rtas_ld(args
, 0);
507 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
509 goto param_error_exit
;
512 rtas_st(rets
, 1, (pci_bus_num(pdev
->bus
) << 16) + 1);
514 case RTAS_GET_PE_MODE
:
515 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
518 goto param_error_exit
;
521 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
525 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
528 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
529 sPAPRMachineState
*spapr
,
530 uint32_t token
, uint32_t nargs
,
531 target_ulong args
, uint32_t nret
,
539 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
540 goto param_error_exit
;
543 buid
= rtas_ldq(args
, 1);
544 sphb
= spapr_pci_find_phb(spapr
, buid
);
546 goto param_error_exit
;
549 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
550 if (!spc
->eeh_get_state
) {
551 goto param_error_exit
;
554 ret
= spc
->eeh_get_state(sphb
, &state
);
555 rtas_st(rets
, 0, ret
);
556 if (ret
!= RTAS_OUT_SUCCESS
) {
560 rtas_st(rets
, 1, state
);
561 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
562 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
564 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
569 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
572 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
573 sPAPRMachineState
*spapr
,
574 uint32_t token
, uint32_t nargs
,
575 target_ulong args
, uint32_t nret
,
584 if ((nargs
!= 4) || (nret
!= 1)) {
585 goto param_error_exit
;
588 buid
= rtas_ldq(args
, 1);
589 option
= rtas_ld(args
, 3);
590 sphb
= spapr_pci_find_phb(spapr
, buid
);
592 goto param_error_exit
;
595 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
596 if (!spc
->eeh_reset
) {
597 goto param_error_exit
;
600 ret
= spc
->eeh_reset(sphb
, option
);
601 rtas_st(rets
, 0, ret
);
605 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
608 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
609 sPAPRMachineState
*spapr
,
610 uint32_t token
, uint32_t nargs
,
611 target_ulong args
, uint32_t nret
,
619 if ((nargs
!= 3) || (nret
!= 1)) {
620 goto param_error_exit
;
623 buid
= rtas_ldq(args
, 1);
624 sphb
= spapr_pci_find_phb(spapr
, buid
);
626 goto param_error_exit
;
629 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
630 if (!spc
->eeh_configure
) {
631 goto param_error_exit
;
634 ret
= spc
->eeh_configure(sphb
);
635 rtas_st(rets
, 0, ret
);
639 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
642 /* To support it later */
643 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
644 sPAPRMachineState
*spapr
,
645 uint32_t token
, uint32_t nargs
,
646 target_ulong args
, uint32_t nret
,
654 if ((nargs
!= 8) || (nret
!= 1)) {
655 goto param_error_exit
;
658 buid
= rtas_ldq(args
, 1);
659 sphb
= spapr_pci_find_phb(spapr
, buid
);
661 goto param_error_exit
;
664 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
665 if (!spc
->eeh_set_option
) {
666 goto param_error_exit
;
669 option
= rtas_ld(args
, 7);
671 case RTAS_SLOT_TEMP_ERR_LOG
:
672 case RTAS_SLOT_PERM_ERR_LOG
:
675 goto param_error_exit
;
678 /* We don't have error log yet */
679 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
683 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
686 static int pci_spapr_swizzle(int slot
, int pin
)
688 return (slot
+ pin
) % PCI_NUM_PINS
;
691 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
694 * Here we need to convert pci_dev + irq_num to some unique value
695 * which is less than number of IRQs on the specific bus (4). We
696 * use standard PCI swizzling, that is (slot number + pin number)
699 return pci_spapr_swizzle(PCI_SLOT(pci_dev
->devfn
), irq_num
);
702 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
705 * Here we use the number returned by pci_spapr_map_irq to find a
706 * corresponding qemu_irq.
708 sPAPRPHBState
*phb
= opaque
;
710 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
711 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
714 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
716 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
719 route
.mode
= PCI_INTX_ENABLED
;
720 route
.irq
= sphb
->lsi_table
[pin
].irq
;
726 * MSI/MSIX memory region implementation.
727 * The handler handles both MSI and MSIX.
728 * For MSI-X, the vector number is encoded as a part of the address,
730 * For MSI, the vector number is encoded in least bits in data.
732 static void spapr_msi_write(void *opaque
, hwaddr addr
,
733 uint64_t data
, unsigned size
)
735 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
738 trace_spapr_pci_msi_write(addr
, data
, irq
);
740 qemu_irq_pulse(xics_get_qirq(spapr
->icp
, irq
));
743 static const MemoryRegionOps spapr_msi_ops
= {
744 /* There is no .read as the read result is undefined by PCI spec */
746 .write
= spapr_msi_write
,
747 .endianness
= DEVICE_LITTLE_ENDIAN
753 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
755 sPAPRPHBState
*phb
= opaque
;
757 return &phb
->iommu_as
;
760 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
762 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
764 /* Get the PCI VFIO host id */
765 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
770 /* Construct the path of the file that will give us the DT location */
771 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
773 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
778 /* Construct and read from host device tree the loc-code */
779 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
781 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
791 static char *spapr_phb_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
794 const char *devtype
= "qemu";
795 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
797 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
798 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
805 * For emulated devices and VFIO-failure case, make up
808 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
809 devtype
, pdev
->name
, sphb
->index
, busnr
,
810 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
814 /* Macros to operate with address in OF binding to PCI */
815 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
816 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
817 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
818 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
819 #define b_ss(x) b_x((x), 24, 2) /* the space code */
820 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
821 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
822 #define b_fff(x) b_x((x), 8, 3) /* function number */
823 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
825 /* for 'reg'/'assigned-addresses' OF properties */
826 #define RESOURCE_CELLS_SIZE 2
827 #define RESOURCE_CELLS_ADDRESS 3
829 typedef struct ResourceFields
{
835 } QEMU_PACKED ResourceFields
;
837 typedef struct ResourceProps
{
838 ResourceFields reg
[8];
839 ResourceFields assigned
[7];
841 uint32_t assigned_len
;
844 /* fill in the 'reg'/'assigned-resources' OF properties for
845 * a PCI device. 'reg' describes resource requirements for a
846 * device's IO/MEM regions, 'assigned-addresses' describes the
847 * actual resource assignments.
849 * the properties are arrays of ('phys-addr', 'size') pairs describing
850 * the addressable regions of the PCI device, where 'phys-addr' is a
851 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
852 * (phys.hi, phys.mid, phys.lo), and 'size' is a
853 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
855 * phys.hi = 0xYYXXXXZZ, where:
860 * ||| + 00 if configuration space
861 * ||| + 01 if IO region,
862 * ||| + 10 if 32-bit MEM region
863 * ||| + 11 if 64-bit MEM region
865 * ||+------ for non-relocatable IO: 1 if aliased
866 * || for relocatable IO: 1 if below 64KB
867 * || for MEM: 1 if below 1MB
868 * |+------- 1 if region is prefetchable
869 * +-------- 1 if region is non-relocatable
870 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
872 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
875 * phys.mid and phys.lo correspond respectively to the hi/lo portions
876 * of the actual address of the region.
878 * how the phys-addr/size values are used differ slightly between
879 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
880 * an additional description for the config space region of the
881 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
882 * to describe the region as relocatable, with an address-mapping
883 * that corresponds directly to the PHB's address space for the
884 * resource. 'assigned-addresses' always has n=1 set with an absolute
885 * address assigned for the resource. in general, 'assigned-addresses'
886 * won't be populated, since addresses for PCI devices are generally
887 * unmapped initially and left to the guest to assign.
889 * note also that addresses defined in these properties are, at least
890 * for PAPR guests, relative to the PHBs IO/MEM windows, and
891 * correspond directly to the addresses in the BARs.
893 * in accordance with PCI Bus Binding to Open Firmware,
894 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
897 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
899 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
900 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
901 b_ddddd(PCI_SLOT(d
->devfn
)) |
902 b_fff(PCI_FUNC(d
->devfn
)));
903 ResourceFields
*reg
, *assigned
;
904 int i
, reg_idx
= 0, assigned_idx
= 0;
906 /* config space region */
907 reg
= &rp
->reg
[reg_idx
++];
908 reg
->phys_hi
= cpu_to_be32(dev_id
);
914 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
915 if (!d
->io_regions
[i
].size
) {
919 reg
= &rp
->reg
[reg_idx
++];
921 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
922 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
923 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
924 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
925 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
927 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
931 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
932 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
934 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
938 assigned
= &rp
->assigned
[assigned_idx
++];
939 assigned
->phys_hi
= cpu_to_be32(reg
->phys_hi
| b_n(1));
940 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
941 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
942 assigned
->size_hi
= reg
->size_hi
;
943 assigned
->size_lo
= reg
->size_lo
;
946 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
947 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
950 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
953 static int spapr_populate_pci_child_dt(PCIDevice
*dev
, void *fdt
, int offset
,
957 bool is_bridge
= false;
960 uint32_t drc_index
= spapr_phb_get_pci_drc_index(sphb
, dev
);
961 uint32_t max_msi
, max_msix
;
963 if (pci_default_read_config(dev
, PCI_HEADER_TYPE
, 1) ==
964 PCI_HEADER_TYPE_BRIDGE
) {
968 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
969 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id",
970 pci_default_read_config(dev
, PCI_VENDOR_ID
, 2)));
971 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id",
972 pci_default_read_config(dev
, PCI_DEVICE_ID
, 2)));
973 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id",
974 pci_default_read_config(dev
, PCI_REVISION_ID
, 1)));
975 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code",
976 pci_default_read_config(dev
, PCI_CLASS_PROG
, 3)));
977 if (pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)) {
978 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts",
979 pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)));
983 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant",
984 pci_default_read_config(dev
, PCI_MIN_GNT
, 1)));
985 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency",
986 pci_default_read_config(dev
, PCI_MAX_LAT
, 1)));
989 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)) {
990 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id",
991 pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)));
994 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)) {
995 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
996 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)));
999 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size",
1000 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1)));
1002 /* the following fdt cells are masked off the pci status register */
1003 pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
1004 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
1005 PCI_STATUS_DEVSEL_MASK
& pci_status
));
1007 if (pci_status
& PCI_STATUS_FAST_BACK
) {
1008 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
1010 if (pci_status
& PCI_STATUS_66MHZ
) {
1011 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1013 if (pci_status
& PCI_STATUS_UDF
) {
1014 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1017 /* NOTE: this is normally generated by firmware via path/unit name,
1018 * but in our case we must set it manually since it does not get
1019 * processed by OF beforehand
1021 _FDT(fdt_setprop_string(fdt
, offset
, "name", "pci"));
1022 buf
= spapr_phb_get_loc_code(sphb
, dev
);
1024 error_report("Failed setting the ibm,loc-code");
1028 err
= fdt_setprop_string(fdt
, offset
, "ibm,loc-code", buf
);
1035 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
));
1038 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1039 RESOURCE_CELLS_ADDRESS
));
1040 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1041 RESOURCE_CELLS_SIZE
));
1043 max_msi
= msi_nr_vectors_allocated(dev
);
1045 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi", max_msi
));
1047 max_msix
= dev
->msix_entries_nr
;
1049 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x", max_msix
));
1052 populate_resource_props(dev
, &rp
);
1053 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1054 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
1055 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
1060 /* create OF node for pci device and required OF DT properties */
1061 static int spapr_create_pci_child_dt(sPAPRPHBState
*phb
, PCIDevice
*dev
,
1062 void *fdt
, int node_offset
)
1065 int slot
= PCI_SLOT(dev
->devfn
);
1066 int func
= PCI_FUNC(dev
->devfn
);
1067 char nodename
[FDT_NAME_MAX
];
1070 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x,%x", slot
, func
);
1072 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x", slot
);
1074 offset
= fdt_add_subnode(fdt
, node_offset
, nodename
);
1075 ret
= spapr_populate_pci_child_dt(dev
, fdt
, offset
, phb
);
1084 static void spapr_phb_add_pci_device(sPAPRDRConnector
*drc
,
1089 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1090 DeviceState
*dev
= DEVICE(pdev
);
1092 int fdt_start_offset
= 0, fdt_size
;
1094 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
1095 sPAPRTCETable
*tcet
= spapr_tce_find_by_liobn(phb
->dma_liobn
);
1097 spapr_tce_set_need_vfio(tcet
, true);
1100 if (dev
->hotplugged
) {
1101 fdt
= create_device_tree(&fdt_size
);
1102 fdt_start_offset
= spapr_create_pci_child_dt(phb
, pdev
, fdt
, 0);
1103 if (!fdt_start_offset
) {
1104 error_setg(errp
, "Failed to create pci child device tree node");
1109 drck
->attach(drc
, DEVICE(pdev
),
1110 fdt
, fdt_start_offset
, !dev
->hotplugged
, errp
);
1117 static void spapr_phb_remove_pci_device_cb(DeviceState
*dev
, void *opaque
)
1119 /* some version guests do not wait for completion of a device
1120 * cleanup (generally done asynchronously by the kernel) before
1121 * signaling to QEMU that the device is safe, but instead sleep
1122 * for some 'safe' period of time. unfortunately on a busy host
1123 * this sleep isn't guaranteed to be long enough, resulting in
1124 * bad things like IRQ lines being left asserted during final
1125 * device removal. to deal with this we call reset just prior
1126 * to finalizing the device, which will put the device back into
1127 * an 'idle' state, as the device cleanup code expects.
1129 pci_device_reset(PCI_DEVICE(dev
));
1130 object_unparent(OBJECT(dev
));
1133 static void spapr_phb_remove_pci_device(sPAPRDRConnector
*drc
,
1138 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1140 drck
->detach(drc
, DEVICE(pdev
), spapr_phb_remove_pci_device_cb
, phb
, errp
);
1143 static sPAPRDRConnector
*spapr_phb_get_pci_drc(sPAPRPHBState
*phb
,
1146 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
1147 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI
,
1148 (phb
->index
<< 16) |
1153 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
1156 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1157 sPAPRDRConnectorClass
*drck
;
1163 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1164 return drck
->get_index(drc
);
1167 static void spapr_phb_hot_plug_child(HotplugHandler
*plug_handler
,
1168 DeviceState
*plugged_dev
, Error
**errp
)
1170 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1171 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1172 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1173 Error
*local_err
= NULL
;
1175 /* if DR is disabled we don't need to do anything in the case of
1176 * hotplug or coldplug callbacks
1178 if (!phb
->dr_enabled
) {
1179 /* if this is a hotplug operation initiated by the user
1180 * we need to let them know it's not enabled
1182 if (plugged_dev
->hotplugged
) {
1183 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1184 object_get_typename(OBJECT(phb
)));
1191 spapr_phb_add_pci_device(drc
, phb
, pdev
, &local_err
);
1193 error_propagate(errp
, local_err
);
1196 if (plugged_dev
->hotplugged
) {
1197 spapr_hotplug_req_add_by_index(drc
);
1201 static void spapr_phb_hot_unplug_child(HotplugHandler
*plug_handler
,
1202 DeviceState
*plugged_dev
, Error
**errp
)
1204 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1205 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1206 sPAPRDRConnectorClass
*drck
;
1207 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1208 Error
*local_err
= NULL
;
1210 if (!phb
->dr_enabled
) {
1211 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1212 object_get_typename(OBJECT(phb
)));
1218 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1219 if (!drck
->release_pending(drc
)) {
1220 spapr_phb_remove_pci_device(drc
, phb
, pdev
, &local_err
);
1222 error_propagate(errp
, local_err
);
1225 spapr_hotplug_req_remove_by_index(drc
);
1229 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1231 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1232 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1233 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1234 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1235 sPAPRPHBClass
*info
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s
);
1239 uint64_t msi_window_size
= 4096;
1241 if (sphb
->index
!= (uint32_t)-1) {
1242 hwaddr windows_base
;
1244 if ((sphb
->buid
!= (uint64_t)-1) || (sphb
->dma_liobn
!= (uint32_t)-1)
1245 || (sphb
->mem_win_addr
!= (hwaddr
)-1)
1246 || (sphb
->io_win_addr
!= (hwaddr
)-1)) {
1247 error_setg(errp
, "Either \"index\" or other parameters must"
1248 " be specified for PAPR PHB, not both");
1252 if (sphb
->index
> SPAPR_PCI_MAX_INDEX
) {
1253 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
1254 SPAPR_PCI_MAX_INDEX
);
1258 sphb
->buid
= SPAPR_PCI_BASE_BUID
+ sphb
->index
;
1259 sphb
->dma_liobn
= SPAPR_PCI_LIOBN(sphb
->index
, 0);
1261 windows_base
= SPAPR_PCI_WINDOW_BASE
1262 + sphb
->index
* SPAPR_PCI_WINDOW_SPACING
;
1263 sphb
->mem_win_addr
= windows_base
+ SPAPR_PCI_MMIO_WIN_OFF
;
1264 sphb
->io_win_addr
= windows_base
+ SPAPR_PCI_IO_WIN_OFF
;
1267 if (sphb
->buid
== (uint64_t)-1) {
1268 error_setg(errp
, "BUID not specified for PHB");
1272 if (sphb
->dma_liobn
== (uint32_t)-1) {
1273 error_setg(errp
, "LIOBN not specified for PHB");
1277 if (sphb
->mem_win_addr
== (hwaddr
)-1) {
1278 error_setg(errp
, "Memory window address not specified for PHB");
1282 if (sphb
->io_win_addr
== (hwaddr
)-1) {
1283 error_setg(errp
, "IO window address not specified for PHB");
1287 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1288 error_setg(errp
, "PCI host bridges must have unique BUIDs");
1292 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1294 namebuf
= alloca(strlen(sphb
->dtbusname
) + 32);
1296 /* Initialize memory regions */
1297 sprintf(namebuf
, "%s.mmio", sphb
->dtbusname
);
1298 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1300 sprintf(namebuf
, "%s.mmio-alias", sphb
->dtbusname
);
1301 memory_region_init_alias(&sphb
->memwindow
, OBJECT(sphb
),
1302 namebuf
, &sphb
->memspace
,
1303 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1304 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1307 /* Initialize IO regions */
1308 sprintf(namebuf
, "%s.io", sphb
->dtbusname
);
1309 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1310 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1312 sprintf(namebuf
, "%s.io-alias", sphb
->dtbusname
);
1313 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1314 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1315 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1318 bus
= pci_register_bus(dev
, NULL
,
1319 pci_spapr_set_irq
, pci_spapr_map_irq
, sphb
,
1320 &sphb
->memspace
, &sphb
->iospace
,
1321 PCI_DEVFN(0, 0), PCI_NUM_PINS
, TYPE_PCI_BUS
);
1323 qbus_set_hotplug_handler(BUS(phb
->bus
), DEVICE(sphb
), NULL
);
1326 * Initialize PHB address space.
1327 * By default there will be at least one subregion for default
1329 * Later the guest might want to create another DMA window
1330 * which will become another memory subregion.
1332 sprintf(namebuf
, "%s.iommu-root", sphb
->dtbusname
);
1334 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1335 namebuf
, UINT64_MAX
);
1336 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1340 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1341 * we need to allocate some memory to catch those writes coming
1342 * from msi_notify()/msix_notify().
1343 * As MSIMessage:addr is going to be the same and MSIMessage:data
1344 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1347 * For KVM we want to ensure that this memory is a full page so that
1348 * our memory slot is of page size granularity.
1351 if (kvm_enabled()) {
1352 msi_window_size
= getpagesize();
1356 memory_region_init_io(&sphb
->msiwindow
, NULL
, &spapr_msi_ops
, spapr
,
1357 "msi", msi_window_size
);
1358 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1361 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1363 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1365 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1367 /* Initialize the LSI table */
1368 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1371 irq
= xics_alloc_block(spapr
->icp
, 0, 1, true, false);
1373 error_setg(errp
, "spapr_allocate_lsi failed");
1377 sphb
->lsi_table
[i
].irq
= irq
;
1380 /* allocate connectors for child PCI devices */
1381 if (sphb
->dr_enabled
) {
1382 for (i
= 0; i
< PCI_SLOT_MAX
* 8; i
++) {
1383 spapr_dr_connector_new(OBJECT(phb
),
1384 SPAPR_DR_CONNECTOR_TYPE_PCI
,
1385 (sphb
->index
<< 16) | i
);
1389 if (!info
->finish_realize
) {
1390 error_setg(errp
, "finish_realize not defined");
1394 info
->finish_realize(sphb
, errp
);
1396 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
1399 static void spapr_phb_finish_realize(sPAPRPHBState
*sphb
, Error
**errp
)
1401 sPAPRTCETable
*tcet
;
1404 nb_table
= sphb
->dma_win_size
>> SPAPR_TCE_PAGE_SHIFT
;
1405 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
,
1406 0, SPAPR_TCE_PAGE_SHIFT
, nb_table
, false);
1408 error_setg(errp
, "Unable to create TCE table for %s",
1413 /* Register default 32bit DMA window */
1414 memory_region_add_subregion(&sphb
->iommu_root
, sphb
->dma_win_addr
,
1415 spapr_tce_get_iommu(tcet
));
1418 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
1420 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
1429 static void spapr_phb_reset(DeviceState
*qdev
)
1431 /* Reset the IOMMU state */
1432 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
1435 static Property spapr_phb_properties
[] = {
1436 DEFINE_PROP_UINT32("index", sPAPRPHBState
, index
, -1),
1437 DEFINE_PROP_UINT64("buid", sPAPRPHBState
, buid
, -1),
1438 DEFINE_PROP_UINT32("liobn", sPAPRPHBState
, dma_liobn
, -1),
1439 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState
, mem_win_addr
, -1),
1440 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState
, mem_win_size
,
1441 SPAPR_PCI_MMIO_WIN_SIZE
),
1442 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState
, io_win_addr
, -1),
1443 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState
, io_win_size
,
1444 SPAPR_PCI_IO_WIN_SIZE
),
1445 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState
, dr_enabled
,
1447 /* Default DMA window is 0..1GB */
1448 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState
, dma_win_addr
, 0),
1449 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState
, dma_win_size
, 0x40000000),
1450 DEFINE_PROP_END_OF_LIST(),
1453 static const VMStateDescription vmstate_spapr_pci_lsi
= {
1454 .name
= "spapr_pci/lsi",
1456 .minimum_version_id
= 1,
1457 .fields
= (VMStateField
[]) {
1458 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
),
1460 VMSTATE_END_OF_LIST()
1464 static const VMStateDescription vmstate_spapr_pci_msi
= {
1465 .name
= "spapr_pci/msi",
1467 .minimum_version_id
= 1,
1468 .fields
= (VMStateField
[]) {
1469 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
1470 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
1471 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
1472 VMSTATE_END_OF_LIST()
1476 static void spapr_pci_pre_save(void *opaque
)
1478 sPAPRPHBState
*sphb
= opaque
;
1479 GHashTableIter iter
;
1480 gpointer key
, value
;
1483 g_free(sphb
->msi_devs
);
1484 sphb
->msi_devs
= NULL
;
1485 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
1486 if (!sphb
->msi_devs_num
) {
1489 sphb
->msi_devs
= g_malloc(sphb
->msi_devs_num
* sizeof(spapr_pci_msi_mig
));
1491 g_hash_table_iter_init(&iter
, sphb
->msi
);
1492 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
1493 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
1494 sphb
->msi_devs
[i
].value
= *(spapr_pci_msi
*) value
;
1498 static int spapr_pci_post_load(void *opaque
, int version_id
)
1500 sPAPRPHBState
*sphb
= opaque
;
1501 gpointer key
, value
;
1504 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
1505 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
1506 sizeof(sphb
->msi_devs
[i
].key
));
1507 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
1508 sizeof(sphb
->msi_devs
[i
].value
));
1509 g_hash_table_insert(sphb
->msi
, key
, value
);
1511 g_free(sphb
->msi_devs
);
1512 sphb
->msi_devs
= NULL
;
1513 sphb
->msi_devs_num
= 0;
1518 static const VMStateDescription vmstate_spapr_pci
= {
1519 .name
= "spapr_pci",
1521 .minimum_version_id
= 2,
1522 .pre_save
= spapr_pci_pre_save
,
1523 .post_load
= spapr_pci_post_load
,
1524 .fields
= (VMStateField
[]) {
1525 VMSTATE_UINT64_EQUAL(buid
, sPAPRPHBState
),
1526 VMSTATE_UINT32_EQUAL(dma_liobn
, sPAPRPHBState
),
1527 VMSTATE_UINT64_EQUAL(mem_win_addr
, sPAPRPHBState
),
1528 VMSTATE_UINT64_EQUAL(mem_win_size
, sPAPRPHBState
),
1529 VMSTATE_UINT64_EQUAL(io_win_addr
, sPAPRPHBState
),
1530 VMSTATE_UINT64_EQUAL(io_win_size
, sPAPRPHBState
),
1531 VMSTATE_STRUCT_ARRAY(lsi_table
, sPAPRPHBState
, PCI_NUM_PINS
, 0,
1532 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
1533 VMSTATE_INT32(msi_devs_num
, sPAPRPHBState
),
1534 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, sPAPRPHBState
, msi_devs_num
, 0,
1535 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
1536 VMSTATE_END_OF_LIST()
1540 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
1543 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
1545 return sphb
->dtbusname
;
1548 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
1550 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
1551 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1552 sPAPRPHBClass
*spc
= SPAPR_PCI_HOST_BRIDGE_CLASS(klass
);
1553 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
1555 hc
->root_bus_path
= spapr_phb_root_bus_path
;
1556 dc
->realize
= spapr_phb_realize
;
1557 dc
->props
= spapr_phb_properties
;
1558 dc
->reset
= spapr_phb_reset
;
1559 dc
->vmsd
= &vmstate_spapr_pci
;
1560 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1561 dc
->cannot_instantiate_with_device_add_yet
= false;
1562 spc
->finish_realize
= spapr_phb_finish_realize
;
1563 hp
->plug
= spapr_phb_hot_plug_child
;
1564 hp
->unplug
= spapr_phb_hot_unplug_child
;
1567 static const TypeInfo spapr_phb_info
= {
1568 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
1569 .parent
= TYPE_PCI_HOST_BRIDGE
,
1570 .instance_size
= sizeof(sPAPRPHBState
),
1571 .class_init
= spapr_phb_class_init
,
1572 .class_size
= sizeof(sPAPRPHBClass
),
1573 .interfaces
= (InterfaceInfo
[]) {
1574 { TYPE_HOTPLUG_HANDLER
},
1579 PCIHostState
*spapr_create_phb(sPAPRMachineState
*spapr
, int index
)
1583 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1584 qdev_prop_set_uint32(dev
, "index", index
);
1585 qdev_init_nofail(dev
);
1587 return PCI_HOST_BRIDGE(dev
);
1590 typedef struct sPAPRFDT
{
1593 sPAPRPHBState
*sphb
;
1596 static void spapr_populate_pci_devices_dt(PCIBus
*bus
, PCIDevice
*pdev
,
1600 sPAPRFDT
*p
= opaque
;
1604 offset
= spapr_create_pci_child_dt(p
->sphb
, pdev
, p
->fdt
, p
->node_off
);
1606 error_report("Failed to create pci child device tree node");
1610 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1611 PCI_HEADER_TYPE_BRIDGE
)) {
1615 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1621 s_fdt
.node_off
= offset
;
1622 s_fdt
.sphb
= p
->sphb
;
1623 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1624 spapr_populate_pci_devices_dt
,
1628 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
1631 unsigned int *bus_no
= opaque
;
1632 unsigned int primary
= *bus_no
;
1633 unsigned int subordinate
= 0xff;
1634 PCIBus
*sec_bus
= NULL
;
1636 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1637 PCI_HEADER_TYPE_BRIDGE
)) {
1642 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, primary
, 1);
1643 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
1644 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1646 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1651 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, subordinate
, 1);
1652 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1653 spapr_phb_pci_enumerate_bridge
, bus_no
);
1654 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1657 static void spapr_phb_pci_enumerate(sPAPRPHBState
*phb
)
1659 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1660 unsigned int bus_no
= 0;
1662 pci_for_each_device(bus
, pci_bus_num(bus
),
1663 spapr_phb_pci_enumerate_bridge
,
1668 int spapr_populate_pci_dt(sPAPRPHBState
*phb
,
1669 uint32_t xics_phandle
,
1672 int bus_off
, i
, j
, ret
;
1673 char nodename
[FDT_NAME_MAX
];
1674 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
1675 const uint64_t mmiosize
= memory_region_size(&phb
->memwindow
);
1676 const uint64_t w32max
= (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET
;
1677 const uint64_t w32size
= MIN(w32max
, mmiosize
);
1678 const uint64_t w64size
= (mmiosize
> w32size
) ? (mmiosize
- w32size
) : 0;
1684 } QEMU_PACKED ranges
[] = {
1686 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
1687 cpu_to_be64(phb
->io_win_addr
),
1688 cpu_to_be64(memory_region_size(&phb
->iospace
)),
1691 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
1692 cpu_to_be64(phb
->mem_win_addr
),
1693 cpu_to_be64(w32size
),
1696 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32),
1697 cpu_to_be64(phb
->mem_win_addr
+ w32size
),
1698 cpu_to_be64(w64size
)
1701 const unsigned sizeof_ranges
= (w64size
? 3 : 2) * sizeof(ranges
[0]);
1702 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
1703 uint32_t interrupt_map_mask
[] = {
1704 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
1705 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
1706 sPAPRTCETable
*tcet
;
1707 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1710 /* Start populating the FDT */
1711 snprintf(nodename
, FDT_NAME_MAX
, "pci@%" PRIx64
, phb
->buid
);
1712 bus_off
= fdt_add_subnode(fdt
, 0, nodename
);
1717 /* Write PHB properties */
1718 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
1719 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
1720 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
1721 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
1722 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
1723 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
1724 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
1725 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
1726 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
1727 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
1728 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", XICS_IRQS
));
1730 /* Build the interrupt-map, this must matches what is done
1731 * in pci_spapr_map_irq
1733 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
1734 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
1735 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
1736 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
1737 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
1738 int lsi_num
= pci_spapr_swizzle(i
, j
);
1740 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
1743 irqmap
[3] = cpu_to_be32(j
+1);
1744 irqmap
[4] = cpu_to_be32(xics_phandle
);
1745 irqmap
[5] = cpu_to_be32(phb
->lsi_table
[lsi_num
].irq
);
1746 irqmap
[6] = cpu_to_be32(0x8);
1749 /* Write interrupt map */
1750 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
1751 sizeof(interrupt_map
)));
1753 tcet
= spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb
->index
, 0));
1754 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
1755 tcet
->liobn
, tcet
->bus_offset
,
1756 tcet
->nb_table
<< tcet
->page_shift
);
1758 /* Walk the bridges and program the bus numbers*/
1759 spapr_phb_pci_enumerate(phb
);
1760 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
1762 /* Populate tree nodes with PCI devices attached */
1764 s_fdt
.node_off
= bus_off
;
1766 pci_for_each_device(bus
, pci_bus_num(bus
),
1767 spapr_populate_pci_devices_dt
,
1770 ret
= spapr_drc_populate_dt(fdt
, bus_off
, OBJECT(phb
),
1771 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1779 void spapr_pci_rtas_init(void)
1781 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
1782 rtas_read_pci_config
);
1783 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
1784 rtas_write_pci_config
);
1785 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
1786 rtas_ibm_read_pci_config
);
1787 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
1788 rtas_ibm_write_pci_config
);
1789 if (msi_supported
) {
1790 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
1791 "ibm,query-interrupt-source-number",
1792 rtas_ibm_query_interrupt_source_number
);
1793 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
1794 rtas_ibm_change_msi
);
1797 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
1798 "ibm,set-eeh-option",
1799 rtas_ibm_set_eeh_option
);
1800 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
1801 "ibm,get-config-addr-info2",
1802 rtas_ibm_get_config_addr_info2
);
1803 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
1804 "ibm,read-slot-reset-state2",
1805 rtas_ibm_read_slot_reset_state2
);
1806 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
1807 "ibm,set-slot-reset",
1808 rtas_ibm_set_slot_reset
);
1809 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
1811 rtas_ibm_configure_pe
);
1812 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
1813 "ibm,slot-error-detail",
1814 rtas_ibm_slot_error_detail
);
1817 static void spapr_pci_register_types(void)
1819 type_register_static(&spapr_phb_info
);
1822 type_init(spapr_pci_register_types
)
1824 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
1826 bool be
= *(bool *)opaque
;
1828 if (object_dynamic_cast(OBJECT(dev
), "VGA")
1829 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
1830 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
1836 void spapr_pci_switch_vga(bool big_endian
)
1838 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1839 sPAPRPHBState
*sphb
;
1842 * For backward compatibility with existing guests, we switch
1843 * the endianness of the VGA controller when changing the guest
1846 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
1847 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
1848 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,