2 * OneNAND flash memories emulation.
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
25 #include "hw/block/flash.h"
27 #include "sysemu/block-backend.h"
28 #include "sysemu/blockdev.h"
29 #include "exec/memory.h"
30 #include "exec/address-spaces.h"
31 #include "hw/sysbus.h"
32 #include "qemu/error-report.h"
34 /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
38 #define BLOCK_SHIFT (PAGE_SHIFT + 6)
40 #define TYPE_ONE_NAND "onenand"
41 #define ONE_NAND(obj) OBJECT_CHECK(OneNANDState, (obj), TYPE_ONE_NAND)
43 typedef struct OneNANDState
{
44 SysBusDevice parent_obj
;
56 BlockBackend
*blk_cur
;
61 MemoryRegion mapped_ram
;
62 uint8_t current_direction
;
66 MemoryRegion container
;
92 ONEN_BUF_DEST_BLOCK
= 2,
93 ONEN_BUF_DEST_PAGE
= 3,
98 ONEN_ERR_CMD
= 1 << 10,
99 ONEN_ERR_ERASE
= 1 << 11,
100 ONEN_ERR_PROG
= 1 << 12,
101 ONEN_ERR_LOAD
= 1 << 13,
105 ONEN_INT_RESET
= 1 << 4,
106 ONEN_INT_ERASE
= 1 << 5,
107 ONEN_INT_PROG
= 1 << 6,
108 ONEN_INT_LOAD
= 1 << 7,
113 ONEN_LOCK_LOCKTIGHTEN
= 1 << 0,
114 ONEN_LOCK_LOCKED
= 1 << 1,
115 ONEN_LOCK_UNLOCKED
= 1 << 2,
118 static void onenand_mem_setup(OneNANDState
*s
)
120 /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
121 * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
122 * write boot commands. Also take note of the BWPS bit. */
123 memory_region_init(&s
->container
, OBJECT(s
), "onenand",
124 0x10000 << s
->shift
);
125 memory_region_add_subregion(&s
->container
, 0, &s
->iomem
);
126 memory_region_init_alias(&s
->mapped_ram
, OBJECT(s
), "onenand-mapped-ram",
127 &s
->ram
, 0x0200 << s
->shift
,
129 memory_region_add_subregion_overlap(&s
->container
,
135 static void onenand_intr_update(OneNANDState
*s
)
137 qemu_set_irq(s
->intr
, ((s
->intstatus
>> 15) ^ (~s
->config
[0] >> 6)) & 1);
140 static void onenand_pre_save(void *opaque
)
142 OneNANDState
*s
= opaque
;
143 if (s
->current
== s
->otp
) {
144 s
->current_direction
= 1;
145 } else if (s
->current
== s
->image
) {
146 s
->current_direction
= 2;
148 s
->current_direction
= 0;
152 static int onenand_post_load(void *opaque
, int version_id
)
154 OneNANDState
*s
= opaque
;
155 switch (s
->current_direction
) {
162 s
->current
= s
->image
;
167 onenand_intr_update(s
);
171 static const VMStateDescription vmstate_onenand
= {
174 .minimum_version_id
= 1,
175 .pre_save
= onenand_pre_save
,
176 .post_load
= onenand_post_load
,
177 .fields
= (VMStateField
[]) {
178 VMSTATE_UINT8(current_direction
, OneNANDState
),
179 VMSTATE_INT32(cycle
, OneNANDState
),
180 VMSTATE_INT32(otpmode
, OneNANDState
),
181 VMSTATE_UINT16_ARRAY(addr
, OneNANDState
, 8),
182 VMSTATE_UINT16_ARRAY(unladdr
, OneNANDState
, 8),
183 VMSTATE_INT32(bufaddr
, OneNANDState
),
184 VMSTATE_INT32(count
, OneNANDState
),
185 VMSTATE_UINT16(command
, OneNANDState
),
186 VMSTATE_UINT16_ARRAY(config
, OneNANDState
, 2),
187 VMSTATE_UINT16(status
, OneNANDState
),
188 VMSTATE_UINT16(intstatus
, OneNANDState
),
189 VMSTATE_UINT16(wpstatus
, OneNANDState
),
190 VMSTATE_INT32(secs_cur
, OneNANDState
),
191 VMSTATE_PARTIAL_VBUFFER(blockwp
, OneNANDState
, blocks
),
192 VMSTATE_UINT8(ecc
.cp
, OneNANDState
),
193 VMSTATE_UINT16_ARRAY(ecc
.lp
, OneNANDState
, 2),
194 VMSTATE_UINT16(ecc
.count
, OneNANDState
),
195 VMSTATE_BUFFER_POINTER_UNSAFE(otp
, OneNANDState
, 0,
196 ((64 + 2) << PAGE_SHIFT
)),
197 VMSTATE_END_OF_LIST()
201 /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
202 static void onenand_reset(OneNANDState
*s
, int cold
)
204 memset(&s
->addr
, 0, sizeof(s
->addr
));
208 s
->config
[0] = 0x40c0;
209 s
->config
[1] = 0x0000;
210 onenand_intr_update(s
);
211 qemu_irq_raise(s
->rdy
);
213 s
->intstatus
= cold
? 0x8080 : 0x8010;
216 s
->wpstatus
= 0x0002;
220 s
->current
= s
->image
;
221 s
->secs_cur
= s
->secs
;
224 /* Lock the whole flash */
225 memset(s
->blockwp
, ONEN_LOCK_LOCKED
, s
->blocks
);
227 if (s
->blk_cur
&& blk_read(s
->blk_cur
, 0, s
->boot
[0], 8) < 0) {
228 hw_error("%s: Loading the BootRAM failed.\n", __func__
);
233 static void onenand_system_reset(DeviceState
*dev
)
235 OneNANDState
*s
= ONE_NAND(dev
);
240 static inline int onenand_load_main(OneNANDState
*s
, int sec
, int secn
,
244 return blk_read(s
->blk_cur
, sec
, dest
, secn
) < 0;
245 } else if (sec
+ secn
> s
->secs_cur
) {
249 memcpy(dest
, s
->current
+ (sec
<< 9), secn
<< 9);
254 static inline int onenand_prog_main(OneNANDState
*s
, int sec
, int secn
,
260 uint32_t size
= (uint32_t)secn
* 512;
261 const uint8_t *sp
= (const uint8_t *)src
;
265 if (!dp
|| blk_read(s
->blk_cur
, sec
, dp
, secn
) < 0) {
269 if (sec
+ secn
> s
->secs_cur
) {
272 dp
= (uint8_t *)s
->current
+ (sec
<< 9);
277 for (i
= 0; i
< size
; i
++) {
281 result
= blk_write(s
->blk_cur
, sec
, dp
, secn
) < 0;
284 if (dp
&& s
->blk_cur
) {
292 static inline int onenand_load_spare(OneNANDState
*s
, int sec
, int secn
,
298 if (blk_read(s
->blk_cur
, s
->secs_cur
+ (sec
>> 5), buf
, 1) < 0) {
301 memcpy(dest
, buf
+ ((sec
& 31) << 4), secn
<< 4);
302 } else if (sec
+ secn
> s
->secs_cur
) {
305 memcpy(dest
, s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4), secn
<< 4);
311 static inline int onenand_prog_spare(OneNANDState
*s
, int sec
, int secn
,
316 const uint8_t *sp
= (const uint8_t *)src
;
317 uint8_t *dp
= 0, *dpp
= 0;
321 || blk_read(s
->blk_cur
, s
->secs_cur
+ (sec
>> 5), dp
, 1) < 0) {
324 dpp
= dp
+ ((sec
& 31) << 4);
327 if (sec
+ secn
> s
->secs_cur
) {
330 dpp
= s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4);
335 for (i
= 0; i
< (secn
<< 4); i
++) {
339 result
= blk_write(s
->blk_cur
, s
->secs_cur
+ (sec
>> 5),
348 static inline int onenand_erase(OneNANDState
*s
, int sec
, int num
)
350 uint8_t *blankbuf
, *tmpbuf
;
352 blankbuf
= g_malloc(512);
353 tmpbuf
= g_malloc(512);
354 memset(blankbuf
, 0xff, 512);
355 for (; num
> 0; num
--, sec
++) {
357 int erasesec
= s
->secs_cur
+ (sec
>> 5);
358 if (blk_write(s
->blk_cur
, sec
, blankbuf
, 1) < 0) {
361 if (blk_read(s
->blk_cur
, erasesec
, tmpbuf
, 1) < 0) {
364 memcpy(tmpbuf
+ ((sec
& 31) << 4), blankbuf
, 1 << 4);
365 if (blk_write(s
->blk_cur
, erasesec
, tmpbuf
, 1) < 0) {
369 if (sec
+ 1 > s
->secs_cur
) {
372 memcpy(s
->current
+ (sec
<< 9), blankbuf
, 512);
373 memcpy(s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4),
388 static void onenand_command(OneNANDState
*s
)
393 #define SETADDR(block, page) \
394 sec = (s->addr[page] & 3) + \
395 ((((s->addr[page] >> 2) & 0x3f) + \
396 (((s->addr[block] & 0xfff) | \
397 (s->addr[block] >> 15 ? \
398 s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
400 buf = (s->bufaddr & 8) ? \
401 s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
402 buf += (s->bufaddr & 3) << 9;
404 buf = (s->bufaddr & 8) ? \
405 s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
406 buf += (s->bufaddr & 3) << 4;
408 switch (s
->command
) {
409 case 0x00: /* Load single/multiple sector data unit into buffer */
410 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
413 if (onenand_load_main(s
, sec
, s
->count
, buf
))
414 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
418 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
419 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
422 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
423 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
424 * then we need two split the read/write into two chunks.
426 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
428 case 0x13: /* Load single/multiple spare sector into buffer */
429 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
432 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
433 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
435 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
436 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
437 * then we need two split the read/write into two chunks.
439 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
441 case 0x80: /* Program single/multiple sector data unit from buffer */
442 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
445 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
446 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
450 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
451 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
454 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
455 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
456 * then we need two split the read/write into two chunks.
458 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
460 case 0x1a: /* Program single/multiple spare area sector from buffer */
461 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
464 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
465 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
467 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
468 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
469 * then we need two split the read/write into two chunks.
471 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
473 case 0x1b: /* Copy-back program */
476 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
477 if (onenand_load_main(s
, sec
, s
->count
, buf
))
478 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
480 SETADDR(ONEN_BUF_DEST_BLOCK
, ONEN_BUF_DEST_PAGE
)
481 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
482 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
484 /* TODO: spare areas */
486 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
489 case 0x23: /* Unlock NAND array block(s) */
490 s
->intstatus
|= ONEN_INT
;
492 /* XXX the previous (?) area should be locked automatically */
493 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
494 if (b
>= s
->blocks
) {
495 s
->status
|= ONEN_ERR_CMD
;
498 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
501 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
504 case 0x27: /* Unlock All NAND array blocks */
505 s
->intstatus
|= ONEN_INT
;
507 for (b
= 0; b
< s
->blocks
; b
++) {
508 if (b
>= s
->blocks
) {
509 s
->status
|= ONEN_ERR_CMD
;
512 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
515 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
519 case 0x2a: /* Lock NAND array block(s) */
520 s
->intstatus
|= ONEN_INT
;
522 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
523 if (b
>= s
->blocks
) {
524 s
->status
|= ONEN_ERR_CMD
;
527 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
530 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKED
;
533 case 0x2c: /* Lock-tight NAND array block(s) */
534 s
->intstatus
|= ONEN_INT
;
536 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
537 if (b
>= s
->blocks
) {
538 s
->status
|= ONEN_ERR_CMD
;
541 if (s
->blockwp
[b
] == ONEN_LOCK_UNLOCKED
)
544 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKTIGHTEN
;
548 case 0x71: /* Erase-Verify-Read */
549 s
->intstatus
|= ONEN_INT
;
551 case 0x95: /* Multi-block erase */
552 qemu_irq_pulse(s
->intr
);
554 case 0x94: /* Block erase */
555 sec
= ((s
->addr
[ONEN_BUF_BLOCK
] & 0xfff) |
556 (s
->addr
[ONEN_BUF_BLOCK
] >> 15 ? s
->density_mask
: 0))
557 << (BLOCK_SHIFT
- 9);
558 if (onenand_erase(s
, sec
, 1 << (BLOCK_SHIFT
- 9)))
559 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_ERASE
;
561 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
563 case 0xb0: /* Erase suspend */
565 case 0x30: /* Erase resume */
566 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
569 case 0xf0: /* Reset NAND Flash core */
572 case 0xf3: /* Reset OneNAND */
576 case 0x65: /* OTP Access */
577 s
->intstatus
|= ONEN_INT
;
580 s
->secs_cur
= 1 << (BLOCK_SHIFT
- 9);
581 s
->addr
[ONEN_BUF_BLOCK
] = 0;
586 s
->status
|= ONEN_ERR_CMD
;
587 s
->intstatus
|= ONEN_INT
;
588 fprintf(stderr
, "%s: unknown OneNAND command %x\n",
589 __func__
, s
->command
);
592 onenand_intr_update(s
);
595 static uint64_t onenand_read(void *opaque
, hwaddr addr
,
598 OneNANDState
*s
= (OneNANDState
*) opaque
;
599 int offset
= addr
>> s
->shift
;
602 case 0x0000 ... 0xc000:
603 return lduw_le_p(s
->boot
[0] + addr
);
605 case 0xf000: /* Manufacturer ID */
607 case 0xf001: /* Device ID */
609 case 0xf002: /* Version ID */
611 /* TODO: get the following values from a real chip! */
612 case 0xf003: /* Data Buffer size */
613 return 1 << PAGE_SHIFT
;
614 case 0xf004: /* Boot Buffer size */
616 case 0xf005: /* Amount of buffers */
618 case 0xf006: /* Technology */
621 case 0xf100 ... 0xf107: /* Start addresses */
622 return s
->addr
[offset
- 0xf100];
624 case 0xf200: /* Start buffer */
625 return (s
->bufaddr
<< 8) | ((s
->count
- 1) & (1 << (PAGE_SHIFT
- 10)));
627 case 0xf220: /* Command */
629 case 0xf221: /* System Configuration 1 */
630 return s
->config
[0] & 0xffe0;
631 case 0xf222: /* System Configuration 2 */
634 case 0xf240: /* Controller Status */
636 case 0xf241: /* Interrupt */
638 case 0xf24c: /* Unlock Start Block Address */
639 return s
->unladdr
[0];
640 case 0xf24d: /* Unlock End Block Address */
641 return s
->unladdr
[1];
642 case 0xf24e: /* Write Protection Status */
645 case 0xff00: /* ECC Status */
647 case 0xff01: /* ECC Result of main area data */
648 case 0xff02: /* ECC Result of spare area data */
649 case 0xff03: /* ECC Result of main area data */
650 case 0xff04: /* ECC Result of spare area data */
651 hw_error("%s: imeplement ECC\n", __FUNCTION__
);
655 fprintf(stderr
, "%s: unknown OneNAND register %x\n",
656 __FUNCTION__
, offset
);
660 static void onenand_write(void *opaque
, hwaddr addr
,
661 uint64_t value
, unsigned size
)
663 OneNANDState
*s
= (OneNANDState
*) opaque
;
664 int offset
= addr
>> s
->shift
;
668 case 0x0000 ... 0x01ff:
669 case 0x8000 ... 0x800f:
673 if (value
== 0x0000) {
674 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
675 onenand_load_main(s
, sec
,
676 1 << (PAGE_SHIFT
- 9), s
->data
[0][0]);
677 s
->addr
[ONEN_BUF_PAGE
] += 4;
678 s
->addr
[ONEN_BUF_PAGE
] &= 0xff;
684 case 0x00f0: /* Reset OneNAND */
688 case 0x00e0: /* Load Data into Buffer */
692 case 0x0090: /* Read Identification Data */
693 memset(s
->boot
[0], 0, 3 << s
->shift
);
694 s
->boot
[0][0 << s
->shift
] = s
->id
.man
& 0xff;
695 s
->boot
[0][1 << s
->shift
] = s
->id
.dev
& 0xff;
696 s
->boot
[0][2 << s
->shift
] = s
->wpstatus
& 0xff;
700 fprintf(stderr
, "%s: unknown OneNAND boot command %"PRIx64
"\n",
701 __FUNCTION__
, value
);
705 case 0xf100 ... 0xf107: /* Start addresses */
706 s
->addr
[offset
- 0xf100] = value
;
709 case 0xf200: /* Start buffer */
710 s
->bufaddr
= (value
>> 8) & 0xf;
711 if (PAGE_SHIFT
== 11)
712 s
->count
= (value
& 3) ?: 4;
713 else if (PAGE_SHIFT
== 10)
714 s
->count
= (value
& 1) ?: 2;
717 case 0xf220: /* Command */
718 if (s
->intstatus
& (1 << 15))
723 case 0xf221: /* System Configuration 1 */
724 s
->config
[0] = value
;
725 onenand_intr_update(s
);
726 qemu_set_irq(s
->rdy
, (s
->config
[0] >> 7) & 1);
728 case 0xf222: /* System Configuration 2 */
729 s
->config
[1] = value
;
732 case 0xf241: /* Interrupt */
733 s
->intstatus
&= value
;
734 if ((1 << 15) & ~s
->intstatus
)
735 s
->status
&= ~(ONEN_ERR_CMD
| ONEN_ERR_ERASE
|
736 ONEN_ERR_PROG
| ONEN_ERR_LOAD
);
737 onenand_intr_update(s
);
739 case 0xf24c: /* Unlock Start Block Address */
740 s
->unladdr
[0] = value
& (s
->blocks
- 1);
741 /* For some reason we have to set the end address to by default
742 * be same as start because the software forgets to write anything
744 s
->unladdr
[1] = value
& (s
->blocks
- 1);
746 case 0xf24d: /* Unlock End Block Address */
747 s
->unladdr
[1] = value
& (s
->blocks
- 1);
751 fprintf(stderr
, "%s: unknown OneNAND register %x\n",
752 __FUNCTION__
, offset
);
756 static const MemoryRegionOps onenand_ops
= {
757 .read
= onenand_read
,
758 .write
= onenand_write
,
759 .endianness
= DEVICE_NATIVE_ENDIAN
,
762 static int onenand_initfn(SysBusDevice
*sbd
)
764 DeviceState
*dev
= DEVICE(sbd
);
765 OneNANDState
*s
= ONE_NAND(dev
);
766 uint32_t size
= 1 << (24 + ((s
->id
.dev
>> 4) & 7));
769 s
->base
= (hwaddr
)-1;
771 s
->blocks
= size
>> BLOCK_SHIFT
;
773 s
->blockwp
= g_malloc(s
->blocks
);
774 s
->density_mask
= (s
->id
.dev
& 0x08)
775 ? (1 << (6 + ((s
->id
.dev
>> 4) & 7))) : 0;
776 memory_region_init_io(&s
->iomem
, OBJECT(s
), &onenand_ops
, s
, "onenand",
777 0x10000 << s
->shift
);
779 s
->image
= memset(g_malloc(size
+ (size
>> 5)),
780 0xff, size
+ (size
>> 5));
782 if (blk_is_read_only(s
->blk
)) {
783 error_report("Can't use a read-only drive");
788 s
->otp
= memset(g_malloc((64 + 2) << PAGE_SHIFT
),
789 0xff, (64 + 2) << PAGE_SHIFT
);
790 memory_region_init_ram(&s
->ram
, OBJECT(s
), "onenand.ram",
791 0xc000 << s
->shift
, &error_fatal
);
792 vmstate_register_ram_global(&s
->ram
);
793 ram
= memory_region_get_ram_ptr(&s
->ram
);
794 s
->boot
[0] = ram
+ (0x0000 << s
->shift
);
795 s
->boot
[1] = ram
+ (0x8000 << s
->shift
);
796 s
->data
[0][0] = ram
+ ((0x0200 + (0 << (PAGE_SHIFT
- 1))) << s
->shift
);
797 s
->data
[0][1] = ram
+ ((0x8010 + (0 << (PAGE_SHIFT
- 6))) << s
->shift
);
798 s
->data
[1][0] = ram
+ ((0x0200 + (1 << (PAGE_SHIFT
- 1))) << s
->shift
);
799 s
->data
[1][1] = ram
+ ((0x8010 + (1 << (PAGE_SHIFT
- 6))) << s
->shift
);
800 onenand_mem_setup(s
);
801 sysbus_init_irq(sbd
, &s
->intr
);
802 sysbus_init_mmio(sbd
, &s
->container
);
803 vmstate_register(dev
,
804 ((s
->shift
& 0x7f) << 24)
805 | ((s
->id
.man
& 0xff) << 16)
806 | ((s
->id
.dev
& 0xff) << 8)
807 | (s
->id
.ver
& 0xff),
808 &vmstate_onenand
, s
);
812 static Property onenand_properties
[] = {
813 DEFINE_PROP_UINT16("manufacturer_id", OneNANDState
, id
.man
, 0),
814 DEFINE_PROP_UINT16("device_id", OneNANDState
, id
.dev
, 0),
815 DEFINE_PROP_UINT16("version_id", OneNANDState
, id
.ver
, 0),
816 DEFINE_PROP_INT32("shift", OneNANDState
, shift
, 0),
817 DEFINE_PROP_DRIVE("drive", OneNANDState
, blk
),
818 DEFINE_PROP_END_OF_LIST(),
821 static void onenand_class_init(ObjectClass
*klass
, void *data
)
823 DeviceClass
*dc
= DEVICE_CLASS(klass
);
824 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
826 k
->init
= onenand_initfn
;
827 dc
->reset
= onenand_system_reset
;
828 dc
->props
= onenand_properties
;
831 static const TypeInfo onenand_info
= {
832 .name
= TYPE_ONE_NAND
,
833 .parent
= TYPE_SYS_BUS_DEVICE
,
834 .instance_size
= sizeof(OneNANDState
),
835 .class_init
= onenand_class_init
,
838 static void onenand_register_types(void)
840 type_register_static(&onenand_info
);
843 void *onenand_raw_otp(DeviceState
*onenand_device
)
845 OneNANDState
*s
= ONE_NAND(onenand_device
);
850 type_init(onenand_register_types
)