hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/irq.h"
  15 #include "hw/ptimer.h"
  16 #include "qemu/module.h"
  17 #include "qemu/log.h"
  18 #include "qom/object.h"
  19
  20 #undef DEBUG_PUV3
  21 #include "hw/unicore32/puv3.h"
  22
  23 #define TYPE_PUV3_OST "puv3_ost"
  24 OBJECT_DECLARE_SIMPLE_TYPE(PUV3OSTState, PUV3_OST)
  25
  26 /* puv3 ostimer implementation. */
  27 struct PUV3OSTState {
  28     SysBusDevice parent_obj;
  29
  30     MemoryRegion iomem;
  31     qemu_irq irq;
  32     ptimer_state *ptimer;
  33
  34     uint32_t reg_OSMR0;
  35     uint32_t reg_OSCR;
  36     uint32_t reg_OSSR;
  37     uint32_t reg_OIER;
  38 };
  39
  40 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  41         unsigned size)
  42 {
  43     PUV3OSTState *s = opaque;
  44     uint32_t ret = 0;
  45
  46     switch (offset) {
  47     case 0x10: /* Counter Register */
  48         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  49         break;
  50     case 0x14: /* Status Register */
  51         ret = s->reg_OSSR;
  52         break;
  53     case 0x1c: /* Interrupt Enable Register */
  54         ret = s->reg_OIER;
  55         break;
  56     default:
  57         qemu_log_mask(LOG_GUEST_ERROR,
  58                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  59                       __func__, offset);
  60     }
  61     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  62     return ret;
  63 }
  64
  65 static void puv3_ost_write(void *opaque, hwaddr offset,
  66         uint64_t value, unsigned size)
  67 {
  68     PUV3OSTState *s = opaque;
  69
  70     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  71     switch (offset) {
  72     case 0x00: /* Match Register 0 */
  73         ptimer_transaction_begin(s->ptimer);
  74         s->reg_OSMR0 = value;
  75         if (s->reg_OSMR0 > s->reg_OSCR) {
  76             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  77         } else {
  78             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  79                     (0xffffffff - s->reg_OSCR));
  80         }
  81         ptimer_run(s->ptimer, 2);
  82         ptimer_transaction_commit(s->ptimer);
  83         break;
  84     case 0x14: /* Status Register */
  85         assert(value == 0);
  86         if (s->reg_OSSR) {
  87             s->reg_OSSR = value;
  88             qemu_irq_lower(s->irq);
  89         }
  90         break;
  91     case 0x1c: /* Interrupt Enable Register */
  92         s->reg_OIER = value;
  93         break;
  94     default:
  95         qemu_log_mask(LOG_GUEST_ERROR,
  96                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  97                       __func__, offset);
  98     }
  99 }
 100
 101 static const MemoryRegionOps puv3_ost_ops = {
 102     .read = puv3_ost_read,
 103     .write = puv3_ost_write,
 104     .impl = {
 105         .min_access_size = 4,
 106         .max_access_size = 4,
 107     },
 108     .endianness = DEVICE_NATIVE_ENDIAN,
 109 };
 110
 111 static void puv3_ost_tick(void *opaque)
 112 {
 113     PUV3OSTState *s = opaque;
 114
 115     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 116             s->reg_OSCR, s->reg_OSMR0);
 117
 118     s->reg_OSCR = s->reg_OSMR0;
 119     if (s->reg_OIER) {
 120         s->reg_OSSR = 1;
 121         qemu_irq_raise(s->irq);
 122     }
 123 }
 124
 125 static void puv3_ost_realize(DeviceState *dev, Error **errp)
 126 {
 127     PUV3OSTState *s = PUV3_OST(dev);
 128     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 129
 130     s->reg_OIER = 0;
 131     s->reg_OSSR = 0;
 132     s->reg_OSMR0 = 0;
 133     s->reg_OSCR = 0;
 134
 135     sysbus_init_irq(sbd, &s->irq);
 136
 137     s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
 138     ptimer_transaction_begin(s->ptimer);
 139     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 140     ptimer_transaction_commit(s->ptimer);
 141
 142     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 143             PUV3_REGS_OFFSET);
 144     sysbus_init_mmio(sbd, &s->iomem);
 145 }
 146
 147 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 148 {
 149     DeviceClass *dc = DEVICE_CLASS(klass);
 150
 151     dc->realize = puv3_ost_realize;
 152 }
 153
 154 static const TypeInfo puv3_ost_info = {
 155     .name = TYPE_PUV3_OST,
 156     .parent = TYPE_SYS_BUS_DEVICE,
 157     .instance_size = sizeof(PUV3OSTState),
 158     .class_init = puv3_ost_class_init,
 159 };
 160
 161 static void puv3_ost_register_type(void)
 162 {
 163     type_register_static(&puv3_ost_info);
 164 }
 165
 166 type_init(puv3_ost_register_type)