2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/spapr.h"
19 #include "hw/ppc/spapr_cpu_core.h"
20 #include "hw/ppc/spapr_xive.h"
21 #include "hw/ppc/xive.h"
22 #include "hw/ppc/xive_regs.h"
25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
26 * use for the ESB pages and the TIMA pages
28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
32 * The allocation of VP blocks is a complex operation in OPAL and the
33 * VP identifiers have a relation with the number of HW chips, the
34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
35 * controller model does not have the same constraints and can use a
36 * simple mapping scheme of the CPU vcpu_id
38 * These identifiers are never returned to the OS.
41 #define SPAPR_XIVE_NVT_BASE 0x400
44 * sPAPR NVT and END indexing helpers
46 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
48 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
51 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
52 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
57 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
61 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
65 static int spapr_xive_target_to_nvt(uint32_t target
,
66 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
68 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
74 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
79 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
82 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
83 uint32_t *out_server
, uint8_t *out_prio
)
86 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
89 *out_server
= end_idx
>> 3;
93 *out_prio
= end_idx
& 0x7;
98 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
99 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
104 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
108 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
112 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
113 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
115 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
121 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
126 * On sPAPR machines, use a simplified output for the XIVE END
127 * structure dumping only the information related to the OS EQ.
129 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
132 uint64_t qaddr_base
= xive_end_qaddr(end
);
133 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
134 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
135 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
136 uint32_t qentries
= 1 << (qsize
+ 10);
137 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
138 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
140 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
141 spapr_xive_nvt_to_target(0, nvt
),
142 priority
, qindex
, qentries
, qaddr_base
, qgen
);
144 xive_end_queue_pic_print_info(end
, 6, mon
);
145 monitor_printf(mon
, "]");
148 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
150 XiveSource
*xsrc
= &xive
->source
;
153 if (kvm_irqchip_in_kernel()) {
154 Error
*local_err
= NULL
;
156 kvmppc_xive_synchronize_state(xive
, &local_err
);
158 error_report_err(local_err
);
163 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
165 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
166 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
167 XiveEAS
*eas
= &xive
->eat
[i
];
169 if (!xive_eas_is_valid(eas
)) {
173 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
174 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
175 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
176 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
177 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
178 xive_eas_is_masked(eas
) ? "M" : " ",
179 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
181 if (!xive_eas_is_masked(eas
)) {
182 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
185 assert(end_idx
< xive
->nr_ends
);
186 end
= &xive
->endt
[end_idx
];
188 if (xive_end_is_valid(end
)) {
189 spapr_xive_end_pic_print_info(xive
, end
, mon
);
192 monitor_printf(mon
, "\n");
196 void spapr_xive_map_mmio(SpaprXive
*xive
)
198 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
199 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
200 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
203 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
205 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
206 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
208 /* Disable the END ESBs until a guest OS makes use of them */
209 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
213 * When a Virtual Processor is scheduled to run on a HW thread, the
214 * hypervisor pushes its identifier in the OS CAM line. Emulate the
215 * same behavior under QEMU.
217 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
223 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
225 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
226 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
229 static void spapr_xive_end_reset(XiveEND
*end
)
231 memset(end
, 0, sizeof(*end
));
233 /* switch off the escalation and notification ESBs */
234 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
237 static void spapr_xive_reset(void *dev
)
239 SpaprXive
*xive
= SPAPR_XIVE(dev
);
243 * The XiveSource has its own reset handler, which mask off all
247 /* Mask all valid EASs in the IRQ number space. */
248 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
249 XiveEAS
*eas
= &xive
->eat
[i
];
250 if (xive_eas_is_valid(eas
)) {
251 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
258 for (i
= 0; i
< xive
->nr_ends
; i
++) {
259 spapr_xive_end_reset(&xive
->endt
[i
]);
263 static void spapr_xive_instance_init(Object
*obj
)
265 SpaprXive
*xive
= SPAPR_XIVE(obj
);
267 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
268 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
270 object_initialize_child(obj
, "end_source", &xive
->end_source
,
271 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
274 /* Not connected to the KVM XIVE device */
278 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
280 SpaprXive
*xive
= SPAPR_XIVE(dev
);
281 XiveSource
*xsrc
= &xive
->source
;
282 XiveENDSource
*end_xsrc
= &xive
->end_source
;
283 Error
*local_err
= NULL
;
285 if (!xive
->nr_irqs
) {
286 error_setg(errp
, "Number of interrupt needs to be greater 0");
290 if (!xive
->nr_ends
) {
291 error_setg(errp
, "Number of interrupt needs to be greater 0");
296 * Initialize the internal sources, for IPIs and virtual devices.
298 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
300 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
302 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
304 error_propagate(errp
, local_err
);
309 * Initialize the END ESB source
311 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
313 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
315 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
317 error_propagate(errp
, local_err
);
321 /* Set the mapping address of the END ESB pages after the source ESBs */
322 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
325 * Allocate the routing tables
327 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
328 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
330 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
331 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
333 qemu_register_reset(spapr_xive_reset
, dev
);
335 /* Define all XIVE MMIO regions on SysBus */
336 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
337 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
338 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
341 void spapr_xive_init(SpaprXive
*xive
, Error
**errp
)
343 XiveSource
*xsrc
= &xive
->source
;
346 * The emulated XIVE device can only be initialized once. If the
347 * ESB memory region has been already mapped, it means we have been
350 if (memory_region_is_mapped(&xsrc
->esb_mmio
)) {
354 /* TIMA initialization */
355 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
356 "xive.tima", 4ull << TM_SHIFT
);
358 /* Map all regions */
359 spapr_xive_map_mmio(xive
);
362 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
363 uint32_t eas_idx
, XiveEAS
*eas
)
365 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
367 if (eas_idx
>= xive
->nr_irqs
) {
371 *eas
= xive
->eat
[eas_idx
];
375 static int spapr_xive_get_end(XiveRouter
*xrtr
,
376 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
378 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
380 if (end_idx
>= xive
->nr_ends
) {
384 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
388 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
389 uint32_t end_idx
, XiveEND
*end
,
392 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
394 if (end_idx
>= xive
->nr_ends
) {
398 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
402 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
403 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
405 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
406 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
409 /* TODO: should we assert() if we can find a NVT ? */
414 * sPAPR does not maintain a NVT table. Return that the NVT is
415 * valid if we have found a matching CPU
417 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
421 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
422 uint32_t nvt_idx
, XiveNVT
*nvt
,
426 * We don't need to write back to the NVTs because the sPAPR
427 * machine should never hit a non-scheduled NVT. It should never
430 g_assert_not_reached();
433 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
435 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
437 return spapr_cpu_state(cpu
)->tctx
;
440 static const VMStateDescription vmstate_spapr_xive_end
= {
441 .name
= TYPE_SPAPR_XIVE
"/end",
443 .minimum_version_id
= 1,
444 .fields
= (VMStateField
[]) {
445 VMSTATE_UINT32(w0
, XiveEND
),
446 VMSTATE_UINT32(w1
, XiveEND
),
447 VMSTATE_UINT32(w2
, XiveEND
),
448 VMSTATE_UINT32(w3
, XiveEND
),
449 VMSTATE_UINT32(w4
, XiveEND
),
450 VMSTATE_UINT32(w5
, XiveEND
),
451 VMSTATE_UINT32(w6
, XiveEND
),
452 VMSTATE_UINT32(w7
, XiveEND
),
453 VMSTATE_END_OF_LIST()
457 static const VMStateDescription vmstate_spapr_xive_eas
= {
458 .name
= TYPE_SPAPR_XIVE
"/eas",
460 .minimum_version_id
= 1,
461 .fields
= (VMStateField
[]) {
462 VMSTATE_UINT64(w
, XiveEAS
),
463 VMSTATE_END_OF_LIST()
467 static int vmstate_spapr_xive_pre_save(void *opaque
)
469 if (kvm_irqchip_in_kernel()) {
470 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
477 * Called by the sPAPR IRQ backend 'post_load' method at the machine
480 int spapr_xive_post_load(SpaprXive
*xive
, int version_id
)
482 if (kvm_irqchip_in_kernel()) {
483 return kvmppc_xive_post_load(xive
, version_id
);
489 static const VMStateDescription vmstate_spapr_xive
= {
490 .name
= TYPE_SPAPR_XIVE
,
492 .minimum_version_id
= 1,
493 .pre_save
= vmstate_spapr_xive_pre_save
,
494 .post_load
= NULL
, /* handled at the machine level */
495 .fields
= (VMStateField
[]) {
496 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
497 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
498 vmstate_spapr_xive_eas
, XiveEAS
),
499 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
500 vmstate_spapr_xive_end
, XiveEND
),
501 VMSTATE_END_OF_LIST()
505 static Property spapr_xive_properties
[] = {
506 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
507 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
508 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
509 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
510 DEFINE_PROP_END_OF_LIST(),
513 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
515 DeviceClass
*dc
= DEVICE_CLASS(klass
);
516 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
518 dc
->desc
= "sPAPR XIVE Interrupt Controller";
519 dc
->props
= spapr_xive_properties
;
520 dc
->realize
= spapr_xive_realize
;
521 dc
->vmsd
= &vmstate_spapr_xive
;
523 xrc
->get_eas
= spapr_xive_get_eas
;
524 xrc
->get_end
= spapr_xive_get_end
;
525 xrc
->write_end
= spapr_xive_write_end
;
526 xrc
->get_nvt
= spapr_xive_get_nvt
;
527 xrc
->write_nvt
= spapr_xive_write_nvt
;
528 xrc
->get_tctx
= spapr_xive_get_tctx
;
531 static const TypeInfo spapr_xive_info
= {
532 .name
= TYPE_SPAPR_XIVE
,
533 .parent
= TYPE_XIVE_ROUTER
,
534 .instance_init
= spapr_xive_instance_init
,
535 .instance_size
= sizeof(SpaprXive
),
536 .class_init
= spapr_xive_class_init
,
539 static void spapr_xive_register_types(void)
541 type_register_static(&spapr_xive_info
);
544 type_init(spapr_xive_register_types
)
546 bool spapr_xive_irq_claim(SpaprXive
*xive
, uint32_t lisn
, bool lsi
)
548 XiveSource
*xsrc
= &xive
->source
;
550 if (lisn
>= xive
->nr_irqs
) {
554 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
556 xive_source_irq_set_lsi(xsrc
, lisn
);
559 if (kvm_irqchip_in_kernel()) {
560 Error
*local_err
= NULL
;
562 kvmppc_xive_source_reset_one(xsrc
, lisn
, &local_err
);
564 error_report_err(local_err
);
572 bool spapr_xive_irq_free(SpaprXive
*xive
, uint32_t lisn
)
574 if (lisn
>= xive
->nr_irqs
) {
578 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
585 * The terminology used by the XIVE hcalls is the following :
588 * EQ Event Queue assigned by OS to receive event data
589 * ESB page for source interrupt management
590 * LISN Logical Interrupt Source Number identifying a source in the
592 * EISN Effective Interrupt Source Number used by guest OS to
593 * identify source in the guest
595 * The EAS, END, NVT structures are not exposed.
599 * Linux hosts under OPAL reserve priority 7 for their own escalation
600 * interrupts (DD2.X POWER9). So we only allow the guest to use
603 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
608 case 7: /* OPAL escalation queue */
615 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
616 * real address of the MMIO page through which the Event State Buffer
617 * entry associated with the value of the "lisn" parameter is managed.
623 * - R5: "lisn" is per "interrupts", "interrupt-map", or
624 * "ibm,xive-lisn-ranges" properties, or as returned by the
625 * ibm,query-interrupt-source-number RTAS call, or as returned
626 * by the H_ALLOCATE_VAS_WINDOW hcall
630 * Bits 0-59: Reserved
631 * Bit 60: H_INT_ESB must be used for Event State Buffer
633 * Bit 61: 1 == LSI 0 == MSI
634 * Bit 62: the full function page supports trigger
635 * Bit 63: Store EOI Supported
636 * - R5: Logical Real address of full function Event State Buffer
637 * management page, -1 if H_INT_ESB hcall flag is set to 1.
638 * - R6: Logical Real Address of trigger only Event State Buffer
639 * management page or -1.
640 * - R7: Power of 2 page size for the ESB management pages returned in
644 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
645 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
646 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
648 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
650 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
651 SpaprMachineState
*spapr
,
655 SpaprXive
*xive
= spapr
->xive
;
656 XiveSource
*xsrc
= &xive
->source
;
657 target_ulong flags
= args
[0];
658 target_ulong lisn
= args
[1];
660 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
668 if (lisn
>= xive
->nr_irqs
) {
669 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
674 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
675 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
681 * All sources are emulated under the main XIVE object and share
682 * the same characteristics.
685 if (!xive_source_esb_has_2page(xsrc
)) {
686 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
688 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
689 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
693 * Force the use of the H_INT_ESB hcall in case of an LSI
694 * interrupt. This is necessary under KVM to re-trigger the
695 * interrupt if the level is still asserted
697 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
698 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
701 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
702 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
707 if (xive_source_esb_has_2page(xsrc
) &&
708 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
709 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
714 if (xive_source_esb_has_2page(xsrc
)) {
715 args
[3] = xsrc
->esb_shift
- 1;
717 args
[3] = xsrc
->esb_shift
;
724 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
725 * Interrupt Source to a target. The Logical Interrupt Source is
726 * designated with the "lisn" parameter and the target is designated
727 * with the "target" and "priority" parameters. Upon return from the
728 * hcall(), no additional interrupts will be directed to the old EQ.
733 * Bits 0-61: Reserved
734 * Bit 62: set the "eisn" in the EAS
735 * Bit 63: masks the interrupt source in the hardware interrupt
736 * control structure. An interrupt masked by this mechanism will
737 * be dropped, but it's source state bits will still be
738 * set. There is no race-free way of unmasking and restoring the
739 * source. Thus this should only be used in interrupts that are
740 * also masked at the source, and only in cases where the
741 * interrupt is not meant to be used for a large amount of time
742 * because no valid target exists for it for example
743 * - R5: "lisn" is per "interrupts", "interrupt-map", or
744 * "ibm,xive-lisn-ranges" properties, or as returned by the
745 * ibm,query-interrupt-source-number RTAS call, or as returned by
746 * the H_ALLOCATE_VAS_WINDOW hcall
747 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
748 * "ibm,ppc-interrupt-gserver#s"
749 * - R7: "priority" is a valid priority not in
750 * "ibm,plat-res-int-priorities"
751 * - R8: "eisn" is the guest EISN associated with the "lisn"
757 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
758 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
760 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
761 SpaprMachineState
*spapr
,
765 SpaprXive
*xive
= spapr
->xive
;
766 XiveEAS eas
, new_eas
;
767 target_ulong flags
= args
[0];
768 target_ulong lisn
= args
[1];
769 target_ulong target
= args
[2];
770 target_ulong priority
= args
[3];
771 target_ulong eisn
= args
[4];
775 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
779 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
783 if (lisn
>= xive
->nr_irqs
) {
784 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
789 eas
= xive
->eat
[lisn
];
790 if (!xive_eas_is_valid(&eas
)) {
791 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
796 /* priority 0xff is used to reset the EAS */
797 if (priority
== 0xff) {
798 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
802 if (flags
& SPAPR_XIVE_SRC_MASK
) {
803 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
805 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
808 if (spapr_xive_priority_is_reserved(priority
)) {
809 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
810 " is reserved\n", priority
);
815 * Validate that "target" is part of the list of threads allocated
816 * to the partition. For that, find the END corresponding to the
819 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
823 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
824 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
826 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
827 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
830 if (kvm_irqchip_in_kernel()) {
831 Error
*local_err
= NULL
;
833 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
835 error_report_err(local_err
);
841 xive
->eat
[lisn
] = new_eas
;
846 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
847 * target/priority pair is assigned to the specified Logical Interrupt
854 * - R5: "lisn" is per "interrupts", "interrupt-map", or
855 * "ibm,xive-lisn-ranges" properties, or as returned by the
856 * ibm,query-interrupt-source-number RTAS call, or as
857 * returned by the H_ALLOCATE_VAS_WINDOW hcall
860 * - R4: Target to which the specified Logical Interrupt Source is
862 * - R5: Priority to which the specified Logical Interrupt Source is
864 * - R6: EISN for the specified Logical Interrupt Source (this will be
865 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
867 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
868 SpaprMachineState
*spapr
,
872 SpaprXive
*xive
= spapr
->xive
;
873 target_ulong flags
= args
[0];
874 target_ulong lisn
= args
[1];
878 uint32_t end_idx
, nvt_idx
;
880 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
888 if (lisn
>= xive
->nr_irqs
) {
889 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
894 eas
= xive
->eat
[lisn
];
895 if (!xive_eas_is_valid(&eas
)) {
896 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
901 /* EAS_END_BLOCK is unused on sPAPR */
902 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
904 assert(end_idx
< xive
->nr_ends
);
905 end
= &xive
->endt
[end_idx
];
907 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
908 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
909 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
911 if (xive_eas_is_masked(&eas
)) {
914 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
917 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
923 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
924 * address of the notification management page associated with the
925 * specified target and priority.
931 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
932 * "ibm,ppc-interrupt-gserver#s"
933 * - R6: "priority" is a valid priority not in
934 * "ibm,plat-res-int-priorities"
937 * - R4: Logical real address of notification page
938 * - R5: Power of 2 page size of the notification page
940 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
941 SpaprMachineState
*spapr
,
945 SpaprXive
*xive
= spapr
->xive
;
946 XiveENDSource
*end_xsrc
= &xive
->end_source
;
947 target_ulong flags
= args
[0];
948 target_ulong target
= args
[1];
949 target_ulong priority
= args
[2];
954 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
963 * H_STATE should be returned if a H_INT_RESET is in progress.
964 * This is not needed when running the emulation under QEMU
967 if (spapr_xive_priority_is_reserved(priority
)) {
968 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
969 " is reserved\n", priority
);
974 * Validate that "target" is part of the list of threads allocated
975 * to the partition. For that, find the END corresponding to the
978 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
982 assert(end_idx
< xive
->nr_ends
);
983 end
= &xive
->endt
[end_idx
];
985 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
986 if (xive_end_is_enqueue(end
)) {
987 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
996 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
997 * a given "target" and "priority". It is also used to set the
998 * notification config associated with the EQ. An EQ size of 0 is
999 * used to reset the EQ config for a given target and priority. If
1000 * resetting the EQ config, the END associated with the given "target"
1001 * and "priority" will be changed to disable queueing.
1003 * Upon return from the hcall(), no additional interrupts will be
1004 * directed to the old EQ (if one was set). The old EQ (if one was
1005 * set) should be investigated for interrupts that occurred prior to
1006 * or during the hcall().
1011 * Bits 0-62: Reserved
1012 * Bit 63: Unconditional Notify (n) per the XIVE spec
1013 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1014 * "ibm,ppc-interrupt-gserver#s"
1015 * - R6: "priority" is a valid priority not in
1016 * "ibm,plat-res-int-priorities"
1017 * - R7: "eventQueue": The logical real address of the start of the EQ
1018 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1024 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1026 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1027 SpaprMachineState
*spapr
,
1028 target_ulong opcode
,
1031 SpaprXive
*xive
= spapr
->xive
;
1032 target_ulong flags
= args
[0];
1033 target_ulong target
= args
[1];
1034 target_ulong priority
= args
[2];
1035 target_ulong qpage
= args
[3];
1036 target_ulong qsize
= args
[4];
1038 uint8_t end_blk
, nvt_blk
;
1039 uint32_t end_idx
, nvt_idx
;
1041 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1045 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1050 * H_STATE should be returned if a H_INT_RESET is in progress.
1051 * This is not needed when running the emulation under QEMU
1054 if (spapr_xive_priority_is_reserved(priority
)) {
1055 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1056 " is reserved\n", priority
);
1061 * Validate that "target" is part of the list of threads allocated
1062 * to the partition. For that, find the END corresponding to the
1066 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1070 assert(end_idx
< xive
->nr_ends
);
1071 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1078 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1079 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1080 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1081 qpage
, (hwaddr
)1 << qsize
);
1084 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1085 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1086 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1087 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1090 /* reset queue and disable queueing */
1091 spapr_xive_end_reset(&end
);
1095 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1101 hwaddr plen
= 1 << qsize
;
1105 * Validate the guest EQ. We should also check that the queue
1106 * has been zeroed by the OS.
1108 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1109 MEMTXATTRS_UNSPECIFIED
);
1110 if (plen
!= 1 << qsize
) {
1111 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1112 HWADDR_PRIx
"\n", qpage
);
1115 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1118 /* "target" should have been validated above */
1119 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1120 g_assert_not_reached();
1124 * Ensure the priority and target are correctly set (they will not
1125 * be right after allocation)
1127 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1128 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1129 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1131 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1132 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1134 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1138 * The generation bit for the END starts at 1 and The END page
1139 * offset counter starts at 0.
1141 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1142 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1143 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1146 * TODO: issue syncs required to ensure all in-flight interrupts
1147 * are complete on the old END
1151 if (kvm_irqchip_in_kernel()) {
1152 Error
*local_err
= NULL
;
1154 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1156 error_report_err(local_err
);
1162 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1167 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1168 * target and priority.
1173 * Bits 0-62: Reserved
1174 * Bit 63: Debug: Return debug data
1175 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1176 * "ibm,ppc-interrupt-gserver#s"
1177 * - R6: "priority" is a valid priority not in
1178 * "ibm,plat-res-int-priorities"
1182 * Bits 0-61: Reserved
1183 * Bit 62: The value of Event Queue Generation Number (g) per
1184 * the XIVE spec if "Debug" = 1
1185 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1186 * - R5: The logical real address of the start of the EQ
1187 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1188 * - R7: The value of Event Queue Offset Counter per XIVE spec
1189 * if "Debug" = 1, else 0
1193 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1195 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1196 SpaprMachineState
*spapr
,
1197 target_ulong opcode
,
1200 SpaprXive
*xive
= spapr
->xive
;
1201 target_ulong flags
= args
[0];
1202 target_ulong target
= args
[1];
1203 target_ulong priority
= args
[2];
1208 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1212 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1217 * H_STATE should be returned if a H_INT_RESET is in progress.
1218 * This is not needed when running the emulation under QEMU
1221 if (spapr_xive_priority_is_reserved(priority
)) {
1222 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1223 " is reserved\n", priority
);
1228 * Validate that "target" is part of the list of threads allocated
1229 * to the partition. For that, find the END corresponding to the
1232 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1236 assert(end_idx
< xive
->nr_ends
);
1237 end
= &xive
->endt
[end_idx
];
1240 if (xive_end_is_notify(end
)) {
1241 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1244 if (xive_end_is_enqueue(end
)) {
1245 args
[1] = xive_end_qaddr(end
);
1246 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1252 if (kvm_irqchip_in_kernel()) {
1253 Error
*local_err
= NULL
;
1255 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1257 error_report_err(local_err
);
1262 /* TODO: do we need any locking on the END ? */
1263 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1264 /* Load the event queue generation number into the return flags */
1265 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1267 /* Load R7 with the event queue offset counter */
1268 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1277 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1278 * reporting cache line pair for the calling thread. The reporting
1279 * cache lines will contain the OS interrupt context when the OS
1280 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1281 * interrupt. The reporting cache lines can be reset by inputting -1
1282 * in "reportingLine". Issuing the CI store byte without reporting
1283 * cache lines registered will result in the data not being accessible
1289 * Bits 0-63: Reserved
1290 * - R5: "reportingLine": The logical real address of the reporting cache
1296 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1297 SpaprMachineState
*spapr
,
1298 target_ulong opcode
,
1301 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1306 * H_STATE should be returned if a H_INT_RESET is in progress.
1307 * This is not needed when running the emulation under QEMU
1310 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1315 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1316 * real address of the reporting cache line pair set for the input
1317 * "target". If no reporting cache line pair has been set, -1 is
1323 * Bits 0-63: Reserved
1324 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1325 * "ibm,ppc-interrupt-gserver#s"
1326 * - R6: "reportingLine": The logical real address of the reporting
1330 * - R4: The logical real address of the reporting line if set, else -1
1332 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1333 SpaprMachineState
*spapr
,
1334 target_ulong opcode
,
1337 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1342 * H_STATE should be returned if a H_INT_RESET is in progress.
1343 * This is not needed when running the emulation under QEMU
1346 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1351 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1352 * page for the input "lisn". This hcall is only supported for LISNs
1353 * that have the ESB hcall flag set to 1 when returned from hcall()
1354 * H_INT_GET_SOURCE_INFO.
1359 * Bits 0-62: Reserved
1360 * bit 63: Store: Store=1, store operation, else load operation
1361 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1362 * "ibm,xive-lisn-ranges" properties, or as returned by the
1363 * ibm,query-interrupt-source-number RTAS call, or as
1364 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1365 * - R6: "esbOffset" is the offset into the ESB page for the load or
1367 * - R7: "storeData" is the data to write for a store operation
1370 * - R4: The value of the load if load operation, else -1
1373 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1375 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1376 SpaprMachineState
*spapr
,
1377 target_ulong opcode
,
1380 SpaprXive
*xive
= spapr
->xive
;
1382 target_ulong flags
= args
[0];
1383 target_ulong lisn
= args
[1];
1384 target_ulong offset
= args
[2];
1385 target_ulong data
= args
[3];
1387 XiveSource
*xsrc
= &xive
->source
;
1389 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1393 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1397 if (lisn
>= xive
->nr_irqs
) {
1398 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1403 eas
= xive
->eat
[lisn
];
1404 if (!xive_eas_is_valid(&eas
)) {
1405 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1410 if (offset
> (1ull << xsrc
->esb_shift
)) {
1414 if (kvm_irqchip_in_kernel()) {
1415 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1416 flags
& SPAPR_XIVE_ESB_STORE
);
1418 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1420 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1421 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1422 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1423 HWADDR_PRIx
"\n", mmio_addr
);
1426 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1432 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1433 * ensure any in flight events for the input lisn are in the event
1439 * Bits 0-63: Reserved
1440 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1441 * "ibm,xive-lisn-ranges" properties, or as returned by the
1442 * ibm,query-interrupt-source-number RTAS call, or as
1443 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1448 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1449 SpaprMachineState
*spapr
,
1450 target_ulong opcode
,
1453 SpaprXive
*xive
= spapr
->xive
;
1455 target_ulong flags
= args
[0];
1456 target_ulong lisn
= args
[1];
1458 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1466 if (lisn
>= xive
->nr_irqs
) {
1467 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1472 eas
= xive
->eat
[lisn
];
1473 if (!xive_eas_is_valid(&eas
)) {
1474 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1480 * H_STATE should be returned if a H_INT_RESET is in progress.
1481 * This is not needed when running the emulation under QEMU
1485 * This is not real hardware. Nothing to be done unless when
1489 if (kvm_irqchip_in_kernel()) {
1490 Error
*local_err
= NULL
;
1492 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1494 error_report_err(local_err
);
1502 * The H_INT_RESET hcall() is used to reset all of the partition's
1503 * interrupt exploitation structures to their initial state. This
1504 * means losing all previously set interrupt state set via
1505 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1510 * Bits 0-63: Reserved
1515 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1516 SpaprMachineState
*spapr
,
1517 target_ulong opcode
,
1520 SpaprXive
*xive
= spapr
->xive
;
1521 target_ulong flags
= args
[0];
1523 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1531 device_reset(DEVICE(xive
));
1533 if (kvm_irqchip_in_kernel()) {
1534 Error
*local_err
= NULL
;
1536 kvmppc_xive_reset(xive
, &local_err
);
1538 error_report_err(local_err
);
1545 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1547 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1548 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1549 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1550 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1551 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1552 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1553 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1554 h_int_set_os_reporting_line
);
1555 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1556 h_int_get_os_reporting_line
);
1557 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1558 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1559 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1562 void spapr_dt_xive(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1565 SpaprXive
*xive
= spapr
->xive
;
1567 uint64_t timas
[2 * 2];
1568 /* Interrupt number ranges for the IPIs */
1569 uint32_t lisn_ranges
[] = {
1571 cpu_to_be32(nr_servers
),
1574 * EQ size - the sizes of pages supported by the system 4K, 64K,
1575 * 2M, 16M. We only advertise 64K for the moment.
1577 uint32_t eq_sizes
[] = {
1578 cpu_to_be32(16), /* 64K */
1581 * The following array is in sync with the reserved priorities
1582 * defined by the 'spapr_xive_priority_is_reserved' routine.
1584 uint32_t plat_res_int_priorities
[] = {
1585 cpu_to_be32(7), /* start */
1586 cpu_to_be32(0xf8), /* count */
1589 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1590 timas
[0] = cpu_to_be64(xive
->tm_base
+
1591 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1592 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1593 timas
[2] = cpu_to_be64(xive
->tm_base
+
1594 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1595 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1597 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
1599 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1600 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1602 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1603 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1605 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1606 sizeof(lisn_ranges
)));
1608 /* For Linux to link the LSIs to the interrupt controller. */
1609 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1610 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1613 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1614 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1617 * The "ibm,plat-res-int-priorities" property defines the priority
1618 * ranges reserved by the hypervisor
1620 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1621 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));