target/xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \
  29               a1, a2, a3, a4, a5, a6) { \
  30     .targno = (no), \
  31     .flags = (fl), \
  32     .type = (typ), \
  33     .group = (grp), \
  34     .size = (sz), \
  35 },
  36 #define XTREG_END { .targno = -1 },
  37
  38 #ifndef XCHAL_HAVE_DEPBITS
  39 #define XCHAL_HAVE_DEPBITS 0
  40 #endif
  41
  42 #ifndef XCHAL_HAVE_DIV32
  43 #define XCHAL_HAVE_DIV32 0
  44 #endif
  45
  46 #ifndef XCHAL_UNALIGNED_LOAD_HW
  47 #define XCHAL_UNALIGNED_LOAD_HW 0
  48 #endif
  49
  50 #ifndef XCHAL_HAVE_VECBASE
  51 #define XCHAL_HAVE_VECBASE 0
  52 #define XCHAL_VECBASE_RESET_VADDR 0
  53 #endif
  54
  55 #ifndef XCHAL_RESET_VECTOR0_VADDR
  56 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
  57 #endif
  58
  59 #ifndef XCHAL_RESET_VECTOR1_VADDR
  60 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
  61 #endif
  62
  63 #ifndef XCHAL_HW_MIN_VERSION
  64 #define XCHAL_HW_MIN_VERSION 0
  65 #endif
  66
  67 #ifndef XCHAL_LOOP_BUFFER_SIZE
  68 #define XCHAL_LOOP_BUFFER_SIZE 0
  69 #endif
  70
  71 #ifndef XCHAL_HAVE_EXTERN_REGS
  72 #define XCHAL_HAVE_EXTERN_REGS 0
  73 #endif
  74
  75 #ifndef XCHAL_HAVE_MPU
  76 #define XCHAL_HAVE_MPU 0
  77 #endif
  78
  79 #ifndef XCHAL_HAVE_EXCLUSIVE
  80 #define XCHAL_HAVE_EXCLUSIVE 0
  81 #endif
  82
  83 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  84
  85 #define XTENSA_OPTIONS ( \
  86     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  87     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  88     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  89     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  90     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  91     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  92     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  93     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  94     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  95     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  96     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  97     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  98     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  99     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
 100     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
 101     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
 102     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
 103     XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
 104                   XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
 105     XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
 106     /* Interrupts and exceptions */ \
 107     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
 108     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
 109     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
 110         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
 111     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
 112     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
 113         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
 114     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
 115     /* Local memory, TODO */ \
 116     XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
 117     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
 118             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
 119     XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
 120     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
 121             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
 122     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
 123     XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
 124                  XTENSA_OPTION_MEMORY_ECC_PARITY) | \
 125     /* Memory protection and translation */ \
 126     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
 127             XTENSA_OPTION_REGION_PROTECTION) | \
 128     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
 129             XTENSA_OPTION_REGION_TRANSLATION) | \
 130     XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \
 131     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
 132     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
 133     /* Other, TODO */ \
 134     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
 135     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
 136     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 137     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 138     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
 139     XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
 140
 141 #ifndef XCHAL_WINDOW_OF4_VECOFS
 142 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 143 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 144 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 145 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 146 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 147 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 148 #endif
 149
 150 #if XCHAL_HAVE_WINDOWED
 151 #define WINDOW_VECTORS \
 152    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 153        XCHAL_WINDOW_VECTORS_VADDR, \
 154    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 155        XCHAL_WINDOW_VECTORS_VADDR, \
 156    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 157        XCHAL_WINDOW_VECTORS_VADDR, \
 158    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 159        XCHAL_WINDOW_VECTORS_VADDR, \
 160    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 161        XCHAL_WINDOW_VECTORS_VADDR, \
 162    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 163        XCHAL_WINDOW_VECTORS_VADDR,
 164 #else
 165 #define WINDOW_VECTORS
 166 #endif
 167
 168 #define EXCEPTION_VECTORS { \
 169         [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
 170         [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
 171         WINDOW_VECTORS \
 172         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 173         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 174         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 175         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 176     }
 177
 178 #define INTERRUPT_VECTORS { \
 179         0, \
 180         0, \
 181         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 182         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 183         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 184         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 185         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 186         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 187     }
 188
 189 #define LEVEL_MASKS { \
 190         [1] = XCHAL_INTLEVEL1_MASK, \
 191         [2] = XCHAL_INTLEVEL2_MASK, \
 192         [3] = XCHAL_INTLEVEL3_MASK, \
 193         [4] = XCHAL_INTLEVEL4_MASK, \
 194         [5] = XCHAL_INTLEVEL5_MASK, \
 195         [6] = XCHAL_INTLEVEL6_MASK, \
 196         [7] = XCHAL_INTLEVEL7_MASK, \
 197     }
 198
 199 #define INTTYPE_MASKS { \
 200         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 201         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 202         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 203     }
 204
 205 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 206 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 207 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 208 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 209 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 210 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 211 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 212 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 213 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 214 #define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE
 215 #define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
 216 #define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
 217
 218
 219 #define INTERRUPT(i) { \
 220         .level = XCHAL_INT ## i ## _LEVEL, \
 221         .inttype = XCHAL_INT ## i ## _TYPE, \
 222     }
 223
 224 #define INTERRUPTS { \
 225         [0] = INTERRUPT(0), \
 226         [1] = INTERRUPT(1), \
 227         [2] = INTERRUPT(2), \
 228         [3] = INTERRUPT(3), \
 229         [4] = INTERRUPT(4), \
 230         [5] = INTERRUPT(5), \
 231         [6] = INTERRUPT(6), \
 232         [7] = INTERRUPT(7), \
 233         [8] = INTERRUPT(8), \
 234         [9] = INTERRUPT(9), \
 235         [10] = INTERRUPT(10), \
 236         [11] = INTERRUPT(11), \
 237         [12] = INTERRUPT(12), \
 238         [13] = INTERRUPT(13), \
 239         [14] = INTERRUPT(14), \
 240         [15] = INTERRUPT(15), \
 241         [16] = INTERRUPT(16), \
 242         [17] = INTERRUPT(17), \
 243         [18] = INTERRUPT(18), \
 244         [19] = INTERRUPT(19), \
 245         [20] = INTERRUPT(20), \
 246         [21] = INTERRUPT(21), \
 247         [22] = INTERRUPT(22), \
 248         [23] = INTERRUPT(23), \
 249         [24] = INTERRUPT(24), \
 250         [25] = INTERRUPT(25), \
 251         [26] = INTERRUPT(26), \
 252         [27] = INTERRUPT(27), \
 253         [28] = INTERRUPT(28), \
 254         [29] = INTERRUPT(29), \
 255         [30] = INTERRUPT(30), \
 256         [31] = INTERRUPT(31), \
 257     }
 258
 259 #define TIMERINTS { \
 260         [0] = XCHAL_TIMER0_INTERRUPT, \
 261         [1] = XCHAL_TIMER1_INTERRUPT, \
 262         [2] = XCHAL_TIMER2_INTERRUPT, \
 263     }
 264
 265 #define EXTINTS { \
 266         [0] = XCHAL_EXTINT0_NUM, \
 267         [1] = XCHAL_EXTINT1_NUM, \
 268         [2] = XCHAL_EXTINT2_NUM, \
 269         [3] = XCHAL_EXTINT3_NUM, \
 270         [4] = XCHAL_EXTINT4_NUM, \
 271         [5] = XCHAL_EXTINT5_NUM, \
 272         [6] = XCHAL_EXTINT6_NUM, \
 273         [7] = XCHAL_EXTINT7_NUM, \
 274         [8] = XCHAL_EXTINT8_NUM, \
 275         [9] = XCHAL_EXTINT9_NUM, \
 276         [10] = XCHAL_EXTINT10_NUM, \
 277         [11] = XCHAL_EXTINT11_NUM, \
 278         [12] = XCHAL_EXTINT12_NUM, \
 279         [13] = XCHAL_EXTINT13_NUM, \
 280         [14] = XCHAL_EXTINT14_NUM, \
 281         [15] = XCHAL_EXTINT15_NUM, \
 282         [16] = XCHAL_EXTINT16_NUM, \
 283         [17] = XCHAL_EXTINT17_NUM, \
 284         [18] = XCHAL_EXTINT18_NUM, \
 285         [19] = XCHAL_EXTINT19_NUM, \
 286         [20] = XCHAL_EXTINT20_NUM, \
 287         [21] = XCHAL_EXTINT21_NUM, \
 288         [22] = XCHAL_EXTINT22_NUM, \
 289         [23] = XCHAL_EXTINT23_NUM, \
 290         [24] = XCHAL_EXTINT24_NUM, \
 291         [25] = XCHAL_EXTINT25_NUM, \
 292         [26] = XCHAL_EXTINT26_NUM, \
 293         [27] = XCHAL_EXTINT27_NUM, \
 294         [28] = XCHAL_EXTINT28_NUM, \
 295         [29] = XCHAL_EXTINT29_NUM, \
 296         [30] = XCHAL_EXTINT30_NUM, \
 297         [31] = XCHAL_EXTINT31_NUM, \
 298     }
 299
 300 #define EXCEPTIONS_SECTION \
 301     .excm_level = XCHAL_EXCM_LEVEL, \
 302     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 303     .exception_vector = EXCEPTION_VECTORS
 304
 305 #define INTERRUPTS_SECTION \
 306     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 307     .nlevel = XCHAL_NUM_INTLEVELS, \
 308     .interrupt_vector = INTERRUPT_VECTORS, \
 309     .level_mask = LEVEL_MASKS, \
 310     .inttype_mask = INTTYPE_MASKS, \
 311     .interrupt = INTERRUPTS, \
 312     .nccompare = XCHAL_NUM_TIMERS, \
 313     .timerint = TIMERINTS, \
 314     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 315     .extint = EXTINTS
 316
 317 #if XCHAL_HAVE_PTP_MMU
 318
 319 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 320         .nways = ways, \
 321         .way_size = { \
 322             (refill_way_size), (refill_way_size), \
 323             (refill_way_size), (refill_way_size), \
 324             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 325         }, \
 326         .varway56 = (way56), \
 327         .nrefillentries = (refill_way_size) * 4, \
 328     }
 329
 330 #define ITLB(varway56) \
 331     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 332
 333 #define DTLB(varway56) \
 334     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 335
 336 #define TLB_SECTION \
 337     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 338     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 339
 340 #ifndef XCHAL_SYSROM0_PADDR
 341 #define XCHAL_SYSROM0_PADDR 0xfe000000
 342 #define XCHAL_SYSROM0_SIZE  0x02000000
 343 #endif
 344
 345 #ifndef XCHAL_SYSRAM0_PADDR
 346 #define XCHAL_SYSRAM0_PADDR 0x00000000
 347 #define XCHAL_SYSRAM0_SIZE  0x08000000
 348 #endif
 349
 350 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 351
 352 #define TLB_TEMPLATE { \
 353         .nways = 1, \
 354         .way_size = { \
 355             8, \
 356         } \
 357     }
 358
 359 #define TLB_SECTION \
 360     .itlb = TLB_TEMPLATE, \
 361     .dtlb = TLB_TEMPLATE
 362
 363 #ifndef XCHAL_SYSROM0_PADDR
 364 #define XCHAL_SYSROM0_PADDR 0x50000000
 365 #define XCHAL_SYSROM0_SIZE  0x04000000
 366 #endif
 367
 368 #ifndef XCHAL_SYSRAM0_PADDR
 369 #define XCHAL_SYSRAM0_PADDR 0x60000000
 370 #define XCHAL_SYSRAM0_SIZE  0x04000000
 371 #endif
 372
 373 #elif XCHAL_HAVE_MPU
 374
 375 #ifndef XTENSA_MPU_BG_MAP
 376 #ifdef XCHAL_MPU_BACKGROUND_MAP
 377 #define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \
 378     { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), },
 379
 380 #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
 381     XCHAL_MPU_BACKGROUND_MAP(0) \
 382 }
 383
 384 #define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES
 385 #else
 386 #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
 387     { .vaddr = 0, .attr = 0x00006700, }, \
 388 }
 389
 390 #define XTENSA_MPU_BG_MAP_ENTRIES 1
 391 #endif
 392 #endif
 393
 394 #define TLB_SECTION \
 395     .mpu_align = XCHAL_MPU_ALIGN, \
 396     .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \
 397     .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \
 398     .mpu_bg = XTENSA_MPU_BG_MAP
 399
 400 #ifndef XCHAL_SYSROM0_PADDR
 401 #define XCHAL_SYSROM0_PADDR 0x50000000
 402 #define XCHAL_SYSROM0_SIZE  0x04000000
 403 #endif
 404
 405 #ifndef XCHAL_SYSRAM0_PADDR
 406 #define XCHAL_SYSRAM0_PADDR 0x60000000
 407 #define XCHAL_SYSRAM0_SIZE  0x04000000
 408 #endif
 409
 410 #else
 411
 412 #ifndef XCHAL_SYSROM0_PADDR
 413 #define XCHAL_SYSROM0_PADDR 0x50000000
 414 #define XCHAL_SYSROM0_SIZE  0x04000000
 415 #endif
 416
 417 #ifndef XCHAL_SYSRAM0_PADDR
 418 #define XCHAL_SYSRAM0_PADDR 0x60000000
 419 #define XCHAL_SYSRAM0_SIZE  0x04000000
 420 #endif
 421
 422 #endif
 423
 424 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 425 #define REGISTER_CORE(core) \
 426     static void __attribute__((constructor)) register_core(void) \
 427     { \
 428         static XtensaConfigList node = { \
 429             .config = &core, \
 430         }; \
 431         xtensa_register_core(&node); \
 432     }
 433 #else
 434 #define REGISTER_CORE(core)
 435 #endif
 436
 437 #define DEBUG_SECTION \
 438     .debug_level = XCHAL_DEBUGLEVEL, \
 439     .nibreak = XCHAL_NUM_IBREAK, \
 440     .ndbreak = XCHAL_NUM_DBREAK
 441
 442 #define CACHE_SECTION \
 443     .icache_ways = XCHAL_ICACHE_WAYS, \
 444     .dcache_ways = XCHAL_DCACHE_WAYS, \
 445     .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
 446     .memctl_mask = \
 447         (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
 448         (XCHAL_DCACHE_SIZE ? \
 449          MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
 450         MEMCTL_ISNP | MEMCTL_DSNP | \
 451         (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
 452
 453 #define MEM_LOCATION(name, n) \
 454     { \
 455         .addr = XCHAL_ ## name ## n ## _PADDR, \
 456         .size = XCHAL_ ## name ## n ## _SIZE, \
 457     }
 458
 459 #define MEM_SECTIONS(name) \
 460     MEM_LOCATION(name, 0), \
 461     MEM_LOCATION(name, 1), \
 462     MEM_LOCATION(name, 2), \
 463     MEM_LOCATION(name, 3)
 464
 465 #define MEM_SECTION(name) \
 466     .num = XCHAL_NUM_ ## name, \
 467     .location = { \
 468         MEM_SECTIONS(name) \
 469     }
 470
 471 #define SYSMEM_SECTION(name) \
 472     .num = 1, \
 473     .location = { \
 474         { \
 475             .addr = XCHAL_ ## name ## 0_PADDR, \
 476             .size = XCHAL_ ## name ## 0_SIZE, \
 477         } \
 478     }
 479
 480 #define LOCAL_MEMORIES_SECTION \
 481     .instrom = { \
 482         MEM_SECTION(INSTROM) \
 483     }, \
 484     .instram = { \
 485         MEM_SECTION(INSTRAM) \
 486     }, \
 487     .datarom = { \
 488         MEM_SECTION(DATAROM) \
 489     }, \
 490     .dataram = { \
 491         MEM_SECTION(DATARAM) \
 492     }, \
 493     .sysrom = { \
 494         SYSMEM_SECTION(SYSROM) \
 495     }, \
 496     .sysram = { \
 497         SYSMEM_SECTION(SYSRAM) \
 498     }
 499
 500 #define CONFIG_SECTION \
 501     .configid = { \
 502         XCHAL_HW_CONFIGID0, \
 503         XCHAL_HW_CONFIGID1, \
 504     }
 505
 506 #define DEFAULT_SECTIONS \
 507     .options = XTENSA_OPTIONS, \
 508     .nareg = XCHAL_NUM_AREGS, \
 509     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 510     .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
 511     .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
 512     EXCEPTIONS_SECTION, \
 513     INTERRUPTS_SECTION, \
 514     TLB_SECTION, \
 515     DEBUG_SECTION, \
 516     CACHE_SECTION, \
 517     LOCAL_MEMORIES_SECTION, \
 518     CONFIG_SECTION
 519
 520
 521 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 522 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 523 #endif
 524 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 525 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 526 #endif
 527 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 528 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 529 #endif
 530 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 531 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 532 #endif
 533 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 534 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 535 #endif
 536 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 537 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 538 #endif
 539
 540
 541 #if XCHAL_NUM_INTERRUPTS <= 0
 542 #define XCHAL_INT0_LEVEL 0
 543 #define XCHAL_INT0_TYPE 0
 544 #endif
 545 #if XCHAL_NUM_INTERRUPTS <= 1
 546 #define XCHAL_INT1_LEVEL 0
 547 #define XCHAL_INT1_TYPE 0
 548 #endif
 549 #if XCHAL_NUM_INTERRUPTS <= 2
 550 #define XCHAL_INT2_LEVEL 0
 551 #define XCHAL_INT2_TYPE 0
 552 #endif
 553 #if XCHAL_NUM_INTERRUPTS <= 3
 554 #define XCHAL_INT3_LEVEL 0
 555 #define XCHAL_INT3_TYPE 0
 556 #endif
 557 #if XCHAL_NUM_INTERRUPTS <= 4
 558 #define XCHAL_INT4_LEVEL 0
 559 #define XCHAL_INT4_TYPE 0
 560 #endif
 561 #if XCHAL_NUM_INTERRUPTS <= 5
 562 #define XCHAL_INT5_LEVEL 0
 563 #define XCHAL_INT5_TYPE 0
 564 #endif
 565 #if XCHAL_NUM_INTERRUPTS <= 6
 566 #define XCHAL_INT6_LEVEL 0
 567 #define XCHAL_INT6_TYPE 0
 568 #endif
 569 #if XCHAL_NUM_INTERRUPTS <= 7
 570 #define XCHAL_INT7_LEVEL 0
 571 #define XCHAL_INT7_TYPE 0
 572 #endif
 573 #if XCHAL_NUM_INTERRUPTS <= 8
 574 #define XCHAL_INT8_LEVEL 0
 575 #define XCHAL_INT8_TYPE 0
 576 #endif
 577 #if XCHAL_NUM_INTERRUPTS <= 9
 578 #define XCHAL_INT9_LEVEL 0
 579 #define XCHAL_INT9_TYPE 0
 580 #endif
 581 #if XCHAL_NUM_INTERRUPTS <= 10
 582 #define XCHAL_INT10_LEVEL 0
 583 #define XCHAL_INT10_TYPE 0
 584 #endif
 585 #if XCHAL_NUM_INTERRUPTS <= 11
 586 #define XCHAL_INT11_LEVEL 0
 587 #define XCHAL_INT11_TYPE 0
 588 #endif
 589 #if XCHAL_NUM_INTERRUPTS <= 12
 590 #define XCHAL_INT12_LEVEL 0
 591 #define XCHAL_INT12_TYPE 0
 592 #endif
 593 #if XCHAL_NUM_INTERRUPTS <= 13
 594 #define XCHAL_INT13_LEVEL 0
 595 #define XCHAL_INT13_TYPE 0
 596 #endif
 597 #if XCHAL_NUM_INTERRUPTS <= 14
 598 #define XCHAL_INT14_LEVEL 0
 599 #define XCHAL_INT14_TYPE 0
 600 #endif
 601 #if XCHAL_NUM_INTERRUPTS <= 15
 602 #define XCHAL_INT15_LEVEL 0
 603 #define XCHAL_INT15_TYPE 0
 604 #endif
 605 #if XCHAL_NUM_INTERRUPTS <= 16
 606 #define XCHAL_INT16_LEVEL 0
 607 #define XCHAL_INT16_TYPE 0
 608 #endif
 609 #if XCHAL_NUM_INTERRUPTS <= 17
 610 #define XCHAL_INT17_LEVEL 0
 611 #define XCHAL_INT17_TYPE 0
 612 #endif
 613 #if XCHAL_NUM_INTERRUPTS <= 18
 614 #define XCHAL_INT18_LEVEL 0
 615 #define XCHAL_INT18_TYPE 0
 616 #endif
 617 #if XCHAL_NUM_INTERRUPTS <= 19
 618 #define XCHAL_INT19_LEVEL 0
 619 #define XCHAL_INT19_TYPE 0
 620 #endif
 621 #if XCHAL_NUM_INTERRUPTS <= 20
 622 #define XCHAL_INT20_LEVEL 0
 623 #define XCHAL_INT20_TYPE 0
 624 #endif
 625 #if XCHAL_NUM_INTERRUPTS <= 21
 626 #define XCHAL_INT21_LEVEL 0
 627 #define XCHAL_INT21_TYPE 0
 628 #endif
 629 #if XCHAL_NUM_INTERRUPTS <= 22
 630 #define XCHAL_INT22_LEVEL 0
 631 #define XCHAL_INT22_TYPE 0
 632 #endif
 633 #if XCHAL_NUM_INTERRUPTS <= 23
 634 #define XCHAL_INT23_LEVEL 0
 635 #define XCHAL_INT23_TYPE 0
 636 #endif
 637 #if XCHAL_NUM_INTERRUPTS <= 24
 638 #define XCHAL_INT24_LEVEL 0
 639 #define XCHAL_INT24_TYPE 0
 640 #endif
 641 #if XCHAL_NUM_INTERRUPTS <= 25
 642 #define XCHAL_INT25_LEVEL 0
 643 #define XCHAL_INT25_TYPE 0
 644 #endif
 645 #if XCHAL_NUM_INTERRUPTS <= 26
 646 #define XCHAL_INT26_LEVEL 0
 647 #define XCHAL_INT26_TYPE 0
 648 #endif
 649 #if XCHAL_NUM_INTERRUPTS <= 27
 650 #define XCHAL_INT27_LEVEL 0
 651 #define XCHAL_INT27_TYPE 0
 652 #endif
 653 #if XCHAL_NUM_INTERRUPTS <= 28
 654 #define XCHAL_INT28_LEVEL 0
 655 #define XCHAL_INT28_TYPE 0
 656 #endif
 657 #if XCHAL_NUM_INTERRUPTS <= 29
 658 #define XCHAL_INT29_LEVEL 0
 659 #define XCHAL_INT29_TYPE 0
 660 #endif
 661 #if XCHAL_NUM_INTERRUPTS <= 30
 662 #define XCHAL_INT30_LEVEL 0
 663 #define XCHAL_INT30_TYPE 0
 664 #endif
 665 #if XCHAL_NUM_INTERRUPTS <= 31
 666 #define XCHAL_INT31_LEVEL 0
 667 #define XCHAL_INT31_TYPE 0
 668 #endif
 669
 670
 671 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 672 #define XCHAL_EXTINT0_NUM 0
 673 #endif
 674 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 675 #define XCHAL_EXTINT1_NUM 0
 676 #endif
 677 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 678 #define XCHAL_EXTINT2_NUM 0
 679 #endif
 680 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 681 #define XCHAL_EXTINT3_NUM 0
 682 #endif
 683 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 684 #define XCHAL_EXTINT4_NUM 0
 685 #endif
 686 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 687 #define XCHAL_EXTINT5_NUM 0
 688 #endif
 689 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 690 #define XCHAL_EXTINT6_NUM 0
 691 #endif
 692 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 693 #define XCHAL_EXTINT7_NUM 0
 694 #endif
 695 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 696 #define XCHAL_EXTINT8_NUM 0
 697 #endif
 698 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 699 #define XCHAL_EXTINT9_NUM 0
 700 #endif
 701 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 702 #define XCHAL_EXTINT10_NUM 0
 703 #endif
 704 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 705 #define XCHAL_EXTINT11_NUM 0
 706 #endif
 707 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 708 #define XCHAL_EXTINT12_NUM 0
 709 #endif
 710 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 711 #define XCHAL_EXTINT13_NUM 0
 712 #endif
 713 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 714 #define XCHAL_EXTINT14_NUM 0
 715 #endif
 716 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 717 #define XCHAL_EXTINT15_NUM 0
 718 #endif
 719 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 720 #define XCHAL_EXTINT16_NUM 0
 721 #endif
 722 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 723 #define XCHAL_EXTINT17_NUM 0
 724 #endif
 725 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 726 #define XCHAL_EXTINT18_NUM 0
 727 #endif
 728 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 729 #define XCHAL_EXTINT19_NUM 0
 730 #endif
 731 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 732 #define XCHAL_EXTINT20_NUM 0
 733 #endif
 734 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 735 #define XCHAL_EXTINT21_NUM 0
 736 #endif
 737 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 738 #define XCHAL_EXTINT22_NUM 0
 739 #endif
 740 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 741 #define XCHAL_EXTINT23_NUM 0
 742 #endif
 743 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 744 #define XCHAL_EXTINT24_NUM 0
 745 #endif
 746 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 747 #define XCHAL_EXTINT25_NUM 0
 748 #endif
 749 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 750 #define XCHAL_EXTINT26_NUM 0
 751 #endif
 752 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 753 #define XCHAL_EXTINT27_NUM 0
 754 #endif
 755 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 756 #define XCHAL_EXTINT28_NUM 0
 757 #endif
 758 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 759 #define XCHAL_EXTINT29_NUM 0
 760 #endif
 761 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 762 #define XCHAL_EXTINT30_NUM 0
 763 #endif
 764 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 765 #define XCHAL_EXTINT31_NUM 0
 766 #endif
 767
 768
 769 #define XTHAL_TIMER_UNCONFIGURED 0
 770
 771 #if XCHAL_NUM_INSTROM < 1
 772 #define XCHAL_INSTROM0_PADDR 0
 773 #define XCHAL_INSTROM0_SIZE 0
 774 #endif
 775 #if XCHAL_NUM_INSTROM < 2
 776 #define XCHAL_INSTROM1_PADDR 0
 777 #define XCHAL_INSTROM1_SIZE 0
 778 #endif
 779 #if XCHAL_NUM_INSTROM < 3
 780 #define XCHAL_INSTROM2_PADDR 0
 781 #define XCHAL_INSTROM2_SIZE 0
 782 #endif
 783 #if XCHAL_NUM_INSTROM < 4
 784 #define XCHAL_INSTROM3_PADDR 0
 785 #define XCHAL_INSTROM3_SIZE 0
 786 #endif
 787 #if XCHAL_NUM_INSTROM > MAX_NMEMORY
 788 #error XCHAL_NUM_INSTROM > MAX_NMEMORY
 789 #endif
 790
 791 #if XCHAL_NUM_INSTRAM < 1
 792 #define XCHAL_INSTRAM0_PADDR 0
 793 #define XCHAL_INSTRAM0_SIZE 0
 794 #endif
 795 #if XCHAL_NUM_INSTRAM < 2
 796 #define XCHAL_INSTRAM1_PADDR 0
 797 #define XCHAL_INSTRAM1_SIZE 0
 798 #endif
 799 #if XCHAL_NUM_INSTRAM < 3
 800 #define XCHAL_INSTRAM2_PADDR 0
 801 #define XCHAL_INSTRAM2_SIZE 0
 802 #endif
 803 #if XCHAL_NUM_INSTRAM < 4
 804 #define XCHAL_INSTRAM3_PADDR 0
 805 #define XCHAL_INSTRAM3_SIZE 0
 806 #endif
 807 #if XCHAL_NUM_INSTRAM > MAX_NMEMORY
 808 #error XCHAL_NUM_INSTRAM > MAX_NMEMORY
 809 #endif
 810
 811 #if XCHAL_NUM_DATAROM < 1
 812 #define XCHAL_DATAROM0_PADDR 0
 813 #define XCHAL_DATAROM0_SIZE 0
 814 #endif
 815 #if XCHAL_NUM_DATAROM < 2
 816 #define XCHAL_DATAROM1_PADDR 0
 817 #define XCHAL_DATAROM1_SIZE 0
 818 #endif
 819 #if XCHAL_NUM_DATAROM < 3
 820 #define XCHAL_DATAROM2_PADDR 0
 821 #define XCHAL_DATAROM2_SIZE 0
 822 #endif
 823 #if XCHAL_NUM_DATAROM < 4
 824 #define XCHAL_DATAROM3_PADDR 0
 825 #define XCHAL_DATAROM3_SIZE 0
 826 #endif
 827 #if XCHAL_NUM_DATAROM > MAX_NMEMORY
 828 #error XCHAL_NUM_DATAROM > MAX_NMEMORY
 829 #endif
 830
 831 #if XCHAL_NUM_DATARAM < 1
 832 #define XCHAL_DATARAM0_PADDR 0
 833 #define XCHAL_DATARAM0_SIZE 0
 834 #endif
 835 #if XCHAL_NUM_DATARAM < 2
 836 #define XCHAL_DATARAM1_PADDR 0
 837 #define XCHAL_DATARAM1_SIZE 0
 838 #endif
 839 #if XCHAL_NUM_DATARAM < 3
 840 #define XCHAL_DATARAM2_PADDR 0
 841 #define XCHAL_DATARAM2_SIZE 0
 842 #endif
 843 #if XCHAL_NUM_DATARAM < 4
 844 #define XCHAL_DATARAM3_PADDR 0
 845 #define XCHAL_DATARAM3_SIZE 0
 846 #endif
 847 #if XCHAL_NUM_DATARAM > MAX_NMEMORY
 848 #error XCHAL_NUM_DATARAM > MAX_NMEMORY
 849 #endif