hw/core/cpu-common.c

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/core/cpu.h"
  24 #include "sysemu/hw_accel.h"
  25 #include "qemu/notify.h"
  26 #include "qemu/log.h"
  27 #include "qemu/main-loop.h"
  28 #include "exec/log.h"
  29 #include "exec/cpu-common.h"
  30 #include "qemu/error-report.h"
  31 #include "qemu/qemu-print.h"
  32 #include "sysemu/tcg.h"
  33 #include "hw/boards.h"
  34 #include "hw/qdev-properties.h"
  35 #include "trace/trace-root.h"
  36 #include "qemu/plugin.h"
  37
  38 CPUState *cpu_by_arch_id(int64_t id)
  39 {
  40     CPUState *cpu;
  41
  42     CPU_FOREACH(cpu) {
  43         CPUClass *cc = CPU_GET_CLASS(cpu);
  44
  45         if (cc->get_arch_id(cpu) == id) {
  46             return cpu;
  47         }
  48     }
  49     return NULL;
  50 }
  51
  52 bool cpu_exists(int64_t id)
  53 {
  54     return !!cpu_by_arch_id(id);
  55 }
  56
  57 CPUState *cpu_create(const char *typename)
  58 {
  59     Error *err = NULL;
  60     CPUState *cpu = CPU(object_new(typename));
  61     if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
  62         error_report_err(err);
  63         object_unref(OBJECT(cpu));
  64         exit(EXIT_FAILURE);
  65     }
  66     return cpu;
  67 }
  68
  69 bool cpu_paging_enabled(const CPUState *cpu)
  70 {
  71     CPUClass *cc = CPU_GET_CLASS(cpu);
  72
  73     return cc->get_paging_enabled(cpu);
  74 }
  75
  76 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
  77 {
  78     return false;
  79 }
  80
  81 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
  82                             Error **errp)
  83 {
  84     CPUClass *cc = CPU_GET_CLASS(cpu);
  85
  86     cc->get_memory_mapping(cpu, list, errp);
  87 }
  88
  89 static void cpu_common_get_memory_mapping(CPUState *cpu,
  90                                           MemoryMappingList *list,
  91                                           Error **errp)
  92 {
  93     error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
  94 }
  95
  96 /* Resetting the IRQ comes from across the code base so we take the
  97  * BQL here if we need to.  cpu_interrupt assumes it is held.*/
  98 void cpu_reset_interrupt(CPUState *cpu, int mask)
  99 {
 100     bool need_lock = !qemu_mutex_iothread_locked();
 101
 102     if (need_lock) {
 103         qemu_mutex_lock_iothread();
 104     }
 105     cpu->interrupt_request &= ~mask;
 106     if (need_lock) {
 107         qemu_mutex_unlock_iothread();
 108     }
 109 }
 110
 111 void cpu_exit(CPUState *cpu)
 112 {
 113     qatomic_set(&cpu->exit_request, 1);
 114     /* Ensure cpu_exec will see the exit request after TCG has exited.  */
 115     smp_wmb();
 116     qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
 117 }
 118
 119 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 120                              void *opaque)
 121 {
 122     CPUClass *cc = CPU_GET_CLASS(cpu);
 123
 124     return (*cc->write_elf32_qemunote)(f, cpu, opaque);
 125 }
 126
 127 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
 128                                            CPUState *cpu, void *opaque)
 129 {
 130     return 0;
 131 }
 132
 133 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 134                          int cpuid, void *opaque)
 135 {
 136     CPUClass *cc = CPU_GET_CLASS(cpu);
 137
 138     return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
 139 }
 140
 141 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
 142                                        CPUState *cpu, int cpuid,
 143                                        void *opaque)
 144 {
 145     return -1;
 146 }
 147
 148 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 149                              void *opaque)
 150 {
 151     CPUClass *cc = CPU_GET_CLASS(cpu);
 152
 153     return (*cc->write_elf64_qemunote)(f, cpu, opaque);
 154 }
 155
 156 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
 157                                            CPUState *cpu, void *opaque)
 158 {
 159     return 0;
 160 }
 161
 162 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 163                          int cpuid, void *opaque)
 164 {
 165     CPUClass *cc = CPU_GET_CLASS(cpu);
 166
 167     return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
 168 }
 169
 170 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
 171                                        CPUState *cpu, int cpuid,
 172                                        void *opaque)
 173 {
 174     return -1;
 175 }
 176
 177
 178 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
 179 {
 180     return 0;
 181 }
 182
 183 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
 184 {
 185     return 0;
 186 }
 187
 188 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
 189 {
 190     CPUClass *cc = CPU_GET_CLASS(cpu);
 191
 192     if (cc->dump_state) {
 193         cpu_synchronize_state(cpu);
 194         cc->dump_state(cpu, f, flags);
 195     }
 196 }
 197
 198 void cpu_dump_statistics(CPUState *cpu, int flags)
 199 {
 200     CPUClass *cc = CPU_GET_CLASS(cpu);
 201
 202     if (cc->dump_statistics) {
 203         cc->dump_statistics(cpu, flags);
 204     }
 205 }
 206
 207 void cpu_reset(CPUState *cpu)
 208 {
 209     device_cold_reset(DEVICE(cpu));
 210
 211     trace_guest_cpu_reset(cpu);
 212 }
 213
 214 static void cpu_common_reset(DeviceState *dev)
 215 {
 216     CPUState *cpu = CPU(dev);
 217     CPUClass *cc = CPU_GET_CLASS(cpu);
 218
 219     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 220         qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
 221         log_cpu_state(cpu, cc->reset_dump_flags);
 222     }
 223
 224     cpu->interrupt_request = 0;
 225     cpu->halted = cpu->start_powered_off;
 226     cpu->mem_io_pc = 0;
 227     cpu->icount_extra = 0;
 228     qatomic_set(&cpu->icount_decr_ptr->u32, 0);
 229     cpu->can_do_io = 1;
 230     cpu->exception_index = -1;
 231     cpu->crash_occurred = false;
 232     cpu->cflags_next_tb = -1;
 233
 234     if (tcg_enabled()) {
 235         cpu_tb_jmp_cache_clear(cpu);
 236
 237         tcg_flush_softmmu_tlb(cpu);
 238     }
 239 }
 240
 241 static bool cpu_common_has_work(CPUState *cs)
 242 {
 243     return false;
 244 }
 245
 246 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
 247 {
 248     CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
 249
 250     assert(cpu_model && cc->class_by_name);
 251     return cc->class_by_name(cpu_model);
 252 }
 253
 254 static void cpu_common_parse_features(const char *typename, char *features,
 255                                       Error **errp)
 256 {
 257     char *val;
 258     static bool cpu_globals_initialized;
 259     /* Single "key=value" string being parsed */
 260     char *featurestr = features ? strtok(features, ",") : NULL;
 261
 262     /* should be called only once, catch invalid users */
 263     assert(!cpu_globals_initialized);
 264     cpu_globals_initialized = true;
 265
 266     while (featurestr) {
 267         val = strchr(featurestr, '=');
 268         if (val) {
 269             GlobalProperty *prop = g_new0(typeof(*prop), 1);
 270             *val = 0;
 271             val++;
 272             prop->driver = typename;
 273             prop->property = g_strdup(featurestr);
 274             prop->value = g_strdup(val);
 275             qdev_prop_register_global(prop);
 276         } else {
 277             error_setg(errp, "Expected key=value format, found %s.",
 278                        featurestr);
 279             return;
 280         }
 281         featurestr = strtok(NULL, ",");
 282     }
 283 }
 284
 285 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
 286 {
 287     CPUState *cpu = CPU(dev);
 288     Object *machine = qdev_get_machine();
 289
 290     /* qdev_get_machine() can return something that's not TYPE_MACHINE
 291      * if this is one of the user-only emulators; in that case there's
 292      * no need to check the ignore_memory_transaction_failures board flag.
 293      */
 294     if (object_dynamic_cast(machine, TYPE_MACHINE)) {
 295         ObjectClass *oc = object_get_class(machine);
 296         MachineClass *mc = MACHINE_CLASS(oc);
 297
 298         if (mc) {
 299             cpu->ignore_memory_transaction_failures =
 300                 mc->ignore_memory_transaction_failures;
 301         }
 302     }
 303
 304     if (dev->hotplugged) {
 305         cpu_synchronize_post_init(cpu);
 306         cpu_resume(cpu);
 307     }
 308
 309     /* NOTE: latest generic point where the cpu is fully realized */
 310     trace_init_vcpu(cpu);
 311 }
 312
 313 static void cpu_common_unrealizefn(DeviceState *dev)
 314 {
 315     CPUState *cpu = CPU(dev);
 316
 317     /* NOTE: latest generic point before the cpu is fully unrealized */
 318     trace_fini_vcpu(cpu);
 319     cpu_exec_unrealizefn(cpu);
 320 }
 321
 322 static void cpu_common_initfn(Object *obj)
 323 {
 324     CPUState *cpu = CPU(obj);
 325     CPUClass *cc = CPU_GET_CLASS(obj);
 326
 327     cpu->cpu_index = UNASSIGNED_CPU_INDEX;
 328     cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
 329     cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
 330     /* *-user doesn't have configurable SMP topology */
 331     /* the default value is changed by qemu_init_vcpu() for softmmu */
 332     cpu->nr_cores = 1;
 333     cpu->nr_threads = 1;
 334
 335     qemu_mutex_init(&cpu->work_mutex);
 336     QSIMPLEQ_INIT(&cpu->work_list);
 337     QTAILQ_INIT(&cpu->breakpoints);
 338     QTAILQ_INIT(&cpu->watchpoints);
 339
 340     cpu_exec_initfn(cpu);
 341 }
 342
 343 static void cpu_common_finalize(Object *obj)
 344 {
 345     CPUState *cpu = CPU(obj);
 346
 347     qemu_mutex_destroy(&cpu->work_mutex);
 348 }
 349
 350 static int64_t cpu_common_get_arch_id(CPUState *cpu)
 351 {
 352     return cpu->cpu_index;
 353 }
 354
 355 static Property cpu_common_props[] = {
 356 #ifndef CONFIG_USER_ONLY
 357     /* Create a memory property for softmmu CPU object,
 358      * so users can wire up its memory. (This can't go in hw/core/cpu.c
 359      * because that file is compiled only once for both user-mode
 360      * and system builds.) The default if no link is set up is to use
 361      * the system address space.
 362      */
 363     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 364                      MemoryRegion *),
 365 #endif
 366     DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 367     DEFINE_PROP_END_OF_LIST(),
 368 };
 369
 370 static void cpu_class_init(ObjectClass *klass, void *data)
 371 {
 372     DeviceClass *dc = DEVICE_CLASS(klass);
 373     CPUClass *k = CPU_CLASS(klass);
 374
 375     k->parse_features = cpu_common_parse_features;
 376     k->get_arch_id = cpu_common_get_arch_id;
 377     k->has_work = cpu_common_has_work;
 378     k->get_paging_enabled = cpu_common_get_paging_enabled;
 379     k->get_memory_mapping = cpu_common_get_memory_mapping;
 380     k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
 381     k->write_elf32_note = cpu_common_write_elf32_note;
 382     k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
 383     k->write_elf64_note = cpu_common_write_elf64_note;
 384     k->gdb_read_register = cpu_common_gdb_read_register;
 385     k->gdb_write_register = cpu_common_gdb_write_register;
 386     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 387     dc->realize = cpu_common_realizefn;
 388     dc->unrealize = cpu_common_unrealizefn;
 389     dc->reset = cpu_common_reset;
 390     device_class_set_props(dc, cpu_common_props);
 391     /*
 392      * Reason: CPUs still need special care by board code: wiring up
 393      * IRQs, adding reset handlers, halting non-first CPUs, ...
 394      */
 395     dc->user_creatable = false;
 396 }
 397
 398 static const TypeInfo cpu_type_info = {
 399     .name = TYPE_CPU,
 400     .parent = TYPE_DEVICE,
 401     .instance_size = sizeof(CPUState),
 402     .instance_init = cpu_common_initfn,
 403     .instance_finalize = cpu_common_finalize,
 404     .abstract = true,
 405     .class_size = sizeof(CPUClass),
 406     .class_init = cpu_class_init,
 407 };
 408
 409 static void cpu_register_types(void)
 410 {
 411     type_register_static(&cpu_type_info);
 412 }
 413
 414 type_init(cpu_register_types)