pci_bridge: upper 32 bit are long registers
[qemu/ar7.git] / cache-utils.h
blob2c57f78fc19984c0ecd79d87b0ce1cee3fa34312
1 #ifndef QEMU_CACHE_UTILS_H
2 #define QEMU_CACHE_UTILS_H
4 #if defined(_ARCH_PPC)
6 #include <stdint.h> /* uintptr_t */
8 struct qemu_cache_conf {
9 unsigned long dcache_bsize;
10 unsigned long icache_bsize;
13 extern struct qemu_cache_conf qemu_cache_conf;
15 void qemu_cache_utils_init(char **envp);
17 /* mildly adjusted code from tcg-dyngen.c */
18 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
20 unsigned long p, start1, stop1;
21 unsigned long dsize = qemu_cache_conf.dcache_bsize;
22 unsigned long isize = qemu_cache_conf.icache_bsize;
24 start1 = start & ~(dsize - 1);
25 stop1 = (stop + dsize - 1) & ~(dsize - 1);
26 for (p = start1; p < stop1; p += dsize) {
27 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
29 asm volatile ("sync" : : : "memory");
31 start &= start & ~(isize - 1);
32 stop1 = (stop + isize - 1) & ~(isize - 1);
33 for (p = start1; p < stop1; p += isize) {
34 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
36 asm volatile ("sync" : : : "memory");
37 asm volatile ("isync" : : : "memory");
40 #else
41 #define qemu_cache_utils_init(envp) do { (void) (envp); } while (0)
42 #endif
44 #endif /* QEMU_CACHE_UTILS_H */