1 /* Support for generating ACPI tables and passing them to Guests
3 * ARM virt ACPI generation
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
9 * Author: Michael S. Tsirkin <mst@redhat.com>
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu-common.h"
32 #include "qemu/bitmap.h"
35 #include "target/arm/cpu.h"
36 #include "hw/acpi/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/pci/pcie_host.h"
44 #include "hw/pci/pci.h"
45 #include "hw/arm/virt.h"
46 #include "sysemu/numa.h"
49 #define ARM_SPI_BASE 32
50 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
52 static void acpi_dsdt_add_cpus(Aml
*scope
, int smp_cpus
)
56 for (i
= 0; i
< smp_cpus
; i
++) {
57 Aml
*dev
= aml_device("C%.03X", i
);
58 aml_append(dev
, aml_name_decl("_HID", aml_string("ACPI0007")));
59 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
60 aml_append(scope
, dev
);
64 static void acpi_dsdt_add_uart(Aml
*scope
, const MemMapEntry
*uart_memmap
,
67 Aml
*dev
= aml_device("COM0");
68 aml_append(dev
, aml_name_decl("_HID", aml_string("ARMH0011")));
69 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
71 Aml
*crs
= aml_resource_template();
72 aml_append(crs
, aml_memory32_fixed(uart_memmap
->base
,
73 uart_memmap
->size
, AML_READ_WRITE
));
75 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
76 AML_EXCLUSIVE
, &uart_irq
, 1));
77 aml_append(dev
, aml_name_decl("_CRS", crs
));
79 /* The _ADR entry is used to link this device to the UART described
80 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
82 aml_append(dev
, aml_name_decl("_ADR", aml_int(uart_memmap
->base
)));
84 aml_append(scope
, dev
);
87 static void acpi_dsdt_add_fw_cfg(Aml
*scope
, const MemMapEntry
*fw_cfg_memmap
)
89 Aml
*dev
= aml_device("FWCF");
90 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
91 /* device present, functioning, decoding, not shown in UI */
92 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
93 aml_append(dev
, aml_name_decl("_CCA", aml_int(1)));
95 Aml
*crs
= aml_resource_template();
96 aml_append(crs
, aml_memory32_fixed(fw_cfg_memmap
->base
,
97 fw_cfg_memmap
->size
, AML_READ_WRITE
));
98 aml_append(dev
, aml_name_decl("_CRS", crs
));
99 aml_append(scope
, dev
);
102 static void acpi_dsdt_add_flash(Aml
*scope
, const MemMapEntry
*flash_memmap
)
105 hwaddr base
= flash_memmap
->base
;
106 hwaddr size
= flash_memmap
->size
/ 2;
108 dev
= aml_device("FLS0");
109 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
110 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
112 crs
= aml_resource_template();
113 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
114 aml_append(dev
, aml_name_decl("_CRS", crs
));
115 aml_append(scope
, dev
);
117 dev
= aml_device("FLS1");
118 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
119 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
120 crs
= aml_resource_template();
121 aml_append(crs
, aml_memory32_fixed(base
+ size
, size
, AML_READ_WRITE
));
122 aml_append(dev
, aml_name_decl("_CRS", crs
));
123 aml_append(scope
, dev
);
126 static void acpi_dsdt_add_virtio(Aml
*scope
,
127 const MemMapEntry
*virtio_mmio_memmap
,
128 uint32_t mmio_irq
, int num
)
130 hwaddr base
= virtio_mmio_memmap
->base
;
131 hwaddr size
= virtio_mmio_memmap
->size
;
134 for (i
= 0; i
< num
; i
++) {
135 uint32_t irq
= mmio_irq
+ i
;
136 Aml
*dev
= aml_device("VR%02u", i
);
137 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0005")));
138 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
139 aml_append(dev
, aml_name_decl("_CCA", aml_int(1)));
141 Aml
*crs
= aml_resource_template();
142 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
144 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
145 AML_EXCLUSIVE
, &irq
, 1));
146 aml_append(dev
, aml_name_decl("_CRS", crs
));
147 aml_append(scope
, dev
);
152 static void acpi_dsdt_add_pci(Aml
*scope
, const MemMapEntry
*memmap
,
153 uint32_t irq
, bool use_highmem
, bool highmem_ecam
)
155 int ecam_id
= VIRT_ECAM_ID(highmem_ecam
);
156 Aml
*method
, *crs
, *ifctx
, *UUID
, *ifctx1
, *elsectx
, *buf
;
158 hwaddr base_mmio
= memmap
[VIRT_PCIE_MMIO
].base
;
159 hwaddr size_mmio
= memmap
[VIRT_PCIE_MMIO
].size
;
160 hwaddr base_pio
= memmap
[VIRT_PCIE_PIO
].base
;
161 hwaddr size_pio
= memmap
[VIRT_PCIE_PIO
].size
;
162 hwaddr base_ecam
= memmap
[ecam_id
].base
;
163 hwaddr size_ecam
= memmap
[ecam_id
].size
;
164 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
166 Aml
*dev
= aml_device("%s", "PCI0");
167 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A08")));
168 aml_append(dev
, aml_name_decl("_CID", aml_string("PNP0A03")));
169 aml_append(dev
, aml_name_decl("_SEG", aml_int(0)));
170 aml_append(dev
, aml_name_decl("_BBN", aml_int(0)));
171 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
172 aml_append(dev
, aml_name_decl("_UID", aml_string("PCI0")));
173 aml_append(dev
, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
174 aml_append(dev
, aml_name_decl("_CCA", aml_int(1)));
176 /* Declare the PCI Routing Table. */
177 Aml
*rt_pkg
= aml_varpackage(nr_pcie_buses
* PCI_NUM_PINS
);
178 for (bus_no
= 0; bus_no
< nr_pcie_buses
; bus_no
++) {
179 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
180 int gsi
= (i
+ bus_no
) % PCI_NUM_PINS
;
181 Aml
*pkg
= aml_package(4);
182 aml_append(pkg
, aml_int((bus_no
<< 16) | 0xFFFF));
183 aml_append(pkg
, aml_int(i
));
184 aml_append(pkg
, aml_name("GSI%d", gsi
));
185 aml_append(pkg
, aml_int(0));
186 aml_append(rt_pkg
, pkg
);
189 aml_append(dev
, aml_name_decl("_PRT", rt_pkg
));
191 /* Create GSI link device */
192 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
193 uint32_t irqs
= irq
+ i
;
194 Aml
*dev_gsi
= aml_device("GSI%d", i
);
195 aml_append(dev_gsi
, aml_name_decl("_HID", aml_string("PNP0C0F")));
196 aml_append(dev_gsi
, aml_name_decl("_UID", aml_int(0)));
197 crs
= aml_resource_template();
199 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
200 AML_EXCLUSIVE
, &irqs
, 1));
201 aml_append(dev_gsi
, aml_name_decl("_PRS", crs
));
202 crs
= aml_resource_template();
204 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
205 AML_EXCLUSIVE
, &irqs
, 1));
206 aml_append(dev_gsi
, aml_name_decl("_CRS", crs
));
207 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
208 aml_append(dev_gsi
, method
);
209 aml_append(dev
, dev_gsi
);
212 method
= aml_method("_CBA", 0, AML_NOTSERIALIZED
);
213 aml_append(method
, aml_return(aml_int(base_ecam
)));
214 aml_append(dev
, method
);
216 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
217 Aml
*rbuf
= aml_resource_template();
219 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
220 0x0000, 0x0000, nr_pcie_buses
- 1, 0x0000,
223 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
224 AML_NON_CACHEABLE
, AML_READ_WRITE
, 0x0000, base_mmio
,
225 base_mmio
+ size_mmio
- 1, 0x0000, size_mmio
));
227 aml_dword_io(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
228 AML_ENTIRE_RANGE
, 0x0000, 0x0000, size_pio
- 1, base_pio
,
232 hwaddr base_mmio_high
= memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
233 hwaddr size_mmio_high
= memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
236 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
237 AML_NON_CACHEABLE
, AML_READ_WRITE
, 0x0000,
239 base_mmio_high
+ size_mmio_high
- 1, 0x0000,
243 aml_append(method
, aml_name_decl("RBUF", rbuf
));
244 aml_append(method
, aml_return(rbuf
));
245 aml_append(dev
, method
);
247 /* Declare an _OSC (OS Control Handoff) method */
248 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
249 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
250 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
252 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
254 /* PCI Firmware Specification 3.0
255 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
256 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
257 * identified by the Universal Unique IDentifier (UUID)
258 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
260 UUID
= aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
261 ifctx
= aml_if(aml_equal(aml_arg(0), UUID
));
263 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
265 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
266 aml_append(ifctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
267 aml_append(ifctx
, aml_store(aml_name("CDW3"), aml_name("CTRL")));
268 aml_append(ifctx
, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL
),
271 ifctx1
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
272 aml_append(ifctx1
, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL
),
274 aml_append(ifctx
, ifctx1
);
276 ifctx1
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
277 aml_append(ifctx1
, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL
),
279 aml_append(ifctx
, ifctx1
);
281 aml_append(ifctx
, aml_store(aml_name("CTRL"), aml_name("CDW3")));
282 aml_append(ifctx
, aml_return(aml_arg(3)));
283 aml_append(method
, ifctx
);
285 elsectx
= aml_else();
286 aml_append(elsectx
, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL
),
288 aml_append(elsectx
, aml_return(aml_arg(3)));
289 aml_append(method
, elsectx
);
290 aml_append(dev
, method
);
292 method
= aml_method("_DSM", 4, AML_NOTSERIALIZED
);
294 /* PCI Firmware Specification 3.0
295 * 4.6.1. _DSM for PCI Express Slot Information
296 * The UUID in _DSM in this context is
297 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
299 UUID
= aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
300 ifctx
= aml_if(aml_equal(aml_arg(0), UUID
));
301 ifctx1
= aml_if(aml_equal(aml_arg(2), aml_int(0)));
302 uint8_t byte_list
[1] = {1};
303 buf
= aml_buffer(1, byte_list
);
304 aml_append(ifctx1
, aml_return(buf
));
305 aml_append(ifctx
, ifctx1
);
306 aml_append(method
, ifctx
);
309 buf
= aml_buffer(1, byte_list
);
310 aml_append(method
, aml_return(buf
));
311 aml_append(dev
, method
);
313 Aml
*dev_rp0
= aml_device("%s", "RP0");
314 aml_append(dev_rp0
, aml_name_decl("_ADR", aml_int(0)));
315 aml_append(dev
, dev_rp0
);
317 Aml
*dev_res0
= aml_device("%s", "RES0");
318 aml_append(dev_res0
, aml_name_decl("_HID", aml_string("PNP0C02")));
319 crs
= aml_resource_template();
321 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
322 AML_NON_CACHEABLE
, AML_READ_WRITE
, 0x0000, base_ecam
,
323 base_ecam
+ size_ecam
- 1, 0x0000, size_ecam
));
324 aml_append(dev_res0
, aml_name_decl("_CRS", crs
));
325 aml_append(dev
, dev_res0
);
326 aml_append(scope
, dev
);
329 static void acpi_dsdt_add_gpio(Aml
*scope
, const MemMapEntry
*gpio_memmap
,
332 Aml
*dev
= aml_device("GPO0");
333 aml_append(dev
, aml_name_decl("_HID", aml_string("ARMH0061")));
334 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
335 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
337 Aml
*crs
= aml_resource_template();
338 aml_append(crs
, aml_memory32_fixed(gpio_memmap
->base
, gpio_memmap
->size
,
340 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
341 AML_EXCLUSIVE
, &gpio_irq
, 1));
342 aml_append(dev
, aml_name_decl("_CRS", crs
));
344 Aml
*aei
= aml_resource_template();
345 /* Pin 3 for power button */
346 const uint32_t pin_list
[1] = {3};
347 aml_append(aei
, aml_gpio_int(AML_CONSUMER
, AML_EDGE
, AML_ACTIVE_HIGH
,
348 AML_EXCLUSIVE
, AML_PULL_UP
, 0, pin_list
, 1,
350 aml_append(dev
, aml_name_decl("_AEI", aei
));
352 /* _E03 is handle for power button */
353 Aml
*method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
354 aml_append(method
, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE
),
356 aml_append(dev
, method
);
357 aml_append(scope
, dev
);
360 static void acpi_dsdt_add_power_button(Aml
*scope
)
362 Aml
*dev
= aml_device(ACPI_POWER_BUTTON_DEVICE
);
363 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0C0C")));
364 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
365 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
366 aml_append(scope
, dev
);
371 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned xsdt_tbl_offset
)
373 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
374 unsigned xsdt_pa_size
= sizeof(rsdp
->xsdt_physical_address
);
375 unsigned xsdt_pa_offset
=
376 (char *)&rsdp
->xsdt_physical_address
- rsdp_table
->data
;
378 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
379 true /* fseg memory */);
381 memcpy(&rsdp
->signature
, "RSD PTR ", sizeof(rsdp
->signature
));
382 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, sizeof(rsdp
->oem_id
));
383 rsdp
->length
= cpu_to_le32(sizeof(*rsdp
));
384 rsdp
->revision
= 0x02;
386 /* Address to be filled by Guest linker */
387 bios_linker_loader_add_pointer(linker
,
388 ACPI_BUILD_RSDP_FILE
, xsdt_pa_offset
, xsdt_pa_size
,
389 ACPI_BUILD_TABLE_FILE
, xsdt_tbl_offset
);
391 /* Checksum to be filled by Guest linker */
392 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
393 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
394 (char *)&rsdp
->checksum
- rsdp_table
->data
);
398 build_iort(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
400 int nb_nodes
, iort_start
= table_data
->len
;
401 AcpiIortIdMapping
*idmap
;
402 AcpiIortItsGroup
*its
;
405 size_t node_size
, iort_node_offset
, iort_length
, smmu_offset
= 0;
408 iort
= acpi_data_push(table_data
, sizeof(*iort
));
410 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
411 nb_nodes
= 3; /* RC, ITS, SMMUv3 */
413 nb_nodes
= 2; /* RC, ITS */
416 iort_length
= sizeof(*iort
);
417 iort
->node_count
= cpu_to_le32(nb_nodes
);
419 * Use a copy in case table_data->data moves during acpi_data_push
422 iort_node_offset
= sizeof(*iort
);
423 iort
->node_offset
= cpu_to_le32(iort_node_offset
);
426 node_size
= sizeof(*its
) + sizeof(uint32_t);
427 iort_length
+= node_size
;
428 its
= acpi_data_push(table_data
, node_size
);
430 its
->type
= ACPI_IORT_NODE_ITS_GROUP
;
431 its
->length
= cpu_to_le16(node_size
);
432 its
->its_count
= cpu_to_le32(1);
433 its
->identifiers
[0] = 0; /* MADT translation_id */
435 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
436 int irq
= vms
->irqmap
[VIRT_SMMU
];
439 smmu_offset
= iort_node_offset
+ node_size
;
440 node_size
= sizeof(*smmu
) + sizeof(*idmap
);
441 iort_length
+= node_size
;
442 smmu
= acpi_data_push(table_data
, node_size
);
444 smmu
->type
= ACPI_IORT_NODE_SMMU_V3
;
445 smmu
->length
= cpu_to_le16(node_size
);
446 smmu
->mapping_count
= cpu_to_le32(1);
447 smmu
->mapping_offset
= cpu_to_le32(sizeof(*smmu
));
448 smmu
->base_address
= cpu_to_le64(vms
->memmap
[VIRT_SMMU
].base
);
449 smmu
->event_gsiv
= cpu_to_le32(irq
);
450 smmu
->pri_gsiv
= cpu_to_le32(irq
+ 1);
451 smmu
->gerr_gsiv
= cpu_to_le32(irq
+ 2);
452 smmu
->sync_gsiv
= cpu_to_le32(irq
+ 3);
454 /* Identity RID mapping covering the whole input RID range */
455 idmap
= &smmu
->id_mapping_array
[0];
456 idmap
->input_base
= 0;
457 idmap
->id_count
= cpu_to_le32(0xFFFF);
458 idmap
->output_base
= 0;
459 /* output IORT node is the ITS group node (the first node) */
460 idmap
->output_reference
= cpu_to_le32(iort_node_offset
);
463 /* Root Complex Node */
464 node_size
= sizeof(*rc
) + sizeof(*idmap
);
465 iort_length
+= node_size
;
466 rc
= acpi_data_push(table_data
, node_size
);
468 rc
->type
= ACPI_IORT_NODE_PCI_ROOT_COMPLEX
;
469 rc
->length
= cpu_to_le16(node_size
);
470 rc
->mapping_count
= cpu_to_le32(1);
471 rc
->mapping_offset
= cpu_to_le32(sizeof(*rc
));
473 /* fully coherent device */
474 rc
->memory_properties
.cache_coherency
= cpu_to_le32(1);
475 rc
->memory_properties
.memory_flags
= 0x3; /* CCA = CPM = DCAS = 1 */
476 rc
->pci_segment_number
= 0; /* MCFG pci_segment */
478 /* Identity RID mapping covering the whole input RID range */
479 idmap
= &rc
->id_mapping_array
[0];
480 idmap
->input_base
= 0;
481 idmap
->id_count
= cpu_to_le32(0xFFFF);
482 idmap
->output_base
= 0;
484 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
485 /* output IORT node is the smmuv3 node */
486 idmap
->output_reference
= cpu_to_le32(smmu_offset
);
488 /* output IORT node is the ITS group node (the first node) */
489 idmap
->output_reference
= cpu_to_le32(iort_node_offset
);
493 * Update the pointer address in case table_data->data moves during above
494 * acpi_data_push operations.
496 iort
= (AcpiIortTable
*)(table_data
->data
+ iort_start
);
497 iort
->length
= cpu_to_le32(iort_length
);
499 build_header(linker
, table_data
, (void *)(table_data
->data
+ iort_start
),
500 "IORT", table_data
->len
- iort_start
, 0, NULL
, NULL
);
504 build_spcr(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
506 AcpiSerialPortConsoleRedirection
*spcr
;
507 const MemMapEntry
*uart_memmap
= &vms
->memmap
[VIRT_UART
];
508 int irq
= vms
->irqmap
[VIRT_UART
] + ARM_SPI_BASE
;
509 int spcr_start
= table_data
->len
;
511 spcr
= acpi_data_push(table_data
, sizeof(*spcr
));
513 spcr
->interface_type
= 0x3; /* ARM PL011 UART */
515 spcr
->base_address
.space_id
= AML_SYSTEM_MEMORY
;
516 spcr
->base_address
.bit_width
= 8;
517 spcr
->base_address
.bit_offset
= 0;
518 spcr
->base_address
.access_width
= 1;
519 spcr
->base_address
.address
= cpu_to_le64(uart_memmap
->base
);
521 spcr
->interrupt_types
= (1 << 3); /* Bit[3] ARMH GIC interrupt */
522 spcr
->gsi
= cpu_to_le32(irq
); /* Global System Interrupt */
524 spcr
->baud
= 3; /* Baud Rate: 3 = 9600 */
525 spcr
->parity
= 0; /* No Parity */
526 spcr
->stopbits
= 1; /* 1 Stop bit */
527 spcr
->flowctrl
= (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
528 spcr
->term_type
= 0; /* Terminal Type: 0 = VT100 */
530 spcr
->pci_device_id
= 0xffff; /* PCI Device ID: not a PCI device */
531 spcr
->pci_vendor_id
= 0xffff; /* PCI Vendor ID: not a PCI device */
533 build_header(linker
, table_data
, (void *)(table_data
->data
+ spcr_start
),
534 "SPCR", table_data
->len
- spcr_start
, 2, NULL
, NULL
);
538 build_srat(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
540 AcpiSystemResourceAffinityTable
*srat
;
541 AcpiSratProcessorGiccAffinity
*core
;
542 AcpiSratMemoryAffinity
*numamem
;
545 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
546 const CPUArchIdList
*cpu_list
= mc
->possible_cpu_arch_ids(MACHINE(vms
));
548 srat_start
= table_data
->len
;
549 srat
= acpi_data_push(table_data
, sizeof(*srat
));
550 srat
->reserved1
= cpu_to_le32(1);
552 for (i
= 0; i
< cpu_list
->len
; ++i
) {
553 core
= acpi_data_push(table_data
, sizeof(*core
));
554 core
->type
= ACPI_SRAT_PROCESSOR_GICC
;
555 core
->length
= sizeof(*core
);
556 core
->proximity
= cpu_to_le32(cpu_list
->cpus
[i
].props
.node_id
);
557 core
->acpi_processor_uid
= cpu_to_le32(i
);
558 core
->flags
= cpu_to_le32(1);
561 mem_base
= vms
->memmap
[VIRT_MEM
].base
;
562 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
563 if (numa_info
[i
].node_mem
> 0) {
564 numamem
= acpi_data_push(table_data
, sizeof(*numamem
));
565 build_srat_memory(numamem
, mem_base
, numa_info
[i
].node_mem
, i
,
566 MEM_AFFINITY_ENABLED
);
567 mem_base
+= numa_info
[i
].node_mem
;
571 build_header(linker
, table_data
, (void *)(table_data
->data
+ srat_start
),
572 "SRAT", table_data
->len
- srat_start
, 3, NULL
, NULL
);
576 build_mcfg(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
579 const MemMapEntry
*memmap
= vms
->memmap
;
580 int ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
581 int len
= sizeof(*mcfg
) + sizeof(mcfg
->allocation
[0]);
582 int mcfg_start
= table_data
->len
;
584 mcfg
= acpi_data_push(table_data
, len
);
585 mcfg
->allocation
[0].address
= cpu_to_le64(memmap
[ecam_id
].base
);
587 /* Only a single allocation so no need to play with segments */
588 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
589 mcfg
->allocation
[0].start_bus_number
= 0;
590 mcfg
->allocation
[0].end_bus_number
= (memmap
[ecam_id
].size
591 / PCIE_MMCFG_SIZE_MIN
) - 1;
593 build_header(linker
, table_data
, (void *)(table_data
->data
+ mcfg_start
),
594 "MCFG", table_data
->len
- mcfg_start
, 1, NULL
, NULL
);
599 build_gtdt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
601 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
602 int gtdt_start
= table_data
->len
;
603 AcpiGenericTimerTable
*gtdt
;
606 if (vmc
->claim_edge_triggered_timers
) {
607 irqflags
= ACPI_GTDT_INTERRUPT_MODE_EDGE
;
609 irqflags
= ACPI_GTDT_INTERRUPT_MODE_LEVEL
;
612 gtdt
= acpi_data_push(table_data
, sizeof *gtdt
);
613 /* The interrupt values are the same with the device tree when adding 16 */
614 gtdt
->secure_el1_interrupt
= cpu_to_le32(ARCH_TIMER_S_EL1_IRQ
+ 16);
615 gtdt
->secure_el1_flags
= cpu_to_le32(irqflags
);
617 gtdt
->non_secure_el1_interrupt
= cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ
+ 16);
618 gtdt
->non_secure_el1_flags
= cpu_to_le32(irqflags
|
619 ACPI_GTDT_CAP_ALWAYS_ON
);
621 gtdt
->virtual_timer_interrupt
= cpu_to_le32(ARCH_TIMER_VIRT_IRQ
+ 16);
622 gtdt
->virtual_timer_flags
= cpu_to_le32(irqflags
);
624 gtdt
->non_secure_el2_interrupt
= cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ
+ 16);
625 gtdt
->non_secure_el2_flags
= cpu_to_le32(irqflags
);
627 build_header(linker
, table_data
,
628 (void *)(table_data
->data
+ gtdt_start
), "GTDT",
629 table_data
->len
- gtdt_start
, 2, NULL
, NULL
);
634 build_madt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
636 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
637 int madt_start
= table_data
->len
;
638 const MemMapEntry
*memmap
= vms
->memmap
;
639 const int *irqmap
= vms
->irqmap
;
640 AcpiMultipleApicTable
*madt
;
641 AcpiMadtGenericDistributor
*gicd
;
642 AcpiMadtGenericMsiFrame
*gic_msi
;
645 madt
= acpi_data_push(table_data
, sizeof *madt
);
647 gicd
= acpi_data_push(table_data
, sizeof *gicd
);
648 gicd
->type
= ACPI_APIC_GENERIC_DISTRIBUTOR
;
649 gicd
->length
= sizeof(*gicd
);
650 gicd
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_DIST
].base
);
651 gicd
->version
= vms
->gic_version
;
653 for (i
= 0; i
< vms
->smp_cpus
; i
++) {
654 AcpiMadtGenericCpuInterface
*gicc
= acpi_data_push(table_data
,
656 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(i
));
658 gicc
->type
= ACPI_APIC_GENERIC_CPU_INTERFACE
;
659 gicc
->length
= sizeof(*gicc
);
660 if (vms
->gic_version
== 2) {
661 gicc
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_CPU
].base
);
662 gicc
->gich_base_address
= cpu_to_le64(memmap
[VIRT_GIC_HYP
].base
);
663 gicc
->gicv_base_address
= cpu_to_le64(memmap
[VIRT_GIC_VCPU
].base
);
665 gicc
->cpu_interface_number
= cpu_to_le32(i
);
666 gicc
->arm_mpidr
= cpu_to_le64(armcpu
->mp_affinity
);
667 gicc
->uid
= cpu_to_le32(i
);
668 gicc
->flags
= cpu_to_le32(ACPI_MADT_GICC_ENABLED
);
670 if (arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
671 gicc
->performance_interrupt
= cpu_to_le32(PPI(VIRTUAL_PMU_IRQ
));
674 gicc
->vgic_interrupt
= cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ
));
678 if (vms
->gic_version
== 3) {
679 AcpiMadtGenericTranslator
*gic_its
;
680 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
681 AcpiMadtGenericRedistributor
*gicr
= acpi_data_push(table_data
,
684 gicr
->type
= ACPI_APIC_GENERIC_REDISTRIBUTOR
;
685 gicr
->length
= sizeof(*gicr
);
686 gicr
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_REDIST
].base
);
687 gicr
->range_length
= cpu_to_le32(memmap
[VIRT_GIC_REDIST
].size
);
689 if (nb_redist_regions
== 2) {
690 gicr
= acpi_data_push(table_data
, sizeof(*gicr
));
691 gicr
->type
= ACPI_APIC_GENERIC_REDISTRIBUTOR
;
692 gicr
->length
= sizeof(*gicr
);
693 gicr
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_REDIST2
].base
);
694 gicr
->range_length
= cpu_to_le32(memmap
[VIRT_GIC_REDIST2
].size
);
697 if (its_class_name() && !vmc
->no_its
) {
698 gic_its
= acpi_data_push(table_data
, sizeof *gic_its
);
699 gic_its
->type
= ACPI_APIC_GENERIC_TRANSLATOR
;
700 gic_its
->length
= sizeof(*gic_its
);
701 gic_its
->translation_id
= 0;
702 gic_its
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_ITS
].base
);
705 gic_msi
= acpi_data_push(table_data
, sizeof *gic_msi
);
706 gic_msi
->type
= ACPI_APIC_GENERIC_MSI_FRAME
;
707 gic_msi
->length
= sizeof(*gic_msi
);
708 gic_msi
->gic_msi_frame_id
= 0;
709 gic_msi
->base_address
= cpu_to_le64(memmap
[VIRT_GIC_V2M
].base
);
710 gic_msi
->flags
= cpu_to_le32(1);
711 gic_msi
->spi_count
= cpu_to_le16(NUM_GICV2M_SPIS
);
712 gic_msi
->spi_base
= cpu_to_le16(irqmap
[VIRT_GIC_V2M
] + ARM_SPI_BASE
);
715 build_header(linker
, table_data
,
716 (void *)(table_data
->data
+ madt_start
), "APIC",
717 table_data
->len
- madt_start
, 3, NULL
, NULL
);
721 static void build_fadt_rev5(GArray
*table_data
, BIOSLinker
*linker
,
722 VirtMachineState
*vms
, unsigned dsdt_tbl_offset
)
725 AcpiFadtData fadt
= {
728 .flags
= 1 << ACPI_FADT_F_HW_REDUCED_ACPI
,
729 .xdsdt_tbl_offset
= &dsdt_tbl_offset
,
732 switch (vms
->psci_conduit
) {
733 case QEMU_PSCI_CONDUIT_DISABLED
:
734 fadt
.arm_boot_arch
= 0;
736 case QEMU_PSCI_CONDUIT_HVC
:
737 fadt
.arm_boot_arch
= ACPI_FADT_ARM_PSCI_COMPLIANT
|
738 ACPI_FADT_ARM_PSCI_USE_HVC
;
740 case QEMU_PSCI_CONDUIT_SMC
:
741 fadt
.arm_boot_arch
= ACPI_FADT_ARM_PSCI_COMPLIANT
;
744 g_assert_not_reached();
747 build_fadt(table_data
, linker
, &fadt
, NULL
, NULL
);
752 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
755 const MemMapEntry
*memmap
= vms
->memmap
;
756 const int *irqmap
= vms
->irqmap
;
758 dsdt
= init_aml_allocator();
759 /* Reserve space for header */
760 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
762 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
763 * While UEFI can use libfdt to disable the RTC device node in the DTB that
764 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
765 * the RTC ACPI device at all when using UEFI.
767 scope
= aml_scope("\\_SB");
768 acpi_dsdt_add_cpus(scope
, vms
->smp_cpus
);
769 acpi_dsdt_add_uart(scope
, &memmap
[VIRT_UART
],
770 (irqmap
[VIRT_UART
] + ARM_SPI_BASE
));
771 acpi_dsdt_add_flash(scope
, &memmap
[VIRT_FLASH
]);
772 acpi_dsdt_add_fw_cfg(scope
, &memmap
[VIRT_FW_CFG
]);
773 acpi_dsdt_add_virtio(scope
, &memmap
[VIRT_MMIO
],
774 (irqmap
[VIRT_MMIO
] + ARM_SPI_BASE
), NUM_VIRTIO_TRANSPORTS
);
775 acpi_dsdt_add_pci(scope
, memmap
, (irqmap
[VIRT_PCIE
] + ARM_SPI_BASE
),
776 vms
->highmem
, vms
->highmem_ecam
);
777 acpi_dsdt_add_gpio(scope
, &memmap
[VIRT_GPIO
],
778 (irqmap
[VIRT_GPIO
] + ARM_SPI_BASE
));
779 acpi_dsdt_add_power_button(scope
);
781 aml_append(dsdt
, scope
);
783 /* copy AML table into ACPI tables blob and patch header there */
784 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
785 build_header(linker
, table_data
,
786 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
787 "DSDT", dsdt
->buf
->len
, 2, NULL
, NULL
);
788 free_aml_allocator();
792 struct AcpiBuildState
{
793 /* Copy of table in RAM (for patching). */
794 MemoryRegion
*table_mr
;
795 MemoryRegion
*rsdp_mr
;
796 MemoryRegion
*linker_mr
;
797 /* Is table patched? */
802 void virt_acpi_build(VirtMachineState
*vms
, AcpiBuildTables
*tables
)
804 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
805 GArray
*table_offsets
;
807 GArray
*tables_blob
= tables
->table_data
;
809 table_offsets
= g_array_new(false, true /* clear */,
812 bios_linker_loader_alloc(tables
->linker
,
813 ACPI_BUILD_TABLE_FILE
, tables_blob
,
814 64, false /* high memory */);
816 /* DSDT is pointed to by FADT */
817 dsdt
= tables_blob
->len
;
818 build_dsdt(tables_blob
, tables
->linker
, vms
);
820 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
821 acpi_add_table(table_offsets
, tables_blob
);
822 build_fadt_rev5(tables_blob
, tables
->linker
, vms
, dsdt
);
824 acpi_add_table(table_offsets
, tables_blob
);
825 build_madt(tables_blob
, tables
->linker
, vms
);
827 acpi_add_table(table_offsets
, tables_blob
);
828 build_gtdt(tables_blob
, tables
->linker
, vms
);
830 acpi_add_table(table_offsets
, tables_blob
);
831 build_mcfg(tables_blob
, tables
->linker
, vms
);
833 acpi_add_table(table_offsets
, tables_blob
);
834 build_spcr(tables_blob
, tables
->linker
, vms
);
836 if (nb_numa_nodes
> 0) {
837 acpi_add_table(table_offsets
, tables_blob
);
838 build_srat(tables_blob
, tables
->linker
, vms
);
839 if (have_numa_distance
) {
840 acpi_add_table(table_offsets
, tables_blob
);
841 build_slit(tables_blob
, tables
->linker
);
845 if (its_class_name() && !vmc
->no_its
) {
846 acpi_add_table(table_offsets
, tables_blob
);
847 build_iort(tables_blob
, tables
->linker
, vms
);
850 /* XSDT is pointed to by RSDP */
851 xsdt
= tables_blob
->len
;
852 build_xsdt(tables_blob
, tables
->linker
, table_offsets
, NULL
, NULL
);
854 /* RSDP is in FSEG memory, so allocate it separately */
855 build_rsdp(tables
->rsdp
, tables
->linker
, xsdt
);
857 /* Cleanup memory that's no longer used. */
858 g_array_free(table_offsets
, true);
861 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
863 uint32_t size
= acpi_data_len(data
);
865 /* Make sure RAM size is correct - in case it got changed
866 * e.g. by migration */
867 memory_region_ram_resize(mr
, size
, &error_abort
);
869 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
870 memory_region_set_dirty(mr
, 0, size
);
873 static void virt_acpi_build_update(void *build_opaque
)
875 AcpiBuildState
*build_state
= build_opaque
;
876 AcpiBuildTables tables
;
878 /* No state to update or already patched? Nothing to do. */
879 if (!build_state
|| build_state
->patched
) {
882 build_state
->patched
= true;
884 acpi_build_tables_init(&tables
);
886 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables
);
888 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
889 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
890 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
892 acpi_build_tables_cleanup(&tables
, true);
895 static void virt_acpi_build_reset(void *build_opaque
)
897 AcpiBuildState
*build_state
= build_opaque
;
898 build_state
->patched
= false;
901 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
902 GArray
*blob
, const char *name
,
905 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
906 name
, virt_acpi_build_update
, build_state
, NULL
, true);
909 static const VMStateDescription vmstate_virt_acpi_build
= {
910 .name
= "virt_acpi_build",
912 .minimum_version_id
= 1,
913 .fields
= (VMStateField
[]) {
914 VMSTATE_BOOL(patched
, AcpiBuildState
),
915 VMSTATE_END_OF_LIST()
919 void virt_acpi_setup(VirtMachineState
*vms
)
921 AcpiBuildTables tables
;
922 AcpiBuildState
*build_state
;
925 trace_virt_acpi_setup();
930 trace_virt_acpi_setup();
934 build_state
= g_malloc0(sizeof *build_state
);
936 acpi_build_tables_init(&tables
);
937 virt_acpi_build(vms
, &tables
);
939 /* Now expose it all to Guest */
940 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
941 ACPI_BUILD_TABLE_FILE
,
942 ACPI_BUILD_TABLE_MAX_SIZE
);
943 assert(build_state
->table_mr
!= NULL
);
945 build_state
->linker_mr
=
946 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
947 "etc/table-loader", 0);
949 fw_cfg_add_file(vms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
, tables
.tcpalog
->data
,
950 acpi_data_len(tables
.tcpalog
));
952 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
953 ACPI_BUILD_RSDP_FILE
, 0);
955 qemu_register_reset(virt_acpi_build_reset
, build_state
);
956 virt_acpi_build_reset(build_state
);
957 vmstate_register(NULL
, 0, &vmstate_virt_acpi_build
, build_state
);
959 /* Cleanup tables but don't free the memory: we track it
962 acpi_build_tables_cleanup(&tables
, false);