target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) cpu_##insn##_data(env, addr);                         \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lw, ldl, int32_t)
  94 #if defined(TARGET_MIPS64)
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     cpu_##insn##_data(env, addr, val);                                  \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #if defined(TARGET_MIPS64)
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 static inline target_ulong bitswap(target_ulong v)
 269 {
 270     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 271               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 272     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 273               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 274     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 275               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 276     return v;
 277 }
 278
 279 #ifdef TARGET_MIPS64
 280 target_ulong helper_dbitswap(target_ulong rt)
 281 {
 282     return bitswap(rt);
 283 }
 284 #endif
 285
 286 target_ulong helper_bitswap(target_ulong rt)
 287 {
 288     return (int32_t)bitswap(rt);
 289 }
 290
 291 #ifndef CONFIG_USER_ONLY
 292
 293 static inline hwaddr do_translate_address(CPUMIPSState *env,
 294                                                       target_ulong address,
 295                                                       int rw)
 296 {
 297     hwaddr lladdr;
 298
 299     lladdr = cpu_mips_translate_address(env, address, rw);
 300
 301     if (lladdr == -1LL) {
 302         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 303     } else {
 304         return lladdr;
 305     }
 306 }
 307
 308 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 310 {                                                                             \
 311     if (arg & almask) {                                                       \
 312         env->CP0_BadVAddr = arg;                                              \
 313         helper_raise_exception(env, EXCP_AdEL);                               \
 314     }                                                                         \
 315     env->lladdr = do_translate_address(env, arg, 0);                          \
 316     env->llval = do_##insn(env, arg, mem_idx);                                \
 317     return env->llval;                                                        \
 318 }
 319 HELPER_LD_ATOMIC(ll, lw, 0x3)
 320 #ifdef TARGET_MIPS64
 321 HELPER_LD_ATOMIC(lld, ld, 0x7)
 322 #endif
 323 #undef HELPER_LD_ATOMIC
 324
 325 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 326 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 327                            target_ulong arg2, int mem_idx)                    \
 328 {                                                                             \
 329     target_long tmp;                                                          \
 330                                                                               \
 331     if (arg2 & almask) {                                                      \
 332         env->CP0_BadVAddr = arg2;                                             \
 333         helper_raise_exception(env, EXCP_AdES);                               \
 334     }                                                                         \
 335     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 336         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 337         if (tmp == env->llval) {                                              \
 338             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 339             return 1;                                                         \
 340         }                                                                     \
 341     }                                                                         \
 342     return 0;                                                                 \
 343 }
 344 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 345 #ifdef TARGET_MIPS64
 346 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 347 #endif
 348 #undef HELPER_ST_ATOMIC
 349 #endif
 350
 351 #ifdef TARGET_WORDS_BIGENDIAN
 352 #define GET_LMASK(v) ((v) & 3)
 353 #define GET_OFFSET(addr, offset) (addr + (offset))
 354 #else
 355 #define GET_LMASK(v) (((v) & 3) ^ 3)
 356 #define GET_OFFSET(addr, offset) (addr - (offset))
 357 #endif
 358
 359 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 360                 int mem_idx)
 361 {
 362     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 363
 364     if (GET_LMASK(arg2) <= 2)
 365         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 366
 367     if (GET_LMASK(arg2) <= 1)
 368         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 369
 370     if (GET_LMASK(arg2) == 0)
 371         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 372 }
 373
 374 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 375                 int mem_idx)
 376 {
 377     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 378
 379     if (GET_LMASK(arg2) >= 1)
 380         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 381
 382     if (GET_LMASK(arg2) >= 2)
 383         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 384
 385     if (GET_LMASK(arg2) == 3)
 386         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 387 }
 388
 389 #if defined(TARGET_MIPS64)
 390 /* "half" load and stores.  We must do the memory access inline,
 391    or fault handling won't work.  */
 392
 393 #ifdef TARGET_WORDS_BIGENDIAN
 394 #define GET_LMASK64(v) ((v) & 7)
 395 #else
 396 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 397 #endif
 398
 399 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 400                 int mem_idx)
 401 {
 402     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 403
 404     if (GET_LMASK64(arg2) <= 6)
 405         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 406
 407     if (GET_LMASK64(arg2) <= 5)
 408         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 409
 410     if (GET_LMASK64(arg2) <= 4)
 411         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 412
 413     if (GET_LMASK64(arg2) <= 3)
 414         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 415
 416     if (GET_LMASK64(arg2) <= 2)
 417         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 418
 419     if (GET_LMASK64(arg2) <= 1)
 420         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 421
 422     if (GET_LMASK64(arg2) <= 0)
 423         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 424 }
 425
 426 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 427                 int mem_idx)
 428 {
 429     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 430
 431     if (GET_LMASK64(arg2) >= 1)
 432         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 433
 434     if (GET_LMASK64(arg2) >= 2)
 435         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 436
 437     if (GET_LMASK64(arg2) >= 3)
 438         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 439
 440     if (GET_LMASK64(arg2) >= 4)
 441         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 442
 443     if (GET_LMASK64(arg2) >= 5)
 444         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 445
 446     if (GET_LMASK64(arg2) >= 6)
 447         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 448
 449     if (GET_LMASK64(arg2) == 7)
 450         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 451 }
 452 #endif /* TARGET_MIPS64 */
 453
 454 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 455
 456 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 457                 uint32_t mem_idx)
 458 {
 459     target_ulong base_reglist = reglist & 0xf;
 460     target_ulong do_r31 = reglist & 0x10;
 461
 462     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 463         target_ulong i;
 464
 465         for (i = 0; i < base_reglist; i++) {
 466             env->active_tc.gpr[multiple_regs[i]] =
 467                 (target_long)do_lw(env, addr, mem_idx);
 468             addr += 4;
 469         }
 470     }
 471
 472     if (do_r31) {
 473         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 474     }
 475 }
 476
 477 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 478                 uint32_t mem_idx)
 479 {
 480     target_ulong base_reglist = reglist & 0xf;
 481     target_ulong do_r31 = reglist & 0x10;
 482
 483     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 484         target_ulong i;
 485
 486         for (i = 0; i < base_reglist; i++) {
 487             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 488             addr += 4;
 489         }
 490     }
 491
 492     if (do_r31) {
 493         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 494     }
 495 }
 496
 497 #if defined(TARGET_MIPS64)
 498 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 499                 uint32_t mem_idx)
 500 {
 501     target_ulong base_reglist = reglist & 0xf;
 502     target_ulong do_r31 = reglist & 0x10;
 503
 504     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 505         target_ulong i;
 506
 507         for (i = 0; i < base_reglist; i++) {
 508             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 509             addr += 8;
 510         }
 511     }
 512
 513     if (do_r31) {
 514         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 515     }
 516 }
 517
 518 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 519                 uint32_t mem_idx)
 520 {
 521     target_ulong base_reglist = reglist & 0xf;
 522     target_ulong do_r31 = reglist & 0x10;
 523
 524     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 525         target_ulong i;
 526
 527         for (i = 0; i < base_reglist; i++) {
 528             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 529             addr += 8;
 530         }
 531     }
 532
 533     if (do_r31) {
 534         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 535     }
 536 }
 537 #endif
 538
 539 #ifndef CONFIG_USER_ONLY
 540 /* SMP helpers.  */
 541 static bool mips_vpe_is_wfi(MIPSCPU *c)
 542 {
 543     CPUState *cpu = CPU(c);
 544     CPUMIPSState *env = &c->env;
 545
 546     /* If the VPE is halted but otherwise active, it means it's waiting for
 547        an interrupt.  */
 548     return cpu->halted && mips_vpe_active(env);
 549 }
 550
 551 static inline void mips_vpe_wake(MIPSCPU *c)
 552 {
 553     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 554        because there might be other conditions that state that c should
 555        be sleeping.  */
 556     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 557 }
 558
 559 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 560 {
 561     CPUState *cs = CPU(cpu);
 562
 563     /* The VPE was shut off, really go to bed.
 564        Reset any old _WAKE requests.  */
 565     cs->halted = 1;
 566     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 567 }
 568
 569 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 570 {
 571     CPUMIPSState *c = &cpu->env;
 572
 573     /* FIXME: TC reschedule.  */
 574     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 575         mips_vpe_wake(cpu);
 576     }
 577 }
 578
 579 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 580 {
 581     CPUMIPSState *c = &cpu->env;
 582
 583     /* FIXME: TC reschedule.  */
 584     if (!mips_vpe_active(c)) {
 585         mips_vpe_sleep(cpu);
 586     }
 587 }
 588
 589 /**
 590  * mips_cpu_map_tc:
 591  * @env: CPU from which mapping is performed.
 592  * @tc: Should point to an int with the value of the global TC index.
 593  *
 594  * This function will transform @tc into a local index within the
 595  * returned #CPUMIPSState.
 596  */
 597 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 598           which depends on runtime setup. Can probably be fixed by
 599           walking the list of CPUMIPSStates.  */
 600 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 601 {
 602     MIPSCPU *cpu;
 603     CPUState *cs;
 604     CPUState *other_cs;
 605     int vpe_idx;
 606     int tc_idx = *tc;
 607
 608     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 609         /* Not allowed to address other CPUs.  */
 610         *tc = env->current_tc;
 611         return env;
 612     }
 613
 614     cs = CPU(mips_env_get_cpu(env));
 615     vpe_idx = tc_idx / cs->nr_threads;
 616     *tc = tc_idx % cs->nr_threads;
 617     other_cs = qemu_get_cpu(vpe_idx);
 618     if (other_cs == NULL) {
 619         return env;
 620     }
 621     cpu = MIPS_CPU(other_cs);
 622     return &cpu->env;
 623 }
 624
 625 /* The per VPE CP0_Status register shares some fields with the per TC
 626    CP0_TCStatus registers. These fields are wired to the same registers,
 627    so changes to either of them should be reflected on both registers.
 628
 629    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 630
 631    These helper call synchronizes the regs for a given cpu.  */
 632
 633 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 634 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 635                                      int tc);  */
 636
 637 /* Called for updates to CP0_TCStatus.  */
 638 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 639                              target_ulong v)
 640 {
 641     uint32_t status;
 642     uint32_t tcu, tmx, tasid, tksu;
 643     uint32_t mask = ((1U << CP0St_CU3)
 644                        | (1 << CP0St_CU2)
 645                        | (1 << CP0St_CU1)
 646                        | (1 << CP0St_CU0)
 647                        | (1 << CP0St_MX)
 648                        | (3 << CP0St_KSU));
 649
 650     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 651     tmx = (v >> CP0TCSt_TMX) & 0x1;
 652     tasid = v & 0xff;
 653     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 654
 655     status = tcu << CP0St_CU0;
 656     status |= tmx << CP0St_MX;
 657     status |= tksu << CP0St_KSU;
 658
 659     cpu->CP0_Status &= ~mask;
 660     cpu->CP0_Status |= status;
 661
 662     /* Sync the TASID with EntryHi.  */
 663     cpu->CP0_EntryHi &= ~0xff;
 664     cpu->CP0_EntryHi = tasid;
 665
 666     compute_hflags(cpu);
 667 }
 668
 669 /* Called for updates to CP0_EntryHi.  */
 670 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 671 {
 672     int32_t *tcst;
 673     uint32_t asid, v = cpu->CP0_EntryHi;
 674
 675     asid = v & 0xff;
 676
 677     if (tc == cpu->current_tc) {
 678         tcst = &cpu->active_tc.CP0_TCStatus;
 679     } else {
 680         tcst = &cpu->tcs[tc].CP0_TCStatus;
 681     }
 682
 683     *tcst &= ~0xff;
 684     *tcst |= asid;
 685 }
 686
 687 /* CP0 helpers */
 688 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 689 {
 690     return env->mvp->CP0_MVPControl;
 691 }
 692
 693 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 694 {
 695     return env->mvp->CP0_MVPConf0;
 696 }
 697
 698 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 699 {
 700     return env->mvp->CP0_MVPConf1;
 701 }
 702
 703 target_ulong helper_mfc0_random(CPUMIPSState *env)
 704 {
 705     return (int32_t)cpu_mips_get_random(env);
 706 }
 707
 708 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 709 {
 710     return env->active_tc.CP0_TCStatus;
 711 }
 712
 713 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 714 {
 715     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 716     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 717
 718     if (other_tc == other->current_tc)
 719         return other->active_tc.CP0_TCStatus;
 720     else
 721         return other->tcs[other_tc].CP0_TCStatus;
 722 }
 723
 724 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 725 {
 726     return env->active_tc.CP0_TCBind;
 727 }
 728
 729 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 730 {
 731     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 732     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 733
 734     if (other_tc == other->current_tc)
 735         return other->active_tc.CP0_TCBind;
 736     else
 737         return other->tcs[other_tc].CP0_TCBind;
 738 }
 739
 740 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 741 {
 742     return env->active_tc.PC;
 743 }
 744
 745 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 746 {
 747     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 748     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 749
 750     if (other_tc == other->current_tc)
 751         return other->active_tc.PC;
 752     else
 753         return other->tcs[other_tc].PC;
 754 }
 755
 756 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 757 {
 758     return env->active_tc.CP0_TCHalt;
 759 }
 760
 761 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 762 {
 763     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 764     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 765
 766     if (other_tc == other->current_tc)
 767         return other->active_tc.CP0_TCHalt;
 768     else
 769         return other->tcs[other_tc].CP0_TCHalt;
 770 }
 771
 772 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 773 {
 774     return env->active_tc.CP0_TCContext;
 775 }
 776
 777 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 778 {
 779     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 780     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 781
 782     if (other_tc == other->current_tc)
 783         return other->active_tc.CP0_TCContext;
 784     else
 785         return other->tcs[other_tc].CP0_TCContext;
 786 }
 787
 788 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 789 {
 790     return env->active_tc.CP0_TCSchedule;
 791 }
 792
 793 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 794 {
 795     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 796     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 797
 798     if (other_tc == other->current_tc)
 799         return other->active_tc.CP0_TCSchedule;
 800     else
 801         return other->tcs[other_tc].CP0_TCSchedule;
 802 }
 803
 804 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 805 {
 806     return env->active_tc.CP0_TCScheFBack;
 807 }
 808
 809 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 810 {
 811     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 812     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 813
 814     if (other_tc == other->current_tc)
 815         return other->active_tc.CP0_TCScheFBack;
 816     else
 817         return other->tcs[other_tc].CP0_TCScheFBack;
 818 }
 819
 820 target_ulong helper_mfc0_count(CPUMIPSState *env)
 821 {
 822     return (int32_t)cpu_mips_get_count(env);
 823 }
 824
 825 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 826 {
 827     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 828     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 829
 830     return other->CP0_EntryHi;
 831 }
 832
 833 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 834 {
 835     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 836     int32_t tccause;
 837     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 838
 839     if (other_tc == other->current_tc) {
 840         tccause = other->CP0_Cause;
 841     } else {
 842         tccause = other->CP0_Cause;
 843     }
 844
 845     return tccause;
 846 }
 847
 848 target_ulong helper_mftc0_status(CPUMIPSState *env)
 849 {
 850     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 851     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 852
 853     return other->CP0_Status;
 854 }
 855
 856 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 857 {
 858     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 859 }
 860
 861 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 862 {
 863     return (int32_t)env->CP0_WatchLo[sel];
 864 }
 865
 866 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 867 {
 868     return env->CP0_WatchHi[sel];
 869 }
 870
 871 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 872 {
 873     target_ulong t0 = env->CP0_Debug;
 874     if (env->hflags & MIPS_HFLAG_DM)
 875         t0 |= 1 << CP0DB_DM;
 876
 877     return t0;
 878 }
 879
 880 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 881 {
 882     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 883     int32_t tcstatus;
 884     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 885
 886     if (other_tc == other->current_tc)
 887         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 888     else
 889         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 890
 891     /* XXX: Might be wrong, check with EJTAG spec. */
 892     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 893             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 894 }
 895
 896 #if defined(TARGET_MIPS64)
 897 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 898 {
 899     return env->active_tc.PC;
 900 }
 901
 902 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 903 {
 904     return env->active_tc.CP0_TCHalt;
 905 }
 906
 907 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 908 {
 909     return env->active_tc.CP0_TCContext;
 910 }
 911
 912 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 913 {
 914     return env->active_tc.CP0_TCSchedule;
 915 }
 916
 917 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 918 {
 919     return env->active_tc.CP0_TCScheFBack;
 920 }
 921
 922 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 923 {
 924     return env->lladdr >> env->CP0_LLAddr_shift;
 925 }
 926
 927 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 928 {
 929     return env->CP0_WatchLo[sel];
 930 }
 931 #endif /* TARGET_MIPS64 */
 932
 933 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 934 {
 935     uint32_t index_p = env->CP0_Index & 0x80000000;
 936     uint32_t tlb_index = arg1 & 0x7fffffff;
 937     if (tlb_index < env->tlb->nb_tlb) {
 938         if (env->insn_flags & ISA_MIPS32R6) {
 939             index_p |= arg1 & 0x80000000;
 940         }
 941         env->CP0_Index = index_p | tlb_index;
 942     }
 943 }
 944
 945 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 946 {
 947     uint32_t mask = 0;
 948     uint32_t newval;
 949
 950     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 951         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 952                 (1 << CP0MVPCo_EVP);
 953     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 954         mask |= (1 << CP0MVPCo_STLB);
 955     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 956
 957     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 958
 959     env->mvp->CP0_MVPControl = newval;
 960 }
 961
 962 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 963 {
 964     uint32_t mask;
 965     uint32_t newval;
 966
 967     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 968            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 969     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 970
 971     /* Yield scheduler intercept not implemented. */
 972     /* Gating storage scheduler intercept not implemented. */
 973
 974     // TODO: Enable/disable TCs.
 975
 976     env->CP0_VPEControl = newval;
 977 }
 978
 979 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 980 {
 981     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 982     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 983     uint32_t mask;
 984     uint32_t newval;
 985
 986     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 987            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 988     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 989
 990     /* TODO: Enable/disable TCs.  */
 991
 992     other->CP0_VPEControl = newval;
 993 }
 994
 995 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 996 {
 997     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 998     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 999     /* FIXME: Mask away return zero on read bits.  */
1000     return other->CP0_VPEControl;
1001 }
1002
1003 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1004 {
1005     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007
1008     return other->CP0_VPEConf0;
1009 }
1010
1011 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1012 {
1013     uint32_t mask = 0;
1014     uint32_t newval;
1015
1016     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1017         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1018             mask |= (0xff << CP0VPEC0_XTC);
1019         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1020     }
1021     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1022
1023     // TODO: TC exclusive handling due to ERL/EXL.
1024
1025     env->CP0_VPEConf0 = newval;
1026 }
1027
1028 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1029 {
1030     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1031     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1032     uint32_t mask = 0;
1033     uint32_t newval;
1034
1035     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1036     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1037
1038     /* TODO: TC exclusive handling due to ERL/EXL.  */
1039     other->CP0_VPEConf0 = newval;
1040 }
1041
1042 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1043 {
1044     uint32_t mask = 0;
1045     uint32_t newval;
1046
1047     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1048         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1049                 (0xff << CP0VPEC1_NCP1);
1050     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1051
1052     /* UDI not implemented. */
1053     /* CP2 not implemented. */
1054
1055     // TODO: Handle FPU (CP1) binding.
1056
1057     env->CP0_VPEConf1 = newval;
1058 }
1059
1060 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1061 {
1062     /* Yield qualifier inputs not implemented. */
1063     env->CP0_YQMask = 0x00000000;
1064 }
1065
1066 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1067 {
1068     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1069 }
1070
1071 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1072 {
1073     /* Large physaddr (PABITS) not implemented */
1074     /* 1k pages not implemented */
1075     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1076     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1077 }
1078
1079 #if defined(TARGET_MIPS64)
1080 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1081 {
1082     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1083     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | rxi;
1084 }
1085 #endif
1086
1087 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1088 {
1089     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1090     uint32_t newval;
1091
1092     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1093
1094     env->active_tc.CP0_TCStatus = newval;
1095     sync_c0_tcstatus(env, env->current_tc, newval);
1096 }
1097
1098 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1099 {
1100     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1101     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1102
1103     if (other_tc == other->current_tc)
1104         other->active_tc.CP0_TCStatus = arg1;
1105     else
1106         other->tcs[other_tc].CP0_TCStatus = arg1;
1107     sync_c0_tcstatus(other, other_tc, arg1);
1108 }
1109
1110 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1111 {
1112     uint32_t mask = (1 << CP0TCBd_TBE);
1113     uint32_t newval;
1114
1115     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1116         mask |= (1 << CP0TCBd_CurVPE);
1117     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1118     env->active_tc.CP0_TCBind = newval;
1119 }
1120
1121 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1122 {
1123     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1124     uint32_t mask = (1 << CP0TCBd_TBE);
1125     uint32_t newval;
1126     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1127
1128     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1129         mask |= (1 << CP0TCBd_CurVPE);
1130     if (other_tc == other->current_tc) {
1131         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1132         other->active_tc.CP0_TCBind = newval;
1133     } else {
1134         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1135         other->tcs[other_tc].CP0_TCBind = newval;
1136     }
1137 }
1138
1139 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1140 {
1141     env->active_tc.PC = arg1;
1142     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1143     env->lladdr = 0ULL;
1144     /* MIPS16 not implemented. */
1145 }
1146
1147 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1148 {
1149     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1150     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1151
1152     if (other_tc == other->current_tc) {
1153         other->active_tc.PC = arg1;
1154         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1155         other->lladdr = 0ULL;
1156         /* MIPS16 not implemented. */
1157     } else {
1158         other->tcs[other_tc].PC = arg1;
1159         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1160         other->lladdr = 0ULL;
1161         /* MIPS16 not implemented. */
1162     }
1163 }
1164
1165 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1166 {
1167     MIPSCPU *cpu = mips_env_get_cpu(env);
1168
1169     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1170
1171     // TODO: Halt TC / Restart (if allocated+active) TC.
1172     if (env->active_tc.CP0_TCHalt & 1) {
1173         mips_tc_sleep(cpu, env->current_tc);
1174     } else {
1175         mips_tc_wake(cpu, env->current_tc);
1176     }
1177 }
1178
1179 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1180 {
1181     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1182     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1183     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1184
1185     // TODO: Halt TC / Restart (if allocated+active) TC.
1186
1187     if (other_tc == other->current_tc)
1188         other->active_tc.CP0_TCHalt = arg1;
1189     else
1190         other->tcs[other_tc].CP0_TCHalt = arg1;
1191
1192     if (arg1 & 1) {
1193         mips_tc_sleep(other_cpu, other_tc);
1194     } else {
1195         mips_tc_wake(other_cpu, other_tc);
1196     }
1197 }
1198
1199 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1200 {
1201     env->active_tc.CP0_TCContext = arg1;
1202 }
1203
1204 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1205 {
1206     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1207     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1208
1209     if (other_tc == other->current_tc)
1210         other->active_tc.CP0_TCContext = arg1;
1211     else
1212         other->tcs[other_tc].CP0_TCContext = arg1;
1213 }
1214
1215 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1216 {
1217     env->active_tc.CP0_TCSchedule = arg1;
1218 }
1219
1220 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1221 {
1222     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1223     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1224
1225     if (other_tc == other->current_tc)
1226         other->active_tc.CP0_TCSchedule = arg1;
1227     else
1228         other->tcs[other_tc].CP0_TCSchedule = arg1;
1229 }
1230
1231 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1232 {
1233     env->active_tc.CP0_TCScheFBack = arg1;
1234 }
1235
1236 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1237 {
1238     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1239     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1240
1241     if (other_tc == other->current_tc)
1242         other->active_tc.CP0_TCScheFBack = arg1;
1243     else
1244         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1245 }
1246
1247 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1248 {
1249     /* Large physaddr (PABITS) not implemented */
1250     /* 1k pages not implemented */
1251     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1252     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1253 }
1254
1255 #if defined(TARGET_MIPS64)
1256 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1257 {
1258     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1259     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | rxi;
1260 }
1261 #endif
1262
1263 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1264 {
1265     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1266 }
1267
1268 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1269 {
1270     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1271     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1272         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1273          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1274          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1275         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1276     }
1277 }
1278
1279 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1280 {
1281     /* SmartMIPS not implemented */
1282     /* Large physaddr (PABITS) not implemented */
1283     /* 1k pages not implemented */
1284     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1285                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1286 }
1287
1288 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1289 {
1290     if (env->insn_flags & ISA_MIPS32R6) {
1291         if (arg1 < env->tlb->nb_tlb) {
1292             env->CP0_Wired = arg1;
1293         }
1294     } else {
1295         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1296     }
1297 }
1298
1299 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1300 {
1301     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1302 }
1303
1304 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1305 {
1306     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1307 }
1308
1309 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1310 {
1311     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1312 }
1313
1314 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1315 {
1316     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1317 }
1318
1319 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1320 {
1321     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1322 }
1323
1324 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1325 {
1326     uint32_t mask = 0x0000000F;
1327
1328     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1329         mask |= (1 << 29);
1330
1331         if (arg1 & (1 << 29)) {
1332             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1333         } else {
1334             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1335         }
1336     }
1337
1338     env->CP0_HWREna = arg1 & mask;
1339 }
1340
1341 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1342 {
1343     cpu_mips_store_count(env, arg1);
1344 }
1345
1346 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1347 {
1348     target_ulong old, val, mask;
1349     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1350     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1351         mask |= 1 << CP0EnHi_EHINV;
1352     }
1353
1354     /* 1k pages not implemented */
1355 #if defined(TARGET_MIPS64)
1356     if (env->insn_flags & ISA_MIPS32R6) {
1357         int entryhi_r = extract64(arg1, 62, 2);
1358         int config0_at = extract32(env->CP0_Config0, 13, 2);
1359         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1360         if ((entryhi_r == 2) ||
1361             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1362             /* skip EntryHi.R field if new value is reserved */
1363             mask &= ~(0x3ull << 62);
1364         }
1365     }
1366     mask &= env->SEGMask;
1367 #endif
1368     old = env->CP0_EntryHi;
1369     val = (arg1 & mask) | (old & ~mask);
1370     env->CP0_EntryHi = val;
1371     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1372         sync_c0_entryhi(env, env->current_tc);
1373     }
1374     /* If the ASID changes, flush qemu's TLB.  */
1375     if ((old & 0xFF) != (val & 0xFF))
1376         cpu_mips_tlb_flush(env, 1);
1377 }
1378
1379 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1380 {
1381     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1382     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1383
1384     other->CP0_EntryHi = arg1;
1385     sync_c0_entryhi(other, other_tc);
1386 }
1387
1388 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1389 {
1390     cpu_mips_store_compare(env, arg1);
1391 }
1392
1393 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     MIPSCPU *cpu = mips_env_get_cpu(env);
1396     uint32_t val, old;
1397
1398     old = env->CP0_Status;
1399     cpu_mips_store_status(env, arg1);
1400     val = env->CP0_Status;
1401
1402     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1403         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1404                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1405                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1406                 env->CP0_Cause);
1407         switch (env->hflags & MIPS_HFLAG_KSU) {
1408         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1409         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1410         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1411         default:
1412             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1413             break;
1414         }
1415     }
1416 }
1417
1418 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1419 {
1420     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1421     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1422     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1423
1424     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1425     sync_c0_status(env, other, other_tc);
1426 }
1427
1428 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1429 {
1430     /* vectored interrupts not implemented, no performance counters. */
1431     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1432 }
1433
1434 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1435 {
1436     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1437     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1438 }
1439
1440 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1441 {
1442     cpu_mips_store_cause(env, arg1);
1443 }
1444
1445 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1446 {
1447     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1448     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1449
1450     cpu_mips_store_cause(other, arg1);
1451 }
1452
1453 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1454 {
1455     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1456     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1457
1458     return other->CP0_EPC;
1459 }
1460
1461 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1462 {
1463     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1464     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1465
1466     return other->CP0_EBase;
1467 }
1468
1469 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1470 {
1471     /* vectored interrupts not implemented */
1472     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1473 }
1474
1475 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1476 {
1477     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1478     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1479     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1480 }
1481
1482 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1483 {
1484     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1485     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1486
1487     switch (idx) {
1488     case 0: return other->CP0_Config0;
1489     case 1: return other->CP0_Config1;
1490     case 2: return other->CP0_Config2;
1491     case 3: return other->CP0_Config3;
1492     /* 4 and 5 are reserved.  */
1493     case 6: return other->CP0_Config6;
1494     case 7: return other->CP0_Config7;
1495     default:
1496         break;
1497     }
1498     return 0;
1499 }
1500
1501 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1502 {
1503     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1504 }
1505
1506 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1507 {
1508     /* tertiary/secondary caches not implemented */
1509     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1510 }
1511
1512 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1513 {
1514     if (env->insn_flags & ASE_MICROMIPS) {
1515         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1516                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1517     }
1518 }
1519
1520 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1521 {
1522     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1523                        (arg1 & env->CP0_Config4_rw_bitmask);
1524 }
1525
1526 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1527 {
1528     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1529                        (arg1 & env->CP0_Config5_rw_bitmask);
1530     compute_hflags(env);
1531 }
1532
1533 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1534 {
1535     target_long mask = env->CP0_LLAddr_rw_bitmask;
1536     arg1 = arg1 << env->CP0_LLAddr_shift;
1537     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1538 }
1539
1540 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1541 {
1542     /* Watch exceptions for instructions, data loads, data stores
1543        not implemented. */
1544     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1545 }
1546
1547 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1548 {
1549     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1550     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1551 }
1552
1553 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1554 {
1555     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1556     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1557 }
1558
1559 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1560 {
1561     env->CP0_Framemask = arg1; /* XXX */
1562 }
1563
1564 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1567     if (arg1 & (1 << CP0DB_DM))
1568         env->hflags |= MIPS_HFLAG_DM;
1569     else
1570         env->hflags &= ~MIPS_HFLAG_DM;
1571 }
1572
1573 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1574 {
1575     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1576     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1577     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1578
1579     /* XXX: Might be wrong, check with EJTAG spec. */
1580     if (other_tc == other->current_tc)
1581         other->active_tc.CP0_Debug_tcstatus = val;
1582     else
1583         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1584     other->CP0_Debug = (other->CP0_Debug &
1585                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1586                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1587 }
1588
1589 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1590 {
1591     env->CP0_Performance0 = arg1 & 0x000007ff;
1592 }
1593
1594 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1597 }
1598
1599 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1600 {
1601     env->CP0_DataLo = arg1; /* XXX */
1602 }
1603
1604 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1605 {
1606     env->CP0_TagHi = arg1; /* XXX */
1607 }
1608
1609 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1610 {
1611     env->CP0_DataHi = arg1; /* XXX */
1612 }
1613
1614 /* MIPS MT functions */
1615 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1616 {
1617     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1618     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1619
1620     if (other_tc == other->current_tc)
1621         return other->active_tc.gpr[sel];
1622     else
1623         return other->tcs[other_tc].gpr[sel];
1624 }
1625
1626 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1627 {
1628     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1629     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1630
1631     if (other_tc == other->current_tc)
1632         return other->active_tc.LO[sel];
1633     else
1634         return other->tcs[other_tc].LO[sel];
1635 }
1636
1637 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1638 {
1639     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1640     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1641
1642     if (other_tc == other->current_tc)
1643         return other->active_tc.HI[sel];
1644     else
1645         return other->tcs[other_tc].HI[sel];
1646 }
1647
1648 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1649 {
1650     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1651     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1652
1653     if (other_tc == other->current_tc)
1654         return other->active_tc.ACX[sel];
1655     else
1656         return other->tcs[other_tc].ACX[sel];
1657 }
1658
1659 target_ulong helper_mftdsp(CPUMIPSState *env)
1660 {
1661     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1662     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1663
1664     if (other_tc == other->current_tc)
1665         return other->active_tc.DSPControl;
1666     else
1667         return other->tcs[other_tc].DSPControl;
1668 }
1669
1670 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1671 {
1672     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1673     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1674
1675     if (other_tc == other->current_tc)
1676         other->active_tc.gpr[sel] = arg1;
1677     else
1678         other->tcs[other_tc].gpr[sel] = arg1;
1679 }
1680
1681 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1682 {
1683     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1684     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1685
1686     if (other_tc == other->current_tc)
1687         other->active_tc.LO[sel] = arg1;
1688     else
1689         other->tcs[other_tc].LO[sel] = arg1;
1690 }
1691
1692 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1693 {
1694     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1695     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1696
1697     if (other_tc == other->current_tc)
1698         other->active_tc.HI[sel] = arg1;
1699     else
1700         other->tcs[other_tc].HI[sel] = arg1;
1701 }
1702
1703 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1704 {
1705     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1706     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1707
1708     if (other_tc == other->current_tc)
1709         other->active_tc.ACX[sel] = arg1;
1710     else
1711         other->tcs[other_tc].ACX[sel] = arg1;
1712 }
1713
1714 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1715 {
1716     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1717     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1718
1719     if (other_tc == other->current_tc)
1720         other->active_tc.DSPControl = arg1;
1721     else
1722         other->tcs[other_tc].DSPControl = arg1;
1723 }
1724
1725 /* MIPS MT functions */
1726 target_ulong helper_dmt(void)
1727 {
1728     // TODO
1729      return 0;
1730 }
1731
1732 target_ulong helper_emt(void)
1733 {
1734     // TODO
1735     return 0;
1736 }
1737
1738 target_ulong helper_dvpe(CPUMIPSState *env)
1739 {
1740     CPUState *other_cs = first_cpu;
1741     target_ulong prev = env->mvp->CP0_MVPControl;
1742
1743     CPU_FOREACH(other_cs) {
1744         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1745         /* Turn off all VPEs except the one executing the dvpe.  */
1746         if (&other_cpu->env != env) {
1747             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1748             mips_vpe_sleep(other_cpu);
1749         }
1750     }
1751     return prev;
1752 }
1753
1754 target_ulong helper_evpe(CPUMIPSState *env)
1755 {
1756     CPUState *other_cs = first_cpu;
1757     target_ulong prev = env->mvp->CP0_MVPControl;
1758
1759     CPU_FOREACH(other_cs) {
1760         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1761
1762         if (&other_cpu->env != env
1763             /* If the VPE is WFI, don't disturb its sleep.  */
1764             && !mips_vpe_is_wfi(other_cpu)) {
1765             /* Enable the VPE.  */
1766             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1767             mips_vpe_wake(other_cpu); /* And wake it up.  */
1768         }
1769     }
1770     return prev;
1771 }
1772 #endif /* !CONFIG_USER_ONLY */
1773
1774 void helper_fork(target_ulong arg1, target_ulong arg2)
1775 {
1776     // arg1 = rt, arg2 = rs
1777     // TODO: store to TC register
1778 }
1779
1780 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1781 {
1782     target_long arg1 = arg;
1783
1784     if (arg1 < 0) {
1785         /* No scheduling policy implemented. */
1786         if (arg1 != -2) {
1787             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1788                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1789                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1790                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1791                 helper_raise_exception(env, EXCP_THREAD);
1792             }
1793         }
1794     } else if (arg1 == 0) {
1795         if (0 /* TODO: TC underflow */) {
1796             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1797             helper_raise_exception(env, EXCP_THREAD);
1798         } else {
1799             // TODO: Deallocate TC
1800         }
1801     } else if (arg1 > 0) {
1802         /* Yield qualifier inputs not implemented. */
1803         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1804         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1805         helper_raise_exception(env, EXCP_THREAD);
1806     }
1807     return env->CP0_YQMask;
1808 }
1809
1810 #ifndef CONFIG_USER_ONLY
1811 /* TLB management */
1812 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1813 {
1814     MIPSCPU *cpu = mips_env_get_cpu(env);
1815
1816     /* Flush qemu's TLB and discard all shadowed entries.  */
1817     tlb_flush(CPU(cpu), flush_global);
1818     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1819 }
1820
1821 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1822 {
1823     /* Discard entries from env->tlb[first] onwards.  */
1824     while (env->tlb->tlb_in_use > first) {
1825         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1826     }
1827 }
1828
1829 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1830 {
1831 #if defined(TARGET_MIPS64)
1832     return extract64(entrylo, 6, 54);
1833 #else
1834     return extract64(entrylo, 6, 24) | /* PFN */
1835            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1836 #endif
1837 }
1838
1839 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1840 {
1841     r4k_tlb_t *tlb;
1842
1843     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1844     tlb = &env->tlb->mmu.r4k.tlb[idx];
1845     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1846         tlb->EHINV = 1;
1847         return;
1848     }
1849     tlb->EHINV = 0;
1850     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1851 #if defined(TARGET_MIPS64)
1852     tlb->VPN &= env->SEGMask;
1853 #endif
1854     tlb->ASID = env->CP0_EntryHi & 0xFF;
1855     tlb->PageMask = env->CP0_PageMask;
1856     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1857     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1858     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1859     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1860     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1861     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1862     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1863     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1864     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1865     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1866     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1867     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1868     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1869 }
1870
1871 void r4k_helper_tlbinv(CPUMIPSState *env)
1872 {
1873     int idx;
1874     r4k_tlb_t *tlb;
1875     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1876
1877     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1878         tlb = &env->tlb->mmu.r4k.tlb[idx];
1879         if (!tlb->G && tlb->ASID == ASID) {
1880             tlb->EHINV = 1;
1881         }
1882     }
1883     cpu_mips_tlb_flush(env, 1);
1884 }
1885
1886 void r4k_helper_tlbinvf(CPUMIPSState *env)
1887 {
1888     int idx;
1889
1890     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1891         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1892     }
1893     cpu_mips_tlb_flush(env, 1);
1894 }
1895
1896 void r4k_helper_tlbwi(CPUMIPSState *env)
1897 {
1898     r4k_tlb_t *tlb;
1899     int idx;
1900     target_ulong VPN;
1901     uint8_t ASID;
1902     bool G, V0, D0, V1, D1;
1903
1904     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1905     tlb = &env->tlb->mmu.r4k.tlb[idx];
1906     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1907 #if defined(TARGET_MIPS64)
1908     VPN &= env->SEGMask;
1909 #endif
1910     ASID = env->CP0_EntryHi & 0xff;
1911     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1912     V0 = (env->CP0_EntryLo0 & 2) != 0;
1913     D0 = (env->CP0_EntryLo0 & 4) != 0;
1914     V1 = (env->CP0_EntryLo1 & 2) != 0;
1915     D1 = (env->CP0_EntryLo1 & 4) != 0;
1916
1917     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1918        permissions on the current entry. */
1919     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1920         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1921         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1922         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1923     }
1924
1925     r4k_invalidate_tlb(env, idx, 0);
1926     r4k_fill_tlb(env, idx);
1927 }
1928
1929 void r4k_helper_tlbwr(CPUMIPSState *env)
1930 {
1931     int r = cpu_mips_get_random(env);
1932
1933     r4k_invalidate_tlb(env, r, 1);
1934     r4k_fill_tlb(env, r);
1935 }
1936
1937 void r4k_helper_tlbp(CPUMIPSState *env)
1938 {
1939     r4k_tlb_t *tlb;
1940     target_ulong mask;
1941     target_ulong tag;
1942     target_ulong VPN;
1943     uint8_t ASID;
1944     int i;
1945
1946     ASID = env->CP0_EntryHi & 0xFF;
1947     for (i = 0; i < env->tlb->nb_tlb; i++) {
1948         tlb = &env->tlb->mmu.r4k.tlb[i];
1949         /* 1k pages are not supported. */
1950         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1951         tag = env->CP0_EntryHi & ~mask;
1952         VPN = tlb->VPN & ~mask;
1953 #if defined(TARGET_MIPS64)
1954         tag &= env->SEGMask;
1955 #endif
1956         /* Check ASID, virtual page number & size */
1957         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1958             /* TLB match */
1959             env->CP0_Index = i;
1960             break;
1961         }
1962     }
1963     if (i == env->tlb->nb_tlb) {
1964         /* No match.  Discard any shadow entries, if any of them match.  */
1965         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1966             tlb = &env->tlb->mmu.r4k.tlb[i];
1967             /* 1k pages are not supported. */
1968             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1969             tag = env->CP0_EntryHi & ~mask;
1970             VPN = tlb->VPN & ~mask;
1971 #if defined(TARGET_MIPS64)
1972             tag &= env->SEGMask;
1973 #endif
1974             /* Check ASID, virtual page number & size */
1975             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1976                 r4k_mips_tlb_flush_extra (env, i);
1977                 break;
1978             }
1979         }
1980
1981         env->CP0_Index |= 0x80000000;
1982     }
1983 }
1984
1985 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
1986 {
1987 #if defined(TARGET_MIPS64)
1988     return tlb_pfn << 6;
1989 #else
1990     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
1991            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
1992 #endif
1993 }
1994
1995 void r4k_helper_tlbr(CPUMIPSState *env)
1996 {
1997     r4k_tlb_t *tlb;
1998     uint8_t ASID;
1999     int idx;
2000
2001     ASID = env->CP0_EntryHi & 0xFF;
2002     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2003     tlb = &env->tlb->mmu.r4k.tlb[idx];
2004
2005     /* If this will change the current ASID, flush qemu's TLB.  */
2006     if (ASID != tlb->ASID)
2007         cpu_mips_tlb_flush (env, 1);
2008
2009     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2010
2011     if (tlb->EHINV) {
2012         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2013         env->CP0_PageMask = 0;
2014         env->CP0_EntryLo0 = 0;
2015         env->CP0_EntryLo1 = 0;
2016     } else {
2017         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2018         env->CP0_PageMask = tlb->PageMask;
2019         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2020                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2021                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2022                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2023         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2024                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2025                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2026                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2027     }
2028 }
2029
2030 void helper_tlbwi(CPUMIPSState *env)
2031 {
2032     env->tlb->helper_tlbwi(env);
2033 }
2034
2035 void helper_tlbwr(CPUMIPSState *env)
2036 {
2037     env->tlb->helper_tlbwr(env);
2038 }
2039
2040 void helper_tlbp(CPUMIPSState *env)
2041 {
2042     env->tlb->helper_tlbp(env);
2043 }
2044
2045 void helper_tlbr(CPUMIPSState *env)
2046 {
2047     env->tlb->helper_tlbr(env);
2048 }
2049
2050 void helper_tlbinv(CPUMIPSState *env)
2051 {
2052     env->tlb->helper_tlbinv(env);
2053 }
2054
2055 void helper_tlbinvf(CPUMIPSState *env)
2056 {
2057     env->tlb->helper_tlbinvf(env);
2058 }
2059
2060 /* Specials */
2061 target_ulong helper_di(CPUMIPSState *env)
2062 {
2063     target_ulong t0 = env->CP0_Status;
2064
2065     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2066     return t0;
2067 }
2068
2069 target_ulong helper_ei(CPUMIPSState *env)
2070 {
2071     target_ulong t0 = env->CP0_Status;
2072
2073     env->CP0_Status = t0 | (1 << CP0St_IE);
2074     return t0;
2075 }
2076
2077 static void debug_pre_eret(CPUMIPSState *env)
2078 {
2079     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2080         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2081                 env->active_tc.PC, env->CP0_EPC);
2082         if (env->CP0_Status & (1 << CP0St_ERL))
2083             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2084         if (env->hflags & MIPS_HFLAG_DM)
2085             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2086         qemu_log("\n");
2087     }
2088 }
2089
2090 static void debug_post_eret(CPUMIPSState *env)
2091 {
2092     MIPSCPU *cpu = mips_env_get_cpu(env);
2093
2094     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2095         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2096                 env->active_tc.PC, env->CP0_EPC);
2097         if (env->CP0_Status & (1 << CP0St_ERL))
2098             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2099         if (env->hflags & MIPS_HFLAG_DM)
2100             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2101         switch (env->hflags & MIPS_HFLAG_KSU) {
2102         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2103         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2104         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2105         default:
2106             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2107             break;
2108         }
2109     }
2110 }
2111
2112 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2113 {
2114     env->active_tc.PC = error_pc & ~(target_ulong)1;
2115     if (error_pc & 1) {
2116         env->hflags |= MIPS_HFLAG_M16;
2117     } else {
2118         env->hflags &= ~(MIPS_HFLAG_M16);
2119     }
2120 }
2121
2122 static inline void exception_return(CPUMIPSState *env)
2123 {
2124     debug_pre_eret(env);
2125     if (env->CP0_Status & (1 << CP0St_ERL)) {
2126         set_pc(env, env->CP0_ErrorEPC);
2127         env->CP0_Status &= ~(1 << CP0St_ERL);
2128     } else {
2129         set_pc(env, env->CP0_EPC);
2130         env->CP0_Status &= ~(1 << CP0St_EXL);
2131     }
2132     compute_hflags(env);
2133     debug_post_eret(env);
2134 }
2135
2136 void helper_eret(CPUMIPSState *env)
2137 {
2138     exception_return(env);
2139     env->lladdr = 1;
2140 }
2141
2142 void helper_eretnc(CPUMIPSState *env)
2143 {
2144     exception_return(env);
2145 }
2146
2147 void helper_deret(CPUMIPSState *env)
2148 {
2149     debug_pre_eret(env);
2150     set_pc(env, env->CP0_DEPC);
2151
2152     env->hflags &= MIPS_HFLAG_DM;
2153     compute_hflags(env);
2154     debug_post_eret(env);
2155     env->lladdr = 1;
2156 }
2157 #endif /* !CONFIG_USER_ONLY */
2158
2159 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2160 {
2161     if ((env->hflags & MIPS_HFLAG_CP0) ||
2162         (env->CP0_HWREna & (1 << 0)))
2163         return env->CP0_EBase & 0x3ff;
2164     else
2165         helper_raise_exception(env, EXCP_RI);
2166
2167     return 0;
2168 }
2169
2170 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2171 {
2172     if ((env->hflags & MIPS_HFLAG_CP0) ||
2173         (env->CP0_HWREna & (1 << 1)))
2174         return env->SYNCI_Step;
2175     else
2176         helper_raise_exception(env, EXCP_RI);
2177
2178     return 0;
2179 }
2180
2181 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2182 {
2183     if ((env->hflags & MIPS_HFLAG_CP0) ||
2184         (env->CP0_HWREna & (1 << 2)))
2185         return env->CP0_Count;
2186     else
2187         helper_raise_exception(env, EXCP_RI);
2188
2189     return 0;
2190 }
2191
2192 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2193 {
2194     if ((env->hflags & MIPS_HFLAG_CP0) ||
2195         (env->CP0_HWREna & (1 << 3)))
2196         return env->CCRes;
2197     else
2198         helper_raise_exception(env, EXCP_RI);
2199
2200     return 0;
2201 }
2202
2203 void helper_pmon(CPUMIPSState *env, int function)
2204 {
2205     function /= 2;
2206     switch (function) {
2207     case 2: /* TODO: char inbyte(int waitflag); */
2208         if (env->active_tc.gpr[4] == 0)
2209             env->active_tc.gpr[2] = -1;
2210         /* Fall through */
2211     case 11: /* TODO: char inbyte (void); */
2212         env->active_tc.gpr[2] = -1;
2213         break;
2214     case 3:
2215     case 12:
2216         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2217         break;
2218     case 17:
2219         break;
2220     case 158:
2221         {
2222             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2223             printf("%s", fmt);
2224         }
2225         break;
2226     }
2227 }
2228
2229 void helper_wait(CPUMIPSState *env)
2230 {
2231     CPUState *cs = CPU(mips_env_get_cpu(env));
2232
2233     cs->halted = 1;
2234     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2235     helper_raise_exception(env, EXCP_HLT);
2236 }
2237
2238 #if !defined(CONFIG_USER_ONLY)
2239
2240 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2241                                   int access_type, int is_user,
2242                                   uintptr_t retaddr)
2243 {
2244     MIPSCPU *cpu = MIPS_CPU(cs);
2245     CPUMIPSState *env = &cpu->env;
2246     int error_code = 0;
2247     int excp;
2248
2249     env->CP0_BadVAddr = addr;
2250
2251     if (access_type == MMU_DATA_STORE) {
2252         excp = EXCP_AdES;
2253     } else {
2254         excp = EXCP_AdEL;
2255         if (access_type == MMU_INST_FETCH) {
2256             error_code |= EXCP_INST_NOTAVAIL;
2257         }
2258     }
2259
2260     do_raise_exception_err(env, excp, error_code, retaddr);
2261 }
2262
2263 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2264               uintptr_t retaddr)
2265 {
2266     int ret;
2267
2268     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2269     if (ret) {
2270         MIPSCPU *cpu = MIPS_CPU(cs);
2271         CPUMIPSState *env = &cpu->env;
2272
2273         do_raise_exception_err(env, cs->exception_index,
2274                                env->error_code, retaddr);
2275     }
2276 }
2277
2278 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2279                                 bool is_write, bool is_exec, int unused,
2280                                 unsigned size)
2281 {
2282     MIPSCPU *cpu = MIPS_CPU(cs);
2283     CPUMIPSState *env = &cpu->env;
2284
2285     /*
2286      * Raising an exception with KVM enabled will crash because it won't be from
2287      * the main execution loop so the longjmp won't have a matching setjmp.
2288      * Until we can trigger a bus error exception through KVM lets just ignore
2289      * the access.
2290      */
2291     if (kvm_enabled()) {
2292         return;
2293     }
2294
2295     if (is_exec) {
2296         helper_raise_exception(env, EXCP_IBE);
2297     } else {
2298         helper_raise_exception(env, EXCP_DBE);
2299     }
2300 }
2301 #endif /* !CONFIG_USER_ONLY */
2302
2303 /* Complex FPU operations which may need stack space. */
2304
2305 #define FLOAT_TWO32 make_float32(1 << 30)
2306 #define FLOAT_TWO64 make_float64(1ULL << 62)
2307 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2308 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2309
2310 /* convert MIPS rounding mode in FCR31 to IEEE library */
2311 unsigned int ieee_rm[] = {
2312     float_round_nearest_even,
2313     float_round_to_zero,
2314     float_round_up,
2315     float_round_down
2316 };
2317
2318 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2319 {
2320     target_ulong arg1 = 0;
2321
2322     switch (reg) {
2323     case 0:
2324         arg1 = (int32_t)env->active_fpu.fcr0;
2325         break;
2326     case 1:
2327         /* UFR Support - Read Status FR */
2328         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2329             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2330                 arg1 = (int32_t)
2331                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2332             } else {
2333                 helper_raise_exception(env, EXCP_RI);
2334             }
2335         }
2336         break;
2337     case 5:
2338         /* FRE Support - read Config5.FRE bit */
2339         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2340             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2341                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2342             } else {
2343                 helper_raise_exception(env, EXCP_RI);
2344             }
2345         }
2346         break;
2347     case 25:
2348         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2349         break;
2350     case 26:
2351         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2352         break;
2353     case 28:
2354         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2355         break;
2356     default:
2357         arg1 = (int32_t)env->active_fpu.fcr31;
2358         break;
2359     }
2360
2361     return arg1;
2362 }
2363
2364 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2365 {
2366     switch (fs) {
2367     case 1:
2368         /* UFR Alias - Reset Status FR */
2369         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2370             return;
2371         }
2372         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2373             env->CP0_Status &= ~(1 << CP0St_FR);
2374             compute_hflags(env);
2375         } else {
2376             helper_raise_exception(env, EXCP_RI);
2377         }
2378         break;
2379     case 4:
2380         /* UNFR Alias - Set Status FR */
2381         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2382             return;
2383         }
2384         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2385             env->CP0_Status |= (1 << CP0St_FR);
2386             compute_hflags(env);
2387         } else {
2388             helper_raise_exception(env, EXCP_RI);
2389         }
2390         break;
2391     case 5:
2392         /* FRE Support - clear Config5.FRE bit */
2393         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2394             return;
2395         }
2396         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2397             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2398             compute_hflags(env);
2399         } else {
2400             helper_raise_exception(env, EXCP_RI);
2401         }
2402         break;
2403     case 6:
2404         /* FRE Support - set Config5.FRE bit */
2405         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2406             return;
2407         }
2408         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2409             env->CP0_Config5 |= (1 << CP0C5_FRE);
2410             compute_hflags(env);
2411         } else {
2412             helper_raise_exception(env, EXCP_RI);
2413         }
2414         break;
2415     case 25:
2416         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2417             return;
2418         }
2419         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2420                      ((arg1 & 0x1) << 23);
2421         break;
2422     case 26:
2423         if (arg1 & 0x007c0000)
2424             return;
2425         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2426         break;
2427     case 28:
2428         if (arg1 & 0x007c0000)
2429             return;
2430         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2431                      ((arg1 & 0x4) << 22);
2432         break;
2433     case 31:
2434         if (env->insn_flags & ISA_MIPS32R6) {
2435             uint32_t mask = 0xfefc0000;
2436             env->active_fpu.fcr31 = (arg1 & ~mask) |
2437                 (env->active_fpu.fcr31 & mask);
2438         } else if (!(arg1 & 0x007c0000)) {
2439             env->active_fpu.fcr31 = arg1;
2440         }
2441         break;
2442     default:
2443         return;
2444     }
2445     /* set rounding mode */
2446     restore_rounding_mode(env);
2447     /* set flush-to-zero mode */
2448     restore_flush_mode(env);
2449     set_float_exception_flags(0, &env->active_fpu.fp_status);
2450     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2451         do_raise_exception(env, EXCP_FPE, GETPC());
2452 }
2453
2454 int ieee_ex_to_mips(int xcpt)
2455 {
2456     int ret = 0;
2457     if (xcpt) {
2458         if (xcpt & float_flag_invalid) {
2459             ret |= FP_INVALID;
2460         }
2461         if (xcpt & float_flag_overflow) {
2462             ret |= FP_OVERFLOW;
2463         }
2464         if (xcpt & float_flag_underflow) {
2465             ret |= FP_UNDERFLOW;
2466         }
2467         if (xcpt & float_flag_divbyzero) {
2468             ret |= FP_DIV0;
2469         }
2470         if (xcpt & float_flag_inexact) {
2471             ret |= FP_INEXACT;
2472         }
2473     }
2474     return ret;
2475 }
2476
2477 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2478 {
2479     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2480
2481     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2482
2483     if (tmp) {
2484         set_float_exception_flags(0, &env->active_fpu.fp_status);
2485
2486         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2487             do_raise_exception(env, EXCP_FPE, pc);
2488         } else {
2489             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2490         }
2491     }
2492 }
2493
2494 /* Float support.
2495    Single precition routines have a "s" suffix, double precision a
2496    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2497    paired single lower "pl", paired single upper "pu".  */
2498
2499 /* unary operations, modifying fp status  */
2500 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2501 {
2502     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2503     update_fcr31(env, GETPC());
2504     return fdt0;
2505 }
2506
2507 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2508 {
2509     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2510     update_fcr31(env, GETPC());
2511     return fst0;
2512 }
2513
2514 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2515 {
2516     uint64_t fdt2;
2517
2518     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2519     update_fcr31(env, GETPC());
2520     return fdt2;
2521 }
2522
2523 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2524 {
2525     uint64_t fdt2;
2526
2527     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2528     update_fcr31(env, GETPC());
2529     return fdt2;
2530 }
2531
2532 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2533 {
2534     uint64_t fdt2;
2535
2536     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2537     update_fcr31(env, GETPC());
2538     return fdt2;
2539 }
2540
2541 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2542 {
2543     uint64_t dt2;
2544
2545     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2546     if (get_float_exception_flags(&env->active_fpu.fp_status)
2547         & (float_flag_invalid | float_flag_overflow)) {
2548         dt2 = FP_TO_INT64_OVERFLOW;
2549     }
2550     update_fcr31(env, GETPC());
2551     return dt2;
2552 }
2553
2554 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2555 {
2556     uint64_t dt2;
2557
2558     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2559     if (get_float_exception_flags(&env->active_fpu.fp_status)
2560         & (float_flag_invalid | float_flag_overflow)) {
2561         dt2 = FP_TO_INT64_OVERFLOW;
2562     }
2563     update_fcr31(env, GETPC());
2564     return dt2;
2565 }
2566
2567 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2568 {
2569     uint32_t fst2;
2570     uint32_t fsth2;
2571
2572     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2573     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2574     update_fcr31(env, GETPC());
2575     return ((uint64_t)fsth2 << 32) | fst2;
2576 }
2577
2578 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2579 {
2580     uint32_t wt2;
2581     uint32_t wth2;
2582     int excp, excph;
2583
2584     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2585     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2586     if (excp & (float_flag_overflow | float_flag_invalid)) {
2587         wt2 = FP_TO_INT32_OVERFLOW;
2588     }
2589
2590     set_float_exception_flags(0, &env->active_fpu.fp_status);
2591     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2592     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2593     if (excph & (float_flag_overflow | float_flag_invalid)) {
2594         wth2 = FP_TO_INT32_OVERFLOW;
2595     }
2596
2597     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2598     update_fcr31(env, GETPC());
2599
2600     return ((uint64_t)wth2 << 32) | wt2;
2601 }
2602
2603 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2604 {
2605     uint32_t fst2;
2606
2607     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2608     update_fcr31(env, GETPC());
2609     return fst2;
2610 }
2611
2612 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2613 {
2614     uint32_t fst2;
2615
2616     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2617     update_fcr31(env, GETPC());
2618     return fst2;
2619 }
2620
2621 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2622 {
2623     uint32_t fst2;
2624
2625     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2626     update_fcr31(env, GETPC());
2627     return fst2;
2628 }
2629
2630 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2631 {
2632     uint32_t wt2;
2633
2634     wt2 = wt0;
2635     update_fcr31(env, GETPC());
2636     return wt2;
2637 }
2638
2639 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2640 {
2641     uint32_t wt2;
2642
2643     wt2 = wth0;
2644     update_fcr31(env, GETPC());
2645     return wt2;
2646 }
2647
2648 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2649 {
2650     uint32_t wt2;
2651
2652     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2653     if (get_float_exception_flags(&env->active_fpu.fp_status)
2654         & (float_flag_invalid | float_flag_overflow)) {
2655         wt2 = FP_TO_INT32_OVERFLOW;
2656     }
2657     update_fcr31(env, GETPC());
2658     return wt2;
2659 }
2660
2661 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2662 {
2663     uint32_t wt2;
2664
2665     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2666     if (get_float_exception_flags(&env->active_fpu.fp_status)
2667         & (float_flag_invalid | float_flag_overflow)) {
2668         wt2 = FP_TO_INT32_OVERFLOW;
2669     }
2670     update_fcr31(env, GETPC());
2671     return wt2;
2672 }
2673
2674 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2675 {
2676     uint64_t dt2;
2677
2678     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2679     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2680     restore_rounding_mode(env);
2681     if (get_float_exception_flags(&env->active_fpu.fp_status)
2682         & (float_flag_invalid | float_flag_overflow)) {
2683         dt2 = FP_TO_INT64_OVERFLOW;
2684     }
2685     update_fcr31(env, GETPC());
2686     return dt2;
2687 }
2688
2689 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2690 {
2691     uint64_t dt2;
2692
2693     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2694     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2695     restore_rounding_mode(env);
2696     if (get_float_exception_flags(&env->active_fpu.fp_status)
2697         & (float_flag_invalid | float_flag_overflow)) {
2698         dt2 = FP_TO_INT64_OVERFLOW;
2699     }
2700     update_fcr31(env, GETPC());
2701     return dt2;
2702 }
2703
2704 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2705 {
2706     uint32_t wt2;
2707
2708     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2709     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2710     restore_rounding_mode(env);
2711     if (get_float_exception_flags(&env->active_fpu.fp_status)
2712         & (float_flag_invalid | float_flag_overflow)) {
2713         wt2 = FP_TO_INT32_OVERFLOW;
2714     }
2715     update_fcr31(env, GETPC());
2716     return wt2;
2717 }
2718
2719 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2720 {
2721     uint32_t wt2;
2722
2723     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2724     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2725     restore_rounding_mode(env);
2726     if (get_float_exception_flags(&env->active_fpu.fp_status)
2727         & (float_flag_invalid | float_flag_overflow)) {
2728         wt2 = FP_TO_INT32_OVERFLOW;
2729     }
2730     update_fcr31(env, GETPC());
2731     return wt2;
2732 }
2733
2734 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2735 {
2736     uint64_t dt2;
2737
2738     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2739     if (get_float_exception_flags(&env->active_fpu.fp_status)
2740         & (float_flag_invalid | float_flag_overflow)) {
2741         dt2 = FP_TO_INT64_OVERFLOW;
2742     }
2743     update_fcr31(env, GETPC());
2744     return dt2;
2745 }
2746
2747 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2748 {
2749     uint64_t dt2;
2750
2751     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2752     if (get_float_exception_flags(&env->active_fpu.fp_status)
2753         & (float_flag_invalid | float_flag_overflow)) {
2754         dt2 = FP_TO_INT64_OVERFLOW;
2755     }
2756     update_fcr31(env, GETPC());
2757     return dt2;
2758 }
2759
2760 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2761 {
2762     uint32_t wt2;
2763
2764     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2765     if (get_float_exception_flags(&env->active_fpu.fp_status)
2766         & (float_flag_invalid | float_flag_overflow)) {
2767         wt2 = FP_TO_INT32_OVERFLOW;
2768     }
2769     update_fcr31(env, GETPC());
2770     return wt2;
2771 }
2772
2773 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2774 {
2775     uint32_t wt2;
2776
2777     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2778     if (get_float_exception_flags(&env->active_fpu.fp_status)
2779         & (float_flag_invalid | float_flag_overflow)) {
2780         wt2 = FP_TO_INT32_OVERFLOW;
2781     }
2782     update_fcr31(env, GETPC());
2783     return wt2;
2784 }
2785
2786 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2787 {
2788     uint64_t dt2;
2789
2790     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2791     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2792     restore_rounding_mode(env);
2793     if (get_float_exception_flags(&env->active_fpu.fp_status)
2794         & (float_flag_invalid | float_flag_overflow)) {
2795         dt2 = FP_TO_INT64_OVERFLOW;
2796     }
2797     update_fcr31(env, GETPC());
2798     return dt2;
2799 }
2800
2801 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2802 {
2803     uint64_t dt2;
2804
2805     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2806     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2807     restore_rounding_mode(env);
2808     if (get_float_exception_flags(&env->active_fpu.fp_status)
2809         & (float_flag_invalid | float_flag_overflow)) {
2810         dt2 = FP_TO_INT64_OVERFLOW;
2811     }
2812     update_fcr31(env, GETPC());
2813     return dt2;
2814 }
2815
2816 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2817 {
2818     uint32_t wt2;
2819
2820     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2821     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2822     restore_rounding_mode(env);
2823     if (get_float_exception_flags(&env->active_fpu.fp_status)
2824         & (float_flag_invalid | float_flag_overflow)) {
2825         wt2 = FP_TO_INT32_OVERFLOW;
2826     }
2827     update_fcr31(env, GETPC());
2828     return wt2;
2829 }
2830
2831 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2832 {
2833     uint32_t wt2;
2834
2835     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2836     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2837     restore_rounding_mode(env);
2838     if (get_float_exception_flags(&env->active_fpu.fp_status)
2839         & (float_flag_invalid | float_flag_overflow)) {
2840         wt2 = FP_TO_INT32_OVERFLOW;
2841     }
2842     update_fcr31(env, GETPC());
2843     return wt2;
2844 }
2845
2846 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2847 {
2848     uint64_t dt2;
2849
2850     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2851     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2852     restore_rounding_mode(env);
2853     if (get_float_exception_flags(&env->active_fpu.fp_status)
2854         & (float_flag_invalid | float_flag_overflow)) {
2855         dt2 = FP_TO_INT64_OVERFLOW;
2856     }
2857     update_fcr31(env, GETPC());
2858     return dt2;
2859 }
2860
2861 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2862 {
2863     uint64_t dt2;
2864
2865     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2866     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2867     restore_rounding_mode(env);
2868     if (get_float_exception_flags(&env->active_fpu.fp_status)
2869         & (float_flag_invalid | float_flag_overflow)) {
2870         dt2 = FP_TO_INT64_OVERFLOW;
2871     }
2872     update_fcr31(env, GETPC());
2873     return dt2;
2874 }
2875
2876 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2877 {
2878     uint32_t wt2;
2879
2880     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2881     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2882     restore_rounding_mode(env);
2883     if (get_float_exception_flags(&env->active_fpu.fp_status)
2884         & (float_flag_invalid | float_flag_overflow)) {
2885         wt2 = FP_TO_INT32_OVERFLOW;
2886     }
2887     update_fcr31(env, GETPC());
2888     return wt2;
2889 }
2890
2891 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2892 {
2893     uint32_t wt2;
2894
2895     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2896     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2897     restore_rounding_mode(env);
2898     if (get_float_exception_flags(&env->active_fpu.fp_status)
2899         & (float_flag_invalid | float_flag_overflow)) {
2900         wt2 = FP_TO_INT32_OVERFLOW;
2901     }
2902     update_fcr31(env, GETPC());
2903     return wt2;
2904 }
2905
2906 /* unary operations, not modifying fp status  */
2907 #define FLOAT_UNOP(name)                                       \
2908 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2909 {                                                              \
2910     return float64_ ## name(fdt0);                             \
2911 }                                                              \
2912 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2913 {                                                              \
2914     return float32_ ## name(fst0);                             \
2915 }                                                              \
2916 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2917 {                                                              \
2918     uint32_t wt0;                                              \
2919     uint32_t wth0;                                             \
2920                                                                \
2921     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2922     wth0 = float32_ ## name(fdt0 >> 32);                       \
2923     return ((uint64_t)wth0 << 32) | wt0;                       \
2924 }
2925 FLOAT_UNOP(abs)
2926 FLOAT_UNOP(chs)
2927 #undef FLOAT_UNOP
2928
2929 /* MIPS specific unary operations */
2930 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2931 {
2932     uint64_t fdt2;
2933
2934     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2935     update_fcr31(env, GETPC());
2936     return fdt2;
2937 }
2938
2939 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2940 {
2941     uint32_t fst2;
2942
2943     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2944     update_fcr31(env, GETPC());
2945     return fst2;
2946 }
2947
2948 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2949 {
2950     uint64_t fdt2;
2951
2952     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2953     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2954     update_fcr31(env, GETPC());
2955     return fdt2;
2956 }
2957
2958 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2959 {
2960     uint32_t fst2;
2961
2962     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2963     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2964     update_fcr31(env, GETPC());
2965     return fst2;
2966 }
2967
2968 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2969 {
2970     uint64_t fdt2;
2971
2972     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2973     update_fcr31(env, GETPC());
2974     return fdt2;
2975 }
2976
2977 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2978 {
2979     uint32_t fst2;
2980
2981     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2982     update_fcr31(env, GETPC());
2983     return fst2;
2984 }
2985
2986 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2987 {
2988     uint32_t fst2;
2989     uint32_t fsth2;
2990
2991     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2992     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2993     update_fcr31(env, GETPC());
2994     return ((uint64_t)fsth2 << 32) | fst2;
2995 }
2996
2997 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2998 {
2999     uint64_t fdt2;
3000
3001     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3002     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3003     update_fcr31(env, GETPC());
3004     return fdt2;
3005 }
3006
3007 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3008 {
3009     uint32_t fst2;
3010
3011     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3012     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3013     update_fcr31(env, GETPC());
3014     return fst2;
3015 }
3016
3017 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3018 {
3019     uint32_t fst2;
3020     uint32_t fsth2;
3021
3022     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3023     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3024     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3025     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3026     update_fcr31(env, GETPC());
3027     return ((uint64_t)fsth2 << 32) | fst2;
3028 }
3029
3030 #define FLOAT_RINT(name, bits)                                              \
3031 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3032                                           uint ## bits ## _t fs)            \
3033 {                                                                           \
3034     uint ## bits ## _t fdret;                                               \
3035                                                                             \
3036     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3037     update_fcr31(env, GETPC());                                             \
3038     return fdret;                                                           \
3039 }
3040
3041 FLOAT_RINT(rint_s, 32)
3042 FLOAT_RINT(rint_d, 64)
3043 #undef FLOAT_RINT
3044
3045 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3046 #define FLOAT_CLASS_QUIET_NAN          0x002
3047 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3048 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3049 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3050 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3051 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3052 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3053 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3054 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3055
3056 #define FLOAT_CLASS(name, bits)                                      \
3057 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3058 {                                                                    \
3059     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3060         return FLOAT_CLASS_SIGNALING_NAN;                            \
3061     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3062         return FLOAT_CLASS_QUIET_NAN;                                \
3063     } else if (float ## bits ## _is_neg(arg)) {                      \
3064         if (float ## bits ## _is_infinity(arg)) {                    \
3065             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3066         } else if (float ## bits ## _is_zero(arg)) {                 \
3067             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3068         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3069             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3070         } else {                                                     \
3071             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3072         }                                                            \
3073     } else {                                                         \
3074         if (float ## bits ## _is_infinity(arg)) {                    \
3075             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3076         } else if (float ## bits ## _is_zero(arg)) {                 \
3077             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3078         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3079             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3080         } else {                                                     \
3081             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3082         }                                                            \
3083     }                                                                \
3084 }
3085
3086 FLOAT_CLASS(class_s, 32)
3087 FLOAT_CLASS(class_d, 64)
3088 #undef FLOAT_CLASS
3089
3090 /* binary operations */
3091 #define FLOAT_BINOP(name)                                          \
3092 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3093                                      uint64_t fdt0, uint64_t fdt1) \
3094 {                                                                  \
3095     uint64_t dt2;                                                  \
3096                                                                    \
3097     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3098     update_fcr31(env, GETPC());                                    \
3099     return dt2;                                                    \
3100 }                                                                  \
3101                                                                    \
3102 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3103                                      uint32_t fst0, uint32_t fst1) \
3104 {                                                                  \
3105     uint32_t wt2;                                                  \
3106                                                                    \
3107     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3108     update_fcr31(env, GETPC());                                    \
3109     return wt2;                                                    \
3110 }                                                                  \
3111                                                                    \
3112 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3113                                       uint64_t fdt0,               \
3114                                       uint64_t fdt1)               \
3115 {                                                                  \
3116     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3117     uint32_t fsth0 = fdt0 >> 32;                                   \
3118     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3119     uint32_t fsth1 = fdt1 >> 32;                                   \
3120     uint32_t wt2;                                                  \
3121     uint32_t wth2;                                                 \
3122                                                                    \
3123     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3124     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3125     update_fcr31(env, GETPC());                                    \
3126     return ((uint64_t)wth2 << 32) | wt2;                           \
3127 }
3128
3129 FLOAT_BINOP(add)
3130 FLOAT_BINOP(sub)
3131 FLOAT_BINOP(mul)
3132 FLOAT_BINOP(div)
3133 #undef FLOAT_BINOP
3134
3135 /* MIPS specific binary operations */
3136 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3137 {
3138     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3139     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3140     update_fcr31(env, GETPC());
3141     return fdt2;
3142 }
3143
3144 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3145 {
3146     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3147     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3148     update_fcr31(env, GETPC());
3149     return fst2;
3150 }
3151
3152 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3153 {
3154     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3155     uint32_t fsth0 = fdt0 >> 32;
3156     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3157     uint32_t fsth2 = fdt2 >> 32;
3158
3159     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3160     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3161     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3162     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3163     update_fcr31(env, GETPC());
3164     return ((uint64_t)fsth2 << 32) | fst2;
3165 }
3166
3167 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3168 {
3169     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3170     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3171     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3172     update_fcr31(env, GETPC());
3173     return fdt2;
3174 }
3175
3176 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3177 {
3178     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3179     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3180     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3181     update_fcr31(env, GETPC());
3182     return fst2;
3183 }
3184
3185 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3186 {
3187     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3188     uint32_t fsth0 = fdt0 >> 32;
3189     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3190     uint32_t fsth2 = fdt2 >> 32;
3191
3192     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3193     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3194     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3195     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3196     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3197     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3198     update_fcr31(env, GETPC());
3199     return ((uint64_t)fsth2 << 32) | fst2;
3200 }
3201
3202 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3203 {
3204     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3205     uint32_t fsth0 = fdt0 >> 32;
3206     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3207     uint32_t fsth1 = fdt1 >> 32;
3208     uint32_t fst2;
3209     uint32_t fsth2;
3210
3211     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3212     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3213     update_fcr31(env, GETPC());
3214     return ((uint64_t)fsth2 << 32) | fst2;
3215 }
3216
3217 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3218 {
3219     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3220     uint32_t fsth0 = fdt0 >> 32;
3221     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3222     uint32_t fsth1 = fdt1 >> 32;
3223     uint32_t fst2;
3224     uint32_t fsth2;
3225
3226     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3227     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3228     update_fcr31(env, GETPC());
3229     return ((uint64_t)fsth2 << 32) | fst2;
3230 }
3231
3232 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3233 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3234                                           uint ## bits ## _t fs,        \
3235                                           uint ## bits ## _t ft)        \
3236 {                                                                       \
3237     uint ## bits ## _t fdret;                                           \
3238                                                                         \
3239     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3240                                            &env->active_fpu.fp_status); \
3241     update_fcr31(env, GETPC());                                         \
3242     return fdret;                                                       \
3243 }
3244
3245 FLOAT_MINMAX(max_s, 32, maxnum)
3246 FLOAT_MINMAX(max_d, 64, maxnum)
3247 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3248 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3249
3250 FLOAT_MINMAX(min_s, 32, minnum)
3251 FLOAT_MINMAX(min_d, 64, minnum)
3252 FLOAT_MINMAX(mina_s, 32, minnummag)
3253 FLOAT_MINMAX(mina_d, 64, minnummag)
3254 #undef FLOAT_MINMAX
3255
3256 /* ternary operations */
3257 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3258 {                                                                    \
3259     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3260     if ((flags) & float_muladd_negate_c) {                           \
3261         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3262     } else {                                                         \
3263         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3264     }                                                                \
3265     if ((flags) & float_muladd_negate_result) {                      \
3266         a = prefix##_chs(a);                                         \
3267     }                                                                \
3268 }
3269
3270 /* FMA based operations */
3271 #define FLOAT_FMA(name, type)                                        \
3272 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3273                                      uint64_t fdt0, uint64_t fdt1,   \
3274                                      uint64_t fdt2)                  \
3275 {                                                                    \
3276     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3277     update_fcr31(env, GETPC());                                      \
3278     return fdt0;                                                     \
3279 }                                                                    \
3280                                                                      \
3281 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3282                                      uint32_t fst0, uint32_t fst1,   \
3283                                      uint32_t fst2)                  \
3284 {                                                                    \
3285     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3286     update_fcr31(env, GETPC());                                      \
3287     return fst0;                                                     \
3288 }                                                                    \
3289                                                                      \
3290 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3291                                       uint64_t fdt0, uint64_t fdt1,  \
3292                                       uint64_t fdt2)                 \
3293 {                                                                    \
3294     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3295     uint32_t fsth0 = fdt0 >> 32;                                     \
3296     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3297     uint32_t fsth1 = fdt1 >> 32;                                     \
3298     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3299     uint32_t fsth2 = fdt2 >> 32;                                     \
3300                                                                      \
3301     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3302     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3303     update_fcr31(env, GETPC());                                      \
3304     return ((uint64_t)fsth0 << 32) | fst0;                           \
3305 }
3306 FLOAT_FMA(madd, 0)
3307 FLOAT_FMA(msub, float_muladd_negate_c)
3308 FLOAT_FMA(nmadd, float_muladd_negate_result)
3309 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3310 #undef FLOAT_FMA
3311
3312 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3313 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3314                                           uint ## bits ## _t fs,        \
3315                                           uint ## bits ## _t ft,        \
3316                                           uint ## bits ## _t fd)        \
3317 {                                                                       \
3318     uint ## bits ## _t fdret;                                           \
3319                                                                         \
3320     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3321                                      &env->active_fpu.fp_status);       \
3322     update_fcr31(env, GETPC());                                         \
3323     return fdret;                                                       \
3324 }
3325
3326 FLOAT_FMADDSUB(maddf_s, 32, 0)
3327 FLOAT_FMADDSUB(maddf_d, 64, 0)
3328 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3329 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3330 #undef FLOAT_FMADDSUB
3331
3332 /* compare operations */
3333 #define FOP_COND_D(op, cond)                                   \
3334 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3335                          uint64_t fdt1, int cc)                \
3336 {                                                              \
3337     int c;                                                     \
3338     c = cond;                                                  \
3339     update_fcr31(env, GETPC());                                \
3340     if (c)                                                     \
3341         SET_FP_COND(cc, env->active_fpu);                      \
3342     else                                                       \
3343         CLEAR_FP_COND(cc, env->active_fpu);                    \
3344 }                                                              \
3345 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3346                             uint64_t fdt1, int cc)             \
3347 {                                                              \
3348     int c;                                                     \
3349     fdt0 = float64_abs(fdt0);                                  \
3350     fdt1 = float64_abs(fdt1);                                  \
3351     c = cond;                                                  \
3352     update_fcr31(env, GETPC());                                \
3353     if (c)                                                     \
3354         SET_FP_COND(cc, env->active_fpu);                      \
3355     else                                                       \
3356         CLEAR_FP_COND(cc, env->active_fpu);                    \
3357 }
3358
3359 /* NOTE: the comma operator will make "cond" to eval to false,
3360  * but float64_unordered_quiet() is still called. */
3361 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3362 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3363 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3364 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3365 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3366 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3367 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3368 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3369 /* NOTE: the comma operator will make "cond" to eval to false,
3370  * but float64_unordered() is still called. */
3371 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3372 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3373 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3374 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3375 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3376 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3377 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3378 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3379
3380 #define FOP_COND_S(op, cond)                                   \
3381 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3382                          uint32_t fst1, int cc)                \
3383 {                                                              \
3384     int c;                                                     \
3385     c = cond;                                                  \
3386     update_fcr31(env, GETPC());                                \
3387     if (c)                                                     \
3388         SET_FP_COND(cc, env->active_fpu);                      \
3389     else                                                       \
3390         CLEAR_FP_COND(cc, env->active_fpu);                    \
3391 }                                                              \
3392 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3393                             uint32_t fst1, int cc)             \
3394 {                                                              \
3395     int c;                                                     \
3396     fst0 = float32_abs(fst0);                                  \
3397     fst1 = float32_abs(fst1);                                  \
3398     c = cond;                                                  \
3399     update_fcr31(env, GETPC());                                \
3400     if (c)                                                     \
3401         SET_FP_COND(cc, env->active_fpu);                      \
3402     else                                                       \
3403         CLEAR_FP_COND(cc, env->active_fpu);                    \
3404 }
3405
3406 /* NOTE: the comma operator will make "cond" to eval to false,
3407  * but float32_unordered_quiet() is still called. */
3408 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3409 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3410 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3411 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3412 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3413 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3414 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3415 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3416 /* NOTE: the comma operator will make "cond" to eval to false,
3417  * but float32_unordered() is still called. */
3418 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3419 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3420 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3421 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3422 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3423 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3424 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3425 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3426
3427 #define FOP_COND_PS(op, condl, condh)                           \
3428 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3429                           uint64_t fdt1, int cc)                \
3430 {                                                               \
3431     uint32_t fst0, fsth0, fst1, fsth1;                          \
3432     int ch, cl;                                                 \
3433     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3434     fsth0 = fdt0 >> 32;                                         \
3435     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3436     fsth1 = fdt1 >> 32;                                         \
3437     cl = condl;                                                 \
3438     ch = condh;                                                 \
3439     update_fcr31(env, GETPC());                                 \
3440     if (cl)                                                     \
3441         SET_FP_COND(cc, env->active_fpu);                       \
3442     else                                                        \
3443         CLEAR_FP_COND(cc, env->active_fpu);                     \
3444     if (ch)                                                     \
3445         SET_FP_COND(cc + 1, env->active_fpu);                   \
3446     else                                                        \
3447         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3448 }                                                               \
3449 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3450                              uint64_t fdt1, int cc)             \
3451 {                                                               \
3452     uint32_t fst0, fsth0, fst1, fsth1;                          \
3453     int ch, cl;                                                 \
3454     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3455     fsth0 = float32_abs(fdt0 >> 32);                            \
3456     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3457     fsth1 = float32_abs(fdt1 >> 32);                            \
3458     cl = condl;                                                 \
3459     ch = condh;                                                 \
3460     update_fcr31(env, GETPC());                                 \
3461     if (cl)                                                     \
3462         SET_FP_COND(cc, env->active_fpu);                       \
3463     else                                                        \
3464         CLEAR_FP_COND(cc, env->active_fpu);                     \
3465     if (ch)                                                     \
3466         SET_FP_COND(cc + 1, env->active_fpu);                   \
3467     else                                                        \
3468         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3469 }
3470
3471 /* NOTE: the comma operator will make "cond" to eval to false,
3472  * but float32_unordered_quiet() is still called. */
3473 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3474                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3475 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3476                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3477 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3478                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3479 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3480                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3481 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3482                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3483 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3484                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3485 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3486                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3487 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3488                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3489 /* NOTE: the comma operator will make "cond" to eval to false,
3490  * but float32_unordered() is still called. */
3491 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3492                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3493 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3494                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3495 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3496                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3497 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3498                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3499 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3500                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3501 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3502                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3503 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3504                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3505 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3506                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3507
3508 /* R6 compare operations */
3509 #define FOP_CONDN_D(op, cond)                                       \
3510 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3511                          uint64_t fdt1)                             \
3512 {                                                                   \
3513     uint64_t c;                                                     \
3514     c = cond;                                                       \
3515     update_fcr31(env, GETPC());                                     \
3516     if (c) {                                                        \
3517         return -1;                                                  \
3518     } else {                                                        \
3519         return 0;                                                   \
3520     }                                                               \
3521 }
3522
3523 /* NOTE: the comma operator will make "cond" to eval to false,
3524  * but float64_unordered_quiet() is still called. */
3525 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3526 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3527 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3528 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3529                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3530 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3531 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3532                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3533 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3534 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3535                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3536 /* NOTE: the comma operator will make "cond" to eval to false,
3537  * but float64_unordered() is still called. */
3538 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3539 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3540 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3541 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3542                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3543 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3544 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3545                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3546 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3547 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3548                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3549 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3550                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3551 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3552                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3553                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3554 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3555                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3556 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3557                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3558 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3559                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3560                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3561 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3562                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3563
3564 #define FOP_CONDN_S(op, cond)                                       \
3565 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3566                          uint32_t fst1)                             \
3567 {                                                                   \
3568     uint64_t c;                                                     \
3569     c = cond;                                                       \
3570     update_fcr31(env, GETPC());                                     \
3571     if (c) {                                                        \
3572         return -1;                                                  \
3573     } else {                                                        \
3574         return 0;                                                   \
3575     }                                                               \
3576 }
3577
3578 /* NOTE: the comma operator will make "cond" to eval to false,
3579  * but float32_unordered_quiet() is still called. */
3580 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3581 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3582 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3583 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3584                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3585 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3586 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3587                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3589 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3590                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3591 /* NOTE: the comma operator will make "cond" to eval to false,
3592  * but float32_unordered() is still called. */
3593 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3594 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3595 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3596 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3597                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3598 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3599 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3600                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3601 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3602 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3603                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3604 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3605                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3606 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3607                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3608                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3609 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3610                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3611 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3612                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3613 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3614                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3615                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3616 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3617                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3618
3619 /* MSA */
3620 /* Data format min and max values */
3621 #define DF_BITS(df) (1 << ((df) + 3))
3622
3623 /* Element-by-element access macros */
3624 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3625
3626 #if !defined(CONFIG_USER_ONLY)
3627 #define MEMOP_IDX(DF)                                           \
3628         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3629                                         cpu_mmu_index(env));
3630 #else
3631 #define MEMOP_IDX(DF)
3632 #endif
3633
3634 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3635 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3636                             target_ulong addr)                          \
3637 {                                                                       \
3638     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3639     wr_t wx;                                                            \
3640     int i;                                                              \
3641     MEMOP_IDX(DF)                                                       \
3642     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3643         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3644     }                                                                   \
3645     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3646 }
3647
3648 #if !defined(CONFIG_USER_ONLY)
3649 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3650 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3651 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3652 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3653 #else
3654 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3655 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3656 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3657 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3658 #endif
3659
3660 #define MSA_PAGESPAN(x) \
3661         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3662
3663 static inline void ensure_writable_pages(CPUMIPSState *env,
3664                                          target_ulong addr,
3665                                          int mmu_idx,
3666                                          uintptr_t retaddr)
3667 {
3668 #if !defined(CONFIG_USER_ONLY)
3669     target_ulong page_addr;
3670     if (unlikely(MSA_PAGESPAN(addr))) {
3671         /* first page */
3672         probe_write(env, addr, mmu_idx, retaddr);
3673         /* second page */
3674         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3675         probe_write(env, page_addr, mmu_idx, retaddr);
3676     }
3677 #endif
3678 }
3679
3680 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3681 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3682                             target_ulong addr)                          \
3683 {                                                                       \
3684     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3685     int mmu_idx = cpu_mmu_index(env);                                   \
3686     int i;                                                              \
3687     MEMOP_IDX(DF)                                                       \
3688     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3689     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3690         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3691     }                                                                   \
3692 }
3693
3694 #if !defined(CONFIG_USER_ONLY)
3695 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3696 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3697 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3698 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3699 #else
3700 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3701 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3702 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3703 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3704 #endif