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i.MX: Split UART emulator in a header file and a source file
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob46eddb8e48f696155e94a34d86982f44369b028b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 */
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
71
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #else
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
78 #endif
79
80 typedef struct AcpiCpuInfo {
81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
82 } AcpiCpuInfo;
83
84 typedef struct AcpiMcfgInfo {
85 uint64_t mcfg_base;
86 uint32_t mcfg_size;
87 } AcpiMcfgInfo;
88
89 typedef struct AcpiPmInfo {
90 bool s3_disabled;
91 bool s4_disabled;
92 bool pcihp_bridge_en;
93 uint8_t s4_val;
94 uint16_t sci_int;
95 uint8_t acpi_enable_cmd;
96 uint8_t acpi_disable_cmd;
97 uint32_t gpe0_blk;
98 uint32_t gpe0_blk_len;
99 uint32_t io_base;
100 uint16_t cpu_hp_io_base;
101 uint16_t cpu_hp_io_len;
102 uint16_t mem_hp_io_base;
103 uint16_t mem_hp_io_len;
104 uint16_t pcihp_io_base;
105 uint16_t pcihp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static void acpi_get_dsdt(AcpiMiscInfo *info)
125 {
126 Object *piix = piix4_pm_find();
127 Object *lpc = ich9_lpc_find();
128 assert(!!piix != !!lpc);
129
130 if (piix) {
131 info->dsdt_code = AcpiDsdtAmlCode;
132 info->dsdt_size = sizeof AcpiDsdtAmlCode;
133 }
134 if (lpc) {
135 info->dsdt_code = Q35AcpiDsdtAmlCode;
136 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
137 }
138 }
139
140 static
141 int acpi_add_cpu_info(Object *o, void *opaque)
142 {
143 AcpiCpuInfo *cpu = opaque;
144 uint64_t apic_id;
145
146 if (object_dynamic_cast(o, TYPE_CPU)) {
147 apic_id = object_property_get_int(o, "apic-id", NULL);
148 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
149
150 set_bit(apic_id, cpu->found_cpus);
151 }
152
153 object_child_foreach(o, acpi_add_cpu_info, opaque);
154 return 0;
155 }
156
157 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
158 {
159 Object *root = object_get_root();
160
161 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
162 object_child_foreach(root, acpi_add_cpu_info, cpu);
163 }
164
165 static void acpi_get_pm_info(AcpiPmInfo *pm)
166 {
167 Object *piix = piix4_pm_find();
168 Object *lpc = ich9_lpc_find();
169 Object *obj = NULL;
170 QObject *o;
171
172 pm->pcihp_io_base = 0;
173 pm->pcihp_io_len = 0;
174 if (piix) {
175 obj = piix;
176 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
177 pm->pcihp_io_base =
178 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
179 pm->pcihp_io_len =
180 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
181 }
182 if (lpc) {
183 obj = lpc;
184 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
185 }
186 assert(obj);
187
188 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
189 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
190 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
191
192 /* Fill in optional s3/s4 related properties */
193 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
194 if (o) {
195 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
196 } else {
197 pm->s3_disabled = false;
198 }
199 qobject_decref(o);
200 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
201 if (o) {
202 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
203 } else {
204 pm->s4_disabled = false;
205 }
206 qobject_decref(o);
207 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
208 if (o) {
209 pm->s4_val = qint_get_int(qobject_to_qint(o));
210 } else {
211 pm->s4_val = false;
212 }
213 qobject_decref(o);
214
215 /* Fill in mandatory properties */
216 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
217
218 pm->acpi_enable_cmd = object_property_get_int(obj,
219 ACPI_PM_PROP_ACPI_ENABLE_CMD,
220 NULL);
221 pm->acpi_disable_cmd = object_property_get_int(obj,
222 ACPI_PM_PROP_ACPI_DISABLE_CMD,
223 NULL);
224 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
225 NULL);
226 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
227 NULL);
228 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
229 NULL);
230 pm->pcihp_bridge_en =
231 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
232 NULL);
233 }
234
235 static void acpi_get_misc_info(AcpiMiscInfo *info)
236 {
237 info->has_hpet = hpet_find();
238 info->tpm_version = tpm_get_version();
239 info->pvpanic_port = pvpanic_port();
240 info->applesmc_io_base = applesmc_port();
241 }
242
243 /*
244 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
245 * On i386 arch we only have two pci hosts, so we can look only for them.
246 */
247 static Object *acpi_get_i386_pci_host(void)
248 {
249 PCIHostState *host;
250
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/i440fx", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 if (!host) {
255 host = OBJECT_CHECK(PCIHostState,
256 object_resolve_path("/machine/q35", NULL),
257 TYPE_PCI_HOST_BRIDGE);
258 }
259
260 return OBJECT(host);
261 }
262
263 static void acpi_get_pci_info(PcPciInfo *info)
264 {
265 Object *pci_host;
266
267
268 pci_host = acpi_get_i386_pci_host();
269 g_assert(pci_host);
270
271 info->w32.begin = object_property_get_int(pci_host,
272 PCI_HOST_PROP_PCI_HOLE_START,
273 NULL);
274 info->w32.end = object_property_get_int(pci_host,
275 PCI_HOST_PROP_PCI_HOLE_END,
276 NULL);
277 info->w64.begin = object_property_get_int(pci_host,
278 PCI_HOST_PROP_PCI_HOLE64_START,
279 NULL);
280 info->w64.end = object_property_get_int(pci_host,
281 PCI_HOST_PROP_PCI_HOLE64_END,
282 NULL);
283 }
284
285 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
286
287 static void acpi_align_size(GArray *blob, unsigned align)
288 {
289 /* Align size to multiple of given size. This reduces the chance
290 * we need to change size in the future (breaking cross version migration).
291 */
292 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
293 }
294
295 /* FACS */
296 static void
297 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
298 {
299 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
300 memcpy(&facs->signature, "FACS", 4);
301 facs->length = cpu_to_le32(sizeof(*facs));
302 }
303
304 /* Load chipset information in FADT */
305 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
306 {
307 fadt->model = 1;
308 fadt->reserved1 = 0;
309 fadt->sci_int = cpu_to_le16(pm->sci_int);
310 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
311 fadt->acpi_enable = pm->acpi_enable_cmd;
312 fadt->acpi_disable = pm->acpi_disable_cmd;
313 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
314 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
315 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
316 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
317 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
318 /* EVT, CNT, TMR length matches hw/acpi/core.c */
319 fadt->pm1_evt_len = 4;
320 fadt->pm1_cnt_len = 2;
321 fadt->pm_tmr_len = 4;
322 fadt->gpe0_blk_len = pm->gpe0_blk_len;
323 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
324 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
325 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
326 (1 << ACPI_FADT_F_PROC_C1) |
327 (1 << ACPI_FADT_F_SLP_BUTTON) |
328 (1 << ACPI_FADT_F_RTC_S4));
329 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
330 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
331 * For more than 8 CPUs, "Clustered Logical" mode has to be used
332 */
333 if (max_cpus > 8) {
334 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
335 }
336 }
337
338
339 /* FADT */
340 static void
341 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
342 unsigned facs, unsigned dsdt)
343 {
344 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
345
346 fadt->firmware_ctrl = cpu_to_le32(facs);
347 /* FACS address to be filled by Guest linker */
348 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
349 ACPI_BUILD_TABLE_FILE,
350 table_data, &fadt->firmware_ctrl,
351 sizeof fadt->firmware_ctrl);
352
353 fadt->dsdt = cpu_to_le32(dsdt);
354 /* DSDT address to be filled by Guest linker */
355 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
356 ACPI_BUILD_TABLE_FILE,
357 table_data, &fadt->dsdt,
358 sizeof fadt->dsdt);
359
360 fadt_setup(fadt, pm);
361
362 build_header(linker, table_data,
363 (void *)fadt, "FACP", sizeof(*fadt), 1);
364 }
365
366 static void
367 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
368 PcGuestInfo *guest_info)
369 {
370 int madt_start = table_data->len;
371
372 AcpiMultipleApicTable *madt;
373 AcpiMadtIoApic *io_apic;
374 AcpiMadtIntsrcovr *intsrcovr;
375 AcpiMadtLocalNmi *local_nmi;
376 int i;
377
378 madt = acpi_data_push(table_data, sizeof *madt);
379 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
380 madt->flags = cpu_to_le32(1);
381
382 for (i = 0; i < guest_info->apic_id_limit; i++) {
383 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
384 apic->type = ACPI_APIC_PROCESSOR;
385 apic->length = sizeof(*apic);
386 apic->processor_id = i;
387 apic->local_apic_id = i;
388 if (test_bit(i, cpu->found_cpus)) {
389 apic->flags = cpu_to_le32(1);
390 } else {
391 apic->flags = cpu_to_le32(0);
392 }
393 }
394 io_apic = acpi_data_push(table_data, sizeof *io_apic);
395 io_apic->type = ACPI_APIC_IO;
396 io_apic->length = sizeof(*io_apic);
397 #define ACPI_BUILD_IOAPIC_ID 0x0
398 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
399 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
400 io_apic->interrupt = cpu_to_le32(0);
401
402 if (guest_info->apic_xrupt_override) {
403 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
404 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
405 intsrcovr->length = sizeof(*intsrcovr);
406 intsrcovr->source = 0;
407 intsrcovr->gsi = cpu_to_le32(2);
408 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
409 }
410 for (i = 1; i < 16; i++) {
411 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
412 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
413 /* No need for a INT source override structure. */
414 continue;
415 }
416 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
417 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
418 intsrcovr->length = sizeof(*intsrcovr);
419 intsrcovr->source = i;
420 intsrcovr->gsi = cpu_to_le32(i);
421 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
422 }
423
424 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
425 local_nmi->type = ACPI_APIC_LOCAL_NMI;
426 local_nmi->length = sizeof(*local_nmi);
427 local_nmi->processor_id = 0xff; /* all processors */
428 local_nmi->flags = cpu_to_le16(0);
429 local_nmi->lint = 1; /* ACPI_LINT1 */
430
431 build_header(linker, table_data,
432 (void *)(table_data->data + madt_start), "APIC",
433 table_data->len - madt_start, 1);
434 }
435
436 /* Assign BSEL property to all buses. In the future, this can be changed
437 * to only assign to buses that support hotplug.
438 */
439 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
440 {
441 unsigned *bsel_alloc = opaque;
442 unsigned *bus_bsel;
443
444 if (qbus_is_hotpluggable(BUS(bus))) {
445 bus_bsel = g_malloc(sizeof *bus_bsel);
446
447 *bus_bsel = (*bsel_alloc)++;
448 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
449 bus_bsel, NULL);
450 }
451
452 return bsel_alloc;
453 }
454
455 static void acpi_set_pci_info(void)
456 {
457 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
458 unsigned bsel_alloc = 0;
459
460 if (bus) {
461 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
462 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
463 }
464 }
465
466 static void build_append_pcihp_notify_entry(Aml *method, int slot)
467 {
468 Aml *if_ctx;
469 int32_t devfn = PCI_DEVFN(slot, 0);
470
471 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
472 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
473 aml_append(method, if_ctx);
474 }
475
476 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
477 bool pcihp_bridge_en)
478 {
479 Aml *dev, *notify_method, *method;
480 QObject *bsel;
481 PCIBus *sec;
482 int i;
483
484 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
485 if (bsel) {
486 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
487
488 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
489 notify_method = aml_method("DVNT", 2);
490 }
491
492 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
493 DeviceClass *dc;
494 PCIDeviceClass *pc;
495 PCIDevice *pdev = bus->devices[i];
496 int slot = PCI_SLOT(i);
497 bool hotplug_enabled_dev;
498 bool bridge_in_acpi;
499
500 if (!pdev) {
501 if (bsel) { /* add hotplug slots for non present devices */
502 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
503 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
504 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
505 method = aml_method("_EJ0", 1);
506 aml_append(method,
507 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
508 );
509 aml_append(dev, method);
510 aml_append(parent_scope, dev);
511
512 build_append_pcihp_notify_entry(notify_method, slot);
513 }
514 continue;
515 }
516
517 pc = PCI_DEVICE_GET_CLASS(pdev);
518 dc = DEVICE_GET_CLASS(pdev);
519
520 /* When hotplug for bridges is enabled, bridges are
521 * described in ACPI separately (see build_pci_bus_end).
522 * In this case they aren't themselves hot-pluggable.
523 * Hotplugged bridges *are* hot-pluggable.
524 */
525 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
526 !DEVICE(pdev)->hotplugged;
527
528 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
529
530 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
531 continue;
532 }
533
534 /* start to compose PCI slot descriptor */
535 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
536 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
537
538 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
539 /* add VGA specific AML methods */
540 int s3d;
541
542 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
543 s3d = 3;
544 } else {
545 s3d = 0;
546 }
547
548 method = aml_method("_S1D", 0);
549 aml_append(method, aml_return(aml_int(0)));
550 aml_append(dev, method);
551
552 method = aml_method("_S2D", 0);
553 aml_append(method, aml_return(aml_int(0)));
554 aml_append(dev, method);
555
556 method = aml_method("_S3D", 0);
557 aml_append(method, aml_return(aml_int(s3d)));
558 aml_append(dev, method);
559 } else if (hotplug_enabled_dev) {
560 /* add _SUN/_EJ0 to make slot hotpluggable */
561 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
562
563 method = aml_method("_EJ0", 1);
564 aml_append(method,
565 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
566 );
567 aml_append(dev, method);
568
569 if (bsel) {
570 build_append_pcihp_notify_entry(notify_method, slot);
571 }
572 } else if (bridge_in_acpi) {
573 /*
574 * device is coldplugged bridge,
575 * add child device descriptions into its scope
576 */
577 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
578
579 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
580 }
581 /* slot descriptor has been composed, add it into parent context */
582 aml_append(parent_scope, dev);
583 }
584
585 if (bsel) {
586 aml_append(parent_scope, notify_method);
587 }
588
589 /* Append PCNT method to notify about events on local and child buses.
590 * Add unconditionally for root since DSDT expects it.
591 */
592 method = aml_method("PCNT", 0);
593
594 /* If bus supports hotplug select it and notify about local events */
595 if (bsel) {
596 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
597 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
598 aml_append(method,
599 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
600 );
601 aml_append(method,
602 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
603 );
604 }
605
606 /* Notify about child bus events in any case */
607 if (pcihp_bridge_en) {
608 QLIST_FOREACH(sec, &bus->child, sibling) {
609 int32_t devfn = sec->parent_dev->devfn;
610
611 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
612 }
613 }
614 aml_append(parent_scope, method);
615 qobject_decref(bsel);
616 }
617
618 /*
619 * initialize_route - Initialize the interrupt routing rule
620 * through a specific LINK:
621 * if (lnk_idx == idx)
622 * route using link 'link_name'
623 */
624 static Aml *initialize_route(Aml *route, const char *link_name,
625 Aml *lnk_idx, int idx)
626 {
627 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
628 Aml *pkg = aml_package(4);
629
630 aml_append(pkg, aml_int(0));
631 aml_append(pkg, aml_int(0));
632 aml_append(pkg, aml_name("%s", link_name));
633 aml_append(pkg, aml_int(0));
634 aml_append(if_ctx, aml_store(pkg, route));
635
636 return if_ctx;
637 }
638
639 /*
640 * build_prt - Define interrupt rounting rules
641 *
642 * Returns an array of 128 routes, one for each device,
643 * based on device location.
644 * The main goal is to equaly distribute the interrupts
645 * over the 4 existing ACPI links (works only for i440fx).
646 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
647 *
648 */
649 static Aml *build_prt(void)
650 {
651 Aml *method, *while_ctx, *pin, *res;
652
653 method = aml_method("_PRT", 0);
654 res = aml_local(0);
655 pin = aml_local(1);
656 aml_append(method, aml_store(aml_package(128), res));
657 aml_append(method, aml_store(aml_int(0), pin));
658
659 /* while (pin < 128) */
660 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
661 {
662 Aml *slot = aml_local(2);
663 Aml *lnk_idx = aml_local(3);
664 Aml *route = aml_local(4);
665
666 /* slot = pin >> 2 */
667 aml_append(while_ctx,
668 aml_store(aml_shiftright(pin, aml_int(2)), slot));
669 /* lnk_idx = (slot + pin) & 3 */
670 aml_append(while_ctx,
671 aml_store(aml_and(aml_add(pin, slot), aml_int(3)), lnk_idx));
672
673 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
674 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
675 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
676 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
677 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
678
679 /* route[0] = 0x[slot]FFFF */
680 aml_append(while_ctx,
681 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF)),
682 aml_index(route, aml_int(0))));
683 /* route[1] = pin & 3 */
684 aml_append(while_ctx,
685 aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1))));
686 /* res[pin] = route */
687 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
688 /* pin++ */
689 aml_append(while_ctx, aml_increment(pin));
690 }
691 aml_append(method, while_ctx);
692 /* return res*/
693 aml_append(method, aml_return(res));
694
695 return method;
696 }
697
698 typedef struct CrsRangeEntry {
699 uint64_t base;
700 uint64_t limit;
701 } CrsRangeEntry;
702
703 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
704 {
705 CrsRangeEntry *entry;
706
707 entry = g_malloc(sizeof(*entry));
708 entry->base = base;
709 entry->limit = limit;
710
711 g_ptr_array_add(ranges, entry);
712 }
713
714 static void crs_range_free(gpointer data)
715 {
716 CrsRangeEntry *entry = (CrsRangeEntry *)data;
717 g_free(entry);
718 }
719
720 static gint crs_range_compare(gconstpointer a, gconstpointer b)
721 {
722 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
723 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
724
725 return (int64_t)entry_a->base - (int64_t)entry_b->base;
726 }
727
728 /*
729 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
730 * interval, computes the 'free' ranges from the same interval.
731 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
732 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
733 */
734 static void crs_replace_with_free_ranges(GPtrArray *ranges,
735 uint64_t start, uint64_t end)
736 {
737 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
738 uint64_t free_base = start;
739 int i;
740
741 g_ptr_array_sort(ranges, crs_range_compare);
742 for (i = 0; i < ranges->len; i++) {
743 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
744
745 if (free_base < used->base) {
746 crs_range_insert(free_ranges, free_base, used->base - 1);
747 }
748
749 free_base = used->limit + 1;
750 }
751
752 if (free_base < end) {
753 crs_range_insert(free_ranges, free_base, end);
754 }
755
756 g_ptr_array_set_size(ranges, 0);
757 for (i = 0; i < free_ranges->len; i++) {
758 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
759 }
760
761 g_ptr_array_free(free_ranges, false);
762 }
763
764 static Aml *build_crs(PCIHostState *host,
765 GPtrArray *io_ranges, GPtrArray *mem_ranges)
766 {
767 Aml *crs = aml_resource_template();
768 uint8_t max_bus = pci_bus_num(host->bus);
769 uint8_t type;
770 int devfn;
771
772 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
773 int i;
774 uint64_t range_base, range_limit;
775 PCIDevice *dev = host->bus->devices[devfn];
776
777 if (!dev) {
778 continue;
779 }
780
781 for (i = 0; i < PCI_NUM_REGIONS; i++) {
782 PCIIORegion *r = &dev->io_regions[i];
783
784 range_base = r->addr;
785 range_limit = r->addr + r->size - 1;
786
787 /*
788 * Work-around for old bioses
789 * that do not support multiple root buses
790 */
791 if (!range_base || range_base > range_limit) {
792 continue;
793 }
794
795 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
796 aml_append(crs,
797 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
798 AML_POS_DECODE, AML_ENTIRE_RANGE,
799 0,
800 range_base,
801 range_limit,
802 0,
803 range_limit - range_base + 1));
804 crs_range_insert(io_ranges, range_base, range_limit);
805 } else { /* "memory" */
806 aml_append(crs,
807 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
808 AML_MAX_FIXED, AML_NON_CACHEABLE,
809 AML_READ_WRITE,
810 0,
811 range_base,
812 range_limit,
813 0,
814 range_limit - range_base + 1));
815 crs_range_insert(mem_ranges, range_base, range_limit);
816 }
817 }
818
819 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
820 if (type == PCI_HEADER_TYPE_BRIDGE) {
821 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
822 if (subordinate > max_bus) {
823 max_bus = subordinate;
824 }
825
826 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
827 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
828
829 /*
830 * Work-around for old bioses
831 * that do not support multiple root buses
832 */
833 if (range_base && range_base <= range_limit) {
834 aml_append(crs,
835 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
836 AML_POS_DECODE, AML_ENTIRE_RANGE,
837 0,
838 range_base,
839 range_limit,
840 0,
841 range_limit - range_base + 1));
842 crs_range_insert(io_ranges, range_base, range_limit);
843 }
844
845 range_base =
846 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
847 range_limit =
848 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
849
850 /*
851 * Work-around for old bioses
852 * that do not support multiple root buses
853 */
854 if (range_base && range_base <= range_limit) {
855 aml_append(crs,
856 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
857 AML_MAX_FIXED, AML_NON_CACHEABLE,
858 AML_READ_WRITE,
859 0,
860 range_base,
861 range_limit,
862 0,
863 range_limit - range_base + 1));
864 crs_range_insert(mem_ranges, range_base, range_limit);
865 }
866
867 range_base =
868 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
869 range_limit =
870 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
871
872 /*
873 * Work-around for old bioses
874 * that do not support multiple root buses
875 */
876 if (range_base && range_base <= range_limit) {
877 aml_append(crs,
878 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
879 AML_MAX_FIXED, AML_NON_CACHEABLE,
880 AML_READ_WRITE,
881 0,
882 range_base,
883 range_limit,
884 0,
885 range_limit - range_base + 1));
886 crs_range_insert(mem_ranges, range_base, range_limit);
887 }
888 }
889 }
890
891 aml_append(crs,
892 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
893 0,
894 pci_bus_num(host->bus),
895 max_bus,
896 0,
897 max_bus - pci_bus_num(host->bus) + 1));
898
899 return crs;
900 }
901
902 static void
903 build_ssdt(GArray *table_data, GArray *linker,
904 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
905 PcPciInfo *pci, PcGuestInfo *guest_info)
906 {
907 MachineState *machine = MACHINE(qdev_get_machine());
908 uint32_t nr_mem = machine->ram_slots;
909 unsigned acpi_cpus = guest_info->apic_id_limit;
910 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
911 PCIBus *bus = NULL;
912 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
913 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
914 CrsRangeEntry *entry;
915 int root_bus_limit = 0xFF;
916 int i;
917
918 ssdt = init_aml_allocator();
919 /* The current AML generator can cover the APIC ID range [0..255],
920 * inclusive, for VCPU hotplug. */
921 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
922 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
923
924 /* Reserve space for header */
925 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
926
927 /* Extra PCI root buses are implemented only for i440fx */
928 bus = find_i440fx();
929 if (bus) {
930 QLIST_FOREACH(bus, &bus->child, sibling) {
931 uint8_t bus_num = pci_bus_num(bus);
932 uint8_t numa_node = pci_bus_numa_node(bus);
933
934 /* look only for expander root buses */
935 if (!pci_bus_is_root(bus)) {
936 continue;
937 }
938
939 if (bus_num < root_bus_limit) {
940 root_bus_limit = bus_num - 1;
941 }
942
943 scope = aml_scope("\\_SB");
944 dev = aml_device("PC%.02X", bus_num);
945 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
946 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
947 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
948
949 if (numa_node != NUMA_NODE_UNASSIGNED) {
950 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
951 }
952
953 aml_append(dev, build_prt());
954 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
955 io_ranges, mem_ranges);
956 aml_append(dev, aml_name_decl("_CRS", crs));
957 aml_append(scope, dev);
958 aml_append(ssdt, scope);
959 }
960 }
961
962 scope = aml_scope("\\_SB.PCI0");
963 /* build PCI0._CRS */
964 crs = aml_resource_template();
965 aml_append(crs,
966 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
967 0x0000, 0x0, root_bus_limit,
968 0x0000, root_bus_limit + 1));
969 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
970
971 aml_append(crs,
972 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
973 AML_POS_DECODE, AML_ENTIRE_RANGE,
974 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
975
976 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
977 for (i = 0; i < io_ranges->len; i++) {
978 entry = g_ptr_array_index(io_ranges, i);
979 aml_append(crs,
980 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
981 AML_POS_DECODE, AML_ENTIRE_RANGE,
982 0x0000, entry->base, entry->limit,
983 0x0000, entry->limit - entry->base + 1));
984 }
985
986 aml_append(crs,
987 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
988 AML_CACHEABLE, AML_READ_WRITE,
989 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
990
991 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
992 for (i = 0; i < mem_ranges->len; i++) {
993 entry = g_ptr_array_index(mem_ranges, i);
994 aml_append(crs,
995 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
996 AML_NON_CACHEABLE, AML_READ_WRITE,
997 0, entry->base, entry->limit,
998 0, entry->limit - entry->base + 1));
999 }
1000
1001 if (pci->w64.begin) {
1002 aml_append(crs,
1003 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1004 AML_CACHEABLE, AML_READ_WRITE,
1005 0, pci->w64.begin, pci->w64.end - 1, 0,
1006 pci->w64.end - pci->w64.begin));
1007 }
1008 aml_append(scope, aml_name_decl("_CRS", crs));
1009
1010 /* reserve GPE0 block resources */
1011 dev = aml_device("GPE0");
1012 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1013 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1014 /* device present, functioning, decoding, not shown in UI */
1015 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1016 crs = aml_resource_template();
1017 aml_append(crs,
1018 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1019 );
1020 aml_append(dev, aml_name_decl("_CRS", crs));
1021 aml_append(scope, dev);
1022
1023 g_ptr_array_free(io_ranges, true);
1024 g_ptr_array_free(mem_ranges, true);
1025
1026 /* reserve PCIHP resources */
1027 if (pm->pcihp_io_len) {
1028 dev = aml_device("PHPR");
1029 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1030 aml_append(dev,
1031 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1032 /* device present, functioning, decoding, not shown in UI */
1033 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1034 crs = aml_resource_template();
1035 aml_append(crs,
1036 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1037 pm->pcihp_io_len)
1038 );
1039 aml_append(dev, aml_name_decl("_CRS", crs));
1040 aml_append(scope, dev);
1041 }
1042 aml_append(ssdt, scope);
1043
1044 /* create S3_ / S4_ / S5_ packages if necessary */
1045 scope = aml_scope("\\");
1046 if (!pm->s3_disabled) {
1047 pkg = aml_package(4);
1048 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1049 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1050 aml_append(pkg, aml_int(0)); /* reserved */
1051 aml_append(pkg, aml_int(0)); /* reserved */
1052 aml_append(scope, aml_name_decl("_S3", pkg));
1053 }
1054
1055 if (!pm->s4_disabled) {
1056 pkg = aml_package(4);
1057 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1058 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1059 aml_append(pkg, aml_int(pm->s4_val));
1060 aml_append(pkg, aml_int(0)); /* reserved */
1061 aml_append(pkg, aml_int(0)); /* reserved */
1062 aml_append(scope, aml_name_decl("_S4", pkg));
1063 }
1064
1065 pkg = aml_package(4);
1066 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1067 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1068 aml_append(pkg, aml_int(0)); /* reserved */
1069 aml_append(pkg, aml_int(0)); /* reserved */
1070 aml_append(scope, aml_name_decl("_S5", pkg));
1071 aml_append(ssdt, scope);
1072
1073 if (misc->applesmc_io_base) {
1074 scope = aml_scope("\\_SB.PCI0.ISA");
1075 dev = aml_device("SMC");
1076
1077 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1078 /* device present, functioning, decoding, not shown in UI */
1079 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1080
1081 crs = aml_resource_template();
1082 aml_append(crs,
1083 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1084 0x01, APPLESMC_MAX_DATA_LENGTH)
1085 );
1086 aml_append(crs, aml_irq_no_flags(6));
1087 aml_append(dev, aml_name_decl("_CRS", crs));
1088
1089 aml_append(scope, dev);
1090 aml_append(ssdt, scope);
1091 }
1092
1093 if (misc->pvpanic_port) {
1094 scope = aml_scope("\\_SB.PCI0.ISA");
1095
1096 dev = aml_device("PEVT");
1097 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1098
1099 crs = aml_resource_template();
1100 aml_append(crs,
1101 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1102 );
1103 aml_append(dev, aml_name_decl("_CRS", crs));
1104
1105 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1106 misc->pvpanic_port, 1));
1107 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE);
1108 aml_append(field, aml_named_field("PEPT", 8));
1109 aml_append(dev, field);
1110
1111 /* device present, functioning, decoding, shown in UI */
1112 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1113
1114 method = aml_method("RDPT", 0);
1115 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1116 aml_append(method, aml_return(aml_local(0)));
1117 aml_append(dev, method);
1118
1119 method = aml_method("WRPT", 1);
1120 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1121 aml_append(dev, method);
1122
1123 aml_append(scope, dev);
1124 aml_append(ssdt, scope);
1125 }
1126
1127 sb_scope = aml_scope("\\_SB");
1128 {
1129 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1130 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
1131 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1132 aml_append(dev,
1133 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1134 );
1135 /* device present, functioning, decoding, not shown in UI */
1136 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1137 crs = aml_resource_template();
1138 aml_append(crs,
1139 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1140 pm->cpu_hp_io_len)
1141 );
1142 aml_append(dev, aml_name_decl("_CRS", crs));
1143 aml_append(sb_scope, dev);
1144 /* declare CPU hotplug MMIO region and PRS field to access it */
1145 aml_append(sb_scope, aml_operation_region(
1146 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1147 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE);
1148 aml_append(field, aml_named_field("PRS", 256));
1149 aml_append(sb_scope, field);
1150
1151 /* build Processor object for each processor */
1152 for (i = 0; i < acpi_cpus; i++) {
1153 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1154
1155 method = aml_method("_MAT", 0);
1156 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1157 aml_append(dev, method);
1158
1159 method = aml_method("_STA", 0);
1160 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1161 aml_append(dev, method);
1162
1163 method = aml_method("_EJ0", 1);
1164 aml_append(method,
1165 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1166 );
1167 aml_append(dev, method);
1168
1169 aml_append(sb_scope, dev);
1170 }
1171
1172 /* build this code:
1173 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1174 */
1175 /* Arg0 = Processor ID = APIC ID */
1176 method = aml_method("NTFY", 2);
1177 for (i = 0; i < acpi_cpus; i++) {
1178 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1179 aml_append(ifctx,
1180 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1181 );
1182 aml_append(method, ifctx);
1183 }
1184 aml_append(sb_scope, method);
1185
1186 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1187 *
1188 * Note: The ability to create variable-sized packages was first
1189 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1190 * ith up to 255 elements. Windows guests up to win2k8 fail when
1191 * VarPackageOp is used.
1192 */
1193 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1194 aml_varpackage(acpi_cpus);
1195
1196 for (i = 0; i < acpi_cpus; i++) {
1197 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1198 aml_append(pkg, aml_int(b));
1199 }
1200 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1201
1202 /* build memory devices */
1203 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1204 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1205 aml_append(scope,
1206 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1207 );
1208
1209 crs = aml_resource_template();
1210 aml_append(crs,
1211 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1212 pm->mem_hp_io_len)
1213 );
1214 aml_append(scope, aml_name_decl("_CRS", crs));
1215
1216 aml_append(scope, aml_operation_region(
1217 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
1218 pm->mem_hp_io_base, pm->mem_hp_io_len)
1219 );
1220
1221 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1222 AML_PRESERVE);
1223 aml_append(field, /* read only */
1224 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1225 aml_append(field, /* read only */
1226 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1227 aml_append(field, /* read only */
1228 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1229 aml_append(field, /* read only */
1230 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1231 aml_append(field, /* read only */
1232 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1233 aml_append(scope, field);
1234
1235 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
1236 AML_WRITE_AS_ZEROS);
1237 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1238 aml_append(field, /* 1 if enabled, read only */
1239 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1240 aml_append(field,
1241 /*(read) 1 if has a insert event. (write) 1 to clear event */
1242 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1243 aml_append(field,
1244 /* (read) 1 if has a remove event. (write) 1 to clear event */
1245 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1));
1246 aml_append(field,
1247 /* initiates device eject, write only */
1248 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
1249 aml_append(scope, field);
1250
1251 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1252 AML_PRESERVE);
1253 aml_append(field, /* DIMM selector, write only */
1254 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1255 aml_append(field, /* _OST event code, write only */
1256 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1257 aml_append(field, /* _OST status code, write only */
1258 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1259 aml_append(scope, field);
1260
1261 aml_append(sb_scope, scope);
1262
1263 for (i = 0; i < nr_mem; i++) {
1264 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1265 const char *s;
1266
1267 dev = aml_device("MP%02X", i);
1268 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1269 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1270
1271 method = aml_method("_CRS", 0);
1272 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1273 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1274 aml_append(dev, method);
1275
1276 method = aml_method("_STA", 0);
1277 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1278 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1279 aml_append(dev, method);
1280
1281 method = aml_method("_PXM", 0);
1282 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1283 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1284 aml_append(dev, method);
1285
1286 method = aml_method("_OST", 3);
1287 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1288 aml_append(method, aml_return(aml_call4(
1289 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1290 )));
1291 aml_append(dev, method);
1292
1293 method = aml_method("_EJ0", 1);
1294 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD);
1295 aml_append(method, aml_return(aml_call2(
1296 s, aml_name("_UID"), aml_arg(0))));
1297 aml_append(dev, method);
1298
1299 aml_append(sb_scope, dev);
1300 }
1301
1302 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1303 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1304 */
1305 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1306 for (i = 0; i < nr_mem; i++) {
1307 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1308 aml_append(ifctx,
1309 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1310 );
1311 aml_append(method, ifctx);
1312 }
1313 aml_append(sb_scope, method);
1314
1315 {
1316 Object *pci_host;
1317 PCIBus *bus = NULL;
1318
1319 pci_host = acpi_get_i386_pci_host();
1320 if (pci_host) {
1321 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1322 }
1323
1324 if (bus) {
1325 Aml *scope = aml_scope("PCI0");
1326 /* Scan all PCI buses. Generate tables to support hotplug. */
1327 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1328
1329 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1330 dev = aml_device("ISA.TPM");
1331 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1332 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1333 crs = aml_resource_template();
1334 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1335 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1336 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1337 aml_append(dev, aml_name_decl("_CRS", crs));
1338 aml_append(scope, dev);
1339 }
1340
1341 aml_append(sb_scope, scope);
1342 }
1343 }
1344 aml_append(ssdt, sb_scope);
1345 }
1346
1347 /* copy AML table into ACPI tables blob and patch header there */
1348 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1349 build_header(linker, table_data,
1350 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1351 "SSDT", ssdt->buf->len, 1);
1352 free_aml_allocator();
1353 }
1354
1355 static void
1356 build_hpet(GArray *table_data, GArray *linker)
1357 {
1358 Acpi20Hpet *hpet;
1359
1360 hpet = acpi_data_push(table_data, sizeof(*hpet));
1361 /* Note timer_block_id value must be kept in sync with value advertised by
1362 * emulated hpet
1363 */
1364 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1365 hpet->addr.address = cpu_to_le64(HPET_BASE);
1366 build_header(linker, table_data,
1367 (void *)hpet, "HPET", sizeof(*hpet), 1);
1368 }
1369
1370 static void
1371 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1372 {
1373 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1374 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1375
1376 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1377 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1378 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1379
1380 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1381 false /* high memory */);
1382
1383 /* log area start address to be filled by Guest linker */
1384 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1385 ACPI_BUILD_TPMLOG_FILE,
1386 table_data, &tcpa->log_area_start_address,
1387 sizeof(tcpa->log_area_start_address));
1388
1389 build_header(linker, table_data,
1390 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1391
1392 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1393 }
1394
1395 static void
1396 build_tpm2(GArray *table_data, GArray *linker)
1397 {
1398 Acpi20TPM2 *tpm2_ptr;
1399
1400 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1401
1402 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1403 tpm2_ptr->control_area_address = cpu_to_le64(0);
1404 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1405
1406 build_header(linker, table_data,
1407 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4);
1408 }
1409
1410 typedef enum {
1411 MEM_AFFINITY_NOFLAGS = 0,
1412 MEM_AFFINITY_ENABLED = (1 << 0),
1413 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1414 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1415 } MemoryAffinityFlags;
1416
1417 static void
1418 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1419 uint64_t len, int node, MemoryAffinityFlags flags)
1420 {
1421 numamem->type = ACPI_SRAT_MEMORY;
1422 numamem->length = sizeof(*numamem);
1423 memset(numamem->proximity, 0, 4);
1424 numamem->proximity[0] = node;
1425 numamem->flags = cpu_to_le32(flags);
1426 numamem->base_addr = cpu_to_le64(base);
1427 numamem->range_length = cpu_to_le64(len);
1428 }
1429
1430 static void
1431 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1432 {
1433 AcpiSystemResourceAffinityTable *srat;
1434 AcpiSratProcessorAffinity *core;
1435 AcpiSratMemoryAffinity *numamem;
1436
1437 int i;
1438 uint64_t curnode;
1439 int srat_start, numa_start, slots;
1440 uint64_t mem_len, mem_base, next_base;
1441 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1442 ram_addr_t hotplugabble_address_space_size =
1443 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1444 NULL);
1445
1446 srat_start = table_data->len;
1447
1448 srat = acpi_data_push(table_data, sizeof *srat);
1449 srat->reserved1 = cpu_to_le32(1);
1450 core = (void *)(srat + 1);
1451
1452 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1453 core = acpi_data_push(table_data, sizeof *core);
1454 core->type = ACPI_SRAT_PROCESSOR;
1455 core->length = sizeof(*core);
1456 core->local_apic_id = i;
1457 curnode = guest_info->node_cpu[i];
1458 core->proximity_lo = curnode;
1459 memset(core->proximity_hi, 0, 3);
1460 core->local_sapic_eid = 0;
1461 core->flags = cpu_to_le32(1);
1462 }
1463
1464
1465 /* the memory map is a bit tricky, it contains at least one hole
1466 * from 640k-1M and possibly another one from 3.5G-4G.
1467 */
1468 next_base = 0;
1469 numa_start = table_data->len;
1470
1471 numamem = acpi_data_push(table_data, sizeof *numamem);
1472 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1473 next_base = 1024 * 1024;
1474 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1475 mem_base = next_base;
1476 mem_len = guest_info->node_mem[i - 1];
1477 if (i == 1) {
1478 mem_len -= 1024 * 1024;
1479 }
1480 next_base = mem_base + mem_len;
1481
1482 /* Cut out the ACPI_PCI hole */
1483 if (mem_base <= guest_info->ram_size_below_4g &&
1484 next_base > guest_info->ram_size_below_4g) {
1485 mem_len -= next_base - guest_info->ram_size_below_4g;
1486 if (mem_len > 0) {
1487 numamem = acpi_data_push(table_data, sizeof *numamem);
1488 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1489 MEM_AFFINITY_ENABLED);
1490 }
1491 mem_base = 1ULL << 32;
1492 mem_len = next_base - guest_info->ram_size_below_4g;
1493 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1494 }
1495 numamem = acpi_data_push(table_data, sizeof *numamem);
1496 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1497 MEM_AFFINITY_ENABLED);
1498 }
1499 slots = (table_data->len - numa_start) / sizeof *numamem;
1500 for (; slots < guest_info->numa_nodes + 2; slots++) {
1501 numamem = acpi_data_push(table_data, sizeof *numamem);
1502 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1503 }
1504
1505 /*
1506 * Entry is required for Windows to enable memory hotplug in OS.
1507 * Memory devices may override proximity set by this entry,
1508 * providing _PXM method if necessary.
1509 */
1510 if (hotplugabble_address_space_size) {
1511 numamem = acpi_data_push(table_data, sizeof *numamem);
1512 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
1513 hotplugabble_address_space_size, 0,
1514 MEM_AFFINITY_HOTPLUGGABLE |
1515 MEM_AFFINITY_ENABLED);
1516 }
1517
1518 build_header(linker, table_data,
1519 (void *)(table_data->data + srat_start),
1520 "SRAT",
1521 table_data->len - srat_start, 1);
1522 }
1523
1524 static void
1525 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1526 {
1527 AcpiTableMcfg *mcfg;
1528 const char *sig;
1529 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1530
1531 mcfg = acpi_data_push(table_data, len);
1532 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1533 /* Only a single allocation so no need to play with segments */
1534 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1535 mcfg->allocation[0].start_bus_number = 0;
1536 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1537
1538 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1539 * To avoid table size changes (which create migration issues),
1540 * always create the table even if there are no allocations,
1541 * but set the signature to a reserved value in this case.
1542 * ACPI spec requires OSPMs to ignore such tables.
1543 */
1544 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1545 /* Reserved signature: ignored by OSPM */
1546 sig = "QEMU";
1547 } else {
1548 sig = "MCFG";
1549 }
1550 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1551 }
1552
1553 static void
1554 build_dmar_q35(GArray *table_data, GArray *linker)
1555 {
1556 int dmar_start = table_data->len;
1557
1558 AcpiTableDmar *dmar;
1559 AcpiDmarHardwareUnit *drhd;
1560
1561 dmar = acpi_data_push(table_data, sizeof(*dmar));
1562 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1563 dmar->flags = 0; /* No intr_remap for now */
1564
1565 /* DMAR Remapping Hardware Unit Definition structure */
1566 drhd = acpi_data_push(table_data, sizeof(*drhd));
1567 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1568 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1569 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1570 drhd->pci_segment = cpu_to_le16(0);
1571 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1572
1573 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1574 "DMAR", table_data->len - dmar_start, 1);
1575 }
1576
1577 static void
1578 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1579 {
1580 AcpiTableHeader *dsdt;
1581
1582 assert(misc->dsdt_code && misc->dsdt_size);
1583
1584 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1585 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1586
1587 memset(dsdt, 0, sizeof *dsdt);
1588 build_header(linker, table_data, dsdt, "DSDT",
1589 misc->dsdt_size, 1);
1590 }
1591
1592 static GArray *
1593 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1594 {
1595 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1596
1597 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1598 true /* fseg memory */);
1599
1600 memcpy(&rsdp->signature, "RSD PTR ", 8);
1601 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1602 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1603 /* Address to be filled by Guest linker */
1604 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1605 ACPI_BUILD_TABLE_FILE,
1606 rsdp_table, &rsdp->rsdt_physical_address,
1607 sizeof rsdp->rsdt_physical_address);
1608 rsdp->checksum = 0;
1609 /* Checksum to be filled by Guest linker */
1610 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1611 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1612
1613 return rsdp_table;
1614 }
1615
1616 typedef
1617 struct AcpiBuildState {
1618 /* Copy of table in RAM (for patching). */
1619 MemoryRegion *table_mr;
1620 /* Is table patched? */
1621 uint8_t patched;
1622 PcGuestInfo *guest_info;
1623 void *rsdp;
1624 MemoryRegion *rsdp_mr;
1625 MemoryRegion *linker_mr;
1626 } AcpiBuildState;
1627
1628 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1629 {
1630 Object *pci_host;
1631 QObject *o;
1632
1633 pci_host = acpi_get_i386_pci_host();
1634 g_assert(pci_host);
1635
1636 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1637 if (!o) {
1638 return false;
1639 }
1640 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1641 qobject_decref(o);
1642
1643 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1644 assert(o);
1645 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1646 qobject_decref(o);
1647 return true;
1648 }
1649
1650 static bool acpi_has_iommu(void)
1651 {
1652 bool ambiguous;
1653 Object *intel_iommu;
1654
1655 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1656 &ambiguous);
1657 return intel_iommu && !ambiguous;
1658 }
1659
1660 static
1661 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1662 {
1663 GArray *table_offsets;
1664 unsigned facs, ssdt, dsdt, rsdt;
1665 AcpiCpuInfo cpu;
1666 AcpiPmInfo pm;
1667 AcpiMiscInfo misc;
1668 AcpiMcfgInfo mcfg;
1669 PcPciInfo pci;
1670 uint8_t *u;
1671 size_t aml_len = 0;
1672 GArray *tables_blob = tables->table_data;
1673
1674 acpi_get_cpu_info(&cpu);
1675 acpi_get_pm_info(&pm);
1676 acpi_get_dsdt(&misc);
1677 acpi_get_misc_info(&misc);
1678 acpi_get_pci_info(&pci);
1679
1680 table_offsets = g_array_new(false, true /* clear */,
1681 sizeof(uint32_t));
1682 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1683
1684 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1685 64 /* Ensure FACS is aligned */,
1686 false /* high memory */);
1687
1688 /*
1689 * FACS is pointed to by FADT.
1690 * We place it first since it's the only table that has alignment
1691 * requirements.
1692 */
1693 facs = tables_blob->len;
1694 build_facs(tables_blob, tables->linker, guest_info);
1695
1696 /* DSDT is pointed to by FADT */
1697 dsdt = tables_blob->len;
1698 build_dsdt(tables_blob, tables->linker, &misc);
1699
1700 /* Count the size of the DSDT and SSDT, we will need it for legacy
1701 * sizing of ACPI tables.
1702 */
1703 aml_len += tables_blob->len - dsdt;
1704
1705 /* ACPI tables pointed to by RSDT */
1706 acpi_add_table(table_offsets, tables_blob);
1707 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1708
1709 ssdt = tables_blob->len;
1710 acpi_add_table(table_offsets, tables_blob);
1711 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1712 guest_info);
1713 aml_len += tables_blob->len - ssdt;
1714
1715 acpi_add_table(table_offsets, tables_blob);
1716 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1717
1718 if (misc.has_hpet) {
1719 acpi_add_table(table_offsets, tables_blob);
1720 build_hpet(tables_blob, tables->linker);
1721 }
1722 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
1723 acpi_add_table(table_offsets, tables_blob);
1724 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1725
1726 if (misc.tpm_version == TPM_VERSION_2_0) {
1727 acpi_add_table(table_offsets, tables_blob);
1728 build_tpm2(tables_blob, tables->linker);
1729 }
1730 }
1731 if (guest_info->numa_nodes) {
1732 acpi_add_table(table_offsets, tables_blob);
1733 build_srat(tables_blob, tables->linker, guest_info);
1734 }
1735 if (acpi_get_mcfg(&mcfg)) {
1736 acpi_add_table(table_offsets, tables_blob);
1737 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1738 }
1739 if (acpi_has_iommu()) {
1740 acpi_add_table(table_offsets, tables_blob);
1741 build_dmar_q35(tables_blob, tables->linker);
1742 }
1743
1744 /* Add tables supplied by user (if any) */
1745 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1746 unsigned len = acpi_table_len(u);
1747
1748 acpi_add_table(table_offsets, tables_blob);
1749 g_array_append_vals(tables_blob, u, len);
1750 }
1751
1752 /* RSDT is pointed to by RSDP */
1753 rsdt = tables_blob->len;
1754 build_rsdt(tables_blob, tables->linker, table_offsets);
1755
1756 /* RSDP is in FSEG memory, so allocate it separately */
1757 build_rsdp(tables->rsdp, tables->linker, rsdt);
1758
1759 /* We'll expose it all to Guest so we want to reduce
1760 * chance of size changes.
1761 *
1762 * We used to align the tables to 4k, but of course this would
1763 * too simple to be enough. 4k turned out to be too small an
1764 * alignment very soon, and in fact it is almost impossible to
1765 * keep the table size stable for all (max_cpus, max_memory_slots)
1766 * combinations. So the table size is always 64k for pc-i440fx-2.1
1767 * and we give an error if the table grows beyond that limit.
1768 *
1769 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1770 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1771 * than 2.0 and we can always pad the smaller tables with zeros. We can
1772 * then use the exact size of the 2.0 tables.
1773 *
1774 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1775 */
1776 if (guest_info->legacy_acpi_table_size) {
1777 /* Subtracting aml_len gives the size of fixed tables. Then add the
1778 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1779 */
1780 int legacy_aml_len =
1781 guest_info->legacy_acpi_table_size +
1782 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1783 int legacy_table_size =
1784 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1785 ACPI_BUILD_ALIGN_SIZE);
1786 if (tables_blob->len > legacy_table_size) {
1787 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1788 error_report("Warning: migration may not work.");
1789 }
1790 g_array_set_size(tables_blob, legacy_table_size);
1791 } else {
1792 /* Make sure we have a buffer in case we need to resize the tables. */
1793 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1794 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1795 error_report("Warning: ACPI tables are larger than 64k.");
1796 error_report("Warning: migration may not work.");
1797 error_report("Warning: please remove CPUs, NUMA nodes, "
1798 "memory slots or PCI bridges.");
1799 }
1800 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1801 }
1802
1803 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1804
1805 /* Cleanup memory that's no longer used. */
1806 g_array_free(table_offsets, true);
1807 }
1808
1809 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1810 {
1811 uint32_t size = acpi_data_len(data);
1812
1813 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1814 memory_region_ram_resize(mr, size, &error_abort);
1815
1816 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1817 memory_region_set_dirty(mr, 0, size);
1818 }
1819
1820 static void acpi_build_update(void *build_opaque, uint32_t offset)
1821 {
1822 AcpiBuildState *build_state = build_opaque;
1823 AcpiBuildTables tables;
1824
1825 /* No state to update or already patched? Nothing to do. */
1826 if (!build_state || build_state->patched) {
1827 return;
1828 }
1829 build_state->patched = 1;
1830
1831 acpi_build_tables_init(&tables);
1832
1833 acpi_build(build_state->guest_info, &tables);
1834
1835 acpi_ram_update(build_state->table_mr, tables.table_data);
1836
1837 if (build_state->rsdp) {
1838 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1839 } else {
1840 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1841 }
1842
1843 acpi_ram_update(build_state->linker_mr, tables.linker);
1844 acpi_build_tables_cleanup(&tables, true);
1845 }
1846
1847 static void acpi_build_reset(void *build_opaque)
1848 {
1849 AcpiBuildState *build_state = build_opaque;
1850 build_state->patched = 0;
1851 }
1852
1853 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
1854 GArray *blob, const char *name,
1855 uint64_t max_size)
1856 {
1857 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1858 name, acpi_build_update, build_state);
1859 }
1860
1861 static const VMStateDescription vmstate_acpi_build = {
1862 .name = "acpi_build",
1863 .version_id = 1,
1864 .minimum_version_id = 1,
1865 .fields = (VMStateField[]) {
1866 VMSTATE_UINT8(patched, AcpiBuildState),
1867 VMSTATE_END_OF_LIST()
1868 },
1869 };
1870
1871 void acpi_setup(PcGuestInfo *guest_info)
1872 {
1873 AcpiBuildTables tables;
1874 AcpiBuildState *build_state;
1875
1876 if (!guest_info->fw_cfg) {
1877 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1878 return;
1879 }
1880
1881 if (!guest_info->has_acpi_build) {
1882 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1883 return;
1884 }
1885
1886 if (!acpi_enabled) {
1887 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1888 return;
1889 }
1890
1891 build_state = g_malloc0(sizeof *build_state);
1892
1893 build_state->guest_info = guest_info;
1894
1895 acpi_set_pci_info();
1896
1897 acpi_build_tables_init(&tables);
1898 acpi_build(build_state->guest_info, &tables);
1899
1900 /* Now expose it all to Guest */
1901 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
1902 ACPI_BUILD_TABLE_FILE,
1903 ACPI_BUILD_TABLE_MAX_SIZE);
1904 assert(build_state->table_mr != NULL);
1905
1906 build_state->linker_mr =
1907 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1908
1909 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1910 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1911
1912 if (!guest_info->rsdp_in_ram) {
1913 /*
1914 * Keep for compatibility with old machine types.
1915 * Though RSDP is small, its contents isn't immutable, so
1916 * we'll update it along with the rest of tables on guest access.
1917 */
1918 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1919
1920 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1921 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1922 acpi_build_update, build_state,
1923 build_state->rsdp, rsdp_size);
1924 build_state->rsdp_mr = NULL;
1925 } else {
1926 build_state->rsdp = NULL;
1927 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
1928 ACPI_BUILD_RSDP_FILE, 0);
1929 }
1930
1931 qemu_register_reset(acpi_build_reset, build_state);
1932 acpi_build_reset(build_state);
1933 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1934
1935 /* Cleanup tables but don't free the memory: we track it
1936 * in build_state.
1937 */
1938 acpi_build_tables_cleanup(&tables, false);
1939 }
AR7 emulation for QEMU