hw/arm/stm32f205_soc.c

   1 /*
   2  * STM32F205 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/arm/arm.h"
  27 #include "exec/address-spaces.h"
  28 #include "hw/arm/stm32f205_soc.h"
  29
  30 /* At the moment only Timer 2 to 5 are modelled */
  31 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  32     0x40000800, 0x40000C00 };
  33 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  34     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  35
  36 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  37 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  38
  39 static void stm32f205_soc_initfn(Object *obj)
  40 {
  41     STM32F205State *s = STM32F205_SOC(obj);
  42     int i;
  43
  44     object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
  45     qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
  46
  47     for (i = 0; i < STM_NUM_USARTS; i++) {
  48         object_initialize(&s->usart[i], sizeof(s->usart[i]),
  49                           TYPE_STM32F2XX_USART);
  50         qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
  51     }
  52
  53     for (i = 0; i < STM_NUM_TIMERS; i++) {
  54         object_initialize(&s->timer[i], sizeof(s->timer[i]),
  55                           TYPE_STM32F2XX_TIMER);
  56         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
  57     }
  58 }
  59
  60 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  61 {
  62     STM32F205State *s = STM32F205_SOC(dev_soc);
  63     DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
  64     SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
  65     Error *err = NULL;
  66     int i;
  67
  68     MemoryRegion *system_memory = get_system_memory();
  69     MemoryRegion *sram = g_new(MemoryRegion, 1);
  70     MemoryRegion *flash = g_new(MemoryRegion, 1);
  71     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  72
  73     memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  74                            &error_fatal);
  75     memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
  76                              flash, 0, FLASH_SIZE);
  77
  78     vmstate_register_ram_global(flash);
  79
  80     memory_region_set_readonly(flash, true);
  81     memory_region_set_readonly(flash_alias, true);
  82
  83     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
  84     memory_region_add_subregion(system_memory, 0, flash_alias);
  85
  86     memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
  87                            &error_fatal);
  88     vmstate_register_ram_global(sram);
  89     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
  90
  91     nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
  92                        s->kernel_filename, s->cpu_model);
  93
  94     /* System configuration controller */
  95     syscfgdev = DEVICE(&s->syscfg);
  96     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
  97     if (err != NULL) {
  98         error_propagate(errp, err);
  99         return;
 100     }
 101     syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
 102     sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
 103     sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
 104
 105     /* Attach UART (uses USART registers) and USART controllers */
 106     for (i = 0; i < STM_NUM_USARTS; i++) {
 107         usartdev = DEVICE(&(s->usart[i]));
 108         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 109         if (err != NULL) {
 110             error_propagate(errp, err);
 111             return;
 112         }
 113         usartbusdev = SYS_BUS_DEVICE(usartdev);
 114         sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
 115         sysbus_connect_irq(usartbusdev, 0,
 116                            qdev_get_gpio_in(nvic, usart_irq[i]));
 117     }
 118
 119     /* Timer 2 to 5 */
 120     for (i = 0; i < STM_NUM_TIMERS; i++) {
 121         timerdev = DEVICE(&(s->timer[i]));
 122         qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
 123         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 124         if (err != NULL) {
 125             error_propagate(errp, err);
 126             return;
 127         }
 128         timerbusdev = SYS_BUS_DEVICE(timerdev);
 129         sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
 130         sysbus_connect_irq(timerbusdev, 0,
 131                            qdev_get_gpio_in(nvic, timer_irq[i]));
 132     }
 133 }
 134
 135 static Property stm32f205_soc_properties[] = {
 136     DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
 137     DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
 138     DEFINE_PROP_END_OF_LIST(),
 139 };
 140
 141 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 142 {
 143     DeviceClass *dc = DEVICE_CLASS(klass);
 144
 145     dc->realize = stm32f205_soc_realize;
 146     dc->props = stm32f205_soc_properties;
 147 }
 148
 149 static const TypeInfo stm32f205_soc_info = {
 150     .name          = TYPE_STM32F205_SOC,
 151     .parent        = TYPE_SYS_BUS_DEVICE,
 152     .instance_size = sizeof(STM32F205State),
 153     .instance_init = stm32f205_soc_initfn,
 154     .class_init    = stm32f205_soc_class_init,
 155 };
 156
 157 static void stm32f205_soc_types(void)
 158 {
 159     type_register_static(&stm32f205_soc_info);
 160 }
 161
 162 type_init(stm32f205_soc_types)