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target/loongarch: Implement xvabsd
[qemu/ar7.git] / target / loongarch / disas.c
blobbbe7ad8322a6ffc4353ae3d645bfff29f165fabd
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU LoongArch Disassembler
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited.
6 */
7
8 #include "qemu/osdep.h"
9 #include "disas/dis-asm.h"
10 #include "qemu/bitops.h"
11 #include "cpu-csr.h"
12
13 typedef struct {
14 disassemble_info *info;
15 uint64_t pc;
16 uint32_t insn;
17 } DisasContext;
18
19 static inline int plus_1(DisasContext *ctx, int x)
20 {
21 return x + 1;
22 }
23
24 static inline int shl_1(DisasContext *ctx, int x)
25 {
26 return x << 1;
27 }
28
29 static inline int shl_2(DisasContext *ctx, int x)
30 {
31 return x << 2;
32 }
33
34 static inline int shl_3(DisasContext *ctx, int x)
35 {
36 return x << 3;
37 }
38
39 #define CSR_NAME(REG) \
40 [LOONGARCH_CSR_##REG] = (#REG)
41
42 static const char * const csr_names[] = {
43 CSR_NAME(CRMD),
44 CSR_NAME(PRMD),
45 CSR_NAME(EUEN),
46 CSR_NAME(MISC),
47 CSR_NAME(ECFG),
48 CSR_NAME(ESTAT),
49 CSR_NAME(ERA),
50 CSR_NAME(BADV),
51 CSR_NAME(BADI),
52 CSR_NAME(EENTRY),
53 CSR_NAME(TLBIDX),
54 CSR_NAME(TLBEHI),
55 CSR_NAME(TLBELO0),
56 CSR_NAME(TLBELO1),
57 CSR_NAME(ASID),
58 CSR_NAME(PGDL),
59 CSR_NAME(PGDH),
60 CSR_NAME(PGD),
61 CSR_NAME(PWCL),
62 CSR_NAME(PWCH),
63 CSR_NAME(STLBPS),
64 CSR_NAME(RVACFG),
65 CSR_NAME(CPUID),
66 CSR_NAME(PRCFG1),
67 CSR_NAME(PRCFG2),
68 CSR_NAME(PRCFG3),
69 CSR_NAME(SAVE(0)),
70 CSR_NAME(SAVE(1)),
71 CSR_NAME(SAVE(2)),
72 CSR_NAME(SAVE(3)),
73 CSR_NAME(SAVE(4)),
74 CSR_NAME(SAVE(5)),
75 CSR_NAME(SAVE(6)),
76 CSR_NAME(SAVE(7)),
77 CSR_NAME(SAVE(8)),
78 CSR_NAME(SAVE(9)),
79 CSR_NAME(SAVE(10)),
80 CSR_NAME(SAVE(11)),
81 CSR_NAME(SAVE(12)),
82 CSR_NAME(SAVE(13)),
83 CSR_NAME(SAVE(14)),
84 CSR_NAME(SAVE(15)),
85 CSR_NAME(TID),
86 CSR_NAME(TCFG),
87 CSR_NAME(TVAL),
88 CSR_NAME(CNTC),
89 CSR_NAME(TICLR),
90 CSR_NAME(LLBCTL),
91 CSR_NAME(IMPCTL1),
92 CSR_NAME(IMPCTL2),
93 CSR_NAME(TLBRENTRY),
94 CSR_NAME(TLBRBADV),
95 CSR_NAME(TLBRERA),
96 CSR_NAME(TLBRSAVE),
97 CSR_NAME(TLBRELO0),
98 CSR_NAME(TLBRELO1),
99 CSR_NAME(TLBREHI),
100 CSR_NAME(TLBRPRMD),
101 CSR_NAME(MERRCTL),
102 CSR_NAME(MERRINFO1),
103 CSR_NAME(MERRINFO2),
104 CSR_NAME(MERRENTRY),
105 CSR_NAME(MERRERA),
106 CSR_NAME(MERRSAVE),
107 CSR_NAME(CTAG),
108 CSR_NAME(DMW(0)),
109 CSR_NAME(DMW(1)),
110 CSR_NAME(DMW(2)),
111 CSR_NAME(DMW(3)),
112 CSR_NAME(DBG),
113 CSR_NAME(DERA),
114 CSR_NAME(DSAVE),
115 };
116
117 static const char *get_csr_name(unsigned num)
118 {
119 return ((num < ARRAY_SIZE(csr_names)) && (csr_names[num] != NULL)) ?
120 csr_names[num] : "Undefined CSR";
121 }
122
123 #define output(C, INSN, FMT, ...) \
124 { \
125 (C)->info->fprintf_func((C)->info->stream, "%08x %-9s\t" FMT, \
126 (C)->insn, INSN, ##__VA_ARGS__); \
127 }
128
129 #include "decode-insns.c.inc"
130
131 int print_insn_loongarch(bfd_vma memaddr, struct disassemble_info *info)
132 {
133 bfd_byte buffer[4];
134 uint32_t insn;
135 int status;
136
137 status = (*info->read_memory_func)(memaddr, buffer, 4, info);
138 if (status != 0) {
139 (*info->memory_error_func)(status, memaddr, info);
140 return -1;
141 }
142 insn = bfd_getl32(buffer);
143 DisasContext ctx = {
144 .info = info,
145 .pc = memaddr,
146 .insn = insn
147 };
148
149 if (!decode(&ctx, insn)) {
150 output(&ctx, "illegal", "");
151 }
152 return 4;
153 }
154
155 static void output_r_i(DisasContext *ctx, arg_r_i *a, const char *mnemonic)
156 {
157 output(ctx, mnemonic, "r%d, %d", a->rd, a->imm);
158 }
159
160 static void output_rrr(DisasContext *ctx, arg_rrr *a, const char *mnemonic)
161 {
162 output(ctx, mnemonic, "r%d, r%d, r%d", a->rd, a->rj, a->rk);
163 }
164
165 static void output_rr_i(DisasContext *ctx, arg_rr_i *a, const char *mnemonic)
166 {
167 output(ctx, mnemonic, "r%d, r%d, %d", a->rd, a->rj, a->imm);
168 }
169
170 static void output_rrr_sa(DisasContext *ctx, arg_rrr_sa *a,
171 const char *mnemonic)
172 {
173 output(ctx, mnemonic, "r%d, r%d, r%d, %d", a->rd, a->rj, a->rk, a->sa);
174 }
175
176 static void output_rr(DisasContext *ctx, arg_rr *a, const char *mnemonic)
177 {
178 output(ctx, mnemonic, "r%d, r%d", a->rd, a->rj);
179 }
180
181 static void output_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
182 const char *mnemonic)
183 {
184 output(ctx, mnemonic, "r%d, r%d, %d, %d", a->rd, a->rj, a->ms, a->ls);
185 }
186
187 static void output_hint_r_i(DisasContext *ctx, arg_hint_r_i *a,
188 const char *mnemonic)
189 {
190 output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm);
191 }
192
193 static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic)
194 {
195 output(ctx, mnemonic, "%d", a->imm);
196 }
197
198 static void output_rr_jk(DisasContext *ctx, arg_rr_jk *a,
199 const char *mnemonic)
200 {
201 output(ctx, mnemonic, "r%d, r%d", a->rj, a->rk);
202 }
203
204 static void output_ff(DisasContext *ctx, arg_ff *a, const char *mnemonic)
205 {
206 output(ctx, mnemonic, "f%d, f%d", a->fd, a->fj);
207 }
208
209 static void output_fff(DisasContext *ctx, arg_fff *a, const char *mnemonic)
210 {
211 output(ctx, mnemonic, "f%d, f%d, f%d", a->fd, a->fj, a->fk);
212 }
213
214 static void output_ffff(DisasContext *ctx, arg_ffff *a, const char *mnemonic)
215 {
216 output(ctx, mnemonic, "f%d, f%d, f%d, f%d", a->fd, a->fj, a->fk, a->fa);
217 }
218
219 static void output_fffc(DisasContext *ctx, arg_fffc *a, const char *mnemonic)
220 {
221 output(ctx, mnemonic, "f%d, f%d, f%d, %d", a->fd, a->fj, a->fk, a->ca);
222 }
223
224 static void output_fr(DisasContext *ctx, arg_fr *a, const char *mnemonic)
225 {
226 output(ctx, mnemonic, "f%d, r%d", a->fd, a->rj);
227 }
228
229 static void output_rf(DisasContext *ctx, arg_rf *a, const char *mnemonic)
230 {
231 output(ctx, mnemonic, "r%d, f%d", a->rd, a->fj);
232 }
233
234 static void output_fcsrd_r(DisasContext *ctx, arg_fcsrd_r *a,
235 const char *mnemonic)
236 {
237 output(ctx, mnemonic, "fcsr%d, r%d", a->fcsrd, a->rj);
238 }
239
240 static void output_r_fcsrs(DisasContext *ctx, arg_r_fcsrs *a,
241 const char *mnemonic)
242 {
243 output(ctx, mnemonic, "r%d, fcsr%d", a->rd, a->fcsrs);
244 }
245
246 static void output_cf(DisasContext *ctx, arg_cf *a, const char *mnemonic)
247 {
248 output(ctx, mnemonic, "fcc%d, f%d", a->cd, a->fj);
249 }
250
251 static void output_fc(DisasContext *ctx, arg_fc *a, const char *mnemonic)
252 {
253 output(ctx, mnemonic, "f%d, fcc%d", a->fd, a->cj);
254 }
255
256 static void output_cr(DisasContext *ctx, arg_cr *a, const char *mnemonic)
257 {
258 output(ctx, mnemonic, "fcc%d, r%d", a->cd, a->rj);
259 }
260
261 static void output_rc(DisasContext *ctx, arg_rc *a, const char *mnemonic)
262 {
263 output(ctx, mnemonic, "r%d, fcc%d", a->rd, a->cj);
264 }
265
266 static void output_frr(DisasContext *ctx, arg_frr *a, const char *mnemonic)
267 {
268 output(ctx, mnemonic, "f%d, r%d, r%d", a->fd, a->rj, a->rk);
269 }
270
271 static void output_fr_i(DisasContext *ctx, arg_fr_i *a, const char *mnemonic)
272 {
273 output(ctx, mnemonic, "f%d, r%d, %d", a->fd, a->rj, a->imm);
274 }
275
276 static void output_r_offs(DisasContext *ctx, arg_r_offs *a,
277 const char *mnemonic)
278 {
279 output(ctx, mnemonic, "r%d, %d # 0x%" PRIx64, a->rj, a->offs,
280 ctx->pc + a->offs);
281 }
282
283 static void output_c_offs(DisasContext *ctx, arg_c_offs *a,
284 const char *mnemonic)
285 {
286 output(ctx, mnemonic, "fcc%d, %d # 0x%" PRIx64, a->cj, a->offs,
287 ctx->pc + a->offs);
288 }
289
290 static void output_offs(DisasContext *ctx, arg_offs *a,
291 const char *mnemonic)
292 {
293 output(ctx, mnemonic, "%d # 0x%" PRIx64, a->offs, ctx->pc + a->offs);
294 }
295
296 static void output_rr_offs(DisasContext *ctx, arg_rr_offs *a,
297 const char *mnemonic)
298 {
299 output(ctx, mnemonic, "r%d, r%d, %d # 0x%" PRIx64, a->rj,
300 a->rd, a->offs, ctx->pc + a->offs);
301 }
302
303 static void output_r_csr(DisasContext *ctx, arg_r_csr *a,
304 const char *mnemonic)
305 {
306 output(ctx, mnemonic, "r%d, %d # %s", a->rd, a->csr, get_csr_name(a->csr));
307 }
308
309 static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a,
310 const char *mnemonic)
311 {
312 output(ctx, mnemonic, "r%d, r%d, %d # %s",
313 a->rd, a->rj, a->csr, get_csr_name(a->csr));
314 }
315
316 static void output_empty(DisasContext *ctx, arg_empty *a,
317 const char *mnemonic)
318 {
319 output(ctx, mnemonic, "");
320 }
321
322 static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic)
323 {
324 output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk);
325 }
326
327 static void output_cop_r_i(DisasContext *ctx, arg_cop_r_i *a,
328 const char *mnemonic)
329 {
330 output(ctx, mnemonic, "%d, r%d, %d", a->cop, a->rj, a->imm);
331 }
332
333 static void output_j_i(DisasContext *ctx, arg_j_i *a, const char *mnemonic)
334 {
335 output(ctx, mnemonic, "r%d, %d", a->rj, a->imm);
336 }
337
338 #define INSN(insn, type) \
339 static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
340 { \
341 output_##type(ctx, a, #insn); \
342 return true; \
343 }
344
345 INSN(clo_w, rr)
346 INSN(clz_w, rr)
347 INSN(cto_w, rr)
348 INSN(ctz_w, rr)
349 INSN(clo_d, rr)
350 INSN(clz_d, rr)
351 INSN(cto_d, rr)
352 INSN(ctz_d, rr)
353 INSN(revb_2h, rr)
354 INSN(revb_4h, rr)
355 INSN(revb_2w, rr)
356 INSN(revb_d, rr)
357 INSN(revh_2w, rr)
358 INSN(revh_d, rr)
359 INSN(bitrev_4b, rr)
360 INSN(bitrev_8b, rr)
361 INSN(bitrev_w, rr)
362 INSN(bitrev_d, rr)
363 INSN(ext_w_h, rr)
364 INSN(ext_w_b, rr)
365 INSN(rdtimel_w, rr)
366 INSN(rdtimeh_w, rr)
367 INSN(rdtime_d, rr)
368 INSN(cpucfg, rr)
369 INSN(asrtle_d, rr_jk)
370 INSN(asrtgt_d, rr_jk)
371 INSN(alsl_w, rrr_sa)
372 INSN(alsl_wu, rrr_sa)
373 INSN(bytepick_w, rrr_sa)
374 INSN(bytepick_d, rrr_sa)
375 INSN(add_w, rrr)
376 INSN(add_d, rrr)
377 INSN(sub_w, rrr)
378 INSN(sub_d, rrr)
379 INSN(slt, rrr)
380 INSN(sltu, rrr)
381 INSN(maskeqz, rrr)
382 INSN(masknez, rrr)
383 INSN(nor, rrr)
384 INSN(and, rrr)
385 INSN(or, rrr)
386 INSN(xor, rrr)
387 INSN(orn, rrr)
388 INSN(andn, rrr)
389 INSN(sll_w, rrr)
390 INSN(srl_w, rrr)
391 INSN(sra_w, rrr)
392 INSN(sll_d, rrr)
393 INSN(srl_d, rrr)
394 INSN(sra_d, rrr)
395 INSN(rotr_w, rrr)
396 INSN(rotr_d, rrr)
397 INSN(mul_w, rrr)
398 INSN(mulh_w, rrr)
399 INSN(mulh_wu, rrr)
400 INSN(mul_d, rrr)
401 INSN(mulh_d, rrr)
402 INSN(mulh_du, rrr)
403 INSN(mulw_d_w, rrr)
404 INSN(mulw_d_wu, rrr)
405 INSN(div_w, rrr)
406 INSN(mod_w, rrr)
407 INSN(div_wu, rrr)
408 INSN(mod_wu, rrr)
409 INSN(div_d, rrr)
410 INSN(mod_d, rrr)
411 INSN(div_du, rrr)
412 INSN(mod_du, rrr)
413 INSN(crc_w_b_w, rrr)
414 INSN(crc_w_h_w, rrr)
415 INSN(crc_w_w_w, rrr)
416 INSN(crc_w_d_w, rrr)
417 INSN(crcc_w_b_w, rrr)
418 INSN(crcc_w_h_w, rrr)
419 INSN(crcc_w_w_w, rrr)
420 INSN(crcc_w_d_w, rrr)
421 INSN(break, i)
422 INSN(syscall, i)
423 INSN(alsl_d, rrr_sa)
424 INSN(slli_w, rr_i)
425 INSN(slli_d, rr_i)
426 INSN(srli_w, rr_i)
427 INSN(srli_d, rr_i)
428 INSN(srai_w, rr_i)
429 INSN(srai_d, rr_i)
430 INSN(rotri_w, rr_i)
431 INSN(rotri_d, rr_i)
432 INSN(bstrins_w, rr_ms_ls)
433 INSN(bstrpick_w, rr_ms_ls)
434 INSN(bstrins_d, rr_ms_ls)
435 INSN(bstrpick_d, rr_ms_ls)
436 INSN(fadd_s, fff)
437 INSN(fadd_d, fff)
438 INSN(fsub_s, fff)
439 INSN(fsub_d, fff)
440 INSN(fmul_s, fff)
441 INSN(fmul_d, fff)
442 INSN(fdiv_s, fff)
443 INSN(fdiv_d, fff)
444 INSN(fmax_s, fff)
445 INSN(fmax_d, fff)
446 INSN(fmin_s, fff)
447 INSN(fmin_d, fff)
448 INSN(fmaxa_s, fff)
449 INSN(fmaxa_d, fff)
450 INSN(fmina_s, fff)
451 INSN(fmina_d, fff)
452 INSN(fscaleb_s, fff)
453 INSN(fscaleb_d, fff)
454 INSN(fcopysign_s, fff)
455 INSN(fcopysign_d, fff)
456 INSN(fabs_s, ff)
457 INSN(fabs_d, ff)
458 INSN(fneg_s, ff)
459 INSN(fneg_d, ff)
460 INSN(flogb_s, ff)
461 INSN(flogb_d, ff)
462 INSN(fclass_s, ff)
463 INSN(fclass_d, ff)
464 INSN(fsqrt_s, ff)
465 INSN(fsqrt_d, ff)
466 INSN(frecip_s, ff)
467 INSN(frecip_d, ff)
468 INSN(frsqrt_s, ff)
469 INSN(frsqrt_d, ff)
470 INSN(fmov_s, ff)
471 INSN(fmov_d, ff)
472 INSN(movgr2fr_w, fr)
473 INSN(movgr2fr_d, fr)
474 INSN(movgr2frh_w, fr)
475 INSN(movfr2gr_s, rf)
476 INSN(movfr2gr_d, rf)
477 INSN(movfrh2gr_s, rf)
478 INSN(movgr2fcsr, fcsrd_r)
479 INSN(movfcsr2gr, r_fcsrs)
480 INSN(movfr2cf, cf)
481 INSN(movcf2fr, fc)
482 INSN(movgr2cf, cr)
483 INSN(movcf2gr, rc)
484 INSN(fcvt_s_d, ff)
485 INSN(fcvt_d_s, ff)
486 INSN(ftintrm_w_s, ff)
487 INSN(ftintrm_w_d, ff)
488 INSN(ftintrm_l_s, ff)
489 INSN(ftintrm_l_d, ff)
490 INSN(ftintrp_w_s, ff)
491 INSN(ftintrp_w_d, ff)
492 INSN(ftintrp_l_s, ff)
493 INSN(ftintrp_l_d, ff)
494 INSN(ftintrz_w_s, ff)
495 INSN(ftintrz_w_d, ff)
496 INSN(ftintrz_l_s, ff)
497 INSN(ftintrz_l_d, ff)
498 INSN(ftintrne_w_s, ff)
499 INSN(ftintrne_w_d, ff)
500 INSN(ftintrne_l_s, ff)
501 INSN(ftintrne_l_d, ff)
502 INSN(ftint_w_s, ff)
503 INSN(ftint_w_d, ff)
504 INSN(ftint_l_s, ff)
505 INSN(ftint_l_d, ff)
506 INSN(ffint_s_w, ff)
507 INSN(ffint_s_l, ff)
508 INSN(ffint_d_w, ff)
509 INSN(ffint_d_l, ff)
510 INSN(frint_s, ff)
511 INSN(frint_d, ff)
512 INSN(slti, rr_i)
513 INSN(sltui, rr_i)
514 INSN(addi_w, rr_i)
515 INSN(addi_d, rr_i)
516 INSN(lu52i_d, rr_i)
517 INSN(andi, rr_i)
518 INSN(ori, rr_i)
519 INSN(xori, rr_i)
520 INSN(fmadd_s, ffff)
521 INSN(fmadd_d, ffff)
522 INSN(fmsub_s, ffff)
523 INSN(fmsub_d, ffff)
524 INSN(fnmadd_s, ffff)
525 INSN(fnmadd_d, ffff)
526 INSN(fnmsub_s, ffff)
527 INSN(fnmsub_d, ffff)
528 INSN(fsel, fffc)
529 INSN(addu16i_d, rr_i)
530 INSN(lu12i_w, r_i)
531 INSN(lu32i_d, r_i)
532 INSN(ll_w, rr_i)
533 INSN(sc_w, rr_i)
534 INSN(ll_d, rr_i)
535 INSN(sc_d, rr_i)
536 INSN(ldptr_w, rr_i)
537 INSN(stptr_w, rr_i)
538 INSN(ldptr_d, rr_i)
539 INSN(stptr_d, rr_i)
540 INSN(ld_b, rr_i)
541 INSN(ld_h, rr_i)
542 INSN(ld_w, rr_i)
543 INSN(ld_d, rr_i)
544 INSN(st_b, rr_i)
545 INSN(st_h, rr_i)
546 INSN(st_w, rr_i)
547 INSN(st_d, rr_i)
548 INSN(ld_bu, rr_i)
549 INSN(ld_hu, rr_i)
550 INSN(ld_wu, rr_i)
551 INSN(preld, hint_r_i)
552 INSN(fld_s, fr_i)
553 INSN(fst_s, fr_i)
554 INSN(fld_d, fr_i)
555 INSN(fst_d, fr_i)
556 INSN(ldx_b, rrr)
557 INSN(ldx_h, rrr)
558 INSN(ldx_w, rrr)
559 INSN(ldx_d, rrr)
560 INSN(stx_b, rrr)
561 INSN(stx_h, rrr)
562 INSN(stx_w, rrr)
563 INSN(stx_d, rrr)
564 INSN(ldx_bu, rrr)
565 INSN(ldx_hu, rrr)
566 INSN(ldx_wu, rrr)
567 INSN(fldx_s, frr)
568 INSN(fldx_d, frr)
569 INSN(fstx_s, frr)
570 INSN(fstx_d, frr)
571 INSN(amswap_w, rrr)
572 INSN(amswap_d, rrr)
573 INSN(amadd_w, rrr)
574 INSN(amadd_d, rrr)
575 INSN(amand_w, rrr)
576 INSN(amand_d, rrr)
577 INSN(amor_w, rrr)
578 INSN(amor_d, rrr)
579 INSN(amxor_w, rrr)
580 INSN(amxor_d, rrr)
581 INSN(ammax_w, rrr)
582 INSN(ammax_d, rrr)
583 INSN(ammin_w, rrr)
584 INSN(ammin_d, rrr)
585 INSN(ammax_wu, rrr)
586 INSN(ammax_du, rrr)
587 INSN(ammin_wu, rrr)
588 INSN(ammin_du, rrr)
589 INSN(amswap_db_w, rrr)
590 INSN(amswap_db_d, rrr)
591 INSN(amadd_db_w, rrr)
592 INSN(amadd_db_d, rrr)
593 INSN(amand_db_w, rrr)
594 INSN(amand_db_d, rrr)
595 INSN(amor_db_w, rrr)
596 INSN(amor_db_d, rrr)
597 INSN(amxor_db_w, rrr)
598 INSN(amxor_db_d, rrr)
599 INSN(ammax_db_w, rrr)
600 INSN(ammax_db_d, rrr)
601 INSN(ammin_db_w, rrr)
602 INSN(ammin_db_d, rrr)
603 INSN(ammax_db_wu, rrr)
604 INSN(ammax_db_du, rrr)
605 INSN(ammin_db_wu, rrr)
606 INSN(ammin_db_du, rrr)
607 INSN(dbar, i)
608 INSN(ibar, i)
609 INSN(fldgt_s, frr)
610 INSN(fldgt_d, frr)
611 INSN(fldle_s, frr)
612 INSN(fldle_d, frr)
613 INSN(fstgt_s, frr)
614 INSN(fstgt_d, frr)
615 INSN(fstle_s, frr)
616 INSN(fstle_d, frr)
617 INSN(ldgt_b, rrr)
618 INSN(ldgt_h, rrr)
619 INSN(ldgt_w, rrr)
620 INSN(ldgt_d, rrr)
621 INSN(ldle_b, rrr)
622 INSN(ldle_h, rrr)
623 INSN(ldle_w, rrr)
624 INSN(ldle_d, rrr)
625 INSN(stgt_b, rrr)
626 INSN(stgt_h, rrr)
627 INSN(stgt_w, rrr)
628 INSN(stgt_d, rrr)
629 INSN(stle_b, rrr)
630 INSN(stle_h, rrr)
631 INSN(stle_w, rrr)
632 INSN(stle_d, rrr)
633 INSN(beqz, r_offs)
634 INSN(bnez, r_offs)
635 INSN(bceqz, c_offs)
636 INSN(bcnez, c_offs)
637 INSN(jirl, rr_i)
638 INSN(b, offs)
639 INSN(bl, offs)
640 INSN(beq, rr_offs)
641 INSN(bne, rr_offs)
642 INSN(blt, rr_offs)
643 INSN(bge, rr_offs)
644 INSN(bltu, rr_offs)
645 INSN(bgeu, rr_offs)
646 INSN(csrrd, r_csr)
647 INSN(csrwr, r_csr)
648 INSN(csrxchg, rr_csr)
649 INSN(iocsrrd_b, rr)
650 INSN(iocsrrd_h, rr)
651 INSN(iocsrrd_w, rr)
652 INSN(iocsrrd_d, rr)
653 INSN(iocsrwr_b, rr)
654 INSN(iocsrwr_h, rr)
655 INSN(iocsrwr_w, rr)
656 INSN(iocsrwr_d, rr)
657 INSN(tlbsrch, empty)
658 INSN(tlbrd, empty)
659 INSN(tlbwr, empty)
660 INSN(tlbfill, empty)
661 INSN(tlbclr, empty)
662 INSN(tlbflush, empty)
663 INSN(invtlb, i_rr)
664 INSN(cacop, cop_r_i)
665 INSN(lddir, rr_i)
666 INSN(ldpte, j_i)
667 INSN(ertn, empty)
668 INSN(idle, i)
669 INSN(dbcl, i)
670
671 #define output_fcmp(C, PREFIX, SUFFIX) \
672 { \
673 (C)->info->fprintf_func((C)->info->stream, "%08x %s%s\tfcc%d, f%d, f%d", \
674 (C)->insn, PREFIX, SUFFIX, a->cd, \
675 a->fj, a->fk); \
676 }
677
678 static bool output_cff_fcond(DisasContext *ctx, arg_cff_fcond * a,
679 const char *suffix)
680 {
681 bool ret = true;
682 switch (a->fcond) {
683 case 0x0:
684 output_fcmp(ctx, "fcmp_caf_", suffix);
685 break;
686 case 0x1:
687 output_fcmp(ctx, "fcmp_saf_", suffix);
688 break;
689 case 0x2:
690 output_fcmp(ctx, "fcmp_clt_", suffix);
691 break;
692 case 0x3:
693 output_fcmp(ctx, "fcmp_slt_", suffix);
694 break;
695 case 0x4:
696 output_fcmp(ctx, "fcmp_ceq_", suffix);
697 break;
698 case 0x5:
699 output_fcmp(ctx, "fcmp_seq_", suffix);
700 break;
701 case 0x6:
702 output_fcmp(ctx, "fcmp_cle_", suffix);
703 break;
704 case 0x7:
705 output_fcmp(ctx, "fcmp_sle_", suffix);
706 break;
707 case 0x8:
708 output_fcmp(ctx, "fcmp_cun_", suffix);
709 break;
710 case 0x9:
711 output_fcmp(ctx, "fcmp_sun_", suffix);
712 break;
713 case 0xA:
714 output_fcmp(ctx, "fcmp_cult_", suffix);
715 break;
716 case 0xB:
717 output_fcmp(ctx, "fcmp_sult_", suffix);
718 break;
719 case 0xC:
720 output_fcmp(ctx, "fcmp_cueq_", suffix);
721 break;
722 case 0xD:
723 output_fcmp(ctx, "fcmp_sueq_", suffix);
724 break;
725 case 0xE:
726 output_fcmp(ctx, "fcmp_cule_", suffix);
727 break;
728 case 0xF:
729 output_fcmp(ctx, "fcmp_sule_", suffix);
730 break;
731 case 0x10:
732 output_fcmp(ctx, "fcmp_cne_", suffix);
733 break;
734 case 0x11:
735 output_fcmp(ctx, "fcmp_sne_", suffix);
736 break;
737 case 0x14:
738 output_fcmp(ctx, "fcmp_cor_", suffix);
739 break;
740 case 0x15:
741 output_fcmp(ctx, "fcmp_sor_", suffix);
742 break;
743 case 0x18:
744 output_fcmp(ctx, "fcmp_cune_", suffix);
745 break;
746 case 0x19:
747 output_fcmp(ctx, "fcmp_sune_", suffix);
748 break;
749 default:
750 ret = false;
751 }
752 return ret;
753 }
754
755 #define FCMP_INSN(suffix) \
756 static bool trans_fcmp_cond_##suffix(DisasContext *ctx, \
757 arg_cff_fcond * a) \
758 { \
759 return output_cff_fcond(ctx, a, #suffix); \
760 }
761
762 FCMP_INSN(s)
763 FCMP_INSN(d)
764
765 #define PCADD_INSN(name) \
766 static bool trans_##name(DisasContext *ctx, arg_##name *a) \
767 { \
768 output(ctx, #name, "r%d, %d # 0x%" PRIx64, \
769 a->rd, a->imm, gen_##name(ctx->pc, a->imm)); \
770 return true; \
771 }
772
773 static uint64_t gen_pcaddi(uint64_t pc, int imm)
774 {
775 return pc + (imm << 2);
776 }
777
778 static uint64_t gen_pcalau12i(uint64_t pc, int imm)
779 {
780 return (pc + (imm << 12)) & ~0xfff;
781 }
782
783 static uint64_t gen_pcaddu12i(uint64_t pc, int imm)
784 {
785 return pc + (imm << 12);
786 }
787
788 static uint64_t gen_pcaddu18i(uint64_t pc, int imm)
789 {
790 return pc + ((uint64_t)(imm) << 18);
791 }
792
793 PCADD_INSN(pcaddi)
794 PCADD_INSN(pcalau12i)
795 PCADD_INSN(pcaddu12i)
796 PCADD_INSN(pcaddu18i)
797
798 #define INSN_LSX(insn, type) \
799 static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
800 { \
801 output_##type(ctx, a, #insn); \
802 return true; \
803 }
804
805 static void output_cv(DisasContext *ctx, arg_cv *a,
806 const char *mnemonic)
807 {
808 output(ctx, mnemonic, "fcc%d, v%d", a->cd, a->vj);
809 }
810
811 static void output_vvv(DisasContext *ctx, arg_vvv *a, const char *mnemonic)
812 {
813 output(ctx, mnemonic, "v%d, v%d, v%d", a->vd, a->vj, a->vk);
814 }
815
816 static void output_vv_i(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
817 {
818 output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
819 }
820
821 static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
822 {
823 output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
824 }
825
826 static void output_vvvv(DisasContext *ctx, arg_vvvv *a, const char *mnemonic)
827 {
828 output(ctx, mnemonic, "v%d, v%d, v%d, v%d", a->vd, a->vj, a->vk, a->va);
829 }
830
831 static void output_vr_i(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
832 {
833 output(ctx, mnemonic, "v%d, r%d, 0x%x", a->vd, a->rj, a->imm);
834 }
835
836 static void output_vr_ii(DisasContext *ctx, arg_vr_ii *a, const char *mnemonic)
837 {
838 output(ctx, mnemonic, "v%d, r%d, 0x%x, 0x%x", a->vd, a->rj, a->imm, a->imm2);
839 }
840
841 static void output_rv_i(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
842 {
843 output(ctx, mnemonic, "r%d, v%d, 0x%x", a->rd, a->vj, a->imm);
844 }
845
846 static void output_vr(DisasContext *ctx, arg_vr *a, const char *mnemonic)
847 {
848 output(ctx, mnemonic, "v%d, r%d", a->vd, a->rj);
849 }
850
851 static void output_vvr(DisasContext *ctx, arg_vvr *a, const char *mnemonic)
852 {
853 output(ctx, mnemonic, "v%d, v%d, r%d", a->vd, a->vj, a->rk);
854 }
855
856 static void output_vrr(DisasContext *ctx, arg_vrr *a, const char *mnemonic)
857 {
858 output(ctx, mnemonic, "v%d, r%d, r%d", a->vd, a->rj, a->rk);
859 }
860
861 static void output_v_i(DisasContext *ctx, arg_v_i *a, const char *mnemonic)
862 {
863 output(ctx, mnemonic, "v%d, 0x%x", a->vd, a->imm);
864 }
865
866 INSN_LSX(vadd_b, vvv)
867 INSN_LSX(vadd_h, vvv)
868 INSN_LSX(vadd_w, vvv)
869 INSN_LSX(vadd_d, vvv)
870 INSN_LSX(vadd_q, vvv)
871 INSN_LSX(vsub_b, vvv)
872 INSN_LSX(vsub_h, vvv)
873 INSN_LSX(vsub_w, vvv)
874 INSN_LSX(vsub_d, vvv)
875 INSN_LSX(vsub_q, vvv)
876
877 INSN_LSX(vaddi_bu, vv_i)
878 INSN_LSX(vaddi_hu, vv_i)
879 INSN_LSX(vaddi_wu, vv_i)
880 INSN_LSX(vaddi_du, vv_i)
881 INSN_LSX(vsubi_bu, vv_i)
882 INSN_LSX(vsubi_hu, vv_i)
883 INSN_LSX(vsubi_wu, vv_i)
884 INSN_LSX(vsubi_du, vv_i)
885
886 INSN_LSX(vneg_b, vv)
887 INSN_LSX(vneg_h, vv)
888 INSN_LSX(vneg_w, vv)
889 INSN_LSX(vneg_d, vv)
890
891 INSN_LSX(vsadd_b, vvv)
892 INSN_LSX(vsadd_h, vvv)
893 INSN_LSX(vsadd_w, vvv)
894 INSN_LSX(vsadd_d, vvv)
895 INSN_LSX(vsadd_bu, vvv)
896 INSN_LSX(vsadd_hu, vvv)
897 INSN_LSX(vsadd_wu, vvv)
898 INSN_LSX(vsadd_du, vvv)
899 INSN_LSX(vssub_b, vvv)
900 INSN_LSX(vssub_h, vvv)
901 INSN_LSX(vssub_w, vvv)
902 INSN_LSX(vssub_d, vvv)
903 INSN_LSX(vssub_bu, vvv)
904 INSN_LSX(vssub_hu, vvv)
905 INSN_LSX(vssub_wu, vvv)
906 INSN_LSX(vssub_du, vvv)
907
908 INSN_LSX(vhaddw_h_b, vvv)
909 INSN_LSX(vhaddw_w_h, vvv)
910 INSN_LSX(vhaddw_d_w, vvv)
911 INSN_LSX(vhaddw_q_d, vvv)
912 INSN_LSX(vhaddw_hu_bu, vvv)
913 INSN_LSX(vhaddw_wu_hu, vvv)
914 INSN_LSX(vhaddw_du_wu, vvv)
915 INSN_LSX(vhaddw_qu_du, vvv)
916 INSN_LSX(vhsubw_h_b, vvv)
917 INSN_LSX(vhsubw_w_h, vvv)
918 INSN_LSX(vhsubw_d_w, vvv)
919 INSN_LSX(vhsubw_q_d, vvv)
920 INSN_LSX(vhsubw_hu_bu, vvv)
921 INSN_LSX(vhsubw_wu_hu, vvv)
922 INSN_LSX(vhsubw_du_wu, vvv)
923 INSN_LSX(vhsubw_qu_du, vvv)
924
925 INSN_LSX(vaddwev_h_b, vvv)
926 INSN_LSX(vaddwev_w_h, vvv)
927 INSN_LSX(vaddwev_d_w, vvv)
928 INSN_LSX(vaddwev_q_d, vvv)
929 INSN_LSX(vaddwod_h_b, vvv)
930 INSN_LSX(vaddwod_w_h, vvv)
931 INSN_LSX(vaddwod_d_w, vvv)
932 INSN_LSX(vaddwod_q_d, vvv)
933 INSN_LSX(vsubwev_h_b, vvv)
934 INSN_LSX(vsubwev_w_h, vvv)
935 INSN_LSX(vsubwev_d_w, vvv)
936 INSN_LSX(vsubwev_q_d, vvv)
937 INSN_LSX(vsubwod_h_b, vvv)
938 INSN_LSX(vsubwod_w_h, vvv)
939 INSN_LSX(vsubwod_d_w, vvv)
940 INSN_LSX(vsubwod_q_d, vvv)
941
942 INSN_LSX(vaddwev_h_bu, vvv)
943 INSN_LSX(vaddwev_w_hu, vvv)
944 INSN_LSX(vaddwev_d_wu, vvv)
945 INSN_LSX(vaddwev_q_du, vvv)
946 INSN_LSX(vaddwod_h_bu, vvv)
947 INSN_LSX(vaddwod_w_hu, vvv)
948 INSN_LSX(vaddwod_d_wu, vvv)
949 INSN_LSX(vaddwod_q_du, vvv)
950 INSN_LSX(vsubwev_h_bu, vvv)
951 INSN_LSX(vsubwev_w_hu, vvv)
952 INSN_LSX(vsubwev_d_wu, vvv)
953 INSN_LSX(vsubwev_q_du, vvv)
954 INSN_LSX(vsubwod_h_bu, vvv)
955 INSN_LSX(vsubwod_w_hu, vvv)
956 INSN_LSX(vsubwod_d_wu, vvv)
957 INSN_LSX(vsubwod_q_du, vvv)
958
959 INSN_LSX(vaddwev_h_bu_b, vvv)
960 INSN_LSX(vaddwev_w_hu_h, vvv)
961 INSN_LSX(vaddwev_d_wu_w, vvv)
962 INSN_LSX(vaddwev_q_du_d, vvv)
963 INSN_LSX(vaddwod_h_bu_b, vvv)
964 INSN_LSX(vaddwod_w_hu_h, vvv)
965 INSN_LSX(vaddwod_d_wu_w, vvv)
966 INSN_LSX(vaddwod_q_du_d, vvv)
967
968 INSN_LSX(vavg_b, vvv)
969 INSN_LSX(vavg_h, vvv)
970 INSN_LSX(vavg_w, vvv)
971 INSN_LSX(vavg_d, vvv)
972 INSN_LSX(vavg_bu, vvv)
973 INSN_LSX(vavg_hu, vvv)
974 INSN_LSX(vavg_wu, vvv)
975 INSN_LSX(vavg_du, vvv)
976 INSN_LSX(vavgr_b, vvv)
977 INSN_LSX(vavgr_h, vvv)
978 INSN_LSX(vavgr_w, vvv)
979 INSN_LSX(vavgr_d, vvv)
980 INSN_LSX(vavgr_bu, vvv)
981 INSN_LSX(vavgr_hu, vvv)
982 INSN_LSX(vavgr_wu, vvv)
983 INSN_LSX(vavgr_du, vvv)
984
985 INSN_LSX(vabsd_b, vvv)
986 INSN_LSX(vabsd_h, vvv)
987 INSN_LSX(vabsd_w, vvv)
988 INSN_LSX(vabsd_d, vvv)
989 INSN_LSX(vabsd_bu, vvv)
990 INSN_LSX(vabsd_hu, vvv)
991 INSN_LSX(vabsd_wu, vvv)
992 INSN_LSX(vabsd_du, vvv)
993
994 INSN_LSX(vadda_b, vvv)
995 INSN_LSX(vadda_h, vvv)
996 INSN_LSX(vadda_w, vvv)
997 INSN_LSX(vadda_d, vvv)
998
999 INSN_LSX(vmax_b, vvv)
1000 INSN_LSX(vmax_h, vvv)
1001 INSN_LSX(vmax_w, vvv)
1002 INSN_LSX(vmax_d, vvv)
1003 INSN_LSX(vmin_b, vvv)
1004 INSN_LSX(vmin_h, vvv)
1005 INSN_LSX(vmin_w, vvv)
1006 INSN_LSX(vmin_d, vvv)
1007 INSN_LSX(vmax_bu, vvv)
1008 INSN_LSX(vmax_hu, vvv)
1009 INSN_LSX(vmax_wu, vvv)
1010 INSN_LSX(vmax_du, vvv)
1011 INSN_LSX(vmin_bu, vvv)
1012 INSN_LSX(vmin_hu, vvv)
1013 INSN_LSX(vmin_wu, vvv)
1014 INSN_LSX(vmin_du, vvv)
1015 INSN_LSX(vmaxi_b, vv_i)
1016 INSN_LSX(vmaxi_h, vv_i)
1017 INSN_LSX(vmaxi_w, vv_i)
1018 INSN_LSX(vmaxi_d, vv_i)
1019 INSN_LSX(vmini_b, vv_i)
1020 INSN_LSX(vmini_h, vv_i)
1021 INSN_LSX(vmini_w, vv_i)
1022 INSN_LSX(vmini_d, vv_i)
1023 INSN_LSX(vmaxi_bu, vv_i)
1024 INSN_LSX(vmaxi_hu, vv_i)
1025 INSN_LSX(vmaxi_wu, vv_i)
1026 INSN_LSX(vmaxi_du, vv_i)
1027 INSN_LSX(vmini_bu, vv_i)
1028 INSN_LSX(vmini_hu, vv_i)
1029 INSN_LSX(vmini_wu, vv_i)
1030 INSN_LSX(vmini_du, vv_i)
1031
1032 INSN_LSX(vmul_b, vvv)
1033 INSN_LSX(vmul_h, vvv)
1034 INSN_LSX(vmul_w, vvv)
1035 INSN_LSX(vmul_d, vvv)
1036 INSN_LSX(vmuh_b, vvv)
1037 INSN_LSX(vmuh_h, vvv)
1038 INSN_LSX(vmuh_w, vvv)
1039 INSN_LSX(vmuh_d, vvv)
1040 INSN_LSX(vmuh_bu, vvv)
1041 INSN_LSX(vmuh_hu, vvv)
1042 INSN_LSX(vmuh_wu, vvv)
1043 INSN_LSX(vmuh_du, vvv)
1044
1045 INSN_LSX(vmulwev_h_b, vvv)
1046 INSN_LSX(vmulwev_w_h, vvv)
1047 INSN_LSX(vmulwev_d_w, vvv)
1048 INSN_LSX(vmulwev_q_d, vvv)
1049 INSN_LSX(vmulwod_h_b, vvv)
1050 INSN_LSX(vmulwod_w_h, vvv)
1051 INSN_LSX(vmulwod_d_w, vvv)
1052 INSN_LSX(vmulwod_q_d, vvv)
1053 INSN_LSX(vmulwev_h_bu, vvv)
1054 INSN_LSX(vmulwev_w_hu, vvv)
1055 INSN_LSX(vmulwev_d_wu, vvv)
1056 INSN_LSX(vmulwev_q_du, vvv)
1057 INSN_LSX(vmulwod_h_bu, vvv)
1058 INSN_LSX(vmulwod_w_hu, vvv)
1059 INSN_LSX(vmulwod_d_wu, vvv)
1060 INSN_LSX(vmulwod_q_du, vvv)
1061 INSN_LSX(vmulwev_h_bu_b, vvv)
1062 INSN_LSX(vmulwev_w_hu_h, vvv)
1063 INSN_LSX(vmulwev_d_wu_w, vvv)
1064 INSN_LSX(vmulwev_q_du_d, vvv)
1065 INSN_LSX(vmulwod_h_bu_b, vvv)
1066 INSN_LSX(vmulwod_w_hu_h, vvv)
1067 INSN_LSX(vmulwod_d_wu_w, vvv)
1068 INSN_LSX(vmulwod_q_du_d, vvv)
1069
1070 INSN_LSX(vmadd_b, vvv)
1071 INSN_LSX(vmadd_h, vvv)
1072 INSN_LSX(vmadd_w, vvv)
1073 INSN_LSX(vmadd_d, vvv)
1074 INSN_LSX(vmsub_b, vvv)
1075 INSN_LSX(vmsub_h, vvv)
1076 INSN_LSX(vmsub_w, vvv)
1077 INSN_LSX(vmsub_d, vvv)
1078
1079 INSN_LSX(vmaddwev_h_b, vvv)
1080 INSN_LSX(vmaddwev_w_h, vvv)
1081 INSN_LSX(vmaddwev_d_w, vvv)
1082 INSN_LSX(vmaddwev_q_d, vvv)
1083 INSN_LSX(vmaddwod_h_b, vvv)
1084 INSN_LSX(vmaddwod_w_h, vvv)
1085 INSN_LSX(vmaddwod_d_w, vvv)
1086 INSN_LSX(vmaddwod_q_d, vvv)
1087 INSN_LSX(vmaddwev_h_bu, vvv)
1088 INSN_LSX(vmaddwev_w_hu, vvv)
1089 INSN_LSX(vmaddwev_d_wu, vvv)
1090 INSN_LSX(vmaddwev_q_du, vvv)
1091 INSN_LSX(vmaddwod_h_bu, vvv)
1092 INSN_LSX(vmaddwod_w_hu, vvv)
1093 INSN_LSX(vmaddwod_d_wu, vvv)
1094 INSN_LSX(vmaddwod_q_du, vvv)
1095 INSN_LSX(vmaddwev_h_bu_b, vvv)
1096 INSN_LSX(vmaddwev_w_hu_h, vvv)
1097 INSN_LSX(vmaddwev_d_wu_w, vvv)
1098 INSN_LSX(vmaddwev_q_du_d, vvv)
1099 INSN_LSX(vmaddwod_h_bu_b, vvv)
1100 INSN_LSX(vmaddwod_w_hu_h, vvv)
1101 INSN_LSX(vmaddwod_d_wu_w, vvv)
1102 INSN_LSX(vmaddwod_q_du_d, vvv)
1103
1104 INSN_LSX(vdiv_b, vvv)
1105 INSN_LSX(vdiv_h, vvv)
1106 INSN_LSX(vdiv_w, vvv)
1107 INSN_LSX(vdiv_d, vvv)
1108 INSN_LSX(vdiv_bu, vvv)
1109 INSN_LSX(vdiv_hu, vvv)
1110 INSN_LSX(vdiv_wu, vvv)
1111 INSN_LSX(vdiv_du, vvv)
1112 INSN_LSX(vmod_b, vvv)
1113 INSN_LSX(vmod_h, vvv)
1114 INSN_LSX(vmod_w, vvv)
1115 INSN_LSX(vmod_d, vvv)
1116 INSN_LSX(vmod_bu, vvv)
1117 INSN_LSX(vmod_hu, vvv)
1118 INSN_LSX(vmod_wu, vvv)
1119 INSN_LSX(vmod_du, vvv)
1120
1121 INSN_LSX(vsat_b, vv_i)
1122 INSN_LSX(vsat_h, vv_i)
1123 INSN_LSX(vsat_w, vv_i)
1124 INSN_LSX(vsat_d, vv_i)
1125 INSN_LSX(vsat_bu, vv_i)
1126 INSN_LSX(vsat_hu, vv_i)
1127 INSN_LSX(vsat_wu, vv_i)
1128 INSN_LSX(vsat_du, vv_i)
1129
1130 INSN_LSX(vexth_h_b, vv)
1131 INSN_LSX(vexth_w_h, vv)
1132 INSN_LSX(vexth_d_w, vv)
1133 INSN_LSX(vexth_q_d, vv)
1134 INSN_LSX(vexth_hu_bu, vv)
1135 INSN_LSX(vexth_wu_hu, vv)
1136 INSN_LSX(vexth_du_wu, vv)
1137 INSN_LSX(vexth_qu_du, vv)
1138
1139 INSN_LSX(vsigncov_b, vvv)
1140 INSN_LSX(vsigncov_h, vvv)
1141 INSN_LSX(vsigncov_w, vvv)
1142 INSN_LSX(vsigncov_d, vvv)
1143
1144 INSN_LSX(vmskltz_b, vv)
1145 INSN_LSX(vmskltz_h, vv)
1146 INSN_LSX(vmskltz_w, vv)
1147 INSN_LSX(vmskltz_d, vv)
1148 INSN_LSX(vmskgez_b, vv)
1149 INSN_LSX(vmsknz_b, vv)
1150
1151 INSN_LSX(vldi, v_i)
1152
1153 INSN_LSX(vand_v, vvv)
1154 INSN_LSX(vor_v, vvv)
1155 INSN_LSX(vxor_v, vvv)
1156 INSN_LSX(vnor_v, vvv)
1157 INSN_LSX(vandn_v, vvv)
1158 INSN_LSX(vorn_v, vvv)
1159
1160 INSN_LSX(vandi_b, vv_i)
1161 INSN_LSX(vori_b, vv_i)
1162 INSN_LSX(vxori_b, vv_i)
1163 INSN_LSX(vnori_b, vv_i)
1164
1165 INSN_LSX(vsll_b, vvv)
1166 INSN_LSX(vsll_h, vvv)
1167 INSN_LSX(vsll_w, vvv)
1168 INSN_LSX(vsll_d, vvv)
1169 INSN_LSX(vslli_b, vv_i)
1170 INSN_LSX(vslli_h, vv_i)
1171 INSN_LSX(vslli_w, vv_i)
1172 INSN_LSX(vslli_d, vv_i)
1173
1174 INSN_LSX(vsrl_b, vvv)
1175 INSN_LSX(vsrl_h, vvv)
1176 INSN_LSX(vsrl_w, vvv)
1177 INSN_LSX(vsrl_d, vvv)
1178 INSN_LSX(vsrli_b, vv_i)
1179 INSN_LSX(vsrli_h, vv_i)
1180 INSN_LSX(vsrli_w, vv_i)
1181 INSN_LSX(vsrli_d, vv_i)
1182
1183 INSN_LSX(vsra_b, vvv)
1184 INSN_LSX(vsra_h, vvv)
1185 INSN_LSX(vsra_w, vvv)
1186 INSN_LSX(vsra_d, vvv)
1187 INSN_LSX(vsrai_b, vv_i)
1188 INSN_LSX(vsrai_h, vv_i)
1189 INSN_LSX(vsrai_w, vv_i)
1190 INSN_LSX(vsrai_d, vv_i)
1191
1192 INSN_LSX(vrotr_b, vvv)
1193 INSN_LSX(vrotr_h, vvv)
1194 INSN_LSX(vrotr_w, vvv)
1195 INSN_LSX(vrotr_d, vvv)
1196 INSN_LSX(vrotri_b, vv_i)
1197 INSN_LSX(vrotri_h, vv_i)
1198 INSN_LSX(vrotri_w, vv_i)
1199 INSN_LSX(vrotri_d, vv_i)
1200
1201 INSN_LSX(vsllwil_h_b, vv_i)
1202 INSN_LSX(vsllwil_w_h, vv_i)
1203 INSN_LSX(vsllwil_d_w, vv_i)
1204 INSN_LSX(vextl_q_d, vv)
1205 INSN_LSX(vsllwil_hu_bu, vv_i)
1206 INSN_LSX(vsllwil_wu_hu, vv_i)
1207 INSN_LSX(vsllwil_du_wu, vv_i)
1208 INSN_LSX(vextl_qu_du, vv)
1209
1210 INSN_LSX(vsrlr_b, vvv)
1211 INSN_LSX(vsrlr_h, vvv)
1212 INSN_LSX(vsrlr_w, vvv)
1213 INSN_LSX(vsrlr_d, vvv)
1214 INSN_LSX(vsrlri_b, vv_i)
1215 INSN_LSX(vsrlri_h, vv_i)
1216 INSN_LSX(vsrlri_w, vv_i)
1217 INSN_LSX(vsrlri_d, vv_i)
1218
1219 INSN_LSX(vsrar_b, vvv)
1220 INSN_LSX(vsrar_h, vvv)
1221 INSN_LSX(vsrar_w, vvv)
1222 INSN_LSX(vsrar_d, vvv)
1223 INSN_LSX(vsrari_b, vv_i)
1224 INSN_LSX(vsrari_h, vv_i)
1225 INSN_LSX(vsrari_w, vv_i)
1226 INSN_LSX(vsrari_d, vv_i)
1227
1228 INSN_LSX(vsrln_b_h, vvv)
1229 INSN_LSX(vsrln_h_w, vvv)
1230 INSN_LSX(vsrln_w_d, vvv)
1231 INSN_LSX(vsran_b_h, vvv)
1232 INSN_LSX(vsran_h_w, vvv)
1233 INSN_LSX(vsran_w_d, vvv)
1234
1235 INSN_LSX(vsrlni_b_h, vv_i)
1236 INSN_LSX(vsrlni_h_w, vv_i)
1237 INSN_LSX(vsrlni_w_d, vv_i)
1238 INSN_LSX(vsrlni_d_q, vv_i)
1239 INSN_LSX(vsrani_b_h, vv_i)
1240 INSN_LSX(vsrani_h_w, vv_i)
1241 INSN_LSX(vsrani_w_d, vv_i)
1242 INSN_LSX(vsrani_d_q, vv_i)
1243
1244 INSN_LSX(vsrlrn_b_h, vvv)
1245 INSN_LSX(vsrlrn_h_w, vvv)
1246 INSN_LSX(vsrlrn_w_d, vvv)
1247 INSN_LSX(vsrarn_b_h, vvv)
1248 INSN_LSX(vsrarn_h_w, vvv)
1249 INSN_LSX(vsrarn_w_d, vvv)
1250
1251 INSN_LSX(vsrlrni_b_h, vv_i)
1252 INSN_LSX(vsrlrni_h_w, vv_i)
1253 INSN_LSX(vsrlrni_w_d, vv_i)
1254 INSN_LSX(vsrlrni_d_q, vv_i)
1255 INSN_LSX(vsrarni_b_h, vv_i)
1256 INSN_LSX(vsrarni_h_w, vv_i)
1257 INSN_LSX(vsrarni_w_d, vv_i)
1258 INSN_LSX(vsrarni_d_q, vv_i)
1259
1260 INSN_LSX(vssrln_b_h, vvv)
1261 INSN_LSX(vssrln_h_w, vvv)
1262 INSN_LSX(vssrln_w_d, vvv)
1263 INSN_LSX(vssran_b_h, vvv)
1264 INSN_LSX(vssran_h_w, vvv)
1265 INSN_LSX(vssran_w_d, vvv)
1266 INSN_LSX(vssrln_bu_h, vvv)
1267 INSN_LSX(vssrln_hu_w, vvv)
1268 INSN_LSX(vssrln_wu_d, vvv)
1269 INSN_LSX(vssran_bu_h, vvv)
1270 INSN_LSX(vssran_hu_w, vvv)
1271 INSN_LSX(vssran_wu_d, vvv)
1272
1273 INSN_LSX(vssrlni_b_h, vv_i)
1274 INSN_LSX(vssrlni_h_w, vv_i)
1275 INSN_LSX(vssrlni_w_d, vv_i)
1276 INSN_LSX(vssrlni_d_q, vv_i)
1277 INSN_LSX(vssrani_b_h, vv_i)
1278 INSN_LSX(vssrani_h_w, vv_i)
1279 INSN_LSX(vssrani_w_d, vv_i)
1280 INSN_LSX(vssrani_d_q, vv_i)
1281 INSN_LSX(vssrlni_bu_h, vv_i)
1282 INSN_LSX(vssrlni_hu_w, vv_i)
1283 INSN_LSX(vssrlni_wu_d, vv_i)
1284 INSN_LSX(vssrlni_du_q, vv_i)
1285 INSN_LSX(vssrani_bu_h, vv_i)
1286 INSN_LSX(vssrani_hu_w, vv_i)
1287 INSN_LSX(vssrani_wu_d, vv_i)
1288 INSN_LSX(vssrani_du_q, vv_i)
1289
1290 INSN_LSX(vssrlrn_b_h, vvv)
1291 INSN_LSX(vssrlrn_h_w, vvv)
1292 INSN_LSX(vssrlrn_w_d, vvv)
1293 INSN_LSX(vssrarn_b_h, vvv)
1294 INSN_LSX(vssrarn_h_w, vvv)
1295 INSN_LSX(vssrarn_w_d, vvv)
1296 INSN_LSX(vssrlrn_bu_h, vvv)
1297 INSN_LSX(vssrlrn_hu_w, vvv)
1298 INSN_LSX(vssrlrn_wu_d, vvv)
1299 INSN_LSX(vssrarn_bu_h, vvv)
1300 INSN_LSX(vssrarn_hu_w, vvv)
1301 INSN_LSX(vssrarn_wu_d, vvv)
1302
1303 INSN_LSX(vssrlrni_b_h, vv_i)
1304 INSN_LSX(vssrlrni_h_w, vv_i)
1305 INSN_LSX(vssrlrni_w_d, vv_i)
1306 INSN_LSX(vssrlrni_d_q, vv_i)
1307 INSN_LSX(vssrlrni_bu_h, vv_i)
1308 INSN_LSX(vssrlrni_hu_w, vv_i)
1309 INSN_LSX(vssrlrni_wu_d, vv_i)
1310 INSN_LSX(vssrlrni_du_q, vv_i)
1311 INSN_LSX(vssrarni_b_h, vv_i)
1312 INSN_LSX(vssrarni_h_w, vv_i)
1313 INSN_LSX(vssrarni_w_d, vv_i)
1314 INSN_LSX(vssrarni_d_q, vv_i)
1315 INSN_LSX(vssrarni_bu_h, vv_i)
1316 INSN_LSX(vssrarni_hu_w, vv_i)
1317 INSN_LSX(vssrarni_wu_d, vv_i)
1318 INSN_LSX(vssrarni_du_q, vv_i)
1319
1320 INSN_LSX(vclo_b, vv)
1321 INSN_LSX(vclo_h, vv)
1322 INSN_LSX(vclo_w, vv)
1323 INSN_LSX(vclo_d, vv)
1324 INSN_LSX(vclz_b, vv)
1325 INSN_LSX(vclz_h, vv)
1326 INSN_LSX(vclz_w, vv)
1327 INSN_LSX(vclz_d, vv)
1328
1329 INSN_LSX(vpcnt_b, vv)
1330 INSN_LSX(vpcnt_h, vv)
1331 INSN_LSX(vpcnt_w, vv)
1332 INSN_LSX(vpcnt_d, vv)
1333
1334 INSN_LSX(vbitclr_b, vvv)
1335 INSN_LSX(vbitclr_h, vvv)
1336 INSN_LSX(vbitclr_w, vvv)
1337 INSN_LSX(vbitclr_d, vvv)
1338 INSN_LSX(vbitclri_b, vv_i)
1339 INSN_LSX(vbitclri_h, vv_i)
1340 INSN_LSX(vbitclri_w, vv_i)
1341 INSN_LSX(vbitclri_d, vv_i)
1342 INSN_LSX(vbitset_b, vvv)
1343 INSN_LSX(vbitset_h, vvv)
1344 INSN_LSX(vbitset_w, vvv)
1345 INSN_LSX(vbitset_d, vvv)
1346 INSN_LSX(vbitseti_b, vv_i)
1347 INSN_LSX(vbitseti_h, vv_i)
1348 INSN_LSX(vbitseti_w, vv_i)
1349 INSN_LSX(vbitseti_d, vv_i)
1350 INSN_LSX(vbitrev_b, vvv)
1351 INSN_LSX(vbitrev_h, vvv)
1352 INSN_LSX(vbitrev_w, vvv)
1353 INSN_LSX(vbitrev_d, vvv)
1354 INSN_LSX(vbitrevi_b, vv_i)
1355 INSN_LSX(vbitrevi_h, vv_i)
1356 INSN_LSX(vbitrevi_w, vv_i)
1357 INSN_LSX(vbitrevi_d, vv_i)
1358
1359 INSN_LSX(vfrstp_b, vvv)
1360 INSN_LSX(vfrstp_h, vvv)
1361 INSN_LSX(vfrstpi_b, vv_i)
1362 INSN_LSX(vfrstpi_h, vv_i)
1363
1364 INSN_LSX(vfadd_s, vvv)
1365 INSN_LSX(vfadd_d, vvv)
1366 INSN_LSX(vfsub_s, vvv)
1367 INSN_LSX(vfsub_d, vvv)
1368 INSN_LSX(vfmul_s, vvv)
1369 INSN_LSX(vfmul_d, vvv)
1370 INSN_LSX(vfdiv_s, vvv)
1371 INSN_LSX(vfdiv_d, vvv)
1372
1373 INSN_LSX(vfmadd_s, vvvv)
1374 INSN_LSX(vfmadd_d, vvvv)
1375 INSN_LSX(vfmsub_s, vvvv)
1376 INSN_LSX(vfmsub_d, vvvv)
1377 INSN_LSX(vfnmadd_s, vvvv)
1378 INSN_LSX(vfnmadd_d, vvvv)
1379 INSN_LSX(vfnmsub_s, vvvv)
1380 INSN_LSX(vfnmsub_d, vvvv)
1381
1382 INSN_LSX(vfmax_s, vvv)
1383 INSN_LSX(vfmax_d, vvv)
1384 INSN_LSX(vfmin_s, vvv)
1385 INSN_LSX(vfmin_d, vvv)
1386
1387 INSN_LSX(vfmaxa_s, vvv)
1388 INSN_LSX(vfmaxa_d, vvv)
1389 INSN_LSX(vfmina_s, vvv)
1390 INSN_LSX(vfmina_d, vvv)
1391
1392 INSN_LSX(vflogb_s, vv)
1393 INSN_LSX(vflogb_d, vv)
1394
1395 INSN_LSX(vfclass_s, vv)
1396 INSN_LSX(vfclass_d, vv)
1397
1398 INSN_LSX(vfsqrt_s, vv)
1399 INSN_LSX(vfsqrt_d, vv)
1400 INSN_LSX(vfrecip_s, vv)
1401 INSN_LSX(vfrecip_d, vv)
1402 INSN_LSX(vfrsqrt_s, vv)
1403 INSN_LSX(vfrsqrt_d, vv)
1404
1405 INSN_LSX(vfcvtl_s_h, vv)
1406 INSN_LSX(vfcvth_s_h, vv)
1407 INSN_LSX(vfcvtl_d_s, vv)
1408 INSN_LSX(vfcvth_d_s, vv)
1409 INSN_LSX(vfcvt_h_s, vvv)
1410 INSN_LSX(vfcvt_s_d, vvv)
1411
1412 INSN_LSX(vfrint_s, vv)
1413 INSN_LSX(vfrint_d, vv)
1414 INSN_LSX(vfrintrm_s, vv)
1415 INSN_LSX(vfrintrm_d, vv)
1416 INSN_LSX(vfrintrp_s, vv)
1417 INSN_LSX(vfrintrp_d, vv)
1418 INSN_LSX(vfrintrz_s, vv)
1419 INSN_LSX(vfrintrz_d, vv)
1420 INSN_LSX(vfrintrne_s, vv)
1421 INSN_LSX(vfrintrne_d, vv)
1422
1423 INSN_LSX(vftint_w_s, vv)
1424 INSN_LSX(vftint_l_d, vv)
1425 INSN_LSX(vftintrm_w_s, vv)
1426 INSN_LSX(vftintrm_l_d, vv)
1427 INSN_LSX(vftintrp_w_s, vv)
1428 INSN_LSX(vftintrp_l_d, vv)
1429 INSN_LSX(vftintrz_w_s, vv)
1430 INSN_LSX(vftintrz_l_d, vv)
1431 INSN_LSX(vftintrne_w_s, vv)
1432 INSN_LSX(vftintrne_l_d, vv)
1433 INSN_LSX(vftint_wu_s, vv)
1434 INSN_LSX(vftint_lu_d, vv)
1435 INSN_LSX(vftintrz_wu_s, vv)
1436 INSN_LSX(vftintrz_lu_d, vv)
1437 INSN_LSX(vftint_w_d, vvv)
1438 INSN_LSX(vftintrm_w_d, vvv)
1439 INSN_LSX(vftintrp_w_d, vvv)
1440 INSN_LSX(vftintrz_w_d, vvv)
1441 INSN_LSX(vftintrne_w_d, vvv)
1442 INSN_LSX(vftintl_l_s, vv)
1443 INSN_LSX(vftinth_l_s, vv)
1444 INSN_LSX(vftintrml_l_s, vv)
1445 INSN_LSX(vftintrmh_l_s, vv)
1446 INSN_LSX(vftintrpl_l_s, vv)
1447 INSN_LSX(vftintrph_l_s, vv)
1448 INSN_LSX(vftintrzl_l_s, vv)
1449 INSN_LSX(vftintrzh_l_s, vv)
1450 INSN_LSX(vftintrnel_l_s, vv)
1451 INSN_LSX(vftintrneh_l_s, vv)
1452
1453 INSN_LSX(vffint_s_w, vv)
1454 INSN_LSX(vffint_s_wu, vv)
1455 INSN_LSX(vffint_d_l, vv)
1456 INSN_LSX(vffint_d_lu, vv)
1457 INSN_LSX(vffintl_d_w, vv)
1458 INSN_LSX(vffinth_d_w, vv)
1459 INSN_LSX(vffint_s_l, vvv)
1460
1461 INSN_LSX(vseq_b, vvv)
1462 INSN_LSX(vseq_h, vvv)
1463 INSN_LSX(vseq_w, vvv)
1464 INSN_LSX(vseq_d, vvv)
1465 INSN_LSX(vseqi_b, vv_i)
1466 INSN_LSX(vseqi_h, vv_i)
1467 INSN_LSX(vseqi_w, vv_i)
1468 INSN_LSX(vseqi_d, vv_i)
1469
1470 INSN_LSX(vsle_b, vvv)
1471 INSN_LSX(vsle_h, vvv)
1472 INSN_LSX(vsle_w, vvv)
1473 INSN_LSX(vsle_d, vvv)
1474 INSN_LSX(vslei_b, vv_i)
1475 INSN_LSX(vslei_h, vv_i)
1476 INSN_LSX(vslei_w, vv_i)
1477 INSN_LSX(vslei_d, vv_i)
1478 INSN_LSX(vsle_bu, vvv)
1479 INSN_LSX(vsle_hu, vvv)
1480 INSN_LSX(vsle_wu, vvv)
1481 INSN_LSX(vsle_du, vvv)
1482 INSN_LSX(vslei_bu, vv_i)
1483 INSN_LSX(vslei_hu, vv_i)
1484 INSN_LSX(vslei_wu, vv_i)
1485 INSN_LSX(vslei_du, vv_i)
1486
1487 INSN_LSX(vslt_b, vvv)
1488 INSN_LSX(vslt_h, vvv)
1489 INSN_LSX(vslt_w, vvv)
1490 INSN_LSX(vslt_d, vvv)
1491 INSN_LSX(vslti_b, vv_i)
1492 INSN_LSX(vslti_h, vv_i)
1493 INSN_LSX(vslti_w, vv_i)
1494 INSN_LSX(vslti_d, vv_i)
1495 INSN_LSX(vslt_bu, vvv)
1496 INSN_LSX(vslt_hu, vvv)
1497 INSN_LSX(vslt_wu, vvv)
1498 INSN_LSX(vslt_du, vvv)
1499 INSN_LSX(vslti_bu, vv_i)
1500 INSN_LSX(vslti_hu, vv_i)
1501 INSN_LSX(vslti_wu, vv_i)
1502 INSN_LSX(vslti_du, vv_i)
1503
1504 #define output_vfcmp(C, PREFIX, SUFFIX) \
1505 { \
1506 (C)->info->fprintf_func((C)->info->stream, "%08x %s%s\t%d, f%d, f%d", \
1507 (C)->insn, PREFIX, SUFFIX, a->vd, \
1508 a->vj, a->vk); \
1509 }
1510
1511 static bool output_vvv_fcond(DisasContext *ctx, arg_vvv_fcond * a,
1512 const char *suffix)
1513 {
1514 bool ret = true;
1515 switch (a->fcond) {
1516 case 0x0:
1517 output_vfcmp(ctx, "vfcmp_caf_", suffix);
1518 break;
1519 case 0x1:
1520 output_vfcmp(ctx, "vfcmp_saf_", suffix);
1521 break;
1522 case 0x2:
1523 output_vfcmp(ctx, "vfcmp_clt_", suffix);
1524 break;
1525 case 0x3:
1526 output_vfcmp(ctx, "vfcmp_slt_", suffix);
1527 break;
1528 case 0x4:
1529 output_vfcmp(ctx, "vfcmp_ceq_", suffix);
1530 break;
1531 case 0x5:
1532 output_vfcmp(ctx, "vfcmp_seq_", suffix);
1533 break;
1534 case 0x6:
1535 output_vfcmp(ctx, "vfcmp_cle_", suffix);
1536 break;
1537 case 0x7:
1538 output_vfcmp(ctx, "vfcmp_sle_", suffix);
1539 break;
1540 case 0x8:
1541 output_vfcmp(ctx, "vfcmp_cun_", suffix);
1542 break;
1543 case 0x9:
1544 output_vfcmp(ctx, "vfcmp_sun_", suffix);
1545 break;
1546 case 0xA:
1547 output_vfcmp(ctx, "vfcmp_cult_", suffix);
1548 break;
1549 case 0xB:
1550 output_vfcmp(ctx, "vfcmp_sult_", suffix);
1551 break;
1552 case 0xC:
1553 output_vfcmp(ctx, "vfcmp_cueq_", suffix);
1554 break;
1555 case 0xD:
1556 output_vfcmp(ctx, "vfcmp_sueq_", suffix);
1557 break;
1558 case 0xE:
1559 output_vfcmp(ctx, "vfcmp_cule_", suffix);
1560 break;
1561 case 0xF:
1562 output_vfcmp(ctx, "vfcmp_sule_", suffix);
1563 break;
1564 case 0x10:
1565 output_vfcmp(ctx, "vfcmp_cne_", suffix);
1566 break;
1567 case 0x11:
1568 output_vfcmp(ctx, "vfcmp_sne_", suffix);
1569 break;
1570 case 0x14:
1571 output_vfcmp(ctx, "vfcmp_cor_", suffix);
1572 break;
1573 case 0x15:
1574 output_vfcmp(ctx, "vfcmp_sor_", suffix);
1575 break;
1576 case 0x18:
1577 output_vfcmp(ctx, "vfcmp_cune_", suffix);
1578 break;
1579 case 0x19:
1580 output_vfcmp(ctx, "vfcmp_sune_", suffix);
1581 break;
1582 default:
1583 ret = false;
1584 }
1585 return ret;
1586 }
1587
1588 #define LSX_FCMP_INSN(suffix) \
1589 static bool trans_vfcmp_cond_##suffix(DisasContext *ctx, \
1590 arg_vvv_fcond * a) \
1591 { \
1592 return output_vvv_fcond(ctx, a, #suffix); \
1593 }
1594
1595 LSX_FCMP_INSN(s)
1596 LSX_FCMP_INSN(d)
1597
1598 INSN_LSX(vbitsel_v, vvvv)
1599 INSN_LSX(vbitseli_b, vv_i)
1600
1601 INSN_LSX(vseteqz_v, cv)
1602 INSN_LSX(vsetnez_v, cv)
1603 INSN_LSX(vsetanyeqz_b, cv)
1604 INSN_LSX(vsetanyeqz_h, cv)
1605 INSN_LSX(vsetanyeqz_w, cv)
1606 INSN_LSX(vsetanyeqz_d, cv)
1607 INSN_LSX(vsetallnez_b, cv)
1608 INSN_LSX(vsetallnez_h, cv)
1609 INSN_LSX(vsetallnez_w, cv)
1610 INSN_LSX(vsetallnez_d, cv)
1611
1612 INSN_LSX(vinsgr2vr_b, vr_i)
1613 INSN_LSX(vinsgr2vr_h, vr_i)
1614 INSN_LSX(vinsgr2vr_w, vr_i)
1615 INSN_LSX(vinsgr2vr_d, vr_i)
1616 INSN_LSX(vpickve2gr_b, rv_i)
1617 INSN_LSX(vpickve2gr_h, rv_i)
1618 INSN_LSX(vpickve2gr_w, rv_i)
1619 INSN_LSX(vpickve2gr_d, rv_i)
1620 INSN_LSX(vpickve2gr_bu, rv_i)
1621 INSN_LSX(vpickve2gr_hu, rv_i)
1622 INSN_LSX(vpickve2gr_wu, rv_i)
1623 INSN_LSX(vpickve2gr_du, rv_i)
1624
1625 INSN_LSX(vreplgr2vr_b, vr)
1626 INSN_LSX(vreplgr2vr_h, vr)
1627 INSN_LSX(vreplgr2vr_w, vr)
1628 INSN_LSX(vreplgr2vr_d, vr)
1629
1630 INSN_LSX(vreplve_b, vvr)
1631 INSN_LSX(vreplve_h, vvr)
1632 INSN_LSX(vreplve_w, vvr)
1633 INSN_LSX(vreplve_d, vvr)
1634 INSN_LSX(vreplvei_b, vv_i)
1635 INSN_LSX(vreplvei_h, vv_i)
1636 INSN_LSX(vreplvei_w, vv_i)
1637 INSN_LSX(vreplvei_d, vv_i)
1638
1639 INSN_LSX(vbsll_v, vv_i)
1640 INSN_LSX(vbsrl_v, vv_i)
1641
1642 INSN_LSX(vpackev_b, vvv)
1643 INSN_LSX(vpackev_h, vvv)
1644 INSN_LSX(vpackev_w, vvv)
1645 INSN_LSX(vpackev_d, vvv)
1646 INSN_LSX(vpackod_b, vvv)
1647 INSN_LSX(vpackod_h, vvv)
1648 INSN_LSX(vpackod_w, vvv)
1649 INSN_LSX(vpackod_d, vvv)
1650
1651 INSN_LSX(vpickev_b, vvv)
1652 INSN_LSX(vpickev_h, vvv)
1653 INSN_LSX(vpickev_w, vvv)
1654 INSN_LSX(vpickev_d, vvv)
1655 INSN_LSX(vpickod_b, vvv)
1656 INSN_LSX(vpickod_h, vvv)
1657 INSN_LSX(vpickod_w, vvv)
1658 INSN_LSX(vpickod_d, vvv)
1659
1660 INSN_LSX(vilvl_b, vvv)
1661 INSN_LSX(vilvl_h, vvv)
1662 INSN_LSX(vilvl_w, vvv)
1663 INSN_LSX(vilvl_d, vvv)
1664 INSN_LSX(vilvh_b, vvv)
1665 INSN_LSX(vilvh_h, vvv)
1666 INSN_LSX(vilvh_w, vvv)
1667 INSN_LSX(vilvh_d, vvv)
1668
1669 INSN_LSX(vshuf_b, vvvv)
1670 INSN_LSX(vshuf_h, vvv)
1671 INSN_LSX(vshuf_w, vvv)
1672 INSN_LSX(vshuf_d, vvv)
1673 INSN_LSX(vshuf4i_b, vv_i)
1674 INSN_LSX(vshuf4i_h, vv_i)
1675 INSN_LSX(vshuf4i_w, vv_i)
1676 INSN_LSX(vshuf4i_d, vv_i)
1677
1678 INSN_LSX(vpermi_w, vv_i)
1679
1680 INSN_LSX(vextrins_d, vv_i)
1681 INSN_LSX(vextrins_w, vv_i)
1682 INSN_LSX(vextrins_h, vv_i)
1683 INSN_LSX(vextrins_b, vv_i)
1684
1685 INSN_LSX(vld, vr_i)
1686 INSN_LSX(vst, vr_i)
1687 INSN_LSX(vldx, vrr)
1688 INSN_LSX(vstx, vrr)
1689
1690 INSN_LSX(vldrepl_d, vr_i)
1691 INSN_LSX(vldrepl_w, vr_i)
1692 INSN_LSX(vldrepl_h, vr_i)
1693 INSN_LSX(vldrepl_b, vr_i)
1694 INSN_LSX(vstelm_d, vr_ii)
1695 INSN_LSX(vstelm_w, vr_ii)
1696 INSN_LSX(vstelm_h, vr_ii)
1697 INSN_LSX(vstelm_b, vr_ii)
1698
1699 #define INSN_LASX(insn, type) \
1700 static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
1701 { \
1702 output_##type ## _x(ctx, a, #insn); \
1703 return true; \
1704 }
1705
1706 static void output_vvv_x(DisasContext *ctx, arg_vvv * a, const char *mnemonic)
1707 {
1708 output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
1709 }
1710
1711 static void output_vr_x(DisasContext *ctx, arg_vr *a, const char *mnemonic)
1712 {
1713 output(ctx, mnemonic, "x%d, r%d", a->vd, a->rj);
1714 }
1715
1716 static void output_vv_i_x(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
1717 {
1718 output(ctx, mnemonic, "x%d, x%d, 0x%x", a->vd, a->vj, a->imm);
1719 }
1720
1721 static void output_vv_x(DisasContext *ctx, arg_vv *a, const char *mnemonic)
1722 {
1723 output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj);
1724 }
1725
1726 INSN_LASX(xvadd_b, vvv)
1727 INSN_LASX(xvadd_h, vvv)
1728 INSN_LASX(xvadd_w, vvv)
1729 INSN_LASX(xvadd_d, vvv)
1730 INSN_LASX(xvadd_q, vvv)
1731 INSN_LASX(xvsub_b, vvv)
1732 INSN_LASX(xvsub_h, vvv)
1733 INSN_LASX(xvsub_w, vvv)
1734 INSN_LASX(xvsub_d, vvv)
1735 INSN_LASX(xvsub_q, vvv)
1736
1737 INSN_LASX(xvaddi_bu, vv_i)
1738 INSN_LASX(xvaddi_hu, vv_i)
1739 INSN_LASX(xvaddi_wu, vv_i)
1740 INSN_LASX(xvaddi_du, vv_i)
1741 INSN_LASX(xvsubi_bu, vv_i)
1742 INSN_LASX(xvsubi_hu, vv_i)
1743 INSN_LASX(xvsubi_wu, vv_i)
1744 INSN_LASX(xvsubi_du, vv_i)
1745
1746 INSN_LASX(xvneg_b, vv)
1747 INSN_LASX(xvneg_h, vv)
1748 INSN_LASX(xvneg_w, vv)
1749 INSN_LASX(xvneg_d, vv)
1750
1751 INSN_LASX(xvsadd_b, vvv)
1752 INSN_LASX(xvsadd_h, vvv)
1753 INSN_LASX(xvsadd_w, vvv)
1754 INSN_LASX(xvsadd_d, vvv)
1755 INSN_LASX(xvsadd_bu, vvv)
1756 INSN_LASX(xvsadd_hu, vvv)
1757 INSN_LASX(xvsadd_wu, vvv)
1758 INSN_LASX(xvsadd_du, vvv)
1759 INSN_LASX(xvssub_b, vvv)
1760 INSN_LASX(xvssub_h, vvv)
1761 INSN_LASX(xvssub_w, vvv)
1762 INSN_LASX(xvssub_d, vvv)
1763 INSN_LASX(xvssub_bu, vvv)
1764 INSN_LASX(xvssub_hu, vvv)
1765 INSN_LASX(xvssub_wu, vvv)
1766 INSN_LASX(xvssub_du, vvv)
1767
1768 INSN_LASX(xvhaddw_h_b, vvv)
1769 INSN_LASX(xvhaddw_w_h, vvv)
1770 INSN_LASX(xvhaddw_d_w, vvv)
1771 INSN_LASX(xvhaddw_q_d, vvv)
1772 INSN_LASX(xvhaddw_hu_bu, vvv)
1773 INSN_LASX(xvhaddw_wu_hu, vvv)
1774 INSN_LASX(xvhaddw_du_wu, vvv)
1775 INSN_LASX(xvhaddw_qu_du, vvv)
1776 INSN_LASX(xvhsubw_h_b, vvv)
1777 INSN_LASX(xvhsubw_w_h, vvv)
1778 INSN_LASX(xvhsubw_d_w, vvv)
1779 INSN_LASX(xvhsubw_q_d, vvv)
1780 INSN_LASX(xvhsubw_hu_bu, vvv)
1781 INSN_LASX(xvhsubw_wu_hu, vvv)
1782 INSN_LASX(xvhsubw_du_wu, vvv)
1783 INSN_LASX(xvhsubw_qu_du, vvv)
1784
1785 INSN_LASX(xvaddwev_h_b, vvv)
1786 INSN_LASX(xvaddwev_w_h, vvv)
1787 INSN_LASX(xvaddwev_d_w, vvv)
1788 INSN_LASX(xvaddwev_q_d, vvv)
1789 INSN_LASX(xvaddwod_h_b, vvv)
1790 INSN_LASX(xvaddwod_w_h, vvv)
1791 INSN_LASX(xvaddwod_d_w, vvv)
1792 INSN_LASX(xvaddwod_q_d, vvv)
1793 INSN_LASX(xvsubwev_h_b, vvv)
1794 INSN_LASX(xvsubwev_w_h, vvv)
1795 INSN_LASX(xvsubwev_d_w, vvv)
1796 INSN_LASX(xvsubwev_q_d, vvv)
1797 INSN_LASX(xvsubwod_h_b, vvv)
1798 INSN_LASX(xvsubwod_w_h, vvv)
1799 INSN_LASX(xvsubwod_d_w, vvv)
1800 INSN_LASX(xvsubwod_q_d, vvv)
1801
1802 INSN_LASX(xvaddwev_h_bu, vvv)
1803 INSN_LASX(xvaddwev_w_hu, vvv)
1804 INSN_LASX(xvaddwev_d_wu, vvv)
1805 INSN_LASX(xvaddwev_q_du, vvv)
1806 INSN_LASX(xvaddwod_h_bu, vvv)
1807 INSN_LASX(xvaddwod_w_hu, vvv)
1808 INSN_LASX(xvaddwod_d_wu, vvv)
1809 INSN_LASX(xvaddwod_q_du, vvv)
1810 INSN_LASX(xvsubwev_h_bu, vvv)
1811 INSN_LASX(xvsubwev_w_hu, vvv)
1812 INSN_LASX(xvsubwev_d_wu, vvv)
1813 INSN_LASX(xvsubwev_q_du, vvv)
1814 INSN_LASX(xvsubwod_h_bu, vvv)
1815 INSN_LASX(xvsubwod_w_hu, vvv)
1816 INSN_LASX(xvsubwod_d_wu, vvv)
1817 INSN_LASX(xvsubwod_q_du, vvv)
1818
1819 INSN_LASX(xvaddwev_h_bu_b, vvv)
1820 INSN_LASX(xvaddwev_w_hu_h, vvv)
1821 INSN_LASX(xvaddwev_d_wu_w, vvv)
1822 INSN_LASX(xvaddwev_q_du_d, vvv)
1823 INSN_LASX(xvaddwod_h_bu_b, vvv)
1824 INSN_LASX(xvaddwod_w_hu_h, vvv)
1825 INSN_LASX(xvaddwod_d_wu_w, vvv)
1826 INSN_LASX(xvaddwod_q_du_d, vvv)
1827
1828 INSN_LASX(xvavg_b, vvv)
1829 INSN_LASX(xvavg_h, vvv)
1830 INSN_LASX(xvavg_w, vvv)
1831 INSN_LASX(xvavg_d, vvv)
1832 INSN_LASX(xvavg_bu, vvv)
1833 INSN_LASX(xvavg_hu, vvv)
1834 INSN_LASX(xvavg_wu, vvv)
1835 INSN_LASX(xvavg_du, vvv)
1836 INSN_LASX(xvavgr_b, vvv)
1837 INSN_LASX(xvavgr_h, vvv)
1838 INSN_LASX(xvavgr_w, vvv)
1839 INSN_LASX(xvavgr_d, vvv)
1840 INSN_LASX(xvavgr_bu, vvv)
1841 INSN_LASX(xvavgr_hu, vvv)
1842 INSN_LASX(xvavgr_wu, vvv)
1843 INSN_LASX(xvavgr_du, vvv)
1844
1845 INSN_LASX(xvabsd_b, vvv)
1846 INSN_LASX(xvabsd_h, vvv)
1847 INSN_LASX(xvabsd_w, vvv)
1848 INSN_LASX(xvabsd_d, vvv)
1849 INSN_LASX(xvabsd_bu, vvv)
1850 INSN_LASX(xvabsd_hu, vvv)
1851 INSN_LASX(xvabsd_wu, vvv)
1852 INSN_LASX(xvabsd_du, vvv)
1853
1854 INSN_LASX(xvreplgr2vr_b, vr)
1855 INSN_LASX(xvreplgr2vr_h, vr)
1856 INSN_LASX(xvreplgr2vr_w, vr)
1857 INSN_LASX(xvreplgr2vr_d, vr)
AR7 emulation for QEMU