tests/ide-test.c

   1 /*
   2  * IDE test cases
   3  *
   4  * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26
  27
  28 #include "libqtest.h"
  29 #include "libqos/libqos.h"
  30 #include "libqos/pci-pc.h"
  31 #include "libqos/malloc-pc.h"
  32 #include "qapi/qmp/qdict.h"
  33 #include "qemu-common.h"
  34 #include "qemu/bswap.h"
  35 #include "hw/pci/pci_ids.h"
  36 #include "hw/pci/pci_regs.h"
  37
  38 /* TODO actually test the results and get rid of this */
  39 #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__))
  40
  41 #define TEST_IMAGE_SIZE 64 * 1024 * 1024
  42
  43 #define IDE_PCI_DEV     1
  44 #define IDE_PCI_FUNC    1
  45
  46 #define IDE_BASE 0x1f0
  47 #define IDE_PRIMARY_IRQ 14
  48
  49 #define ATAPI_BLOCK_SIZE 2048
  50
  51 /* How many bytes to receive via ATAPI PIO at one time.
  52  * Must be less than 0xFFFF. */
  53 #define BYTE_COUNT_LIMIT 5120
  54
  55 enum {
  56     reg_data        = 0x0,
  57     reg_feature     = 0x1,
  58     reg_error       = 0x1,
  59     reg_nsectors    = 0x2,
  60     reg_lba_low     = 0x3,
  61     reg_lba_middle  = 0x4,
  62     reg_lba_high    = 0x5,
  63     reg_device      = 0x6,
  64     reg_status      = 0x7,
  65     reg_command     = 0x7,
  66 };
  67
  68 enum {
  69     BSY     = 0x80,
  70     DRDY    = 0x40,
  71     DF      = 0x20,
  72     DRQ     = 0x08,
  73     ERR     = 0x01,
  74 };
  75
  76 /* Error field */
  77 enum {
  78     ABRT    = 0x04,
  79 };
  80
  81 enum {
  82     DEV     = 0x10,
  83     LBA     = 0x40,
  84 };
  85
  86 enum {
  87     bmreg_cmd       = 0x0,
  88     bmreg_status    = 0x2,
  89     bmreg_prdt      = 0x4,
  90 };
  91
  92 enum {
  93     CMD_DSM         = 0x06,
  94     CMD_READ_DMA    = 0xc8,
  95     CMD_WRITE_DMA   = 0xca,
  96     CMD_FLUSH_CACHE = 0xe7,
  97     CMD_IDENTIFY    = 0xec,
  98     CMD_PACKET      = 0xa0,
  99
 100     CMDF_ABORT      = 0x100,
 101     CMDF_NO_BM      = 0x200,
 102 };
 103
 104 enum {
 105     BM_CMD_START    =  0x1,
 106     BM_CMD_WRITE    =  0x8, /* write = from device to memory */
 107 };
 108
 109 enum {
 110     BM_STS_ACTIVE   =  0x1,
 111     BM_STS_ERROR    =  0x2,
 112     BM_STS_INTR     =  0x4,
 113 };
 114
 115 enum {
 116     PRDT_EOT        = 0x80000000,
 117 };
 118
 119 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 120 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 121
 122 static QPCIBus *pcibus = NULL;
 123 static QGuestAllocator *guest_malloc;
 124
 125 static char tmp_path[] = "/tmp/qtest.XXXXXX";
 126 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
 127
 128 static void GCC_FMT_ATTR(1, 2) ide_test_start(const char *cmdline_fmt, ...)
 129 {
 130     va_list ap;
 131     char *cmdline;
 132
 133     va_start(ap, cmdline_fmt);
 134     cmdline = g_strdup_vprintf(cmdline_fmt, ap);
 135     va_end(ap);
 136
 137     qtest_start(cmdline);
 138     guest_malloc = pc_alloc_init(global_qtest);
 139
 140     g_free(cmdline);
 141 }
 142
 143 static void ide_test_quit(void)
 144 {
 145     pc_alloc_uninit(guest_malloc);
 146     guest_malloc = NULL;
 147     qtest_end();
 148 }
 149
 150 static QPCIDevice *get_pci_device(QPCIBar *bmdma_bar, QPCIBar *ide_bar)
 151 {
 152     QPCIDevice *dev;
 153     uint16_t vendor_id, device_id;
 154
 155     if (!pcibus) {
 156         pcibus = qpci_init_pc(global_qtest, NULL);
 157     }
 158
 159     /* Find PCI device and verify it's the right one */
 160     dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
 161     g_assert(dev != NULL);
 162
 163     vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
 164     device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
 165     g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
 166     g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
 167
 168     /* Map bmdma BAR */
 169     *bmdma_bar = qpci_iomap(dev, 4, NULL);
 170
 171     *ide_bar = qpci_legacy_iomap(dev, IDE_BASE);
 172
 173     qpci_device_enable(dev);
 174
 175     return dev;
 176 }
 177
 178 static void free_pci_device(QPCIDevice *dev)
 179 {
 180     /* libqos doesn't have a function for this, so free it manually */
 181     g_free(dev);
 182 }
 183
 184 typedef struct PrdtEntry {
 185     uint32_t addr;
 186     uint32_t size;
 187 } QEMU_PACKED PrdtEntry;
 188
 189 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 190 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 191
 192 static uint64_t trim_range_le(uint64_t sector, uint16_t count)
 193 {
 194     /* 2-byte range, 6-byte LBA */
 195     return cpu_to_le64(((uint64_t)count << 48) + sector);
 196 }
 197
 198 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
 199                             PrdtEntry *prdt, int prdt_entries,
 200                             void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar,
 201                                              uint64_t sector, int nb_sectors))
 202 {
 203     QPCIDevice *dev;
 204     QPCIBar bmdma_bar, ide_bar;
 205     uintptr_t guest_prdt;
 206     size_t len;
 207     bool from_dev;
 208     uint8_t status;
 209     int flags;
 210
 211     dev = get_pci_device(&bmdma_bar, &ide_bar);
 212
 213     flags = cmd & ~0xff;
 214     cmd &= 0xff;
 215
 216     switch (cmd) {
 217     case CMD_READ_DMA:
 218     case CMD_PACKET:
 219         /* Assuming we only test data reads w/ ATAPI, otherwise we need to know
 220          * the SCSI command being sent in the packet, too. */
 221         from_dev = true;
 222         break;
 223     case CMD_DSM:
 224     case CMD_WRITE_DMA:
 225         from_dev = false;
 226         break;
 227     default:
 228         g_assert_not_reached();
 229     }
 230
 231     if (flags & CMDF_NO_BM) {
 232         qpci_config_writew(dev, PCI_COMMAND,
 233                            PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
 234     }
 235
 236     /* Select device 0 */
 237     qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA);
 238
 239     /* Stop any running transfer, clear any pending interrupt */
 240     qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
 241     qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR);
 242
 243     /* Setup PRDT */
 244     len = sizeof(*prdt) * prdt_entries;
 245     guest_prdt = guest_alloc(guest_malloc, len);
 246     memwrite(guest_prdt, prdt, len);
 247     qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt);
 248
 249     /* ATA DMA command */
 250     if (cmd == CMD_PACKET) {
 251         /* Enables ATAPI DMA; otherwise PIO is attempted */
 252         qpci_io_writeb(dev, ide_bar, reg_feature, 0x01);
 253     } else {
 254         if (cmd == CMD_DSM) {
 255             /* trim bit */
 256             qpci_io_writeb(dev, ide_bar, reg_feature, 0x01);
 257         }
 258         qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors);
 259         qpci_io_writeb(dev, ide_bar, reg_lba_low,    sector & 0xff);
 260         qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff);
 261         qpci_io_writeb(dev, ide_bar, reg_lba_high,   (sector >> 16) & 0xff);
 262     }
 263
 264     qpci_io_writeb(dev, ide_bar, reg_command, cmd);
 265
 266     if (post_exec) {
 267         post_exec(dev, ide_bar, sector, nb_sectors);
 268     }
 269
 270     /* Start DMA transfer */
 271     qpci_io_writeb(dev, bmdma_bar, bmreg_cmd,
 272                    BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));
 273
 274     if (flags & CMDF_ABORT) {
 275         qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
 276     }
 277
 278     /* Wait for the DMA transfer to complete */
 279     do {
 280         status = qpci_io_readb(dev, bmdma_bar, bmreg_status);
 281     } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
 282
 283     g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
 284
 285     /* Check IDE status code */
 286     assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY);
 287     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ);
 288
 289     /* Reading the status register clears the IRQ */
 290     g_assert(!get_irq(IDE_PRIMARY_IRQ));
 291
 292     /* Stop DMA transfer if still active */
 293     if (status & BM_STS_ACTIVE) {
 294         qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
 295     }
 296
 297     free_pci_device(dev);
 298
 299     return status;
 300 }
 301
 302 static void test_bmdma_simple_rw(void)
 303 {
 304     QPCIDevice *dev;
 305     QPCIBar bmdma_bar, ide_bar;
 306     uint8_t status;
 307     uint8_t *buf;
 308     uint8_t *cmpbuf;
 309     size_t len = 512;
 310     uintptr_t guest_buf = guest_alloc(guest_malloc, len);
 311
 312     PrdtEntry prdt[] = {
 313         {
 314             .addr = cpu_to_le32(guest_buf),
 315             .size = cpu_to_le32(len | PRDT_EOT),
 316         },
 317     };
 318
 319     dev = get_pci_device(&bmdma_bar, &ide_bar);
 320
 321     buf = g_malloc(len);
 322     cmpbuf = g_malloc(len);
 323
 324     /* Write 0x55 pattern to sector 0 */
 325     memset(buf, 0x55, len);
 326     memwrite(guest_buf, buf, len);
 327
 328     status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt,
 329                               ARRAY_SIZE(prdt), NULL);
 330     g_assert_cmphex(status, ==, BM_STS_INTR);
 331     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 332
 333     /* Write 0xaa pattern to sector 1 */
 334     memset(buf, 0xaa, len);
 335     memwrite(guest_buf, buf, len);
 336
 337     status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
 338                               ARRAY_SIZE(prdt), NULL);
 339     g_assert_cmphex(status, ==, BM_STS_INTR);
 340     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 341
 342     /* Read and verify 0x55 pattern in sector 0 */
 343     memset(cmpbuf, 0x55, len);
 344
 345     status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL);
 346     g_assert_cmphex(status, ==, BM_STS_INTR);
 347     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 348
 349     memread(guest_buf, buf, len);
 350     g_assert(memcmp(buf, cmpbuf, len) == 0);
 351
 352     /* Read and verify 0xaa pattern in sector 1 */
 353     memset(cmpbuf, 0xaa, len);
 354
 355     status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL);
 356     g_assert_cmphex(status, ==, BM_STS_INTR);
 357     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 358
 359     memread(guest_buf, buf, len);
 360     g_assert(memcmp(buf, cmpbuf, len) == 0);
 361
 362
 363     free_pci_device(dev);
 364     g_free(buf);
 365     g_free(cmpbuf);
 366 }
 367
 368 static void test_bmdma_trim(void)
 369 {
 370     QPCIDevice *dev;
 371     QPCIBar bmdma_bar, ide_bar;
 372     uint8_t status;
 373     const uint64_t trim_range[] = { trim_range_le(0, 2),
 374                                     trim_range_le(6, 8),
 375                                     trim_range_le(10, 1),
 376                                   };
 377     const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2);
 378     size_t len = 512;
 379     uint8_t *buf;
 380     uintptr_t guest_buf = guest_alloc(guest_malloc, len);
 381
 382     PrdtEntry prdt[] = {
 383         {
 384             .addr = cpu_to_le32(guest_buf),
 385             .size = cpu_to_le32(len | PRDT_EOT),
 386         },
 387     };
 388
 389     dev = get_pci_device(&bmdma_bar, &ide_bar);
 390
 391     buf = g_malloc(len);
 392
 393     /* Normal request */
 394     *((uint64_t *)buf) = trim_range[0];
 395     *((uint64_t *)buf + 1) = trim_range[1];
 396
 397     memwrite(guest_buf, buf, 2 * sizeof(uint64_t));
 398
 399     status = send_dma_request(CMD_DSM, 0, 1, prdt,
 400                               ARRAY_SIZE(prdt), NULL);
 401     g_assert_cmphex(status, ==, BM_STS_INTR);
 402     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 403
 404     /* Request contains invalid range */
 405     *((uint64_t *)buf) = trim_range[2];
 406     *((uint64_t *)buf + 1) = bad_range;
 407
 408     memwrite(guest_buf, buf, 2 * sizeof(uint64_t));
 409
 410     status = send_dma_request(CMD_DSM, 0, 1, prdt,
 411                               ARRAY_SIZE(prdt), NULL);
 412     g_assert_cmphex(status, ==, BM_STS_INTR);
 413     assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR);
 414     assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT);
 415
 416     free_pci_device(dev);
 417     g_free(buf);
 418 }
 419
 420 static void test_bmdma_short_prdt(void)
 421 {
 422     QPCIDevice *dev;
 423     QPCIBar bmdma_bar, ide_bar;
 424     uint8_t status;
 425
 426     PrdtEntry prdt[] = {
 427         {
 428             .addr = 0,
 429             .size = cpu_to_le32(0x10 | PRDT_EOT),
 430         },
 431     };
 432
 433     dev = get_pci_device(&bmdma_bar, &ide_bar);
 434
 435     /* Normal request */
 436     status = send_dma_request(CMD_READ_DMA, 0, 1,
 437                               prdt, ARRAY_SIZE(prdt), NULL);
 438     g_assert_cmphex(status, ==, 0);
 439     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 440
 441     /* Abort the request before it completes */
 442     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
 443                               prdt, ARRAY_SIZE(prdt), NULL);
 444     g_assert_cmphex(status, ==, 0);
 445     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 446     free_pci_device(dev);
 447 }
 448
 449 static void test_bmdma_one_sector_short_prdt(void)
 450 {
 451     QPCIDevice *dev;
 452     QPCIBar bmdma_bar, ide_bar;
 453     uint8_t status;
 454
 455     /* Read 2 sectors but only give 1 sector in PRDT */
 456     PrdtEntry prdt[] = {
 457         {
 458             .addr = 0,
 459             .size = cpu_to_le32(0x200 | PRDT_EOT),
 460         },
 461     };
 462
 463     dev = get_pci_device(&bmdma_bar, &ide_bar);
 464
 465     /* Normal request */
 466     status = send_dma_request(CMD_READ_DMA, 0, 2,
 467                               prdt, ARRAY_SIZE(prdt), NULL);
 468     g_assert_cmphex(status, ==, 0);
 469     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 470
 471     /* Abort the request before it completes */
 472     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2,
 473                               prdt, ARRAY_SIZE(prdt), NULL);
 474     g_assert_cmphex(status, ==, 0);
 475     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 476     free_pci_device(dev);
 477 }
 478
 479 static void test_bmdma_long_prdt(void)
 480 {
 481     QPCIDevice *dev;
 482     QPCIBar bmdma_bar, ide_bar;
 483     uint8_t status;
 484
 485     PrdtEntry prdt[] = {
 486         {
 487             .addr = 0,
 488             .size = cpu_to_le32(0x1000 | PRDT_EOT),
 489         },
 490     };
 491
 492     dev = get_pci_device(&bmdma_bar, &ide_bar);
 493
 494     /* Normal request */
 495     status = send_dma_request(CMD_READ_DMA, 0, 1,
 496                               prdt, ARRAY_SIZE(prdt), NULL);
 497     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
 498     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 499
 500     /* Abort the request before it completes */
 501     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
 502                               prdt, ARRAY_SIZE(prdt), NULL);
 503     g_assert_cmphex(status, ==, BM_STS_INTR);
 504     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 505     free_pci_device(dev);
 506 }
 507
 508 static void test_bmdma_no_busmaster(void)
 509 {
 510     QPCIDevice *dev;
 511     QPCIBar bmdma_bar, ide_bar;
 512     uint8_t status;
 513
 514     dev = get_pci_device(&bmdma_bar, &ide_bar);
 515
 516     /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
 517      * able to access it anyway because the Bus Master bit in the PCI command
 518      * register isn't set. This is complete nonsense, but it used to be pretty
 519      * good at confusing and occasionally crashing qemu. */
 520     PrdtEntry prdt[4096] = { };
 521
 522     status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512,
 523                               prdt, ARRAY_SIZE(prdt), NULL);
 524
 525     /* Not entirely clear what the expected result is, but this is what we get
 526      * in practice. At least we want to be aware of any changes. */
 527     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
 528     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 529     free_pci_device(dev);
 530 }
 531
 532 static void test_bmdma_setup(void)
 533 {
 534     ide_test_start(
 535         "-drive file=%s,if=ide,cache=writeback,format=raw "
 536         "-global ide-hd.serial=%s -global ide-hd.ver=%s",
 537         tmp_path, "testdisk", "version");
 538     qtest_irq_intercept_in(global_qtest, "ioapic");
 539 }
 540
 541 static void test_bmdma_teardown(void)
 542 {
 543     ide_test_quit();
 544 }
 545
 546 static void string_cpu_to_be16(uint16_t *s, size_t bytes)
 547 {
 548     g_assert((bytes & 1) == 0);
 549     bytes /= 2;
 550
 551     while (bytes--) {
 552         *s = cpu_to_be16(*s);
 553         s++;
 554     }
 555 }
 556
 557 static void test_identify(void)
 558 {
 559     QPCIDevice *dev;
 560     QPCIBar bmdma_bar, ide_bar;
 561     uint8_t data;
 562     uint16_t buf[256];
 563     int i;
 564     int ret;
 565
 566     ide_test_start(
 567         "-drive file=%s,if=ide,cache=writeback,format=raw "
 568         "-global ide-hd.serial=%s -global ide-hd.ver=%s",
 569         tmp_path, "testdisk", "version");
 570
 571     dev = get_pci_device(&bmdma_bar, &ide_bar);
 572
 573     /* IDENTIFY command on device 0*/
 574     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 575     qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY);
 576
 577     /* Read in the IDENTIFY buffer and check registers */
 578     data = qpci_io_readb(dev, ide_bar, reg_device);
 579     g_assert_cmpint(data & DEV, ==, 0);
 580
 581     for (i = 0; i < 256; i++) {
 582         data = qpci_io_readb(dev, ide_bar, reg_status);
 583         assert_bit_set(data, DRDY | DRQ);
 584         assert_bit_clear(data, BSY | DF | ERR);
 585
 586         buf[i] = qpci_io_readw(dev, ide_bar, reg_data);
 587     }
 588
 589     data = qpci_io_readb(dev, ide_bar, reg_status);
 590     assert_bit_set(data, DRDY);
 591     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 592
 593     /* Check serial number/version in the buffer */
 594     string_cpu_to_be16(&buf[10], 20);
 595     ret = memcmp(&buf[10], "testdisk            ", 20);
 596     g_assert(ret == 0);
 597
 598     string_cpu_to_be16(&buf[23], 8);
 599     ret = memcmp(&buf[23], "version ", 8);
 600     g_assert(ret == 0);
 601
 602     /* Write cache enabled bit */
 603     assert_bit_set(buf[85], 0x20);
 604
 605     ide_test_quit();
 606     free_pci_device(dev);
 607 }
 608
 609 /*
 610  * Write sector 1 with random data to make IDE storage dirty
 611  * Needed for flush tests so that flushes actually go though the block layer
 612  */
 613 static void make_dirty(uint8_t device)
 614 {
 615     QPCIDevice *dev;
 616     QPCIBar bmdma_bar, ide_bar;
 617     uint8_t status;
 618     size_t len = 512;
 619     uintptr_t guest_buf;
 620     void* buf;
 621
 622     dev = get_pci_device(&bmdma_bar, &ide_bar);
 623
 624     guest_buf = guest_alloc(guest_malloc, len);
 625     buf = g_malloc(len);
 626     memset(buf, rand() % 255 + 1, len);
 627     g_assert(guest_buf);
 628     g_assert(buf);
 629
 630     memwrite(guest_buf, buf, len);
 631
 632     PrdtEntry prdt[] = {
 633         {
 634             .addr = cpu_to_le32(guest_buf),
 635             .size = cpu_to_le32(len | PRDT_EOT),
 636         },
 637     };
 638
 639     status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
 640                               ARRAY_SIZE(prdt), NULL);
 641     g_assert_cmphex(status, ==, BM_STS_INTR);
 642     assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
 643
 644     g_free(buf);
 645     free_pci_device(dev);
 646 }
 647
 648 static void test_flush(void)
 649 {
 650     QPCIDevice *dev;
 651     QPCIBar bmdma_bar, ide_bar;
 652     uint8_t data;
 653
 654     ide_test_start(
 655         "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
 656         tmp_path);
 657
 658     dev = get_pci_device(&bmdma_bar, &ide_bar);
 659
 660     qtest_irq_intercept_in(global_qtest, "ioapic");
 661
 662     /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
 663     make_dirty(0);
 664
 665     /* Delay the completion of the flush request until we explicitly do it */
 666     g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\""));
 667
 668     /* FLUSH CACHE command on device 0*/
 669     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 670     qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
 671
 672     /* Check status while request is in flight*/
 673     data = qpci_io_readb(dev, ide_bar, reg_status);
 674     assert_bit_set(data, BSY | DRDY);
 675     assert_bit_clear(data, DF | ERR | DRQ);
 676
 677     /* Complete the command */
 678     g_free(hmp("qemu-io ide0-hd0 \"resume A\""));
 679
 680     /* Check registers */
 681     data = qpci_io_readb(dev, ide_bar, reg_device);
 682     g_assert_cmpint(data & DEV, ==, 0);
 683
 684     do {
 685         data = qpci_io_readb(dev, ide_bar, reg_status);
 686     } while (data & BSY);
 687
 688     assert_bit_set(data, DRDY);
 689     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 690
 691     ide_test_quit();
 692     free_pci_device(dev);
 693 }
 694
 695 static void test_retry_flush(const char *machine)
 696 {
 697     QPCIDevice *dev;
 698     QPCIBar bmdma_bar, ide_bar;
 699     uint8_t data;
 700
 701     prepare_blkdebug_script(debug_path, "flush_to_disk");
 702
 703     ide_test_start(
 704         "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
 705         "rerror=stop,werror=stop",
 706         debug_path, tmp_path);
 707
 708     dev = get_pci_device(&bmdma_bar, &ide_bar);
 709
 710     qtest_irq_intercept_in(global_qtest, "ioapic");
 711
 712     /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
 713     make_dirty(0);
 714
 715     /* FLUSH CACHE command on device 0*/
 716     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 717     qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
 718
 719     /* Check status while request is in flight*/
 720     data = qpci_io_readb(dev, ide_bar, reg_status);
 721     assert_bit_set(data, BSY | DRDY);
 722     assert_bit_clear(data, DF | ERR | DRQ);
 723
 724     qmp_eventwait("STOP");
 725
 726     /* Complete the command */
 727     qmp_discard_response("{'execute':'cont' }");
 728
 729     /* Check registers */
 730     data = qpci_io_readb(dev, ide_bar, reg_device);
 731     g_assert_cmpint(data & DEV, ==, 0);
 732
 733     do {
 734         data = qpci_io_readb(dev, ide_bar, reg_status);
 735     } while (data & BSY);
 736
 737     assert_bit_set(data, DRDY);
 738     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 739
 740     ide_test_quit();
 741     free_pci_device(dev);
 742 }
 743
 744 static void test_flush_nodev(void)
 745 {
 746     QPCIDevice *dev;
 747     QPCIBar bmdma_bar, ide_bar;
 748
 749 #pragma GCC diagnostic ignored "-Wformat-zero-length"
 750     ide_test_start("");
 751 #pragma GCC diagnostic error "-Wformat-zero-length"
 752
 753     dev = get_pci_device(&bmdma_bar, &ide_bar);
 754
 755     /* FLUSH CACHE command on device 0*/
 756     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 757     qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
 758
 759     /* Just testing that qemu doesn't crash... */
 760
 761     free_pci_device(dev);
 762     ide_test_quit();
 763 }
 764
 765 static void test_flush_empty_drive(void)
 766 {
 767     QPCIDevice *dev;
 768     QPCIBar bmdma_bar, ide_bar;
 769
 770     ide_test_start("-device ide-cd,bus=ide.0");
 771     dev = get_pci_device(&bmdma_bar, &ide_bar);
 772
 773     /* FLUSH CACHE command on device 0 */
 774     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 775     qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
 776
 777     /* Just testing that qemu doesn't crash... */
 778
 779     free_pci_device(dev);
 780     ide_test_quit();
 781 }
 782
 783 static void test_pci_retry_flush(void)
 784 {
 785     test_retry_flush("pc");
 786 }
 787
 788 static void test_isa_retry_flush(void)
 789 {
 790     test_retry_flush("isapc");
 791 }
 792
 793 typedef struct Read10CDB {
 794     uint8_t opcode;
 795     uint8_t flags;
 796     uint32_t lba;
 797     uint8_t reserved;
 798     uint16_t nblocks;
 799     uint8_t control;
 800     uint16_t padding;
 801 } __attribute__((__packed__)) Read10CDB;
 802
 803 static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar,
 804                                  uint64_t lba, int nblocks)
 805 {
 806     Read10CDB pkt = { .padding = 0 };
 807     int i;
 808
 809     g_assert_cmpint(lba, <=, UINT32_MAX);
 810     g_assert_cmpint(nblocks, <=, UINT16_MAX);
 811     g_assert_cmpint(nblocks, >=, 0);
 812
 813     /* Construct SCSI CDB packet */
 814     pkt.opcode = 0x28;
 815     pkt.lba = cpu_to_be32(lba);
 816     pkt.nblocks = cpu_to_be16(nblocks);
 817
 818     /* Send Packet */
 819     for (i = 0; i < sizeof(Read10CDB)/2; i++) {
 820         qpci_io_writew(dev, ide_bar, reg_data,
 821                        le16_to_cpu(((uint16_t *)&pkt)[i]));
 822     }
 823 }
 824
 825 static void nsleep(int64_t nsecs)
 826 {
 827     const struct timespec val = { .tv_nsec = nsecs };
 828     nanosleep(&val, NULL);
 829     clock_set(nsecs);
 830 }
 831
 832 static uint8_t ide_wait_clear(uint8_t flag)
 833 {
 834     QPCIDevice *dev;
 835     QPCIBar bmdma_bar, ide_bar;
 836     uint8_t data;
 837     time_t st;
 838
 839     dev = get_pci_device(&bmdma_bar, &ide_bar);
 840
 841     /* Wait with a 5 second timeout */
 842     time(&st);
 843     while (true) {
 844         data = qpci_io_readb(dev, ide_bar, reg_status);
 845         if (!(data & flag)) {
 846             free_pci_device(dev);
 847             return data;
 848         }
 849         if (difftime(time(NULL), st) > 5.0) {
 850             break;
 851         }
 852         nsleep(400);
 853     }
 854     g_assert_not_reached();
 855 }
 856
 857 static void ide_wait_intr(int irq)
 858 {
 859     time_t st;
 860     bool intr;
 861
 862     time(&st);
 863     while (true) {
 864         intr = get_irq(irq);
 865         if (intr) {
 866             return;
 867         }
 868         if (difftime(time(NULL), st) > 5.0) {
 869             break;
 870         }
 871         nsleep(400);
 872     }
 873
 874     g_assert_not_reached();
 875 }
 876
 877 static void cdrom_pio_impl(int nblocks)
 878 {
 879     QPCIDevice *dev;
 880     QPCIBar bmdma_bar, ide_bar;
 881     FILE *fh;
 882     int patt_blocks = MAX(16, nblocks);
 883     size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;
 884     char *pattern = g_malloc(patt_len);
 885     size_t rxsize = ATAPI_BLOCK_SIZE * nblocks;
 886     uint16_t *rx = g_malloc0(rxsize);
 887     int i, j;
 888     uint8_t data;
 889     uint16_t limit;
 890     size_t ret;
 891
 892     /* Prepopulate the CDROM with an interesting pattern */
 893     generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
 894     fh = fopen(tmp_path, "w+");
 895     ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
 896     g_assert_cmpint(ret, ==, patt_blocks);
 897     fclose(fh);
 898
 899     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
 900                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
 901     dev = get_pci_device(&bmdma_bar, &ide_bar);
 902     qtest_irq_intercept_in(global_qtest, "ioapic");
 903
 904     /* PACKET command on device 0 */
 905     qpci_io_writeb(dev, ide_bar, reg_device, 0);
 906     qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
 907     qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
 908     qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET);
 909     /* HP0: Check_Status_A State */
 910     nsleep(400);
 911     data = ide_wait_clear(BSY);
 912     /* HP1: Send_Packet State */
 913     assert_bit_set(data, DRQ | DRDY);
 914     assert_bit_clear(data, ERR | DF | BSY);
 915
 916     /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
 917     send_scsi_cdb_read10(dev, ide_bar, 0, nblocks);
 918
 919     /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
 920      * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
 921      * We allow an odd limit only when the remaining transfer size is
 922      * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only
 923      * request n blocks, so our request size is always even.
 924      * For this reason, we assume there is never a hanging byte to fetch. */
 925     g_assert(!(rxsize & 1));
 926     limit = BYTE_COUNT_LIMIT & ~1;
 927     for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
 928         size_t offset = i * (limit / 2);
 929         size_t rem = (rxsize / 2) - offset;
 930
 931         /* HP3: INTRQ_Wait */
 932         ide_wait_intr(IDE_PRIMARY_IRQ);
 933
 934         /* HP2: Check_Status_B (and clear IRQ) */
 935         data = ide_wait_clear(BSY);
 936         assert_bit_set(data, DRQ | DRDY);
 937         assert_bit_clear(data, ERR | DF | BSY);
 938
 939         /* HP4: Transfer_Data */
 940         for (j = 0; j < MIN((limit / 2), rem); j++) {
 941             rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar,
 942                                                        reg_data));
 943         }
 944     }
 945
 946     /* Check for final completion IRQ */
 947     ide_wait_intr(IDE_PRIMARY_IRQ);
 948
 949     /* Sanity check final state */
 950     data = ide_wait_clear(DRQ);
 951     assert_bit_set(data, DRDY);
 952     assert_bit_clear(data, DRQ | ERR | DF | BSY);
 953
 954     g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0);
 955     g_free(pattern);
 956     g_free(rx);
 957     test_bmdma_teardown();
 958     free_pci_device(dev);
 959 }
 960
 961 static void test_cdrom_pio(void)
 962 {
 963     cdrom_pio_impl(1);
 964 }
 965
 966 static void test_cdrom_pio_large(void)
 967 {
 968     /* Test a few loops of the PIO DRQ mechanism. */
 969     cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE);
 970 }
 971
 972
 973 static void test_cdrom_dma(void)
 974 {
 975     static const size_t len = ATAPI_BLOCK_SIZE;
 976     size_t ret;
 977     char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
 978     char *rx = g_malloc0(len);
 979     uintptr_t guest_buf;
 980     PrdtEntry prdt[1];
 981     FILE *fh;
 982
 983     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
 984                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
 985     qtest_irq_intercept_in(global_qtest, "ioapic");
 986
 987     guest_buf = guest_alloc(guest_malloc, len);
 988     prdt[0].addr = cpu_to_le32(guest_buf);
 989     prdt[0].size = cpu_to_le32(len | PRDT_EOT);
 990
 991     generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
 992     fh = fopen(tmp_path, "w+");
 993     ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
 994     g_assert_cmpint(ret, ==, 16);
 995     fclose(fh);
 996
 997     send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);
 998
 999     /* Read back data from guest memory into local qtest memory */
1000     memread(guest_buf, rx, len);
1001     g_assert_cmpint(memcmp(pattern, rx, len), ==, 0);
1002
1003     g_free(pattern);
1004     g_free(rx);
1005     test_bmdma_teardown();
1006 }
1007
1008 int main(int argc, char **argv)
1009 {
1010     const char *arch = qtest_get_arch();
1011     int fd;
1012     int ret;
1013
1014     /* Check architecture */
1015     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1016         g_test_message("Skipping test for non-x86\n");
1017         return 0;
1018     }
1019
1020     /* Create temporary blkdebug instructions */
1021     fd = mkstemp(debug_path);
1022     g_assert(fd >= 0);
1023     close(fd);
1024
1025     /* Create a temporary raw image */
1026     fd = mkstemp(tmp_path);
1027     g_assert(fd >= 0);
1028     ret = ftruncate(fd, TEST_IMAGE_SIZE);
1029     g_assert(ret == 0);
1030     close(fd);
1031
1032     /* Run the tests */
1033     g_test_init(&argc, &argv, NULL);
1034
1035     qtest_add_func("/ide/identify", test_identify);
1036
1037     qtest_add_func("/ide/bmdma/setup", test_bmdma_setup);
1038     qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
1039     qtest_add_func("/ide/bmdma/trim", test_bmdma_trim);
1040     qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt);
1041     qtest_add_func("/ide/bmdma/one_sector_short_prdt",
1042                    test_bmdma_one_sector_short_prdt);
1043     qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt);
1044     qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
1045     qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown);
1046
1047     qtest_add_func("/ide/flush", test_flush);
1048     qtest_add_func("/ide/flush/nodev", test_flush_nodev);
1049     qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive);
1050     qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush);
1051     qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush);
1052
1053     qtest_add_func("/ide/cdrom/pio", test_cdrom_pio);
1054     qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large);
1055     qtest_add_func("/ide/cdrom/dma", test_cdrom_dma);
1056
1057     ret = g_test_run();
1058
1059     /* Cleanup */
1060     unlink(tmp_path);
1061     unlink(debug_path);
1062
1063     return ret;
1064 }