build-sys: add a "pixman" feature
[qemu/ar7.git] / hw / usb / hcd-ohci.h
blobe1827227ac3a503dd8f50ec03645d4dcf0821703
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef HCD_OHCI_H
22 #define HCD_OHCI_H
24 #include "hw/sysbus.h"
25 #include "sysemu/dma.h"
26 #include "hw/usb.h"
27 #include "qom/object.h"
29 /* Number of Downstream Ports on the root hub: */
30 #define OHCI_MAX_PORTS 15
32 typedef struct OHCIPort {
33 USBPort port;
34 uint32_t ctrl;
35 } OHCIPort;
37 typedef struct OHCIState OHCIState;
39 struct OHCIState {
40 USBBus bus;
41 qemu_irq irq;
42 MemoryRegion mem;
43 AddressSpace *as;
44 uint32_t num_ports;
45 const char *name;
47 QEMUTimer *eof_timer;
48 int64_t sof_time;
50 /* OHCI state */
51 /* Control partition */
52 uint32_t ctl, status;
53 uint32_t intr_status;
54 uint32_t intr;
56 /* memory pointer partition */
57 uint32_t hcca;
58 uint32_t ctrl_head, ctrl_cur;
59 uint32_t bulk_head, bulk_cur;
60 uint32_t per_cur;
61 uint32_t done;
62 int32_t done_count;
64 /* Frame counter partition */
65 uint16_t fsmps;
66 uint8_t fit;
67 uint16_t fi;
68 uint8_t frt;
69 uint16_t frame_number;
70 uint16_t padding;
71 uint32_t pstart;
72 uint32_t lst;
74 /* Root Hub partition */
75 uint32_t rhdesc_a, rhdesc_b;
76 uint32_t rhstatus;
77 OHCIPort rhport[OHCI_MAX_PORTS];
79 /* PXA27x Non-OHCI events */
80 uint32_t hstatus;
81 uint32_t hmask;
82 uint32_t hreset;
83 uint32_t htest;
85 /* SM501 local memory offset */
86 dma_addr_t localmem_base;
88 /* Active packets. */
89 uint32_t old_ctl;
90 USBPacket usb_packet;
91 uint8_t usb_buf[8192];
92 uint32_t async_td;
93 bool async_complete;
95 void (*ohci_die)(OHCIState *ohci);
98 #define TYPE_SYSBUS_OHCI "sysbus-ohci"
99 OBJECT_DECLARE_SIMPLE_TYPE(OHCISysBusState, SYSBUS_OHCI)
101 struct OHCISysBusState {
102 /*< private >*/
103 SysBusDevice parent_obj;
104 /*< public >*/
106 OHCIState ohci;
107 char *masterbus;
108 uint32_t num_ports;
109 uint32_t firstport;
110 dma_addr_t dma_offset;
113 extern const VMStateDescription vmstate_ohci_state;
115 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
116 dma_addr_t localmem_base, char *masterbus,
117 uint32_t firstport, AddressSpace *as,
118 void (*ohci_die_fn)(OHCIState *), Error **errp);
119 void ohci_bus_stop(OHCIState *ohci);
120 void ohci_stop_endpoints(OHCIState *ohci);
121 void ohci_hard_reset(OHCIState *ohci);
122 void ohci_sysbus_die(struct OHCIState *ohci);
124 #endif