2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUState struct CPUXtensaState
37 #include "qemu-common.h"
40 #define TARGET_HAS_ICE 1
42 #define NB_MMU_MODES 4
44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 #define TARGET_PAGE_BITS 12
49 /* Additional instructions */
50 XTENSA_OPTION_CODE_DENSITY
,
52 XTENSA_OPTION_EXTENDED_L32R
,
53 XTENSA_OPTION_16_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
56 XTENSA_OPTION_32_BIT_IDIV
,
58 XTENSA_OPTION_MISC_OP_NSA
,
59 XTENSA_OPTION_MISC_OP_MINMAX
,
60 XTENSA_OPTION_MISC_OP_SEXT
,
61 XTENSA_OPTION_MISC_OP_CLAMPS
,
62 XTENSA_OPTION_COPROCESSOR
,
63 XTENSA_OPTION_BOOLEAN
,
64 XTENSA_OPTION_FP_COPROCESSOR
,
65 XTENSA_OPTION_MP_SYNCHRO
,
66 XTENSA_OPTION_CONDITIONAL_STORE
,
68 /* Interrupts and exceptions */
69 XTENSA_OPTION_EXCEPTION
,
70 XTENSA_OPTION_RELOCATABLE_VECTOR
,
71 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
72 XTENSA_OPTION_INTERRUPT
,
73 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
74 XTENSA_OPTION_TIMER_INTERRUPT
,
78 XTENSA_OPTION_ICACHE_TEST
,
79 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
81 XTENSA_OPTION_DCACHE_TEST
,
82 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
88 XTENSA_OPTION_HW_ALIGNMENT
,
89 XTENSA_OPTION_MEMORY_ECC_PARITY
,
91 /* Memory protection and translation */
92 XTENSA_OPTION_REGION_PROTECTION
,
93 XTENSA_OPTION_REGION_TRANSLATION
,
97 XTENSA_OPTION_WINDOWED_REGISTER
,
98 XTENSA_OPTION_PROCESSOR_INTERFACE
,
99 XTENSA_OPTION_MISC_SR
,
100 XTENSA_OPTION_THREAD_POINTER
,
101 XTENSA_OPTION_PROCESSOR_ID
,
103 XTENSA_OPTION_TRACE_PORT
,
146 #define PS_INTLEVEL 0xf
147 #define PS_INTLEVEL_SHIFT 0
153 #define PS_RING_SHIFT 6
156 #define PS_OWB_SHIFT 8
158 #define PS_CALLINC 0x30000
159 #define PS_CALLINC_SHIFT 16
160 #define PS_CALLINC_LEN 2
162 #define PS_WOE 0x40000
165 #define MAX_NINTERRUPT 32
168 #define MAX_NCCOMPARE 3
169 #define MAX_TLB_WAY_SIZE 8
171 #define REGION_PAGE_MASK 0xe0000000
178 /* Dynamic vectors */
179 EXC_WINDOW_OVERFLOW4
,
180 EXC_WINDOW_UNDERFLOW4
,
181 EXC_WINDOW_OVERFLOW8
,
182 EXC_WINDOW_UNDERFLOW8
,
183 EXC_WINDOW_OVERFLOW12
,
184 EXC_WINDOW_UNDERFLOW12
,
193 ILLEGAL_INSTRUCTION_CAUSE
= 0,
195 INSTRUCTION_FETCH_ERROR_CAUSE
,
196 LOAD_STORE_ERROR_CAUSE
,
197 LEVEL1_INTERRUPT_CAUSE
,
199 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
200 PRIVILEGED_CAUSE
= 8,
201 LOAD_STORE_ALIGNMENT_CAUSE
,
203 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
204 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
205 INSTR_PIF_ADDR_ERROR_CAUSE
,
206 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
209 INST_TLB_MULTI_HIT_CAUSE
,
210 INST_FETCH_PRIVILEGE_CAUSE
,
211 INST_FETCH_PROHIBITED_CAUSE
= 20,
212 LOAD_STORE_TLB_MISS_CAUSE
= 24,
213 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
214 LOAD_STORE_PRIVILEGE_CAUSE
,
215 LOAD_PROHIBITED_CAUSE
= 28,
216 STORE_PROHIBITED_CAUSE
,
218 COPROCESSOR0_DISABLED
= 32,
232 typedef struct xtensa_tlb_entry
{
240 typedef struct xtensa_tlb
{
242 const unsigned way_size
[10];
244 unsigned nrefillentries
;
247 typedef struct XtensaGdbReg
{
253 typedef struct XtensaGdbRegmap
{
256 /* PC + a + ar + sr + ur */
257 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
260 typedef struct XtensaConfig
{
263 XtensaGdbRegmap gdb_regmap
;
268 uint32_t exception_vector
[EXC_MAX
];
271 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
272 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
273 uint32_t inttype_mask
[INTTYPE_MAX
];
276 interrupt_type inttype
;
277 } interrupt
[MAX_NINTERRUPT
];
279 uint32_t timerint
[MAX_NCCOMPARE
];
281 unsigned extint
[MAX_NINTERRUPT
];
282 uint32_t clock_freq_khz
;
288 typedef struct XtensaConfigList
{
289 const XtensaConfig
*config
;
290 struct XtensaConfigList
*next
;
293 typedef struct CPUXtensaState
{
294 const XtensaConfig
*config
;
299 uint32_t phys_regs
[MAX_NAREG
];
301 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
302 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
303 unsigned autorefill_idx
;
305 int pending_irq_level
; /* level of last raised IRQ */
307 QEMUTimer
*ccompare_timer
;
308 uint32_t wake_ccount
;
316 #define cpu_init cpu_xtensa_init
317 #define cpu_exec cpu_xtensa_exec
318 #define cpu_gen_code cpu_xtensa_gen_code
319 #define cpu_signal_handler cpu_xtensa_signal_handler
320 #define cpu_list xtensa_cpu_list
322 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
);
323 void xtensa_translate_init(void);
324 int cpu_xtensa_exec(CPUXtensaState
*s
);
325 void xtensa_register_core(XtensaConfigList
*node
);
326 void do_interrupt(CPUXtensaState
*s
);
327 void check_interrupts(CPUXtensaState
*s
);
328 void xtensa_irq_init(CPUState
*env
);
329 void *xtensa_get_extint(CPUState
*env
, unsigned extint
);
330 void xtensa_advance_ccount(CPUState
*env
, uint32_t d
);
331 void xtensa_timer_irq(CPUState
*env
, uint32_t id
, uint32_t active
);
332 void xtensa_rearm_ccompare_timer(CPUState
*env
);
333 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
334 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
335 void xtensa_sync_window_from_phys(CPUState
*env
);
336 void xtensa_sync_phys_from_window(CPUState
*env
);
337 uint32_t xtensa_tlb_get_addr_mask(const CPUState
*env
, bool dtlb
, uint32_t way
);
338 void split_tlb_entry_spec_way(const CPUState
*env
, uint32_t v
, bool dtlb
,
339 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
340 int xtensa_tlb_lookup(const CPUState
*env
, uint32_t addr
, bool dtlb
,
341 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
342 void xtensa_tlb_set_entry(CPUState
*env
, bool dtlb
,
343 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
344 int xtensa_get_physical_addr(CPUState
*env
,
345 uint32_t vaddr
, int is_write
, int mmu_idx
,
346 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
349 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
351 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
354 return (config
->options
& opt
) != 0;
357 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
359 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
362 static inline int xtensa_get_cintlevel(const CPUState
*env
)
364 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
365 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
366 level
= env
->config
->excm_level
;
371 static inline int xtensa_get_ring(const CPUState
*env
)
373 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
374 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
380 static inline int xtensa_get_cring(const CPUState
*env
)
382 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
383 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
384 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
390 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUState
*env
,
391 bool dtlb
, unsigned wi
, unsigned ei
)
398 /* MMU modes definitions */
399 #define MMU_MODE0_SUFFIX _ring0
400 #define MMU_MODE1_SUFFIX _ring1
401 #define MMU_MODE2_SUFFIX _ring2
402 #define MMU_MODE3_SUFFIX _ring3
404 static inline int cpu_mmu_index(CPUState
*env
)
406 return xtensa_get_cring(env
);
409 #define XTENSA_TBFLAG_RING_MASK 0x3
410 #define XTENSA_TBFLAG_EXCM 0x4
411 #define XTENSA_TBFLAG_LITBASE 0x8
413 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
414 target_ulong
*cs_base
, int *flags
)
419 *flags
|= xtensa_get_ring(env
);
420 if (env
->sregs
[PS
] & PS_EXCM
) {
421 *flags
|= XTENSA_TBFLAG_EXCM
;
423 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
424 (env
->sregs
[LITBASE
] & 1)) {
425 *flags
|= XTENSA_TBFLAG_LITBASE
;
430 #include "exec-all.h"
432 static inline int cpu_has_work(CPUState
*env
)
434 return env
->pending_irq_level
;
437 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)