2 * Miscellaneous PowerPC emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/error-report.h"
25 #include "qemu/main-loop.h"
27 #include "helper_regs.h"
29 /*****************************************************************************/
31 void helper_load_dump_spr(CPUPPCState
*env
, uint32_t sprn
)
33 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx
"\n", sprn
, sprn
,
37 void helper_store_dump_spr(CPUPPCState
*env
, uint32_t sprn
)
39 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx
"\n", sprn
, sprn
,
44 static void raise_hv_fu_exception(CPUPPCState
*env
, uint32_t bit
,
45 const char *caller
, uint32_t cause
,
48 qemu_log_mask(CPU_LOG_INT
, "HV Facility %d is unavailable (%s)\n",
51 env
->spr
[SPR_HFSCR
] &= ~((target_ulong
)FSCR_IC_MASK
<< FSCR_IC_POS
);
53 raise_exception_err_ra(env
, POWERPC_EXCP_HV_FU
, cause
, raddr
);
56 static void raise_fu_exception(CPUPPCState
*env
, uint32_t bit
,
57 uint32_t sprn
, uint32_t cause
,
60 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn
, bit
);
62 env
->spr
[SPR_FSCR
] &= ~((target_ulong
)FSCR_IC_MASK
<< FSCR_IC_POS
);
63 cause
&= FSCR_IC_MASK
;
64 env
->spr
[SPR_FSCR
] |= (target_ulong
)cause
<< FSCR_IC_POS
;
66 raise_exception_err_ra(env
, POWERPC_EXCP_FU
, 0, raddr
);
70 void helper_hfscr_facility_check(CPUPPCState
*env
, uint32_t bit
,
71 const char *caller
, uint32_t cause
)
74 if ((env
->msr_mask
& MSR_HVB
) && !msr_hv
&&
75 !(env
->spr
[SPR_HFSCR
] & (1UL << bit
))) {
76 raise_hv_fu_exception(env
, bit
, caller
, cause
, GETPC());
81 void helper_fscr_facility_check(CPUPPCState
*env
, uint32_t bit
,
82 uint32_t sprn
, uint32_t cause
)
85 if (env
->spr
[SPR_FSCR
] & (1ULL << bit
)) {
86 /* Facility is enabled, continue */
89 raise_fu_exception(env
, bit
, sprn
, cause
, GETPC());
93 void helper_msr_facility_check(CPUPPCState
*env
, uint32_t bit
,
94 uint32_t sprn
, uint32_t cause
)
97 if (env
->msr
& (1ULL << bit
)) {
98 /* Facility is enabled, continue */
101 raise_fu_exception(env
, bit
, sprn
, cause
, GETPC());
105 #if !defined(CONFIG_USER_ONLY)
107 void helper_store_sdr1(CPUPPCState
*env
, target_ulong val
)
109 if (env
->spr
[SPR_SDR1
] != val
) {
110 ppc_store_sdr1(env
, val
);
111 tlb_flush(env_cpu(env
));
115 #if defined(TARGET_PPC64)
116 void helper_store_ptcr(CPUPPCState
*env
, target_ulong val
)
118 if (env
->spr
[SPR_PTCR
] != val
) {
119 ppc_store_ptcr(env
, val
);
120 tlb_flush(env_cpu(env
));
124 void helper_store_pcr(CPUPPCState
*env
, target_ulong value
)
126 PowerPCCPU
*cpu
= env_archcpu(env
);
127 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
129 env
->spr
[SPR_PCR
] = value
& pcc
->pcr_mask
;
133 * DPDES register is shared. Each bit reflects the state of the
134 * doorbell interrupt of a thread of the same core.
136 target_ulong
helper_load_dpdes(CPUPPCState
*env
)
138 target_ulong dpdes
= 0;
140 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "load DPDES", HFSCR_IC_MSGP
);
142 /* TODO: TCG supports only one thread */
143 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DOORBELL
)) {
150 void helper_store_dpdes(CPUPPCState
*env
, target_ulong val
)
152 PowerPCCPU
*cpu
= env_archcpu(env
);
153 CPUState
*cs
= CPU(cpu
);
155 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "store DPDES", HFSCR_IC_MSGP
);
157 /* TODO: TCG supports only one thread */
159 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid DPDES register value "
160 TARGET_FMT_lx
"\n", val
);
165 env
->pending_interrupts
|= 1 << PPC_INTERRUPT_DOORBELL
;
166 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
168 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DOORBELL
);
171 #endif /* defined(TARGET_PPC64) */
173 void helper_store_pidr(CPUPPCState
*env
, target_ulong val
)
175 env
->spr
[SPR_BOOKS_PID
] = val
;
176 tlb_flush(env_cpu(env
));
179 void helper_store_lpidr(CPUPPCState
*env
, target_ulong val
)
181 env
->spr
[SPR_LPIDR
] = val
;
184 * We need to flush the TLB on LPID changes as we only tag HV vs
185 * guest in TCG TLB. Also the quadrants means the HV will
186 * potentially access and cache entries for the current LPID as
189 tlb_flush(env_cpu(env
));
192 void helper_store_hid0_601(CPUPPCState
*env
, target_ulong val
)
196 hid0
= env
->spr
[SPR_HID0
];
197 if ((val
^ hid0
) & 0x00000008) {
198 /* Change current endianness */
199 env
->hflags
&= ~(1 << MSR_LE
);
200 env
->hflags_nmsr
&= ~(1 << MSR_LE
);
201 env
->hflags_nmsr
|= (1 << MSR_LE
) & (((val
>> 3) & 1) << MSR_LE
);
202 env
->hflags
|= env
->hflags_nmsr
;
203 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx
"\n", __func__
,
204 val
& 0x8 ? 'l' : 'b', env
->hflags
);
206 env
->spr
[SPR_HID0
] = (uint32_t)val
;
209 void helper_store_403_pbr(CPUPPCState
*env
, uint32_t num
, target_ulong value
)
211 if (likely(env
->pb
[num
] != value
)) {
212 env
->pb
[num
] = value
;
213 /* Should be optimized */
214 tlb_flush(env_cpu(env
));
218 void helper_store_40x_dbcr0(CPUPPCState
*env
, target_ulong val
)
220 store_40x_dbcr0(env
, val
);
223 void helper_store_40x_sler(CPUPPCState
*env
, target_ulong val
)
225 store_40x_sler(env
, val
);
228 /*****************************************************************************/
229 /* PowerPC 601 specific instructions (POWER bridge) */
231 target_ulong
helper_clcs(CPUPPCState
*env
, uint32_t arg
)
235 /* Instruction cache line size */
236 return env
->icache_line_size
;
239 /* Data cache line size */
240 return env
->dcache_line_size
;
243 /* Minimum cache line size */
244 return (env
->icache_line_size
< env
->dcache_line_size
) ?
245 env
->icache_line_size
: env
->dcache_line_size
;
248 /* Maximum cache line size */
249 return (env
->icache_line_size
> env
->dcache_line_size
) ?
250 env
->icache_line_size
: env
->dcache_line_size
;
259 /*****************************************************************************/
260 /* Special registers manipulation */
262 /* GDBstub can read and write MSR... */
263 void ppc_store_msr(CPUPPCState
*env
, target_ulong value
)
265 hreg_store_msr(env
, value
, 0);
269 * This code is lifted from MacOnLinux. It is called whenever THRM1,2
270 * or 3 is read an fixes up the values in such a way that will make
271 * MacOS not hang. These registers exist on some 75x and 74xx
274 void helper_fixup_thrm(CPUPPCState
*env
)
279 #define THRM1_TIN (1 << 31)
280 #define THRM1_TIV (1 << 30)
281 #define THRM1_THRES(x) (((x) & 0x7f) << 23)
282 #define THRM1_TID (1 << 2)
283 #define THRM1_TIE (1 << 1)
284 #define THRM1_V (1 << 0)
285 #define THRM3_E (1 << 0)
287 if (!(env
->spr
[SPR_THRM3
] & THRM3_E
)) {
291 /* Note: Thermal interrupts are unimplemented */
292 for (i
= SPR_THRM1
; i
<= SPR_THRM2
; i
++) {
294 if (!(v
& THRM1_V
)) {
299 t
= v
& THRM1_THRES(127);
300 if ((v
& THRM1_TID
) && t
< THRM1_THRES(24)) {
303 if (!(v
& THRM1_TID
) && t
> THRM1_THRES(24)) {