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smbios: fix typo
[qemu/ar7.git] / target-ppc / translate.c
blobd485d7c7cb181b065eb4a40f5c7e8ccb4df9f496
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/host-utils.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32 #include "exec/log.h"
33
34
35 #define CPU_SINGLE_STEP 0x1
36 #define CPU_BRANCH_STEP 0x2
37 #define GDBSTUB_SINGLE_STEP 0x4
38
39 /* Include definitions for instructions classes and implementations flags */
40 //#define PPC_DEBUG_DISAS
41 //#define DO_PPC_STATISTICS
42
43 #ifdef PPC_DEBUG_DISAS
44 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
45 #else
46 # define LOG_DISAS(...) do { } while (0)
47 #endif
48 /*****************************************************************************/
49 /* Code translation helpers */
50
51 /* global register indexes */
52 static TCGv_env cpu_env;
53 static char cpu_reg_names[10*3 + 22*4 /* GPR */
54 + 10*4 + 22*5 /* SPE GPRh */
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 10*5 + 22*6 /* VSR */
58 + 8*5 /* CRF */];
59 static TCGv cpu_gpr[32];
60 static TCGv cpu_gprh[32];
61 static TCGv_i64 cpu_fpr[32];
62 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63 static TCGv_i64 cpu_vsr[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 #if defined(TARGET_PPC64)
70 static TCGv cpu_cfar;
71 #endif
72 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
73 static TCGv cpu_reserve;
74 static TCGv cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76
77 #include "exec/gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char* p;
83 size_t cpu_reg_names_size;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92 cpu_reg_names_size = sizeof(cpu_reg_names);
93
94 for (i = 0; i < 8; i++) {
95 snprintf(p, cpu_reg_names_size, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
97 offsetof(CPUPPCState, crf[i]), p);
98 p += 5;
99 cpu_reg_names_size -= 5;
100 }
101
102 for (i = 0; i < 32; i++) {
103 snprintf(p, cpu_reg_names_size, "r%d", i);
104 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
105 offsetof(CPUPPCState, gpr[i]), p);
106 p += (i < 10) ? 3 : 4;
107 cpu_reg_names_size -= (i < 10) ? 3 : 4;
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113
114 snprintf(p, cpu_reg_names_size, "fp%d", i);
115 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
116 offsetof(CPUPPCState, fpr[i]), p);
117 p += (i < 10) ? 4 : 5;
118 cpu_reg_names_size -= (i < 10) ? 4 : 5;
119
120 snprintf(p, cpu_reg_names_size, "avr%dH", i);
121 #ifdef HOST_WORDS_BIGENDIAN
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[0]), p);
124 #else
125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
126 offsetof(CPUPPCState, avr[i].u64[1]), p);
127 #endif
128 p += (i < 10) ? 6 : 7;
129 cpu_reg_names_size -= (i < 10) ? 6 : 7;
130
131 snprintf(p, cpu_reg_names_size, "avr%dL", i);
132 #ifdef HOST_WORDS_BIGENDIAN
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[1]), p);
135 #else
136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
137 offsetof(CPUPPCState, avr[i].u64[0]), p);
138 #endif
139 p += (i < 10) ? 6 : 7;
140 cpu_reg_names_size -= (i < 10) ? 6 : 7;
141 snprintf(p, cpu_reg_names_size, "vsr%d", i);
142 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
143 offsetof(CPUPPCState, vsr[i]), p);
144 p += (i < 10) ? 5 : 6;
145 cpu_reg_names_size -= (i < 10) ? 5 : 6;
146 }
147
148 cpu_nip = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, nip), "nip");
150
151 cpu_msr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, msr), "msr");
153
154 cpu_ctr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, ctr), "ctr");
156
157 cpu_lr = tcg_global_mem_new(cpu_env,
158 offsetof(CPUPPCState, lr), "lr");
159
160 #if defined(TARGET_PPC64)
161 cpu_cfar = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, cfar), "cfar");
163 #endif
164
165 cpu_xer = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, xer), "xer");
167 cpu_so = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, so), "SO");
169 cpu_ov = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, ov), "OV");
171 cpu_ca = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ca), "CA");
173
174 cpu_reserve = tcg_global_mem_new(cpu_env,
175 offsetof(CPUPPCState, reserve_addr),
176 "reserve_addr");
177
178 cpu_fpscr = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, fpscr), "fpscr");
180
181 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
182 offsetof(CPUPPCState, access_type), "access_type");
183
184 done_init = 1;
185 }
186
187 /* internal defines */
188 struct DisasContext {
189 struct TranslationBlock *tb;
190 target_ulong nip;
191 uint32_t opcode;
192 uint32_t exception;
193 /* Routine used to access memory */
194 bool pr, hv;
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 TCGMemOp default_tcg_memop_mask;
200 #if defined(TARGET_PPC64)
201 int sf_mode;
202 int has_cfar;
203 #endif
204 int fpu_enabled;
205 int altivec_enabled;
206 int vsx_enabled;
207 int spe_enabled;
208 int tm_enabled;
209 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
210 int singlestep_enabled;
211 uint64_t insns_flags;
212 uint64_t insns_flags2;
213 };
214
215 /* Return true iff byteswap is needed in a scalar memop */
216 static inline bool need_byteswap(const DisasContext *ctx)
217 {
218 #if defined(TARGET_WORDS_BIGENDIAN)
219 return ctx->le_mode;
220 #else
221 return !ctx->le_mode;
222 #endif
223 }
224
225 /* True when active word size < size of target_long. */
226 #ifdef TARGET_PPC64
227 # define NARROW_MODE(C) (!(C)->sf_mode)
228 #else
229 # define NARROW_MODE(C) 0
230 #endif
231
232 struct opc_handler_t {
233 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
234 uint32_t inval1;
235 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
236 uint32_t inval2;
237 /* instruction type */
238 uint64_t type;
239 /* extended instruction type */
240 uint64_t type2;
241 /* handler */
242 void (*handler)(DisasContext *ctx);
243 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
244 const char *oname;
245 #endif
246 #if defined(DO_PPC_STATISTICS)
247 uint64_t count;
248 #endif
249 };
250
251 static inline void gen_reset_fpstatus(void)
252 {
253 gen_helper_reset_fpstatus(cpu_env);
254 }
255
256 static inline void gen_compute_fprf(TCGv_i64 arg)
257 {
258 gen_helper_compute_fprf(cpu_env, arg);
259 gen_helper_float_check_status(cpu_env);
260 }
261
262 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
263 {
264 if (ctx->access_type != access_type) {
265 tcg_gen_movi_i32(cpu_access_type, access_type);
266 ctx->access_type = access_type;
267 }
268 }
269
270 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
271 {
272 if (NARROW_MODE(ctx)) {
273 nip = (uint32_t)nip;
274 }
275 tcg_gen_movi_tl(cpu_nip, nip);
276 }
277
278 void gen_update_current_nip(void *opaque)
279 {
280 DisasContext *ctx = opaque;
281
282 tcg_gen_movi_tl(cpu_nip, ctx->nip);
283 }
284
285 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
286 {
287 TCGv_i32 t0, t1;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 t1 = tcg_const_i32(error);
293 gen_helper_raise_exception_err(cpu_env, t0, t1);
294 tcg_temp_free_i32(t0);
295 tcg_temp_free_i32(t1);
296 ctx->exception = (excp);
297 }
298
299 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
300 {
301 TCGv_i32 t0;
302 if (ctx->exception == POWERPC_EXCP_NONE) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(excp);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 ctx->exception = (excp);
309 }
310
311 static inline void gen_debug_exception(DisasContext *ctx)
312 {
313 TCGv_i32 t0;
314
315 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
316 (ctx->exception != POWERPC_EXCP_SYNC)) {
317 gen_update_nip(ctx, ctx->nip);
318 }
319 t0 = tcg_const_i32(EXCP_DEBUG);
320 gen_helper_raise_exception(cpu_env, t0);
321 tcg_temp_free_i32(t0);
322 }
323
324 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
325 {
326 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
327 }
328
329 /* Stop translation */
330 static inline void gen_stop_exception(DisasContext *ctx)
331 {
332 gen_update_nip(ctx, ctx->nip);
333 ctx->exception = POWERPC_EXCP_STOP;
334 }
335
336 #ifndef CONFIG_USER_ONLY
337 /* No need to update nip here, as execution flow will change */
338 static inline void gen_sync_exception(DisasContext *ctx)
339 {
340 ctx->exception = POWERPC_EXCP_SYNC;
341 }
342 #endif
343
344 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
345 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
346
347 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
349
350 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
351 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
352
353 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
355
356 typedef struct opcode_t {
357 unsigned char opc1, opc2, opc3;
358 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
359 unsigned char pad[5];
360 #else
361 unsigned char pad[1];
362 #endif
363 opc_handler_t handler;
364 const char *oname;
365 } opcode_t;
366
367 /*****************************************************************************/
368 /*** Instruction decoding ***/
369 #define EXTRACT_HELPER(name, shift, nb) \
370 static inline uint32_t name(uint32_t opcode) \
371 { \
372 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
373 }
374
375 #define EXTRACT_SHELPER(name, shift, nb) \
376 static inline int32_t name(uint32_t opcode) \
377 { \
378 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
379 }
380
381 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
382 static inline uint32_t name(uint32_t opcode) \
383 { \
384 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
385 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
386 }
387 /* Opcode part 1 */
388 EXTRACT_HELPER(opc1, 26, 6);
389 /* Opcode part 2 */
390 EXTRACT_HELPER(opc2, 1, 5);
391 /* Opcode part 3 */
392 EXTRACT_HELPER(opc3, 6, 5);
393 /* Update Cr0 flags */
394 EXTRACT_HELPER(Rc, 0, 1);
395 /* Update Cr6 flags (Altivec) */
396 EXTRACT_HELPER(Rc21, 10, 1);
397 /* Destination */
398 EXTRACT_HELPER(rD, 21, 5);
399 /* Source */
400 EXTRACT_HELPER(rS, 21, 5);
401 /* First operand */
402 EXTRACT_HELPER(rA, 16, 5);
403 /* Second operand */
404 EXTRACT_HELPER(rB, 11, 5);
405 /* Third operand */
406 EXTRACT_HELPER(rC, 6, 5);
407 /*** Get CRn ***/
408 EXTRACT_HELPER(crfD, 23, 3);
409 EXTRACT_HELPER(crfS, 18, 3);
410 EXTRACT_HELPER(crbD, 21, 5);
411 EXTRACT_HELPER(crbA, 16, 5);
412 EXTRACT_HELPER(crbB, 11, 5);
413 /* SPR / TBL */
414 EXTRACT_HELPER(_SPR, 11, 10);
415 static inline uint32_t SPR(uint32_t opcode)
416 {
417 uint32_t sprn = _SPR(opcode);
418
419 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
420 }
421 /*** Get constants ***/
422 /* 16 bits signed immediate value */
423 EXTRACT_SHELPER(SIMM, 0, 16);
424 /* 16 bits unsigned immediate value */
425 EXTRACT_HELPER(UIMM, 0, 16);
426 /* 5 bits signed immediate value */
427 EXTRACT_HELPER(SIMM5, 16, 5);
428 /* 5 bits signed immediate value */
429 EXTRACT_HELPER(UIMM5, 16, 5);
430 /* Bit count */
431 EXTRACT_HELPER(NB, 11, 5);
432 /* Shift count */
433 EXTRACT_HELPER(SH, 11, 5);
434 /* Vector shift count */
435 EXTRACT_HELPER(VSH, 6, 4);
436 /* Mask start */
437 EXTRACT_HELPER(MB, 6, 5);
438 /* Mask end */
439 EXTRACT_HELPER(ME, 1, 5);
440 /* Trap operand */
441 EXTRACT_HELPER(TO, 21, 5);
442
443 EXTRACT_HELPER(CRM, 12, 8);
444
445 #ifndef CONFIG_USER_ONLY
446 EXTRACT_HELPER(SR, 16, 4);
447 #endif
448
449 /* mtfsf/mtfsfi */
450 EXTRACT_HELPER(FPBF, 23, 3);
451 EXTRACT_HELPER(FPIMM, 12, 4);
452 EXTRACT_HELPER(FPL, 25, 1);
453 EXTRACT_HELPER(FPFLM, 17, 8);
454 EXTRACT_HELPER(FPW, 16, 1);
455
456 /*** Jump target decoding ***/
457 /* Immediate address */
458 static inline target_ulong LI(uint32_t opcode)
459 {
460 return (opcode >> 0) & 0x03FFFFFC;
461 }
462
463 static inline uint32_t BD(uint32_t opcode)
464 {
465 return (opcode >> 0) & 0xFFFC;
466 }
467
468 EXTRACT_HELPER(BO, 21, 5);
469 EXTRACT_HELPER(BI, 16, 5);
470 /* Absolute/relative address */
471 EXTRACT_HELPER(AA, 1, 1);
472 /* Link */
473 EXTRACT_HELPER(LK, 0, 1);
474
475 /* DFP Z22-form */
476 EXTRACT_HELPER(DCM, 10, 6)
477
478 /* DFP Z23-form */
479 EXTRACT_HELPER(RMC, 9, 2)
480
481 /* Create a mask between <start> and <end> bits */
482 static inline target_ulong MASK(uint32_t start, uint32_t end)
483 {
484 target_ulong ret;
485
486 #if defined(TARGET_PPC64)
487 if (likely(start == 0)) {
488 ret = UINT64_MAX << (63 - end);
489 } else if (likely(end == 63)) {
490 ret = UINT64_MAX >> start;
491 }
492 #else
493 if (likely(start == 0)) {
494 ret = UINT32_MAX << (31 - end);
495 } else if (likely(end == 31)) {
496 ret = UINT32_MAX >> start;
497 }
498 #endif
499 else {
500 ret = (((target_ulong)(-1ULL)) >> (start)) ^
501 (((target_ulong)(-1ULL) >> (end)) >> 1);
502 if (unlikely(start > end))
503 return ~ret;
504 }
505
506 return ret;
507 }
508
509 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
510 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
512 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
513 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
514 EXTRACT_HELPER(DM, 8, 2);
515 EXTRACT_HELPER(UIM, 16, 2);
516 EXTRACT_HELPER(SHW, 8, 2);
517 EXTRACT_HELPER(SP, 19, 2);
518 /*****************************************************************************/
519 /* PowerPC instructions table */
520
521 #if defined(DO_PPC_STATISTICS)
522 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
523 { \
524 .opc1 = op1, \
525 .opc2 = op2, \
526 .opc3 = op3, \
527 .pad = { 0, }, \
528 .handler = { \
529 .inval1 = invl, \
530 .type = _typ, \
531 .type2 = _typ2, \
532 .handler = &gen_##name, \
533 .oname = stringify(name), \
534 }, \
535 .oname = stringify(name), \
536 }
537 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
538 { \
539 .opc1 = op1, \
540 .opc2 = op2, \
541 .opc3 = op3, \
542 .pad = { 0, }, \
543 .handler = { \
544 .inval1 = invl1, \
545 .inval2 = invl2, \
546 .type = _typ, \
547 .type2 = _typ2, \
548 .handler = &gen_##name, \
549 .oname = stringify(name), \
550 }, \
551 .oname = stringify(name), \
552 }
553 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
554 { \
555 .opc1 = op1, \
556 .opc2 = op2, \
557 .opc3 = op3, \
558 .pad = { 0, }, \
559 .handler = { \
560 .inval1 = invl, \
561 .type = _typ, \
562 .type2 = _typ2, \
563 .handler = &gen_##name, \
564 .oname = onam, \
565 }, \
566 .oname = onam, \
567 }
568 #else
569 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl, \
577 .type = _typ, \
578 .type2 = _typ2, \
579 .handler = &gen_##name, \
580 }, \
581 .oname = stringify(name), \
582 }
583 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
584 { \
585 .opc1 = op1, \
586 .opc2 = op2, \
587 .opc3 = op3, \
588 .pad = { 0, }, \
589 .handler = { \
590 .inval1 = invl1, \
591 .inval2 = invl2, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = stringify(name), \
597 }
598 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
599 { \
600 .opc1 = op1, \
601 .opc2 = op2, \
602 .opc3 = op3, \
603 .pad = { 0, }, \
604 .handler = { \
605 .inval1 = invl, \
606 .type = _typ, \
607 .type2 = _typ2, \
608 .handler = &gen_##name, \
609 }, \
610 .oname = onam, \
611 }
612 #endif
613
614 /* SPR load/store helpers */
615 static inline void gen_load_spr(TCGv t, int reg)
616 {
617 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
618 }
619
620 static inline void gen_store_spr(int reg, TCGv t)
621 {
622 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
623 }
624
625 /* Invalid instruction */
626 static void gen_invalid(DisasContext *ctx)
627 {
628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
629 }
630
631 static opc_handler_t invalid_handler = {
632 .inval1 = 0xFFFFFFFF,
633 .inval2 = 0xFFFFFFFF,
634 .type = PPC_NONE,
635 .type2 = PPC_NONE,
636 .handler = gen_invalid,
637 };
638
639 /*** Integer comparison ***/
640
641 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_temp_new();
644 TCGv_i32 t1 = tcg_temp_new_i32();
645
646 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
647
648 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
649 tcg_gen_trunc_tl_i32(t1, t0);
650 tcg_gen_shli_i32(t1, t1, CRF_LT);
651 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
652
653 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
654 tcg_gen_trunc_tl_i32(t1, t0);
655 tcg_gen_shli_i32(t1, t1, CRF_GT);
656 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
657
658 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
659 tcg_gen_trunc_tl_i32(t1, t0);
660 tcg_gen_shli_i32(t1, t1, CRF_EQ);
661 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
662
663 tcg_temp_free(t0);
664 tcg_temp_free_i32(t1);
665 }
666
667 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
668 {
669 TCGv t0 = tcg_const_tl(arg1);
670 gen_op_cmp(arg0, t0, s, crf);
671 tcg_temp_free(t0);
672 }
673
674 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
675 {
676 TCGv t0, t1;
677 t0 = tcg_temp_new();
678 t1 = tcg_temp_new();
679 if (s) {
680 tcg_gen_ext32s_tl(t0, arg0);
681 tcg_gen_ext32s_tl(t1, arg1);
682 } else {
683 tcg_gen_ext32u_tl(t0, arg0);
684 tcg_gen_ext32u_tl(t1, arg1);
685 }
686 gen_op_cmp(t0, t1, s, crf);
687 tcg_temp_free(t1);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
692 {
693 TCGv t0 = tcg_const_tl(arg1);
694 gen_op_cmp32(arg0, t0, s, crf);
695 tcg_temp_free(t0);
696 }
697
698 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
699 {
700 if (NARROW_MODE(ctx)) {
701 gen_op_cmpi32(reg, 0, 1, 0);
702 } else {
703 gen_op_cmpi(reg, 0, 1, 0);
704 }
705 }
706
707 /* cmp */
708 static void gen_cmp(DisasContext *ctx)
709 {
710 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
711 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 1, crfD(ctx->opcode));
713 } else {
714 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 }
717 }
718
719 /* cmpi */
720 static void gen_cmpi(DisasContext *ctx)
721 {
722 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
723 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
724 1, crfD(ctx->opcode));
725 } else {
726 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 }
729 }
730
731 /* cmpl */
732 static void gen_cmpl(DisasContext *ctx)
733 {
734 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
735 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 0, crfD(ctx->opcode));
737 } else {
738 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 }
741 }
742
743 /* cmpli */
744 static void gen_cmpli(DisasContext *ctx)
745 {
746 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
747 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
748 0, crfD(ctx->opcode));
749 } else {
750 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 }
753 }
754
755 /* isel (PowerPC 2.03 specification) */
756 static void gen_isel(DisasContext *ctx)
757 {
758 TCGLabel *l1, *l2;
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask;
761 TCGv_i32 t0;
762
763 l1 = gen_new_label();
764 l2 = gen_new_label();
765
766 mask = 0x08 >> (bi & 0x03);
767 t0 = tcg_temp_new_i32();
768 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
769 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
770 if (rA(ctx->opcode) == 0)
771 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
772 else
773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
774 tcg_gen_br(l2);
775 gen_set_label(l1);
776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
777 gen_set_label(l2);
778 tcg_temp_free_i32(t0);
779 }
780
781 /* cmpb: PowerPC 2.05 specification */
782 static void gen_cmpb(DisasContext *ctx)
783 {
784 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
785 cpu_gpr[rB(ctx->opcode)]);
786 }
787
788 /*** Integer arithmetic ***/
789
790 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
791 TCGv arg1, TCGv arg2, int sub)
792 {
793 TCGv t0 = tcg_temp_new();
794
795 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
796 tcg_gen_xor_tl(t0, arg1, arg2);
797 if (sub) {
798 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
799 } else {
800 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
801 }
802 tcg_temp_free(t0);
803 if (NARROW_MODE(ctx)) {
804 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
805 }
806 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
807 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, bool add_ca, bool compute_ca,
813 bool compute_ov, bool compute_rc0)
814 {
815 TCGv t0 = ret;
816
817 if (compute_ca || compute_ov) {
818 t0 = tcg_temp_new();
819 }
820
821 if (compute_ca) {
822 if (NARROW_MODE(ctx)) {
823 /* Caution: a non-obvious corner case of the spec is that we
824 must produce the *entire* 64-bit addition, but produce the
825 carry into bit 32. */
826 TCGv t1 = tcg_temp_new();
827 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
828 tcg_gen_add_tl(t0, arg1, arg2);
829 if (add_ca) {
830 tcg_gen_add_tl(t0, t0, cpu_ca);
831 }
832 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
833 tcg_temp_free(t1);
834 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
835 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
836 } else {
837 TCGv zero = tcg_const_tl(0);
838 if (add_ca) {
839 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
840 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
841 } else {
842 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
843 }
844 tcg_temp_free(zero);
845 }
846 } else {
847 tcg_gen_add_tl(t0, arg1, arg2);
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, cpu_ca);
850 }
851 }
852
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856 if (unlikely(compute_rc0)) {
857 gen_set_Rc0(ctx, t0);
858 }
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
910 cpu_gpr[rA(ctx->opcode)], simm);
911 }
912 }
913 /* addic addic.*/
914 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
915 {
916 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
917 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
918 c, 0, 1, 0, compute_rc0);
919 tcg_temp_free(c);
920 }
921
922 static void gen_addic(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 0);
925 }
926
927 static void gen_addic_(DisasContext *ctx)
928 {
929 gen_op_addic(ctx, 1);
930 }
931
932 /* addis */
933 static void gen_addis(DisasContext *ctx)
934 {
935 target_long simm = SIMM(ctx->opcode);
936
937 if (rA(ctx->opcode) == 0) {
938 /* lis case */
939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
940 } else {
941 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
942 cpu_gpr[rA(ctx->opcode)], simm << 16);
943 }
944 }
945
946 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
947 TCGv arg2, int sign, int compute_ov)
948 {
949 TCGLabel *l1 = gen_new_label();
950 TCGLabel *l2 = gen_new_label();
951 TCGv_i32 t0 = tcg_temp_local_new_i32();
952 TCGv_i32 t1 = tcg_temp_local_new_i32();
953
954 tcg_gen_trunc_tl_i32(t0, arg1);
955 tcg_gen_trunc_tl_i32(t1, arg2);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
957 if (sign) {
958 TCGLabel *l3 = gen_new_label();
959 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
960 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
961 gen_set_label(l3);
962 tcg_gen_div_i32(t0, t0, t1);
963 } else {
964 tcg_gen_divu_i32(t0, t0, t1);
965 }
966 if (compute_ov) {
967 tcg_gen_movi_tl(cpu_ov, 0);
968 }
969 tcg_gen_br(l2);
970 gen_set_label(l1);
971 if (sign) {
972 tcg_gen_sari_i32(t0, t0, 31);
973 } else {
974 tcg_gen_movi_i32(t0, 0);
975 }
976 if (compute_ov) {
977 tcg_gen_movi_tl(cpu_ov, 1);
978 tcg_gen_movi_tl(cpu_so, 1);
979 }
980 gen_set_label(l2);
981 tcg_gen_extu_i32_tl(ret, t0);
982 tcg_temp_free_i32(t0);
983 tcg_temp_free_i32(t1);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 /* Div functions */
988 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
989 static void glue(gen_, name)(DisasContext *ctx) \
990 { \
991 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
993 sign, compute_ov); \
994 }
995 /* divwu divwu. divwuo divwuo. */
996 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
997 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
998 /* divw divw. divwo divwo. */
999 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1001
1002 /* div[wd]eu[o][.] */
1003 #define GEN_DIVE(name, hlpr, compute_ov) \
1004 static void gen_##name(DisasContext *ctx) \
1005 { \
1006 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1007 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1008 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009 tcg_temp_free_i32(t0); \
1010 if (unlikely(Rc(ctx->opcode) != 0)) { \
1011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1012 } \
1013 }
1014
1015 GEN_DIVE(divweu, divweu, 0);
1016 GEN_DIVE(divweuo, divweu, 1);
1017 GEN_DIVE(divwe, divwe, 0);
1018 GEN_DIVE(divweo, divwe, 1);
1019
1020 #if defined(TARGET_PPC64)
1021 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022 TCGv arg2, int sign, int compute_ov)
1023 {
1024 TCGLabel *l1 = gen_new_label();
1025 TCGLabel *l2 = gen_new_label();
1026
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028 if (sign) {
1029 TCGLabel *l3 = gen_new_label();
1030 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032 gen_set_label(l3);
1033 tcg_gen_div_i64(ret, arg1, arg2);
1034 } else {
1035 tcg_gen_divu_i64(ret, arg1, arg2);
1036 }
1037 if (compute_ov) {
1038 tcg_gen_movi_tl(cpu_ov, 0);
1039 }
1040 tcg_gen_br(l2);
1041 gen_set_label(l1);
1042 if (sign) {
1043 tcg_gen_sari_i64(ret, arg1, 63);
1044 } else {
1045 tcg_gen_movi_i64(ret, 0);
1046 }
1047 if (compute_ov) {
1048 tcg_gen_movi_tl(cpu_ov, 1);
1049 tcg_gen_movi_tl(cpu_so, 1);
1050 }
1051 gen_set_label(l2);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, ret);
1054 }
1055 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1056 static void glue(gen_, name)(DisasContext *ctx) \
1057 { \
1058 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1060 sign, compute_ov); \
1061 }
1062 /* divwu divwu. divwuo divwuo. */
1063 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065 /* divw divw. divwo divwo. */
1066 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1068
1069 GEN_DIVE(divdeu, divdeu, 0);
1070 GEN_DIVE(divdeuo, divdeu, 1);
1071 GEN_DIVE(divde, divde, 0);
1072 GEN_DIVE(divdeo, divde, 1);
1073 #endif
1074
1075 /* mulhw mulhw. */
1076 static void gen_mulhw(DisasContext *ctx)
1077 {
1078 TCGv_i32 t0 = tcg_temp_new_i32();
1079 TCGv_i32 t1 = tcg_temp_new_i32();
1080
1081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083 tcg_gen_muls2_i32(t0, t1, t0, t1);
1084 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mulhwu mulhwu. */
1092 static void gen_mulhwu(DisasContext *ctx)
1093 {
1094 TCGv_i32 t0 = tcg_temp_new_i32();
1095 TCGv_i32 t1 = tcg_temp_new_i32();
1096
1097 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101 tcg_temp_free_i32(t0);
1102 tcg_temp_free_i32(t1);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mullw mullw. */
1108 static void gen_mullw(DisasContext *ctx)
1109 {
1110 #if defined(TARGET_PPC64)
1111 TCGv_i64 t0, t1;
1112 t0 = tcg_temp_new_i64();
1113 t1 = tcg_temp_new_i64();
1114 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1115 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1117 tcg_temp_free(t0);
1118 tcg_temp_free(t1);
1119 #else
1120 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 cpu_gpr[rB(ctx->opcode)]);
1122 #endif
1123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125 }
1126
1127 /* mullwo mullwo. */
1128 static void gen_mullwo(DisasContext *ctx)
1129 {
1130 TCGv_i32 t0 = tcg_temp_new_i32();
1131 TCGv_i32 t1 = tcg_temp_new_i32();
1132
1133 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1135 tcg_gen_muls2_i32(t0, t1, t0, t1);
1136 #if defined(TARGET_PPC64)
1137 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1138 #else
1139 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1140 #endif
1141
1142 tcg_gen_sari_i32(t0, t0, 31);
1143 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1144 tcg_gen_extu_i32_tl(cpu_ov, t0);
1145 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1146
1147 tcg_temp_free_i32(t0);
1148 tcg_temp_free_i32(t1);
1149 if (unlikely(Rc(ctx->opcode) != 0))
1150 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1151 }
1152
1153 /* mulli */
1154 static void gen_mulli(DisasContext *ctx)
1155 {
1156 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1157 SIMM(ctx->opcode));
1158 }
1159
1160 #if defined(TARGET_PPC64)
1161 /* mulhd mulhd. */
1162 static void gen_mulhd(DisasContext *ctx)
1163 {
1164 TCGv lo = tcg_temp_new();
1165 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167 tcg_temp_free(lo);
1168 if (unlikely(Rc(ctx->opcode) != 0)) {
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170 }
1171 }
1172
1173 /* mulhdu mulhdu. */
1174 static void gen_mulhdu(DisasContext *ctx)
1175 {
1176 TCGv lo = tcg_temp_new();
1177 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1178 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1179 tcg_temp_free(lo);
1180 if (unlikely(Rc(ctx->opcode) != 0)) {
1181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1182 }
1183 }
1184
1185 /* mulld mulld. */
1186 static void gen_mulld(DisasContext *ctx)
1187 {
1188 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1189 cpu_gpr[rB(ctx->opcode)]);
1190 if (unlikely(Rc(ctx->opcode) != 0))
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193
1194 /* mulldo mulldo. */
1195 static void gen_mulldo(DisasContext *ctx)
1196 {
1197 TCGv_i64 t0 = tcg_temp_new_i64();
1198 TCGv_i64 t1 = tcg_temp_new_i64();
1199
1200 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1201 cpu_gpr[rB(ctx->opcode)]);
1202 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1203
1204 tcg_gen_sari_i64(t0, t0, 63);
1205 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1206 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1207
1208 tcg_temp_free_i64(t0);
1209 tcg_temp_free_i64(t1);
1210
1211 if (unlikely(Rc(ctx->opcode) != 0)) {
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214 }
1215 #endif
1216
1217 /* Common subf function */
1218 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1219 TCGv arg2, bool add_ca, bool compute_ca,
1220 bool compute_ov, bool compute_rc0)
1221 {
1222 TCGv t0 = ret;
1223
1224 if (compute_ca || compute_ov) {
1225 t0 = tcg_temp_new();
1226 }
1227
1228 if (compute_ca) {
1229 /* dest = ~arg1 + arg2 [+ ca]. */
1230 if (NARROW_MODE(ctx)) {
1231 /* Caution: a non-obvious corner case of the spec is that we
1232 must produce the *entire* 64-bit addition, but produce the
1233 carry into bit 32. */
1234 TCGv inv1 = tcg_temp_new();
1235 TCGv t1 = tcg_temp_new();
1236 tcg_gen_not_tl(inv1, arg1);
1237 if (add_ca) {
1238 tcg_gen_add_tl(t0, arg2, cpu_ca);
1239 } else {
1240 tcg_gen_addi_tl(t0, arg2, 1);
1241 }
1242 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1243 tcg_gen_add_tl(t0, t0, inv1);
1244 tcg_temp_free(inv1);
1245 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1246 tcg_temp_free(t1);
1247 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1248 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1249 } else if (add_ca) {
1250 TCGv zero, inv1 = tcg_temp_new();
1251 tcg_gen_not_tl(inv1, arg1);
1252 zero = tcg_const_tl(0);
1253 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1254 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1255 tcg_temp_free(zero);
1256 tcg_temp_free(inv1);
1257 } else {
1258 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 }
1261 } else if (add_ca) {
1262 /* Since we're ignoring carry-out, we can simplify the
1263 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1264 tcg_gen_sub_tl(t0, arg2, arg1);
1265 tcg_gen_add_tl(t0, t0, cpu_ca);
1266 tcg_gen_subi_tl(t0, t0, 1);
1267 } else {
1268 tcg_gen_sub_tl(t0, arg2, arg1);
1269 }
1270
1271 if (compute_ov) {
1272 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1273 }
1274 if (unlikely(compute_rc0)) {
1275 gen_set_Rc0(ctx, t0);
1276 }
1277
1278 if (!TCGV_EQUAL(t0, ret)) {
1279 tcg_gen_mov_tl(ret, t0);
1280 tcg_temp_free(t0);
1281 }
1282 }
1283 /* Sub functions with Two operands functions */
1284 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1285 static void glue(gen_, name)(DisasContext *ctx) \
1286 { \
1287 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1289 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1290 }
1291 /* Sub functions with one operand and one immediate */
1292 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1293 add_ca, compute_ca, compute_ov) \
1294 static void glue(gen_, name)(DisasContext *ctx) \
1295 { \
1296 TCGv t0 = tcg_const_tl(const_val); \
1297 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1298 cpu_gpr[rA(ctx->opcode)], t0, \
1299 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1300 tcg_temp_free(t0); \
1301 }
1302 /* subf subf. subfo subfo. */
1303 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1304 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1305 /* subfc subfc. subfco subfco. */
1306 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1307 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1308 /* subfe subfe. subfeo subfo. */
1309 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1310 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1311 /* subfme subfme. subfmeo subfmeo. */
1312 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1313 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1314 /* subfze subfze. subfzeo subfzeo.*/
1315 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1316 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1317
1318 /* subfic */
1319 static void gen_subfic(DisasContext *ctx)
1320 {
1321 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1322 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1323 c, 0, 1, 0, 0);
1324 tcg_temp_free(c);
1325 }
1326
1327 /* neg neg. nego nego. */
1328 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1329 {
1330 TCGv zero = tcg_const_tl(0);
1331 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1332 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1333 tcg_temp_free(zero);
1334 }
1335
1336 static void gen_neg(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 0);
1339 }
1340
1341 static void gen_nego(DisasContext *ctx)
1342 {
1343 gen_op_arith_neg(ctx, 1);
1344 }
1345
1346 /*** Integer logical ***/
1347 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348 static void glue(gen_, name)(DisasContext *ctx) \
1349 { \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357 static void glue(gen_, name)(DisasContext *ctx) \
1358 { \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1362 }
1363
1364 /* and & and. */
1365 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1366 /* andc & andc. */
1367 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1368
1369 /* andi. */
1370 static void gen_andi_(DisasContext *ctx)
1371 {
1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374 }
1375
1376 /* andis. */
1377 static void gen_andis_(DisasContext *ctx)
1378 {
1379 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382
1383 /* cntlzw */
1384 static void gen_cntlzw(DisasContext *ctx)
1385 {
1386 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1387 if (unlikely(Rc(ctx->opcode) != 0))
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389 }
1390 /* eqv & eqv. */
1391 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1392 /* extsb & extsb. */
1393 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1394 /* extsh & extsh. */
1395 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1396 /* nand & nand. */
1397 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1398 /* nor & nor. */
1399 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1400
1401 /* or & or. */
1402 static void gen_or(DisasContext *ctx)
1403 {
1404 int rs, ra, rb;
1405
1406 rs = rS(ctx->opcode);
1407 ra = rA(ctx->opcode);
1408 rb = rB(ctx->opcode);
1409 /* Optimisation for mr. ri case */
1410 if (rs != ra || rs != rb) {
1411 if (rs != rb)
1412 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413 else
1414 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1415 if (unlikely(Rc(ctx->opcode) != 0))
1416 gen_set_Rc0(ctx, cpu_gpr[ra]);
1417 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1418 gen_set_Rc0(ctx, cpu_gpr[rs]);
1419 #if defined(TARGET_PPC64)
1420 } else {
1421 int prio = 0;
1422
1423 switch (rs) {
1424 case 1:
1425 /* Set process priority to low */
1426 prio = 2;
1427 break;
1428 case 6:
1429 /* Set process priority to medium-low */
1430 prio = 3;
1431 break;
1432 case 2:
1433 /* Set process priority to normal */
1434 prio = 4;
1435 break;
1436 #if !defined(CONFIG_USER_ONLY)
1437 case 31:
1438 if (!ctx->pr) {
1439 /* Set process priority to very low */
1440 prio = 1;
1441 }
1442 break;
1443 case 5:
1444 if (!ctx->pr) {
1445 /* Set process priority to medium-hight */
1446 prio = 5;
1447 }
1448 break;
1449 case 3:
1450 if (!ctx->pr) {
1451 /* Set process priority to high */
1452 prio = 6;
1453 }
1454 break;
1455 case 7:
1456 if (ctx->hv) {
1457 /* Set process priority to very high */
1458 prio = 7;
1459 }
1460 break;
1461 #endif
1462 default:
1463 /* nop */
1464 break;
1465 }
1466 if (prio) {
1467 TCGv t0 = tcg_temp_new();
1468 gen_load_spr(t0, SPR_PPR);
1469 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1471 gen_store_spr(SPR_PPR, t0);
1472 tcg_temp_free(t0);
1473 }
1474 #endif
1475 }
1476 }
1477 /* orc & orc. */
1478 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1479
1480 /* xor & xor. */
1481 static void gen_xor(DisasContext *ctx)
1482 {
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx->opcode) != rB(ctx->opcode))
1485 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1486 else
1487 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1488 if (unlikely(Rc(ctx->opcode) != 0))
1489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1490 }
1491
1492 /* ori */
1493 static void gen_ori(DisasContext *ctx)
1494 {
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 /* XXX: should handle special NOPs for POWER series */
1500 return;
1501 }
1502 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1503 }
1504
1505 /* oris */
1506 static void gen_oris(DisasContext *ctx)
1507 {
1508 target_ulong uimm = UIMM(ctx->opcode);
1509
1510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511 /* NOP */
1512 return;
1513 }
1514 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1515 }
1516
1517 /* xori */
1518 static void gen_xori(DisasContext *ctx)
1519 {
1520 target_ulong uimm = UIMM(ctx->opcode);
1521
1522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523 /* NOP */
1524 return;
1525 }
1526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1527 }
1528
1529 /* xoris */
1530 static void gen_xoris(DisasContext *ctx)
1531 {
1532 target_ulong uimm = UIMM(ctx->opcode);
1533
1534 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535 /* NOP */
1536 return;
1537 }
1538 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1539 }
1540
1541 /* popcntb : PowerPC 2.03 specification */
1542 static void gen_popcntb(DisasContext *ctx)
1543 {
1544 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 static void gen_popcntw(DisasContext *ctx)
1548 {
1549 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550 }
1551
1552 #if defined(TARGET_PPC64)
1553 /* popcntd: PowerPC 2.06 specification */
1554 static void gen_popcntd(DisasContext *ctx)
1555 {
1556 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 /* prtyw: PowerPC 2.05 specification */
1561 static void gen_prtyw(DisasContext *ctx)
1562 {
1563 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1564 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1565 TCGv t0 = tcg_temp_new();
1566 tcg_gen_shri_tl(t0, rs, 16);
1567 tcg_gen_xor_tl(ra, rs, t0);
1568 tcg_gen_shri_tl(t0, ra, 8);
1569 tcg_gen_xor_tl(ra, ra, t0);
1570 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1571 tcg_temp_free(t0);
1572 }
1573
1574 #if defined(TARGET_PPC64)
1575 /* prtyd: PowerPC 2.05 specification */
1576 static void gen_prtyd(DisasContext *ctx)
1577 {
1578 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1579 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1580 TCGv t0 = tcg_temp_new();
1581 tcg_gen_shri_tl(t0, rs, 32);
1582 tcg_gen_xor_tl(ra, rs, t0);
1583 tcg_gen_shri_tl(t0, ra, 16);
1584 tcg_gen_xor_tl(ra, ra, t0);
1585 tcg_gen_shri_tl(t0, ra, 8);
1586 tcg_gen_xor_tl(ra, ra, t0);
1587 tcg_gen_andi_tl(ra, ra, 1);
1588 tcg_temp_free(t0);
1589 }
1590 #endif
1591
1592 #if defined(TARGET_PPC64)
1593 /* bpermd */
1594 static void gen_bpermd(DisasContext *ctx)
1595 {
1596 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1597 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1598 }
1599 #endif
1600
1601 #if defined(TARGET_PPC64)
1602 /* extsw & extsw. */
1603 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1604
1605 /* cntlzd */
1606 static void gen_cntlzd(DisasContext *ctx)
1607 {
1608 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1609 if (unlikely(Rc(ctx->opcode) != 0))
1610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1611 }
1612 #endif
1613
1614 /*** Integer rotate ***/
1615
1616 /* rlwimi & rlwimi. */
1617 static void gen_rlwimi(DisasContext *ctx)
1618 {
1619 uint32_t mb, me, sh;
1620
1621 mb = MB(ctx->opcode);
1622 me = ME(ctx->opcode);
1623 sh = SH(ctx->opcode);
1624 if (likely(sh == (31-me) && mb <= me)) {
1625 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1626 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1627 } else {
1628 target_ulong mask;
1629 TCGv t1;
1630 TCGv t0 = tcg_temp_new();
1631 #if defined(TARGET_PPC64)
1632 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1633 cpu_gpr[rS(ctx->opcode)], 32, 32);
1634 tcg_gen_rotli_i64(t0, t0, sh);
1635 #else
1636 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1637 #endif
1638 #if defined(TARGET_PPC64)
1639 mb += 32;
1640 me += 32;
1641 #endif
1642 mask = MASK(mb, me);
1643 t1 = tcg_temp_new();
1644 tcg_gen_andi_tl(t0, t0, mask);
1645 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1646 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1647 tcg_temp_free(t0);
1648 tcg_temp_free(t1);
1649 }
1650 if (unlikely(Rc(ctx->opcode) != 0))
1651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1652 }
1653
1654 /* rlwinm & rlwinm. */
1655 static void gen_rlwinm(DisasContext *ctx)
1656 {
1657 uint32_t mb, me, sh;
1658
1659 sh = SH(ctx->opcode);
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
1662
1663 if (likely(mb == 0 && me == (31 - sh))) {
1664 if (likely(sh == 0)) {
1665 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1666 } else {
1667 TCGv t0 = tcg_temp_new();
1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shli_tl(t0, t0, sh);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
1672 }
1673 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1674 TCGv t0 = tcg_temp_new();
1675 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1676 tcg_gen_shri_tl(t0, t0, mb);
1677 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1678 tcg_temp_free(t0);
1679 } else if (likely(mb == 0 && me == 31)) {
1680 TCGv_i32 t0 = tcg_temp_new_i32();
1681 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1682 tcg_gen_rotli_i32(t0, t0, sh);
1683 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1684 tcg_temp_free_i32(t0);
1685 } else {
1686 TCGv t0 = tcg_temp_new();
1687 #if defined(TARGET_PPC64)
1688 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1689 cpu_gpr[rS(ctx->opcode)], 32, 32);
1690 tcg_gen_rotli_i64(t0, t0, sh);
1691 #else
1692 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1693 #endif
1694 #if defined(TARGET_PPC64)
1695 mb += 32;
1696 me += 32;
1697 #endif
1698 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1699 tcg_temp_free(t0);
1700 }
1701 if (unlikely(Rc(ctx->opcode) != 0))
1702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1703 }
1704
1705 /* rlwnm & rlwnm. */
1706 static void gen_rlwnm(DisasContext *ctx)
1707 {
1708 uint32_t mb, me;
1709 mb = MB(ctx->opcode);
1710 me = ME(ctx->opcode);
1711
1712 if (likely(mb == 0 && me == 31)) {
1713 TCGv_i32 t0, t1;
1714 t0 = tcg_temp_new_i32();
1715 t1 = tcg_temp_new_i32();
1716 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1717 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1718 tcg_gen_andi_i32(t0, t0, 0x1f);
1719 tcg_gen_rotl_i32(t1, t1, t0);
1720 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721 tcg_temp_free_i32(t0);
1722 tcg_temp_free_i32(t1);
1723 } else {
1724 TCGv t0;
1725 #if defined(TARGET_PPC64)
1726 TCGv t1;
1727 #endif
1728
1729 t0 = tcg_temp_new();
1730 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1731 #if defined(TARGET_PPC64)
1732 t1 = tcg_temp_new_i64();
1733 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1734 cpu_gpr[rS(ctx->opcode)], 32, 32);
1735 tcg_gen_rotl_i64(t0, t1, t0);
1736 tcg_temp_free_i64(t1);
1737 #else
1738 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739 #endif
1740 if (unlikely(mb != 0 || me != 31)) {
1741 #if defined(TARGET_PPC64)
1742 mb += 32;
1743 me += 32;
1744 #endif
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 } else {
1747 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1749 }
1750 tcg_temp_free(t0);
1751 }
1752 if (unlikely(Rc(ctx->opcode) != 0))
1753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1754 }
1755
1756 #if defined(TARGET_PPC64)
1757 #define GEN_PPC64_R2(name, opc1, opc2) \
1758 static void glue(gen_, name##0)(DisasContext *ctx) \
1759 { \
1760 gen_##name(ctx, 0); \
1761 } \
1762 \
1763 static void glue(gen_, name##1)(DisasContext *ctx) \
1764 { \
1765 gen_##name(ctx, 1); \
1766 }
1767 #define GEN_PPC64_R4(name, opc1, opc2) \
1768 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 { \
1770 gen_##name(ctx, 0, 0); \
1771 } \
1772 \
1773 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 { \
1775 gen_##name(ctx, 0, 1); \
1776 } \
1777 \
1778 static void glue(gen_, name##2)(DisasContext *ctx) \
1779 { \
1780 gen_##name(ctx, 1, 0); \
1781 } \
1782 \
1783 static void glue(gen_, name##3)(DisasContext *ctx) \
1784 { \
1785 gen_##name(ctx, 1, 1); \
1786 }
1787
1788 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1789 uint32_t sh)
1790 {
1791 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1792 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1793 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1794 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1795 } else {
1796 TCGv t0 = tcg_temp_new();
1797 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1798 if (likely(mb == 0 && me == 63)) {
1799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1800 } else {
1801 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1802 }
1803 tcg_temp_free(t0);
1804 }
1805 if (unlikely(Rc(ctx->opcode) != 0))
1806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1807 }
1808 /* rldicl - rldicl. */
1809 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1810 {
1811 uint32_t sh, mb;
1812
1813 sh = SH(ctx->opcode) | (shn << 5);
1814 mb = MB(ctx->opcode) | (mbn << 5);
1815 gen_rldinm(ctx, mb, 63, sh);
1816 }
1817 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1818 /* rldicr - rldicr. */
1819 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1820 {
1821 uint32_t sh, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 me = MB(ctx->opcode) | (men << 5);
1825 gen_rldinm(ctx, 0, me, sh);
1826 }
1827 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1828 /* rldic - rldic. */
1829 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1830 {
1831 uint32_t sh, mb;
1832
1833 sh = SH(ctx->opcode) | (shn << 5);
1834 mb = MB(ctx->opcode) | (mbn << 5);
1835 gen_rldinm(ctx, mb, 63 - sh, sh);
1836 }
1837 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1838
1839 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1840 {
1841 TCGv t0;
1842
1843 t0 = tcg_temp_new();
1844 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1845 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1846 if (unlikely(mb != 0 || me != 63)) {
1847 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1848 } else {
1849 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1850 }
1851 tcg_temp_free(t0);
1852 if (unlikely(Rc(ctx->opcode) != 0))
1853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1854 }
1855
1856 /* rldcl - rldcl. */
1857 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1858 {
1859 uint32_t mb;
1860
1861 mb = MB(ctx->opcode) | (mbn << 5);
1862 gen_rldnm(ctx, mb, 63);
1863 }
1864 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1865 /* rldcr - rldcr. */
1866 static inline void gen_rldcr(DisasContext *ctx, int men)
1867 {
1868 uint32_t me;
1869
1870 me = MB(ctx->opcode) | (men << 5);
1871 gen_rldnm(ctx, 0, me);
1872 }
1873 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1874 /* rldimi - rldimi. */
1875 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1876 {
1877 uint32_t sh, mb, me;
1878
1879 sh = SH(ctx->opcode) | (shn << 5);
1880 mb = MB(ctx->opcode) | (mbn << 5);
1881 me = 63 - sh;
1882 if (unlikely(sh == 0 && mb == 0)) {
1883 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1884 } else {
1885 TCGv t0, t1;
1886 target_ulong mask;
1887
1888 t0 = tcg_temp_new();
1889 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1890 t1 = tcg_temp_new();
1891 mask = MASK(mb, me);
1892 tcg_gen_andi_tl(t0, t0, mask);
1893 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1894 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895 tcg_temp_free(t0);
1896 tcg_temp_free(t1);
1897 }
1898 if (unlikely(Rc(ctx->opcode) != 0))
1899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1900 }
1901 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1902 #endif
1903
1904 /*** Integer shift ***/
1905
1906 /* slw & slw. */
1907 static void gen_slw(DisasContext *ctx)
1908 {
1909 TCGv t0, t1;
1910
1911 t0 = tcg_temp_new();
1912 /* AND rS with a mask that is 0 when rB >= 0x20 */
1913 #if defined(TARGET_PPC64)
1914 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1915 tcg_gen_sari_tl(t0, t0, 0x3f);
1916 #else
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1918 tcg_gen_sari_tl(t0, t0, 0x1f);
1919 #endif
1920 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1921 t1 = tcg_temp_new();
1922 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1923 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1924 tcg_temp_free(t1);
1925 tcg_temp_free(t0);
1926 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1927 if (unlikely(Rc(ctx->opcode) != 0))
1928 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1929 }
1930
1931 /* sraw & sraw. */
1932 static void gen_sraw(DisasContext *ctx)
1933 {
1934 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1935 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1936 if (unlikely(Rc(ctx->opcode) != 0))
1937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1938 }
1939
1940 /* srawi & srawi. */
1941 static void gen_srawi(DisasContext *ctx)
1942 {
1943 int sh = SH(ctx->opcode);
1944 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1945 TCGv src = cpu_gpr[rS(ctx->opcode)];
1946 if (sh == 0) {
1947 tcg_gen_ext32s_tl(dst, src);
1948 tcg_gen_movi_tl(cpu_ca, 0);
1949 } else {
1950 TCGv t0;
1951 tcg_gen_ext32s_tl(dst, src);
1952 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1953 t0 = tcg_temp_new();
1954 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1955 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1956 tcg_temp_free(t0);
1957 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1958 tcg_gen_sari_tl(dst, dst, sh);
1959 }
1960 if (unlikely(Rc(ctx->opcode) != 0)) {
1961 gen_set_Rc0(ctx, dst);
1962 }
1963 }
1964
1965 /* srw & srw. */
1966 static void gen_srw(DisasContext *ctx)
1967 {
1968 TCGv t0, t1;
1969
1970 t0 = tcg_temp_new();
1971 /* AND rS with a mask that is 0 when rB >= 0x20 */
1972 #if defined(TARGET_PPC64)
1973 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1974 tcg_gen_sari_tl(t0, t0, 0x3f);
1975 #else
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1977 tcg_gen_sari_tl(t0, t0, 0x1f);
1978 #endif
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 tcg_gen_ext32u_tl(t0, t0);
1981 t1 = tcg_temp_new();
1982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1983 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1984 tcg_temp_free(t1);
1985 tcg_temp_free(t0);
1986 if (unlikely(Rc(ctx->opcode) != 0))
1987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988 }
1989
1990 #if defined(TARGET_PPC64)
1991 /* sld & sld. */
1992 static void gen_sld(DisasContext *ctx)
1993 {
1994 TCGv t0, t1;
1995
1996 t0 = tcg_temp_new();
1997 /* AND rS with a mask that is 0 when rB >= 0x40 */
1998 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1999 tcg_gen_sari_tl(t0, t0, 0x3f);
2000 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2001 t1 = tcg_temp_new();
2002 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2003 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2004 tcg_temp_free(t1);
2005 tcg_temp_free(t0);
2006 if (unlikely(Rc(ctx->opcode) != 0))
2007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2008 }
2009
2010 /* srad & srad. */
2011 static void gen_srad(DisasContext *ctx)
2012 {
2013 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2014 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017 }
2018 /* sradi & sradi. */
2019 static inline void gen_sradi(DisasContext *ctx, int n)
2020 {
2021 int sh = SH(ctx->opcode) + (n << 5);
2022 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2023 TCGv src = cpu_gpr[rS(ctx->opcode)];
2024 if (sh == 0) {
2025 tcg_gen_mov_tl(dst, src);
2026 tcg_gen_movi_tl(cpu_ca, 0);
2027 } else {
2028 TCGv t0;
2029 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2030 t0 = tcg_temp_new();
2031 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2032 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2033 tcg_temp_free(t0);
2034 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2035 tcg_gen_sari_tl(dst, src, sh);
2036 }
2037 if (unlikely(Rc(ctx->opcode) != 0)) {
2038 gen_set_Rc0(ctx, dst);
2039 }
2040 }
2041
2042 static void gen_sradi0(DisasContext *ctx)
2043 {
2044 gen_sradi(ctx, 0);
2045 }
2046
2047 static void gen_sradi1(DisasContext *ctx)
2048 {
2049 gen_sradi(ctx, 1);
2050 }
2051
2052 /* srd & srd. */
2053 static void gen_srd(DisasContext *ctx)
2054 {
2055 TCGv t0, t1;
2056
2057 t0 = tcg_temp_new();
2058 /* AND rS with a mask that is 0 when rB >= 0x40 */
2059 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2060 tcg_gen_sari_tl(t0, t0, 0x3f);
2061 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2062 t1 = tcg_temp_new();
2063 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2064 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2065 tcg_temp_free(t1);
2066 tcg_temp_free(t0);
2067 if (unlikely(Rc(ctx->opcode) != 0))
2068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2069 }
2070 #endif
2071
2072 #if defined(TARGET_PPC64)
2073 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2074 {
2075 TCGv_i32 tmp = tcg_temp_new_i32();
2076 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2077 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2078 tcg_temp_free_i32(tmp);
2079 }
2080 #else
2081 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2082 {
2083 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2084 }
2085 #endif
2086
2087 /*** Floating-Point arithmetic ***/
2088 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2089 static void gen_f##name(DisasContext *ctx) \
2090 { \
2091 if (unlikely(!ctx->fpu_enabled)) { \
2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
2093 return; \
2094 } \
2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
2097 gen_reset_fpstatus(); \
2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2099 cpu_fpr[rA(ctx->opcode)], \
2100 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2101 if (isfloat) { \
2102 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2103 cpu_fpr[rD(ctx->opcode)]); \
2104 } \
2105 if (set_fprf) { \
2106 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2107 } \
2108 if (unlikely(Rc(ctx->opcode) != 0)) { \
2109 gen_set_cr1_from_fpscr(ctx); \
2110 } \
2111 }
2112
2113 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2114 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2115 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2116
2117 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2118 static void gen_f##name(DisasContext *ctx) \
2119 { \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2122 return; \
2123 } \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rA(ctx->opcode)], \
2129 cpu_fpr[rB(ctx->opcode)]); \
2130 if (isfloat) { \
2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2132 cpu_fpr[rD(ctx->opcode)]); \
2133 } \
2134 if (set_fprf) { \
2135 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2136 } \
2137 if (unlikely(Rc(ctx->opcode) != 0)) { \
2138 gen_set_cr1_from_fpscr(ctx); \
2139 } \
2140 }
2141 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2142 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2143 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144
2145 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2146 static void gen_f##name(DisasContext *ctx) \
2147 { \
2148 if (unlikely(!ctx->fpu_enabled)) { \
2149 gen_exception(ctx, POWERPC_EXCP_FPU); \
2150 return; \
2151 } \
2152 /* NIP cannot be restored if the memory exception comes from an helper */ \
2153 gen_update_nip(ctx, ctx->nip - 4); \
2154 gen_reset_fpstatus(); \
2155 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2156 cpu_fpr[rA(ctx->opcode)], \
2157 cpu_fpr[rC(ctx->opcode)]); \
2158 if (isfloat) { \
2159 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2160 cpu_fpr[rD(ctx->opcode)]); \
2161 } \
2162 if (set_fprf) { \
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2164 } \
2165 if (unlikely(Rc(ctx->opcode) != 0)) { \
2166 gen_set_cr1_from_fpscr(ctx); \
2167 } \
2168 }
2169 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2170 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2171 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2172
2173 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2174 static void gen_f##name(DisasContext *ctx) \
2175 { \
2176 if (unlikely(!ctx->fpu_enabled)) { \
2177 gen_exception(ctx, POWERPC_EXCP_FPU); \
2178 return; \
2179 } \
2180 /* NIP cannot be restored if the memory exception comes from an helper */ \
2181 gen_update_nip(ctx, ctx->nip - 4); \
2182 gen_reset_fpstatus(); \
2183 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2184 cpu_fpr[rB(ctx->opcode)]); \
2185 if (set_fprf) { \
2186 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 } \
2188 if (unlikely(Rc(ctx->opcode) != 0)) { \
2189 gen_set_cr1_from_fpscr(ctx); \
2190 } \
2191 }
2192
2193 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2194 static void gen_f##name(DisasContext *ctx) \
2195 { \
2196 if (unlikely(!ctx->fpu_enabled)) { \
2197 gen_exception(ctx, POWERPC_EXCP_FPU); \
2198 return; \
2199 } \
2200 /* NIP cannot be restored if the memory exception comes from an helper */ \
2201 gen_update_nip(ctx, ctx->nip - 4); \
2202 gen_reset_fpstatus(); \
2203 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2204 cpu_fpr[rB(ctx->opcode)]); \
2205 if (set_fprf) { \
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2207 } \
2208 if (unlikely(Rc(ctx->opcode) != 0)) { \
2209 gen_set_cr1_from_fpscr(ctx); \
2210 } \
2211 }
2212
2213 /* fadd - fadds */
2214 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2215 /* fdiv - fdivs */
2216 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2217 /* fmul - fmuls */
2218 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2219
2220 /* fre */
2221 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2222
2223 /* fres */
2224 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2225
2226 /* frsqrte */
2227 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2228
2229 /* frsqrtes */
2230 static void gen_frsqrtes(DisasContext *ctx)
2231 {
2232 if (unlikely(!ctx->fpu_enabled)) {
2233 gen_exception(ctx, POWERPC_EXCP_FPU);
2234 return;
2235 }
2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx, ctx->nip - 4);
2238 gen_reset_fpstatus();
2239 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240 cpu_fpr[rB(ctx->opcode)]);
2241 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2242 cpu_fpr[rD(ctx->opcode)]);
2243 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2244 if (unlikely(Rc(ctx->opcode) != 0)) {
2245 gen_set_cr1_from_fpscr(ctx);
2246 }
2247 }
2248
2249 /* fsel */
2250 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2251 /* fsub - fsubs */
2252 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2253 /* Optional: */
2254
2255 /* fsqrt */
2256 static void gen_fsqrt(DisasContext *ctx)
2257 {
2258 if (unlikely(!ctx->fpu_enabled)) {
2259 gen_exception(ctx, POWERPC_EXCP_FPU);
2260 return;
2261 }
2262 /* NIP cannot be restored if the memory exception comes from an helper */
2263 gen_update_nip(ctx, ctx->nip - 4);
2264 gen_reset_fpstatus();
2265 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2266 cpu_fpr[rB(ctx->opcode)]);
2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 gen_set_cr1_from_fpscr(ctx);
2270 }
2271 }
2272
2273 static void gen_fsqrts(DisasContext *ctx)
2274 {
2275 if (unlikely(!ctx->fpu_enabled)) {
2276 gen_exception(ctx, POWERPC_EXCP_FPU);
2277 return;
2278 }
2279 /* NIP cannot be restored if the memory exception comes from an helper */
2280 gen_update_nip(ctx, ctx->nip - 4);
2281 gen_reset_fpstatus();
2282 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283 cpu_fpr[rB(ctx->opcode)]);
2284 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2285 cpu_fpr[rD(ctx->opcode)]);
2286 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2287 if (unlikely(Rc(ctx->opcode) != 0)) {
2288 gen_set_cr1_from_fpscr(ctx);
2289 }
2290 }
2291
2292 /*** Floating-Point multiply-and-add ***/
2293 /* fmadd - fmadds */
2294 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2295 /* fmsub - fmsubs */
2296 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2297 /* fnmadd - fnmadds */
2298 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2299 /* fnmsub - fnmsubs */
2300 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2301
2302 /*** Floating-Point round & convert ***/
2303 /* fctiw */
2304 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2305 /* fctiwu */
2306 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2307 /* fctiwz */
2308 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2309 /* fctiwuz */
2310 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2311 /* frsp */
2312 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2313 /* fcfid */
2314 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2315 /* fcfids */
2316 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2317 /* fcfidu */
2318 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2319 /* fcfidus */
2320 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2321 /* fctid */
2322 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2323 /* fctidu */
2324 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2325 /* fctidz */
2326 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2327 /* fctidu */
2328 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2329
2330 /* frin */
2331 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2332 /* friz */
2333 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2334 /* frip */
2335 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2336 /* frim */
2337 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2338
2339 static void gen_ftdiv(DisasContext *ctx)
2340 {
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2346 cpu_fpr[rB(ctx->opcode)]);
2347 }
2348
2349 static void gen_ftsqrt(DisasContext *ctx)
2350 {
2351 if (unlikely(!ctx->fpu_enabled)) {
2352 gen_exception(ctx, POWERPC_EXCP_FPU);
2353 return;
2354 }
2355 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2356 }
2357
2358
2359
2360 /*** Floating-Point compare ***/
2361
2362 /* fcmpo */
2363 static void gen_fcmpo(DisasContext *ctx)
2364 {
2365 TCGv_i32 crf;
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 /* NIP cannot be restored if the memory exception comes from an helper */
2371 gen_update_nip(ctx, ctx->nip - 4);
2372 gen_reset_fpstatus();
2373 crf = tcg_const_i32(crfD(ctx->opcode));
2374 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2375 cpu_fpr[rB(ctx->opcode)], crf);
2376 tcg_temp_free_i32(crf);
2377 gen_helper_float_check_status(cpu_env);
2378 }
2379
2380 /* fcmpu */
2381 static void gen_fcmpu(DisasContext *ctx)
2382 {
2383 TCGv_i32 crf;
2384 if (unlikely(!ctx->fpu_enabled)) {
2385 gen_exception(ctx, POWERPC_EXCP_FPU);
2386 return;
2387 }
2388 /* NIP cannot be restored if the memory exception comes from an helper */
2389 gen_update_nip(ctx, ctx->nip - 4);
2390 gen_reset_fpstatus();
2391 crf = tcg_const_i32(crfD(ctx->opcode));
2392 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2393 cpu_fpr[rB(ctx->opcode)], crf);
2394 tcg_temp_free_i32(crf);
2395 gen_helper_float_check_status(cpu_env);
2396 }
2397
2398 /*** Floating-point move ***/
2399 /* fabs */
2400 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2401 static void gen_fabs(DisasContext *ctx)
2402 {
2403 if (unlikely(!ctx->fpu_enabled)) {
2404 gen_exception(ctx, POWERPC_EXCP_FPU);
2405 return;
2406 }
2407 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2408 ~(1ULL << 63));
2409 if (unlikely(Rc(ctx->opcode))) {
2410 gen_set_cr1_from_fpscr(ctx);
2411 }
2412 }
2413
2414 /* fmr - fmr. */
2415 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2416 static void gen_fmr(DisasContext *ctx)
2417 {
2418 if (unlikely(!ctx->fpu_enabled)) {
2419 gen_exception(ctx, POWERPC_EXCP_FPU);
2420 return;
2421 }
2422 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2423 if (unlikely(Rc(ctx->opcode))) {
2424 gen_set_cr1_from_fpscr(ctx);
2425 }
2426 }
2427
2428 /* fnabs */
2429 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2430 static void gen_fnabs(DisasContext *ctx)
2431 {
2432 if (unlikely(!ctx->fpu_enabled)) {
2433 gen_exception(ctx, POWERPC_EXCP_FPU);
2434 return;
2435 }
2436 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2437 1ULL << 63);
2438 if (unlikely(Rc(ctx->opcode))) {
2439 gen_set_cr1_from_fpscr(ctx);
2440 }
2441 }
2442
2443 /* fneg */
2444 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2445 static void gen_fneg(DisasContext *ctx)
2446 {
2447 if (unlikely(!ctx->fpu_enabled)) {
2448 gen_exception(ctx, POWERPC_EXCP_FPU);
2449 return;
2450 }
2451 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2452 1ULL << 63);
2453 if (unlikely(Rc(ctx->opcode))) {
2454 gen_set_cr1_from_fpscr(ctx);
2455 }
2456 }
2457
2458 /* fcpsgn: PowerPC 2.05 specification */
2459 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2460 static void gen_fcpsgn(DisasContext *ctx)
2461 {
2462 if (unlikely(!ctx->fpu_enabled)) {
2463 gen_exception(ctx, POWERPC_EXCP_FPU);
2464 return;
2465 }
2466 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2467 cpu_fpr[rB(ctx->opcode)], 0, 63);
2468 if (unlikely(Rc(ctx->opcode))) {
2469 gen_set_cr1_from_fpscr(ctx);
2470 }
2471 }
2472
2473 static void gen_fmrgew(DisasContext *ctx)
2474 {
2475 TCGv_i64 b0;
2476 if (unlikely(!ctx->fpu_enabled)) {
2477 gen_exception(ctx, POWERPC_EXCP_FPU);
2478 return;
2479 }
2480 b0 = tcg_temp_new_i64();
2481 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2482 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2483 b0, 0, 32);
2484 tcg_temp_free_i64(b0);
2485 }
2486
2487 static void gen_fmrgow(DisasContext *ctx)
2488 {
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2494 cpu_fpr[rB(ctx->opcode)],
2495 cpu_fpr[rA(ctx->opcode)],
2496 32, 32);
2497 }
2498
2499 /*** Floating-Point status & ctrl register ***/
2500
2501 /* mcrfs */
2502 static void gen_mcrfs(DisasContext *ctx)
2503 {
2504 TCGv tmp = tcg_temp_new();
2505 TCGv_i32 tmask;
2506 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2507 int bfa;
2508 int nibble;
2509 int shift;
2510
2511 if (unlikely(!ctx->fpu_enabled)) {
2512 gen_exception(ctx, POWERPC_EXCP_FPU);
2513 return;
2514 }
2515 bfa = crfS(ctx->opcode);
2516 nibble = 7 - bfa;
2517 shift = 4 * nibble;
2518 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2519 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2520 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2521 tcg_temp_free(tmp);
2522 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2523 /* Only the exception bits (including FX) should be cleared if read */
2524 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2525 /* FEX and VX need to be updated, so don't set fpscr directly */
2526 tmask = tcg_const_i32(1 << nibble);
2527 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2528 tcg_temp_free_i32(tmask);
2529 tcg_temp_free_i64(tnew_fpscr);
2530 }
2531
2532 /* mffs */
2533 static void gen_mffs(DisasContext *ctx)
2534 {
2535 if (unlikely(!ctx->fpu_enabled)) {
2536 gen_exception(ctx, POWERPC_EXCP_FPU);
2537 return;
2538 }
2539 gen_reset_fpstatus();
2540 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2541 if (unlikely(Rc(ctx->opcode))) {
2542 gen_set_cr1_from_fpscr(ctx);
2543 }
2544 }
2545
2546 /* mtfsb0 */
2547 static void gen_mtfsb0(DisasContext *ctx)
2548 {
2549 uint8_t crb;
2550
2551 if (unlikely(!ctx->fpu_enabled)) {
2552 gen_exception(ctx, POWERPC_EXCP_FPU);
2553 return;
2554 }
2555 crb = 31 - crbD(ctx->opcode);
2556 gen_reset_fpstatus();
2557 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2558 TCGv_i32 t0;
2559 /* NIP cannot be restored if the memory exception comes from an helper */
2560 gen_update_nip(ctx, ctx->nip - 4);
2561 t0 = tcg_const_i32(crb);
2562 gen_helper_fpscr_clrbit(cpu_env, t0);
2563 tcg_temp_free_i32(t0);
2564 }
2565 if (unlikely(Rc(ctx->opcode) != 0)) {
2566 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2567 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2568 }
2569 }
2570
2571 /* mtfsb1 */
2572 static void gen_mtfsb1(DisasContext *ctx)
2573 {
2574 uint8_t crb;
2575
2576 if (unlikely(!ctx->fpu_enabled)) {
2577 gen_exception(ctx, POWERPC_EXCP_FPU);
2578 return;
2579 }
2580 crb = 31 - crbD(ctx->opcode);
2581 gen_reset_fpstatus();
2582 /* XXX: we pretend we can only do IEEE floating-point computations */
2583 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2584 TCGv_i32 t0;
2585 /* NIP cannot be restored if the memory exception comes from an helper */
2586 gen_update_nip(ctx, ctx->nip - 4);
2587 t0 = tcg_const_i32(crb);
2588 gen_helper_fpscr_setbit(cpu_env, t0);
2589 tcg_temp_free_i32(t0);
2590 }
2591 if (unlikely(Rc(ctx->opcode) != 0)) {
2592 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2593 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2594 }
2595 /* We can raise a differed exception */
2596 gen_helper_float_check_status(cpu_env);
2597 }
2598
2599 /* mtfsf */
2600 static void gen_mtfsf(DisasContext *ctx)
2601 {
2602 TCGv_i32 t0;
2603 int flm, l, w;
2604
2605 if (unlikely(!ctx->fpu_enabled)) {
2606 gen_exception(ctx, POWERPC_EXCP_FPU);
2607 return;
2608 }
2609 flm = FPFLM(ctx->opcode);
2610 l = FPL(ctx->opcode);
2611 w = FPW(ctx->opcode);
2612 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2614 return;
2615 }
2616 /* NIP cannot be restored if the memory exception comes from an helper */
2617 gen_update_nip(ctx, ctx->nip - 4);
2618 gen_reset_fpstatus();
2619 if (l) {
2620 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2621 } else {
2622 t0 = tcg_const_i32(flm << (w * 8));
2623 }
2624 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2625 tcg_temp_free_i32(t0);
2626 if (unlikely(Rc(ctx->opcode) != 0)) {
2627 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2628 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2629 }
2630 /* We can raise a differed exception */
2631 gen_helper_float_check_status(cpu_env);
2632 }
2633
2634 /* mtfsfi */
2635 static void gen_mtfsfi(DisasContext *ctx)
2636 {
2637 int bf, sh, w;
2638 TCGv_i64 t0;
2639 TCGv_i32 t1;
2640
2641 if (unlikely(!ctx->fpu_enabled)) {
2642 gen_exception(ctx, POWERPC_EXCP_FPU);
2643 return;
2644 }
2645 w = FPW(ctx->opcode);
2646 bf = FPBF(ctx->opcode);
2647 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2649 return;
2650 }
2651 sh = (8 * w) + 7 - bf;
2652 /* NIP cannot be restored if the memory exception comes from an helper */
2653 gen_update_nip(ctx, ctx->nip - 4);
2654 gen_reset_fpstatus();
2655 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2656 t1 = tcg_const_i32(1 << sh);
2657 gen_helper_store_fpscr(cpu_env, t0, t1);
2658 tcg_temp_free_i64(t0);
2659 tcg_temp_free_i32(t1);
2660 if (unlikely(Rc(ctx->opcode) != 0)) {
2661 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2662 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2663 }
2664 /* We can raise a differed exception */
2665 gen_helper_float_check_status(cpu_env);
2666 }
2667
2668 /*** Addressing modes ***/
2669 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2670 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2671 target_long maskl)
2672 {
2673 target_long simm = SIMM(ctx->opcode);
2674
2675 simm &= ~maskl;
2676 if (rA(ctx->opcode) == 0) {
2677 if (NARROW_MODE(ctx)) {
2678 simm = (uint32_t)simm;
2679 }
2680 tcg_gen_movi_tl(EA, simm);
2681 } else if (likely(simm != 0)) {
2682 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2683 if (NARROW_MODE(ctx)) {
2684 tcg_gen_ext32u_tl(EA, EA);
2685 }
2686 } else {
2687 if (NARROW_MODE(ctx)) {
2688 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2689 } else {
2690 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2691 }
2692 }
2693 }
2694
2695 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2696 {
2697 if (rA(ctx->opcode) == 0) {
2698 if (NARROW_MODE(ctx)) {
2699 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2700 } else {
2701 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2702 }
2703 } else {
2704 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2705 if (NARROW_MODE(ctx)) {
2706 tcg_gen_ext32u_tl(EA, EA);
2707 }
2708 }
2709 }
2710
2711 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2712 {
2713 if (rA(ctx->opcode) == 0) {
2714 tcg_gen_movi_tl(EA, 0);
2715 } else if (NARROW_MODE(ctx)) {
2716 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2717 } else {
2718 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2719 }
2720 }
2721
2722 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2723 target_long val)
2724 {
2725 tcg_gen_addi_tl(ret, arg1, val);
2726 if (NARROW_MODE(ctx)) {
2727 tcg_gen_ext32u_tl(ret, ret);
2728 }
2729 }
2730
2731 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2732 {
2733 TCGLabel *l1 = gen_new_label();
2734 TCGv t0 = tcg_temp_new();
2735 TCGv_i32 t1, t2;
2736 /* NIP cannot be restored if the memory exception comes from an helper */
2737 gen_update_nip(ctx, ctx->nip - 4);
2738 tcg_gen_andi_tl(t0, EA, mask);
2739 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2740 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2741 t2 = tcg_const_i32(0);
2742 gen_helper_raise_exception_err(cpu_env, t1, t2);
2743 tcg_temp_free_i32(t1);
2744 tcg_temp_free_i32(t2);
2745 gen_set_label(l1);
2746 tcg_temp_free(t0);
2747 }
2748
2749 /*** Integer load ***/
2750 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2751 {
2752 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2753 }
2754
2755 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2756 {
2757 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2758 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2759 }
2760
2761 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2762 {
2763 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2764 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2765 }
2766
2767 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2768 {
2769 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2770 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2771 }
2772
2773 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2774 {
2775 TCGv tmp = tcg_temp_new();
2776 gen_qemu_ld32u(ctx, tmp, addr);
2777 tcg_gen_extu_tl_i64(val, tmp);
2778 tcg_temp_free(tmp);
2779 }
2780
2781 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2782 {
2783 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2784 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2785 }
2786
2787 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2788 {
2789 TCGv tmp = tcg_temp_new();
2790 gen_qemu_ld32s(ctx, tmp, addr);
2791 tcg_gen_ext_tl_i64(val, tmp);
2792 tcg_temp_free(tmp);
2793 }
2794
2795 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2796 {
2797 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2798 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2799 }
2800
2801 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2802 {
2803 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2804 }
2805
2806 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2807 {
2808 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2810 }
2811
2812 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2813 {
2814 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2815 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2816 }
2817
2818 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2819 {
2820 TCGv tmp = tcg_temp_new();
2821 tcg_gen_trunc_i64_tl(tmp, val);
2822 gen_qemu_st32(ctx, tmp, addr);
2823 tcg_temp_free(tmp);
2824 }
2825
2826 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2827 {
2828 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2829 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2830 }
2831
2832 #define GEN_LD(name, ldop, opc, type) \
2833 static void glue(gen_, name)(DisasContext *ctx) \
2834 { \
2835 TCGv EA; \
2836 gen_set_access_type(ctx, ACCESS_INT); \
2837 EA = tcg_temp_new(); \
2838 gen_addr_imm_index(ctx, EA, 0); \
2839 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2840 tcg_temp_free(EA); \
2841 }
2842
2843 #define GEN_LDU(name, ldop, opc, type) \
2844 static void glue(gen_, name##u)(DisasContext *ctx) \
2845 { \
2846 TCGv EA; \
2847 if (unlikely(rA(ctx->opcode) == 0 || \
2848 rA(ctx->opcode) == rD(ctx->opcode))) { \
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2850 return; \
2851 } \
2852 gen_set_access_type(ctx, ACCESS_INT); \
2853 EA = tcg_temp_new(); \
2854 if (type == PPC_64B) \
2855 gen_addr_imm_index(ctx, EA, 0x03); \
2856 else \
2857 gen_addr_imm_index(ctx, EA, 0); \
2858 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2860 tcg_temp_free(EA); \
2861 }
2862
2863 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2864 static void glue(gen_, name##ux)(DisasContext *ctx) \
2865 { \
2866 TCGv EA; \
2867 if (unlikely(rA(ctx->opcode) == 0 || \
2868 rA(ctx->opcode) == rD(ctx->opcode))) { \
2869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2870 return; \
2871 } \
2872 gen_set_access_type(ctx, ACCESS_INT); \
2873 EA = tcg_temp_new(); \
2874 gen_addr_reg_index(ctx, EA); \
2875 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2877 tcg_temp_free(EA); \
2878 }
2879
2880 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2881 static void glue(gen_, name##x)(DisasContext *ctx) \
2882 { \
2883 TCGv EA; \
2884 gen_set_access_type(ctx, ACCESS_INT); \
2885 EA = tcg_temp_new(); \
2886 gen_addr_reg_index(ctx, EA); \
2887 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2888 tcg_temp_free(EA); \
2889 }
2890 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2891 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2892
2893 #define GEN_LDS(name, ldop, op, type) \
2894 GEN_LD(name, ldop, op | 0x20, type); \
2895 GEN_LDU(name, ldop, op | 0x21, type); \
2896 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2897 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2898
2899 /* lbz lbzu lbzux lbzx */
2900 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2901 /* lha lhau lhaux lhax */
2902 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2903 /* lhz lhzu lhzux lhzx */
2904 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2905 /* lwz lwzu lwzux lwzx */
2906 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2907 #if defined(TARGET_PPC64)
2908 /* lwaux */
2909 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2910 /* lwax */
2911 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2912 /* ldux */
2913 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2914 /* ldx */
2915 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2916
2917 static void gen_ld(DisasContext *ctx)
2918 {
2919 TCGv EA;
2920 if (Rc(ctx->opcode)) {
2921 if (unlikely(rA(ctx->opcode) == 0 ||
2922 rA(ctx->opcode) == rD(ctx->opcode))) {
2923 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2924 return;
2925 }
2926 }
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 EA = tcg_temp_new();
2929 gen_addr_imm_index(ctx, EA, 0x03);
2930 if (ctx->opcode & 0x02) {
2931 /* lwa (lwau is undefined) */
2932 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2933 } else {
2934 /* ld - ldu */
2935 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2936 }
2937 if (Rc(ctx->opcode))
2938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2939 tcg_temp_free(EA);
2940 }
2941
2942 /* lq */
2943 static void gen_lq(DisasContext *ctx)
2944 {
2945 int ra, rd;
2946 TCGv EA;
2947
2948 /* lq is a legal user mode instruction starting in ISA 2.07 */
2949 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2950 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951
2952 if (!legal_in_user_mode && ctx->pr) {
2953 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2954 return;
2955 }
2956
2957 if (!le_is_supported && ctx->le_mode) {
2958 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2959 return;
2960 }
2961
2962 ra = rA(ctx->opcode);
2963 rd = rD(ctx->opcode);
2964 if (unlikely((rd & 1) || rd == ra)) {
2965 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2966 return;
2967 }
2968
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 EA = tcg_temp_new();
2971 gen_addr_imm_index(ctx, EA, 0x0F);
2972
2973 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2974 64-bit byteswap already. */
2975 if (unlikely(ctx->le_mode)) {
2976 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2977 gen_addr_add(ctx, EA, EA, 8);
2978 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2979 } else {
2980 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2981 gen_addr_add(ctx, EA, EA, 8);
2982 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2983 }
2984 tcg_temp_free(EA);
2985 }
2986 #endif
2987
2988 /*** Integer store ***/
2989 #define GEN_ST(name, stop, opc, type) \
2990 static void glue(gen_, name)(DisasContext *ctx) \
2991 { \
2992 TCGv EA; \
2993 gen_set_access_type(ctx, ACCESS_INT); \
2994 EA = tcg_temp_new(); \
2995 gen_addr_imm_index(ctx, EA, 0); \
2996 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2997 tcg_temp_free(EA); \
2998 }
2999
3000 #define GEN_STU(name, stop, opc, type) \
3001 static void glue(gen_, stop##u)(DisasContext *ctx) \
3002 { \
3003 TCGv EA; \
3004 if (unlikely(rA(ctx->opcode) == 0)) { \
3005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3006 return; \
3007 } \
3008 gen_set_access_type(ctx, ACCESS_INT); \
3009 EA = tcg_temp_new(); \
3010 if (type == PPC_64B) \
3011 gen_addr_imm_index(ctx, EA, 0x03); \
3012 else \
3013 gen_addr_imm_index(ctx, EA, 0); \
3014 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3015 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3016 tcg_temp_free(EA); \
3017 }
3018
3019 #define GEN_STUX(name, stop, opc2, opc3, type) \
3020 static void glue(gen_, name##ux)(DisasContext *ctx) \
3021 { \
3022 TCGv EA; \
3023 if (unlikely(rA(ctx->opcode) == 0)) { \
3024 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3025 return; \
3026 } \
3027 gen_set_access_type(ctx, ACCESS_INT); \
3028 EA = tcg_temp_new(); \
3029 gen_addr_reg_index(ctx, EA); \
3030 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3032 tcg_temp_free(EA); \
3033 }
3034
3035 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3036 static void glue(gen_, name##x)(DisasContext *ctx) \
3037 { \
3038 TCGv EA; \
3039 gen_set_access_type(ctx, ACCESS_INT); \
3040 EA = tcg_temp_new(); \
3041 gen_addr_reg_index(ctx, EA); \
3042 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3043 tcg_temp_free(EA); \
3044 }
3045 #define GEN_STX(name, stop, opc2, opc3, type) \
3046 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3047
3048 #define GEN_STS(name, stop, op, type) \
3049 GEN_ST(name, stop, op | 0x20, type); \
3050 GEN_STU(name, stop, op | 0x21, type); \
3051 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3052 GEN_STX(name, stop, 0x17, op | 0x00, type)
3053
3054 /* stb stbu stbux stbx */
3055 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3056 /* sth sthu sthux sthx */
3057 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3058 /* stw stwu stwux stwx */
3059 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3060 #if defined(TARGET_PPC64)
3061 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3062 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3063
3064 static void gen_std(DisasContext *ctx)
3065 {
3066 int rs;
3067 TCGv EA;
3068
3069 rs = rS(ctx->opcode);
3070 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3071
3072 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3073 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074
3075 if (!legal_in_user_mode && ctx->pr) {
3076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3077 return;
3078 }
3079
3080 if (!le_is_supported && ctx->le_mode) {
3081 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3082 return;
3083 }
3084
3085 if (unlikely(rs & 1)) {
3086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3087 return;
3088 }
3089 gen_set_access_type(ctx, ACCESS_INT);
3090 EA = tcg_temp_new();
3091 gen_addr_imm_index(ctx, EA, 0x03);
3092
3093 /* We only need to swap high and low halves. gen_qemu_st64 does
3094 necessary 64-bit byteswap already. */
3095 if (unlikely(ctx->le_mode)) {
3096 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3097 gen_addr_add(ctx, EA, EA, 8);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099 } else {
3100 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3101 gen_addr_add(ctx, EA, EA, 8);
3102 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3103 }
3104 tcg_temp_free(EA);
3105 } else {
3106 /* std / stdu*/
3107 if (Rc(ctx->opcode)) {
3108 if (unlikely(rA(ctx->opcode) == 0)) {
3109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3110 return;
3111 }
3112 }
3113 gen_set_access_type(ctx, ACCESS_INT);
3114 EA = tcg_temp_new();
3115 gen_addr_imm_index(ctx, EA, 0x03);
3116 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3117 if (Rc(ctx->opcode))
3118 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3119 tcg_temp_free(EA);
3120 }
3121 }
3122 #endif
3123 /*** Integer load and store with byte reverse ***/
3124
3125 /* lhbrx */
3126 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3127 {
3128 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3129 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3130 }
3131 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3132
3133 /* lwbrx */
3134 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3135 {
3136 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3138 }
3139 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3140
3141 #if defined(TARGET_PPC64)
3142 /* ldbrx */
3143 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3144 {
3145 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3146 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3147 }
3148 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3149 #endif /* TARGET_PPC64 */
3150
3151 /* sthbrx */
3152 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3153 {
3154 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3155 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3156 }
3157 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3158
3159 /* stwbrx */
3160 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3161 {
3162 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3163 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3164 }
3165 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3166
3167 #if defined(TARGET_PPC64)
3168 /* stdbrx */
3169 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3170 {
3171 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3172 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3173 }
3174 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3175 #endif /* TARGET_PPC64 */
3176
3177 /*** Integer load and store multiple ***/
3178
3179 /* lmw */
3180 static void gen_lmw(DisasContext *ctx)
3181 {
3182 TCGv t0;
3183 TCGv_i32 t1;
3184 gen_set_access_type(ctx, ACCESS_INT);
3185 /* NIP cannot be restored if the memory exception comes from an helper */
3186 gen_update_nip(ctx, ctx->nip - 4);
3187 t0 = tcg_temp_new();
3188 t1 = tcg_const_i32(rD(ctx->opcode));
3189 gen_addr_imm_index(ctx, t0, 0);
3190 gen_helper_lmw(cpu_env, t0, t1);
3191 tcg_temp_free(t0);
3192 tcg_temp_free_i32(t1);
3193 }
3194
3195 /* stmw */
3196 static void gen_stmw(DisasContext *ctx)
3197 {
3198 TCGv t0;
3199 TCGv_i32 t1;
3200 gen_set_access_type(ctx, ACCESS_INT);
3201 /* NIP cannot be restored if the memory exception comes from an helper */
3202 gen_update_nip(ctx, ctx->nip - 4);
3203 t0 = tcg_temp_new();
3204 t1 = tcg_const_i32(rS(ctx->opcode));
3205 gen_addr_imm_index(ctx, t0, 0);
3206 gen_helper_stmw(cpu_env, t0, t1);
3207 tcg_temp_free(t0);
3208 tcg_temp_free_i32(t1);
3209 }
3210
3211 /*** Integer load and store strings ***/
3212
3213 /* lswi */
3214 /* PowerPC32 specification says we must generate an exception if
3215 * rA is in the range of registers to be loaded.
3216 * In an other hand, IBM says this is valid, but rA won't be loaded.
3217 * For now, I'll follow the spec...
3218 */
3219 static void gen_lswi(DisasContext *ctx)
3220 {
3221 TCGv t0;
3222 TCGv_i32 t1, t2;
3223 int nb = NB(ctx->opcode);
3224 int start = rD(ctx->opcode);
3225 int ra = rA(ctx->opcode);
3226 int nr;
3227
3228 if (nb == 0)
3229 nb = 32;
3230 nr = (nb + 3) / 4;
3231 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3232 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3233 return;
3234 }
3235 gen_set_access_type(ctx, ACCESS_INT);
3236 /* NIP cannot be restored if the memory exception comes from an helper */
3237 gen_update_nip(ctx, ctx->nip - 4);
3238 t0 = tcg_temp_new();
3239 gen_addr_register(ctx, t0);
3240 t1 = tcg_const_i32(nb);
3241 t2 = tcg_const_i32(start);
3242 gen_helper_lsw(cpu_env, t0, t1, t2);
3243 tcg_temp_free(t0);
3244 tcg_temp_free_i32(t1);
3245 tcg_temp_free_i32(t2);
3246 }
3247
3248 /* lswx */
3249 static void gen_lswx(DisasContext *ctx)
3250 {
3251 TCGv t0;
3252 TCGv_i32 t1, t2, t3;
3253 gen_set_access_type(ctx, ACCESS_INT);
3254 /* NIP cannot be restored if the memory exception comes from an helper */
3255 gen_update_nip(ctx, ctx->nip - 4);
3256 t0 = tcg_temp_new();
3257 gen_addr_reg_index(ctx, t0);
3258 t1 = tcg_const_i32(rD(ctx->opcode));
3259 t2 = tcg_const_i32(rA(ctx->opcode));
3260 t3 = tcg_const_i32(rB(ctx->opcode));
3261 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3262 tcg_temp_free(t0);
3263 tcg_temp_free_i32(t1);
3264 tcg_temp_free_i32(t2);
3265 tcg_temp_free_i32(t3);
3266 }
3267
3268 /* stswi */
3269 static void gen_stswi(DisasContext *ctx)
3270 {
3271 TCGv t0;
3272 TCGv_i32 t1, t2;
3273 int nb = NB(ctx->opcode);
3274 gen_set_access_type(ctx, ACCESS_INT);
3275 /* NIP cannot be restored if the memory exception comes from an helper */
3276 gen_update_nip(ctx, ctx->nip - 4);
3277 t0 = tcg_temp_new();
3278 gen_addr_register(ctx, t0);
3279 if (nb == 0)
3280 nb = 32;
3281 t1 = tcg_const_i32(nb);
3282 t2 = tcg_const_i32(rS(ctx->opcode));
3283 gen_helper_stsw(cpu_env, t0, t1, t2);
3284 tcg_temp_free(t0);
3285 tcg_temp_free_i32(t1);
3286 tcg_temp_free_i32(t2);
3287 }
3288
3289 /* stswx */
3290 static void gen_stswx(DisasContext *ctx)
3291 {
3292 TCGv t0;
3293 TCGv_i32 t1, t2;
3294 gen_set_access_type(ctx, ACCESS_INT);
3295 /* NIP cannot be restored if the memory exception comes from an helper */
3296 gen_update_nip(ctx, ctx->nip - 4);
3297 t0 = tcg_temp_new();
3298 gen_addr_reg_index(ctx, t0);
3299 t1 = tcg_temp_new_i32();
3300 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3301 tcg_gen_andi_i32(t1, t1, 0x7F);
3302 t2 = tcg_const_i32(rS(ctx->opcode));
3303 gen_helper_stsw(cpu_env, t0, t1, t2);
3304 tcg_temp_free(t0);
3305 tcg_temp_free_i32(t1);
3306 tcg_temp_free_i32(t2);
3307 }
3308
3309 /*** Memory synchronisation ***/
3310 /* eieio */
3311 static void gen_eieio(DisasContext *ctx)
3312 {
3313 }
3314
3315 /* isync */
3316 static void gen_isync(DisasContext *ctx)
3317 {
3318 gen_stop_exception(ctx);
3319 }
3320
3321 #define LARX(name, len, loadop) \
3322 static void gen_##name(DisasContext *ctx) \
3323 { \
3324 TCGv t0; \
3325 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3326 gen_set_access_type(ctx, ACCESS_RES); \
3327 t0 = tcg_temp_local_new(); \
3328 gen_addr_reg_index(ctx, t0); \
3329 if ((len) > 1) { \
3330 gen_check_align(ctx, t0, (len)-1); \
3331 } \
3332 gen_qemu_##loadop(ctx, gpr, t0); \
3333 tcg_gen_mov_tl(cpu_reserve, t0); \
3334 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3335 tcg_temp_free(t0); \
3336 }
3337
3338 /* lwarx */
3339 LARX(lbarx, 1, ld8u);
3340 LARX(lharx, 2, ld16u);
3341 LARX(lwarx, 4, ld32u);
3342
3343
3344 #if defined(CONFIG_USER_ONLY)
3345 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3346 int reg, int size)
3347 {
3348 TCGv t0 = tcg_temp_new();
3349 uint32_t save_exception = ctx->exception;
3350
3351 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3352 tcg_gen_movi_tl(t0, (size << 5) | reg);
3353 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3354 tcg_temp_free(t0);
3355 gen_update_nip(ctx, ctx->nip-4);
3356 ctx->exception = POWERPC_EXCP_BRANCH;
3357 gen_exception(ctx, POWERPC_EXCP_STCX);
3358 ctx->exception = save_exception;
3359 }
3360 #else
3361 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3362 int reg, int size)
3363 {
3364 TCGLabel *l1;
3365
3366 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3367 l1 = gen_new_label();
3368 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3369 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3370 #if defined(TARGET_PPC64)
3371 if (size == 8) {
3372 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3373 } else
3374 #endif
3375 if (size == 4) {
3376 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3377 } else if (size == 2) {
3378 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3379 #if defined(TARGET_PPC64)
3380 } else if (size == 16) {
3381 TCGv gpr1, gpr2 , EA8;
3382 if (unlikely(ctx->le_mode)) {
3383 gpr1 = cpu_gpr[reg+1];
3384 gpr2 = cpu_gpr[reg];
3385 } else {
3386 gpr1 = cpu_gpr[reg];
3387 gpr2 = cpu_gpr[reg+1];
3388 }
3389 gen_qemu_st64(ctx, gpr1, EA);
3390 EA8 = tcg_temp_local_new();
3391 gen_addr_add(ctx, EA8, EA, 8);
3392 gen_qemu_st64(ctx, gpr2, EA8);
3393 tcg_temp_free(EA8);
3394 #endif
3395 } else {
3396 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3397 }
3398 gen_set_label(l1);
3399 tcg_gen_movi_tl(cpu_reserve, -1);
3400 }
3401 #endif
3402
3403 #define STCX(name, len) \
3404 static void gen_##name(DisasContext *ctx) \
3405 { \
3406 TCGv t0; \
3407 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3408 gen_inval_exception(ctx, \
3409 POWERPC_EXCP_INVAL_INVAL); \
3410 return; \
3411 } \
3412 gen_set_access_type(ctx, ACCESS_RES); \
3413 t0 = tcg_temp_local_new(); \
3414 gen_addr_reg_index(ctx, t0); \
3415 if (len > 1) { \
3416 gen_check_align(ctx, t0, (len)-1); \
3417 } \
3418 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3419 tcg_temp_free(t0); \
3420 }
3421
3422 STCX(stbcx_, 1);
3423 STCX(sthcx_, 2);
3424 STCX(stwcx_, 4);
3425
3426 #if defined(TARGET_PPC64)
3427 /* ldarx */
3428 LARX(ldarx, 8, ld64);
3429
3430 /* lqarx */
3431 static void gen_lqarx(DisasContext *ctx)
3432 {
3433 TCGv EA;
3434 int rd = rD(ctx->opcode);
3435 TCGv gpr1, gpr2;
3436
3437 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3438 (rd == rB(ctx->opcode)))) {
3439 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3440 return;
3441 }
3442
3443 gen_set_access_type(ctx, ACCESS_RES);
3444 EA = tcg_temp_local_new();
3445 gen_addr_reg_index(ctx, EA);
3446 gen_check_align(ctx, EA, 15);
3447 if (unlikely(ctx->le_mode)) {
3448 gpr1 = cpu_gpr[rd+1];
3449 gpr2 = cpu_gpr[rd];
3450 } else {
3451 gpr1 = cpu_gpr[rd];
3452 gpr2 = cpu_gpr[rd+1];
3453 }
3454 gen_qemu_ld64(ctx, gpr1, EA);
3455 tcg_gen_mov_tl(cpu_reserve, EA);
3456
3457 gen_addr_add(ctx, EA, EA, 8);
3458 gen_qemu_ld64(ctx, gpr2, EA);
3459
3460 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3461 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3462
3463 tcg_temp_free(EA);
3464 }
3465
3466 /* stdcx. */
3467 STCX(stdcx_, 8);
3468 STCX(stqcx_, 16);
3469 #endif /* defined(TARGET_PPC64) */
3470
3471 /* sync */
3472 static void gen_sync(DisasContext *ctx)
3473 {
3474 }
3475
3476 /* wait */
3477 static void gen_wait(DisasContext *ctx)
3478 {
3479 TCGv_i32 t0 = tcg_temp_new_i32();
3480 tcg_gen_st_i32(t0, cpu_env,
3481 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3482 tcg_temp_free_i32(t0);
3483 /* Stop translation, as the CPU is supposed to sleep from now */
3484 gen_exception_err(ctx, EXCP_HLT, 1);
3485 }
3486
3487 /*** Floating-point load ***/
3488 #define GEN_LDF(name, ldop, opc, type) \
3489 static void glue(gen_, name)(DisasContext *ctx) \
3490 { \
3491 TCGv EA; \
3492 if (unlikely(!ctx->fpu_enabled)) { \
3493 gen_exception(ctx, POWERPC_EXCP_FPU); \
3494 return; \
3495 } \
3496 gen_set_access_type(ctx, ACCESS_FLOAT); \
3497 EA = tcg_temp_new(); \
3498 gen_addr_imm_index(ctx, EA, 0); \
3499 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3500 tcg_temp_free(EA); \
3501 }
3502
3503 #define GEN_LDUF(name, ldop, opc, type) \
3504 static void glue(gen_, name##u)(DisasContext *ctx) \
3505 { \
3506 TCGv EA; \
3507 if (unlikely(!ctx->fpu_enabled)) { \
3508 gen_exception(ctx, POWERPC_EXCP_FPU); \
3509 return; \
3510 } \
3511 if (unlikely(rA(ctx->opcode) == 0)) { \
3512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3513 return; \
3514 } \
3515 gen_set_access_type(ctx, ACCESS_FLOAT); \
3516 EA = tcg_temp_new(); \
3517 gen_addr_imm_index(ctx, EA, 0); \
3518 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3519 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3520 tcg_temp_free(EA); \
3521 }
3522
3523 #define GEN_LDUXF(name, ldop, opc, type) \
3524 static void glue(gen_, name##ux)(DisasContext *ctx) \
3525 { \
3526 TCGv EA; \
3527 if (unlikely(!ctx->fpu_enabled)) { \
3528 gen_exception(ctx, POWERPC_EXCP_FPU); \
3529 return; \
3530 } \
3531 if (unlikely(rA(ctx->opcode) == 0)) { \
3532 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3533 return; \
3534 } \
3535 gen_set_access_type(ctx, ACCESS_FLOAT); \
3536 EA = tcg_temp_new(); \
3537 gen_addr_reg_index(ctx, EA); \
3538 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3540 tcg_temp_free(EA); \
3541 }
3542
3543 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3544 static void glue(gen_, name##x)(DisasContext *ctx) \
3545 { \
3546 TCGv EA; \
3547 if (unlikely(!ctx->fpu_enabled)) { \
3548 gen_exception(ctx, POWERPC_EXCP_FPU); \
3549 return; \
3550 } \
3551 gen_set_access_type(ctx, ACCESS_FLOAT); \
3552 EA = tcg_temp_new(); \
3553 gen_addr_reg_index(ctx, EA); \
3554 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3555 tcg_temp_free(EA); \
3556 }
3557
3558 #define GEN_LDFS(name, ldop, op, type) \
3559 GEN_LDF(name, ldop, op | 0x20, type); \
3560 GEN_LDUF(name, ldop, op | 0x21, type); \
3561 GEN_LDUXF(name, ldop, op | 0x01, type); \
3562 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3563
3564 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3565 {
3566 TCGv t0 = tcg_temp_new();
3567 TCGv_i32 t1 = tcg_temp_new_i32();
3568 gen_qemu_ld32u(ctx, t0, arg2);
3569 tcg_gen_trunc_tl_i32(t1, t0);
3570 tcg_temp_free(t0);
3571 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3572 tcg_temp_free_i32(t1);
3573 }
3574
3575 /* lfd lfdu lfdux lfdx */
3576 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3577 /* lfs lfsu lfsux lfsx */
3578 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3579
3580 /* lfdp */
3581 static void gen_lfdp(DisasContext *ctx)
3582 {
3583 TCGv EA;
3584 if (unlikely(!ctx->fpu_enabled)) {
3585 gen_exception(ctx, POWERPC_EXCP_FPU);
3586 return;
3587 }
3588 gen_set_access_type(ctx, ACCESS_FLOAT);
3589 EA = tcg_temp_new();
3590 gen_addr_imm_index(ctx, EA, 0);
3591 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3592 64-bit byteswap already. */
3593 if (unlikely(ctx->le_mode)) {
3594 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3595 tcg_gen_addi_tl(EA, EA, 8);
3596 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3597 } else {
3598 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3599 tcg_gen_addi_tl(EA, EA, 8);
3600 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3601 }
3602 tcg_temp_free(EA);
3603 }
3604
3605 /* lfdpx */
3606 static void gen_lfdpx(DisasContext *ctx)
3607 {
3608 TCGv EA;
3609 if (unlikely(!ctx->fpu_enabled)) {
3610 gen_exception(ctx, POWERPC_EXCP_FPU);
3611 return;
3612 }
3613 gen_set_access_type(ctx, ACCESS_FLOAT);
3614 EA = tcg_temp_new();
3615 gen_addr_reg_index(ctx, EA);
3616 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3617 64-bit byteswap already. */
3618 if (unlikely(ctx->le_mode)) {
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3620 tcg_gen_addi_tl(EA, EA, 8);
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 } else {
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3624 tcg_gen_addi_tl(EA, EA, 8);
3625 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3626 }
3627 tcg_temp_free(EA);
3628 }
3629
3630 /* lfiwax */
3631 static void gen_lfiwax(DisasContext *ctx)
3632 {
3633 TCGv EA;
3634 TCGv t0;
3635 if (unlikely(!ctx->fpu_enabled)) {
3636 gen_exception(ctx, POWERPC_EXCP_FPU);
3637 return;
3638 }
3639 gen_set_access_type(ctx, ACCESS_FLOAT);
3640 EA = tcg_temp_new();
3641 t0 = tcg_temp_new();
3642 gen_addr_reg_index(ctx, EA);
3643 gen_qemu_ld32s(ctx, t0, EA);
3644 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3645 tcg_temp_free(EA);
3646 tcg_temp_free(t0);
3647 }
3648
3649 /* lfiwzx */
3650 static void gen_lfiwzx(DisasContext *ctx)
3651 {
3652 TCGv EA;
3653 if (unlikely(!ctx->fpu_enabled)) {
3654 gen_exception(ctx, POWERPC_EXCP_FPU);
3655 return;
3656 }
3657 gen_set_access_type(ctx, ACCESS_FLOAT);
3658 EA = tcg_temp_new();
3659 gen_addr_reg_index(ctx, EA);
3660 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3661 tcg_temp_free(EA);
3662 }
3663 /*** Floating-point store ***/
3664 #define GEN_STF(name, stop, opc, type) \
3665 static void glue(gen_, name)(DisasContext *ctx) \
3666 { \
3667 TCGv EA; \
3668 if (unlikely(!ctx->fpu_enabled)) { \
3669 gen_exception(ctx, POWERPC_EXCP_FPU); \
3670 return; \
3671 } \
3672 gen_set_access_type(ctx, ACCESS_FLOAT); \
3673 EA = tcg_temp_new(); \
3674 gen_addr_imm_index(ctx, EA, 0); \
3675 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3676 tcg_temp_free(EA); \
3677 }
3678
3679 #define GEN_STUF(name, stop, opc, type) \
3680 static void glue(gen_, name##u)(DisasContext *ctx) \
3681 { \
3682 TCGv EA; \
3683 if (unlikely(!ctx->fpu_enabled)) { \
3684 gen_exception(ctx, POWERPC_EXCP_FPU); \
3685 return; \
3686 } \
3687 if (unlikely(rA(ctx->opcode) == 0)) { \
3688 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3689 return; \
3690 } \
3691 gen_set_access_type(ctx, ACCESS_FLOAT); \
3692 EA = tcg_temp_new(); \
3693 gen_addr_imm_index(ctx, EA, 0); \
3694 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3695 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3696 tcg_temp_free(EA); \
3697 }
3698
3699 #define GEN_STUXF(name, stop, opc, type) \
3700 static void glue(gen_, name##ux)(DisasContext *ctx) \
3701 { \
3702 TCGv EA; \
3703 if (unlikely(!ctx->fpu_enabled)) { \
3704 gen_exception(ctx, POWERPC_EXCP_FPU); \
3705 return; \
3706 } \
3707 if (unlikely(rA(ctx->opcode) == 0)) { \
3708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3709 return; \
3710 } \
3711 gen_set_access_type(ctx, ACCESS_FLOAT); \
3712 EA = tcg_temp_new(); \
3713 gen_addr_reg_index(ctx, EA); \
3714 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3716 tcg_temp_free(EA); \
3717 }
3718
3719 #define GEN_STXF(name, stop, opc2, opc3, type) \
3720 static void glue(gen_, name##x)(DisasContext *ctx) \
3721 { \
3722 TCGv EA; \
3723 if (unlikely(!ctx->fpu_enabled)) { \
3724 gen_exception(ctx, POWERPC_EXCP_FPU); \
3725 return; \
3726 } \
3727 gen_set_access_type(ctx, ACCESS_FLOAT); \
3728 EA = tcg_temp_new(); \
3729 gen_addr_reg_index(ctx, EA); \
3730 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3731 tcg_temp_free(EA); \
3732 }
3733
3734 #define GEN_STFS(name, stop, op, type) \
3735 GEN_STF(name, stop, op | 0x20, type); \
3736 GEN_STUF(name, stop, op | 0x21, type); \
3737 GEN_STUXF(name, stop, op | 0x01, type); \
3738 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3739
3740 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3741 {
3742 TCGv_i32 t0 = tcg_temp_new_i32();
3743 TCGv t1 = tcg_temp_new();
3744 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3745 tcg_gen_extu_i32_tl(t1, t0);
3746 tcg_temp_free_i32(t0);
3747 gen_qemu_st32(ctx, t1, arg2);
3748 tcg_temp_free(t1);
3749 }
3750
3751 /* stfd stfdu stfdux stfdx */
3752 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3753 /* stfs stfsu stfsux stfsx */
3754 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3755
3756 /* stfdp */
3757 static void gen_stfdp(DisasContext *ctx)
3758 {
3759 TCGv EA;
3760 if (unlikely(!ctx->fpu_enabled)) {
3761 gen_exception(ctx, POWERPC_EXCP_FPU);
3762 return;
3763 }
3764 gen_set_access_type(ctx, ACCESS_FLOAT);
3765 EA = tcg_temp_new();
3766 gen_addr_imm_index(ctx, EA, 0);
3767 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3768 64-bit byteswap already. */
3769 if (unlikely(ctx->le_mode)) {
3770 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3771 tcg_gen_addi_tl(EA, EA, 8);
3772 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3773 } else {
3774 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3775 tcg_gen_addi_tl(EA, EA, 8);
3776 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3777 }
3778 tcg_temp_free(EA);
3779 }
3780
3781 /* stfdpx */
3782 static void gen_stfdpx(DisasContext *ctx)
3783 {
3784 TCGv EA;
3785 if (unlikely(!ctx->fpu_enabled)) {
3786 gen_exception(ctx, POWERPC_EXCP_FPU);
3787 return;
3788 }
3789 gen_set_access_type(ctx, ACCESS_FLOAT);
3790 EA = tcg_temp_new();
3791 gen_addr_reg_index(ctx, EA);
3792 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3793 64-bit byteswap already. */
3794 if (unlikely(ctx->le_mode)) {
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3796 tcg_gen_addi_tl(EA, EA, 8);
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 } else {
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3800 tcg_gen_addi_tl(EA, EA, 8);
3801 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3802 }
3803 tcg_temp_free(EA);
3804 }
3805
3806 /* Optional: */
3807 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3808 {
3809 TCGv t0 = tcg_temp_new();
3810 tcg_gen_trunc_i64_tl(t0, arg1),
3811 gen_qemu_st32(ctx, t0, arg2);
3812 tcg_temp_free(t0);
3813 }
3814 /* stfiwx */
3815 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3816
3817 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3818 {
3819 #if defined(TARGET_PPC64)
3820 if (ctx->has_cfar)
3821 tcg_gen_movi_tl(cpu_cfar, nip);
3822 #endif
3823 }
3824
3825 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3826 {
3827 if (unlikely(ctx->singlestep_enabled)) {
3828 return false;
3829 }
3830
3831 #ifndef CONFIG_USER_ONLY
3832 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3833 #else
3834 return true;
3835 #endif
3836 }
3837
3838 /*** Branch ***/
3839 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3840 {
3841 if (NARROW_MODE(ctx)) {
3842 dest = (uint32_t) dest;
3843 }
3844 if (use_goto_tb(ctx, dest)) {
3845 tcg_gen_goto_tb(n);
3846 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3847 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3848 } else {
3849 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3850 if (unlikely(ctx->singlestep_enabled)) {
3851 if ((ctx->singlestep_enabled &
3852 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3853 (ctx->exception == POWERPC_EXCP_BRANCH ||
3854 ctx->exception == POWERPC_EXCP_TRACE)) {
3855 target_ulong tmp = ctx->nip;
3856 ctx->nip = dest;
3857 gen_exception(ctx, POWERPC_EXCP_TRACE);
3858 ctx->nip = tmp;
3859 }
3860 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3861 gen_debug_exception(ctx);
3862 }
3863 }
3864 tcg_gen_exit_tb(0);
3865 }
3866 }
3867
3868 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3869 {
3870 if (NARROW_MODE(ctx)) {
3871 nip = (uint32_t)nip;
3872 }
3873 tcg_gen_movi_tl(cpu_lr, nip);
3874 }
3875
3876 /* b ba bl bla */
3877 static void gen_b(DisasContext *ctx)
3878 {
3879 target_ulong li, target;
3880
3881 ctx->exception = POWERPC_EXCP_BRANCH;
3882 /* sign extend LI */
3883 li = LI(ctx->opcode);
3884 li = (li ^ 0x02000000) - 0x02000000;
3885 if (likely(AA(ctx->opcode) == 0)) {
3886 target = ctx->nip + li - 4;
3887 } else {
3888 target = li;
3889 }
3890 if (LK(ctx->opcode)) {
3891 gen_setlr(ctx, ctx->nip);
3892 }
3893 gen_update_cfar(ctx, ctx->nip);
3894 gen_goto_tb(ctx, 0, target);
3895 }
3896
3897 #define BCOND_IM 0
3898 #define BCOND_LR 1
3899 #define BCOND_CTR 2
3900 #define BCOND_TAR 3
3901
3902 static inline void gen_bcond(DisasContext *ctx, int type)
3903 {
3904 uint32_t bo = BO(ctx->opcode);
3905 TCGLabel *l1;
3906 TCGv target;
3907
3908 ctx->exception = POWERPC_EXCP_BRANCH;
3909 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3910 target = tcg_temp_local_new();
3911 if (type == BCOND_CTR)
3912 tcg_gen_mov_tl(target, cpu_ctr);
3913 else if (type == BCOND_TAR)
3914 gen_load_spr(target, SPR_TAR);
3915 else
3916 tcg_gen_mov_tl(target, cpu_lr);
3917 } else {
3918 TCGV_UNUSED(target);
3919 }
3920 if (LK(ctx->opcode))
3921 gen_setlr(ctx, ctx->nip);
3922 l1 = gen_new_label();
3923 if ((bo & 0x4) == 0) {
3924 /* Decrement and test CTR */
3925 TCGv temp = tcg_temp_new();
3926 if (unlikely(type == BCOND_CTR)) {
3927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3928 return;
3929 }
3930 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3931 if (NARROW_MODE(ctx)) {
3932 tcg_gen_ext32u_tl(temp, cpu_ctr);
3933 } else {
3934 tcg_gen_mov_tl(temp, cpu_ctr);
3935 }
3936 if (bo & 0x2) {
3937 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3938 } else {
3939 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3940 }
3941 tcg_temp_free(temp);
3942 }
3943 if ((bo & 0x10) == 0) {
3944 /* Test CR */
3945 uint32_t bi = BI(ctx->opcode);
3946 uint32_t mask = 0x08 >> (bi & 0x03);
3947 TCGv_i32 temp = tcg_temp_new_i32();
3948
3949 if (bo & 0x8) {
3950 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3951 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3952 } else {
3953 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3954 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3955 }
3956 tcg_temp_free_i32(temp);
3957 }
3958 gen_update_cfar(ctx, ctx->nip);
3959 if (type == BCOND_IM) {
3960 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3961 if (likely(AA(ctx->opcode) == 0)) {
3962 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3963 } else {
3964 gen_goto_tb(ctx, 0, li);
3965 }
3966 gen_set_label(l1);
3967 gen_goto_tb(ctx, 1, ctx->nip);
3968 } else {
3969 if (NARROW_MODE(ctx)) {
3970 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3971 } else {
3972 tcg_gen_andi_tl(cpu_nip, target, ~3);
3973 }
3974 tcg_gen_exit_tb(0);
3975 gen_set_label(l1);
3976 gen_update_nip(ctx, ctx->nip);
3977 tcg_gen_exit_tb(0);
3978 }
3979 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3980 tcg_temp_free(target);
3981 }
3982 }
3983
3984 static void gen_bc(DisasContext *ctx)
3985 {
3986 gen_bcond(ctx, BCOND_IM);
3987 }
3988
3989 static void gen_bcctr(DisasContext *ctx)
3990 {
3991 gen_bcond(ctx, BCOND_CTR);
3992 }
3993
3994 static void gen_bclr(DisasContext *ctx)
3995 {
3996 gen_bcond(ctx, BCOND_LR);
3997 }
3998
3999 static void gen_bctar(DisasContext *ctx)
4000 {
4001 gen_bcond(ctx, BCOND_TAR);
4002 }
4003
4004 /*** Condition register logical ***/
4005 #define GEN_CRLOGIC(name, tcg_op, opc) \
4006 static void glue(gen_, name)(DisasContext *ctx) \
4007 { \
4008 uint8_t bitmask; \
4009 int sh; \
4010 TCGv_i32 t0, t1; \
4011 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4012 t0 = tcg_temp_new_i32(); \
4013 if (sh > 0) \
4014 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4015 else if (sh < 0) \
4016 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4017 else \
4018 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4019 t1 = tcg_temp_new_i32(); \
4020 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4021 if (sh > 0) \
4022 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4023 else if (sh < 0) \
4024 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4025 else \
4026 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4027 tcg_op(t0, t0, t1); \
4028 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4029 tcg_gen_andi_i32(t0, t0, bitmask); \
4030 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4031 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4032 tcg_temp_free_i32(t0); \
4033 tcg_temp_free_i32(t1); \
4034 }
4035
4036 /* crand */
4037 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4038 /* crandc */
4039 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4040 /* creqv */
4041 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4042 /* crnand */
4043 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4044 /* crnor */
4045 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4046 /* cror */
4047 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4048 /* crorc */
4049 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4050 /* crxor */
4051 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4052
4053 /* mcrf */
4054 static void gen_mcrf(DisasContext *ctx)
4055 {
4056 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4057 }
4058
4059 /*** System linkage ***/
4060
4061 /* rfi (supervisor only) */
4062 static void gen_rfi(DisasContext *ctx)
4063 {
4064 #if defined(CONFIG_USER_ONLY)
4065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4066 #else
4067 /* Restore CPU state */
4068 if (unlikely(ctx->pr)) {
4069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4070 return;
4071 }
4072 gen_update_cfar(ctx, ctx->nip);
4073 gen_helper_rfi(cpu_env);
4074 gen_sync_exception(ctx);
4075 #endif
4076 }
4077
4078 #if defined(TARGET_PPC64)
4079 static void gen_rfid(DisasContext *ctx)
4080 {
4081 #if defined(CONFIG_USER_ONLY)
4082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4083 #else
4084 /* Restore CPU state */
4085 if (unlikely(ctx->pr)) {
4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4087 return;
4088 }
4089 gen_update_cfar(ctx, ctx->nip);
4090 gen_helper_rfid(cpu_env);
4091 gen_sync_exception(ctx);
4092 #endif
4093 }
4094
4095 static void gen_hrfid(DisasContext *ctx)
4096 {
4097 #if defined(CONFIG_USER_ONLY)
4098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4099 #else
4100 /* Restore CPU state */
4101 if (unlikely(!ctx->hv)) {
4102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4103 return;
4104 }
4105 gen_helper_hrfid(cpu_env);
4106 gen_sync_exception(ctx);
4107 #endif
4108 }
4109 #endif
4110
4111 /* sc */
4112 #if defined(CONFIG_USER_ONLY)
4113 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4114 #else
4115 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4116 #endif
4117 static void gen_sc(DisasContext *ctx)
4118 {
4119 uint32_t lev;
4120
4121 lev = (ctx->opcode >> 5) & 0x7F;
4122 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4123 }
4124
4125 /*** Trap ***/
4126
4127 /* tw */
4128 static void gen_tw(DisasContext *ctx)
4129 {
4130 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4131 /* Update the nip since this might generate a trap exception */
4132 gen_update_nip(ctx, ctx->nip);
4133 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4134 t0);
4135 tcg_temp_free_i32(t0);
4136 }
4137
4138 /* twi */
4139 static void gen_twi(DisasContext *ctx)
4140 {
4141 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4142 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4143 /* Update the nip since this might generate a trap exception */
4144 gen_update_nip(ctx, ctx->nip);
4145 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4146 tcg_temp_free(t0);
4147 tcg_temp_free_i32(t1);
4148 }
4149
4150 #if defined(TARGET_PPC64)
4151 /* td */
4152 static void gen_td(DisasContext *ctx)
4153 {
4154 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4155 /* Update the nip since this might generate a trap exception */
4156 gen_update_nip(ctx, ctx->nip);
4157 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4158 t0);
4159 tcg_temp_free_i32(t0);
4160 }
4161
4162 /* tdi */
4163 static void gen_tdi(DisasContext *ctx)
4164 {
4165 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4166 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4167 /* Update the nip since this might generate a trap exception */
4168 gen_update_nip(ctx, ctx->nip);
4169 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4170 tcg_temp_free(t0);
4171 tcg_temp_free_i32(t1);
4172 }
4173 #endif
4174
4175 /*** Processor control ***/
4176
4177 static void gen_read_xer(TCGv dst)
4178 {
4179 TCGv t0 = tcg_temp_new();
4180 TCGv t1 = tcg_temp_new();
4181 TCGv t2 = tcg_temp_new();
4182 tcg_gen_mov_tl(dst, cpu_xer);
4183 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4184 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4185 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4186 tcg_gen_or_tl(t0, t0, t1);
4187 tcg_gen_or_tl(dst, dst, t2);
4188 tcg_gen_or_tl(dst, dst, t0);
4189 tcg_temp_free(t0);
4190 tcg_temp_free(t1);
4191 tcg_temp_free(t2);
4192 }
4193
4194 static void gen_write_xer(TCGv src)
4195 {
4196 tcg_gen_andi_tl(cpu_xer, src,
4197 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4198 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4199 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4200 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4201 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4202 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4203 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4204 }
4205
4206 /* mcrxr */
4207 static void gen_mcrxr(DisasContext *ctx)
4208 {
4209 TCGv_i32 t0 = tcg_temp_new_i32();
4210 TCGv_i32 t1 = tcg_temp_new_i32();
4211 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4212
4213 tcg_gen_trunc_tl_i32(t0, cpu_so);
4214 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4215 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4216 tcg_gen_shli_i32(t0, t0, 3);
4217 tcg_gen_shli_i32(t1, t1, 2);
4218 tcg_gen_shli_i32(dst, dst, 1);
4219 tcg_gen_or_i32(dst, dst, t0);
4220 tcg_gen_or_i32(dst, dst, t1);
4221 tcg_temp_free_i32(t0);
4222 tcg_temp_free_i32(t1);
4223
4224 tcg_gen_movi_tl(cpu_so, 0);
4225 tcg_gen_movi_tl(cpu_ov, 0);
4226 tcg_gen_movi_tl(cpu_ca, 0);
4227 }
4228
4229 /* mfcr mfocrf */
4230 static void gen_mfcr(DisasContext *ctx)
4231 {
4232 uint32_t crm, crn;
4233
4234 if (likely(ctx->opcode & 0x00100000)) {
4235 crm = CRM(ctx->opcode);
4236 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4237 crn = ctz32 (crm);
4238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4239 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4240 cpu_gpr[rD(ctx->opcode)], crn * 4);
4241 }
4242 } else {
4243 TCGv_i32 t0 = tcg_temp_new_i32();
4244 tcg_gen_mov_i32(t0, cpu_crf[0]);
4245 tcg_gen_shli_i32(t0, t0, 4);
4246 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4247 tcg_gen_shli_i32(t0, t0, 4);
4248 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4249 tcg_gen_shli_i32(t0, t0, 4);
4250 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4251 tcg_gen_shli_i32(t0, t0, 4);
4252 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4253 tcg_gen_shli_i32(t0, t0, 4);
4254 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4255 tcg_gen_shli_i32(t0, t0, 4);
4256 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4257 tcg_gen_shli_i32(t0, t0, 4);
4258 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4259 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4260 tcg_temp_free_i32(t0);
4261 }
4262 }
4263
4264 /* mfmsr */
4265 static void gen_mfmsr(DisasContext *ctx)
4266 {
4267 #if defined(CONFIG_USER_ONLY)
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 #else
4270 if (unlikely(ctx->pr)) {
4271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4272 return;
4273 }
4274 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4275 #endif
4276 }
4277
4278 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4279 {
4280 #if 0
4281 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4282 printf("ERROR: try to access SPR %d !\n", sprn);
4283 #endif
4284 }
4285 #define SPR_NOACCESS (&spr_noaccess)
4286
4287 /* mfspr */
4288 static inline void gen_op_mfspr(DisasContext *ctx)
4289 {
4290 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4291 uint32_t sprn = SPR(ctx->opcode);
4292
4293 #if defined(CONFIG_USER_ONLY)
4294 read_cb = ctx->spr_cb[sprn].uea_read;
4295 #else
4296 if (ctx->pr) {
4297 read_cb = ctx->spr_cb[sprn].uea_read;
4298 } else if (ctx->hv) {
4299 read_cb = ctx->spr_cb[sprn].hea_read;
4300 } else {
4301 read_cb = ctx->spr_cb[sprn].oea_read;
4302 }
4303 #endif
4304 if (likely(read_cb != NULL)) {
4305 if (likely(read_cb != SPR_NOACCESS)) {
4306 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4307 } else {
4308 /* Privilege exception */
4309 /* This is a hack to avoid warnings when running Linux:
4310 * this OS breaks the PowerPC virtualisation model,
4311 * allowing userland application to read the PVR
4312 */
4313 if (sprn != SPR_PVR) {
4314 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4315 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4316 if (qemu_log_separate()) {
4317 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4318 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4319 }
4320 }
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 }
4323 } else {
4324 /* Not defined */
4325 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4326 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4327 if (qemu_log_separate()) {
4328 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4329 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4330 }
4331 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4332 }
4333 }
4334
4335 static void gen_mfspr(DisasContext *ctx)
4336 {
4337 gen_op_mfspr(ctx);
4338 }
4339
4340 /* mftb */
4341 static void gen_mftb(DisasContext *ctx)
4342 {
4343 gen_op_mfspr(ctx);
4344 }
4345
4346 /* mtcrf mtocrf*/
4347 static void gen_mtcrf(DisasContext *ctx)
4348 {
4349 uint32_t crm, crn;
4350
4351 crm = CRM(ctx->opcode);
4352 if (likely((ctx->opcode & 0x00100000))) {
4353 if (crm && ((crm & (crm - 1)) == 0)) {
4354 TCGv_i32 temp = tcg_temp_new_i32();
4355 crn = ctz32 (crm);
4356 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4357 tcg_gen_shri_i32(temp, temp, crn * 4);
4358 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4359 tcg_temp_free_i32(temp);
4360 }
4361 } else {
4362 TCGv_i32 temp = tcg_temp_new_i32();
4363 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4364 for (crn = 0 ; crn < 8 ; crn++) {
4365 if (crm & (1 << crn)) {
4366 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4367 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4368 }
4369 }
4370 tcg_temp_free_i32(temp);
4371 }
4372 }
4373
4374 /* mtmsr */
4375 #if defined(TARGET_PPC64)
4376 static void gen_mtmsrd(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4380 #else
4381 if (unlikely(ctx->pr)) {
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4383 return;
4384 }
4385 if (ctx->opcode & 0x00010000) {
4386 /* Special form that does not need any synchronisation */
4387 TCGv t0 = tcg_temp_new();
4388 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4389 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4390 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4391 tcg_temp_free(t0);
4392 } else {
4393 /* XXX: we need to update nip before the store
4394 * if we enter power saving mode, we will exit the loop
4395 * directly from ppc_store_msr
4396 */
4397 gen_update_nip(ctx, ctx->nip);
4398 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4399 /* Must stop the translation as machine state (may have) changed */
4400 /* Note that mtmsr is not always defined as context-synchronizing */
4401 gen_stop_exception(ctx);
4402 }
4403 #endif
4404 }
4405 #endif
4406
4407 static void gen_mtmsr(DisasContext *ctx)
4408 {
4409 #if defined(CONFIG_USER_ONLY)
4410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4411 #else
4412 if (unlikely(ctx->pr)) {
4413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4414 return;
4415 }
4416 if (ctx->opcode & 0x00010000) {
4417 /* Special form that does not need any synchronisation */
4418 TCGv t0 = tcg_temp_new();
4419 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4420 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4421 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4422 tcg_temp_free(t0);
4423 } else {
4424 TCGv msr = tcg_temp_new();
4425
4426 /* XXX: we need to update nip before the store
4427 * if we enter power saving mode, we will exit the loop
4428 * directly from ppc_store_msr
4429 */
4430 gen_update_nip(ctx, ctx->nip);
4431 #if defined(TARGET_PPC64)
4432 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4433 #else
4434 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4435 #endif
4436 gen_helper_store_msr(cpu_env, msr);
4437 tcg_temp_free(msr);
4438 /* Must stop the translation as machine state (may have) changed */
4439 /* Note that mtmsr is not always defined as context-synchronizing */
4440 gen_stop_exception(ctx);
4441 }
4442 #endif
4443 }
4444
4445 /* mtspr */
4446 static void gen_mtspr(DisasContext *ctx)
4447 {
4448 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4449 uint32_t sprn = SPR(ctx->opcode);
4450
4451 #if defined(CONFIG_USER_ONLY)
4452 write_cb = ctx->spr_cb[sprn].uea_write;
4453 #else
4454 if (ctx->pr) {
4455 write_cb = ctx->spr_cb[sprn].uea_write;
4456 } else if (ctx->hv) {
4457 write_cb = ctx->spr_cb[sprn].hea_write;
4458 } else {
4459 write_cb = ctx->spr_cb[sprn].oea_write;
4460 }
4461 #endif
4462 if (likely(write_cb != NULL)) {
4463 if (likely(write_cb != SPR_NOACCESS)) {
4464 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4465 } else {
4466 /* Privilege exception */
4467 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4468 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4469 if (qemu_log_separate()) {
4470 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4471 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4472 }
4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4474 }
4475 } else {
4476 /* Not defined */
4477 if (qemu_log_separate()) {
4478 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4479 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4480 }
4481 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4482 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4483 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4484 }
4485 }
4486
4487 /*** Cache management ***/
4488
4489 /* dcbf */
4490 static void gen_dcbf(DisasContext *ctx)
4491 {
4492 /* XXX: specification says this is treated as a load by the MMU */
4493 TCGv t0;
4494 gen_set_access_type(ctx, ACCESS_CACHE);
4495 t0 = tcg_temp_new();
4496 gen_addr_reg_index(ctx, t0);
4497 gen_qemu_ld8u(ctx, t0, t0);
4498 tcg_temp_free(t0);
4499 }
4500
4501 /* dcbi (Supervisor only) */
4502 static void gen_dcbi(DisasContext *ctx)
4503 {
4504 #if defined(CONFIG_USER_ONLY)
4505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4506 #else
4507 TCGv EA, val;
4508 if (unlikely(ctx->pr)) {
4509 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4510 return;
4511 }
4512 EA = tcg_temp_new();
4513 gen_set_access_type(ctx, ACCESS_CACHE);
4514 gen_addr_reg_index(ctx, EA);
4515 val = tcg_temp_new();
4516 /* XXX: specification says this should be treated as a store by the MMU */
4517 gen_qemu_ld8u(ctx, val, EA);
4518 gen_qemu_st8(ctx, val, EA);
4519 tcg_temp_free(val);
4520 tcg_temp_free(EA);
4521 #endif
4522 }
4523
4524 /* dcdst */
4525 static void gen_dcbst(DisasContext *ctx)
4526 {
4527 /* XXX: specification say this is treated as a load by the MMU */
4528 TCGv t0;
4529 gen_set_access_type(ctx, ACCESS_CACHE);
4530 t0 = tcg_temp_new();
4531 gen_addr_reg_index(ctx, t0);
4532 gen_qemu_ld8u(ctx, t0, t0);
4533 tcg_temp_free(t0);
4534 }
4535
4536 /* dcbt */
4537 static void gen_dcbt(DisasContext *ctx)
4538 {
4539 /* interpreted as no-op */
4540 /* XXX: specification say this is treated as a load by the MMU
4541 * but does not generate any exception
4542 */
4543 }
4544
4545 /* dcbtst */
4546 static void gen_dcbtst(DisasContext *ctx)
4547 {
4548 /* interpreted as no-op */
4549 /* XXX: specification say this is treated as a load by the MMU
4550 * but does not generate any exception
4551 */
4552 }
4553
4554 /* dcbtls */
4555 static void gen_dcbtls(DisasContext *ctx)
4556 {
4557 /* Always fails locking the cache */
4558 TCGv t0 = tcg_temp_new();
4559 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4560 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4561 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4562 tcg_temp_free(t0);
4563 }
4564
4565 /* dcbz */
4566 static void gen_dcbz(DisasContext *ctx)
4567 {
4568 TCGv tcgv_addr;
4569 TCGv_i32 tcgv_is_dcbzl;
4570 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4571
4572 gen_set_access_type(ctx, ACCESS_CACHE);
4573 /* NIP cannot be restored if the memory exception comes from an helper */
4574 gen_update_nip(ctx, ctx->nip - 4);
4575 tcgv_addr = tcg_temp_new();
4576 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4577
4578 gen_addr_reg_index(ctx, tcgv_addr);
4579 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4580
4581 tcg_temp_free(tcgv_addr);
4582 tcg_temp_free_i32(tcgv_is_dcbzl);
4583 }
4584
4585 /* dst / dstt */
4586 static void gen_dst(DisasContext *ctx)
4587 {
4588 if (rA(ctx->opcode) == 0) {
4589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4590 } else {
4591 /* interpreted as no-op */
4592 }
4593 }
4594
4595 /* dstst /dststt */
4596 static void gen_dstst(DisasContext *ctx)
4597 {
4598 if (rA(ctx->opcode) == 0) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4600 } else {
4601 /* interpreted as no-op */
4602 }
4603
4604 }
4605
4606 /* dss / dssall */
4607 static void gen_dss(DisasContext *ctx)
4608 {
4609 /* interpreted as no-op */
4610 }
4611
4612 /* icbi */
4613 static void gen_icbi(DisasContext *ctx)
4614 {
4615 TCGv t0;
4616 gen_set_access_type(ctx, ACCESS_CACHE);
4617 /* NIP cannot be restored if the memory exception comes from an helper */
4618 gen_update_nip(ctx, ctx->nip - 4);
4619 t0 = tcg_temp_new();
4620 gen_addr_reg_index(ctx, t0);
4621 gen_helper_icbi(cpu_env, t0);
4622 tcg_temp_free(t0);
4623 }
4624
4625 /* Optional: */
4626 /* dcba */
4627 static void gen_dcba(DisasContext *ctx)
4628 {
4629 /* interpreted as no-op */
4630 /* XXX: specification say this is treated as a store by the MMU
4631 * but does not generate any exception
4632 */
4633 }
4634
4635 /*** Segment register manipulation ***/
4636 /* Supervisor only: */
4637
4638 /* mfsr */
4639 static void gen_mfsr(DisasContext *ctx)
4640 {
4641 #if defined(CONFIG_USER_ONLY)
4642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4643 #else
4644 TCGv t0;
4645 if (unlikely(ctx->pr)) {
4646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4647 return;
4648 }
4649 t0 = tcg_const_tl(SR(ctx->opcode));
4650 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4651 tcg_temp_free(t0);
4652 #endif
4653 }
4654
4655 /* mfsrin */
4656 static void gen_mfsrin(DisasContext *ctx)
4657 {
4658 #if defined(CONFIG_USER_ONLY)
4659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4660 #else
4661 TCGv t0;
4662 if (unlikely(ctx->pr)) {
4663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4664 return;
4665 }
4666 t0 = tcg_temp_new();
4667 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4668 tcg_gen_andi_tl(t0, t0, 0xF);
4669 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4670 tcg_temp_free(t0);
4671 #endif
4672 }
4673
4674 /* mtsr */
4675 static void gen_mtsr(DisasContext *ctx)
4676 {
4677 #if defined(CONFIG_USER_ONLY)
4678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4679 #else
4680 TCGv t0;
4681 if (unlikely(ctx->pr)) {
4682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4683 return;
4684 }
4685 t0 = tcg_const_tl(SR(ctx->opcode));
4686 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4687 tcg_temp_free(t0);
4688 #endif
4689 }
4690
4691 /* mtsrin */
4692 static void gen_mtsrin(DisasContext *ctx)
4693 {
4694 #if defined(CONFIG_USER_ONLY)
4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4696 #else
4697 TCGv t0;
4698 if (unlikely(ctx->pr)) {
4699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4700 return;
4701 }
4702 t0 = tcg_temp_new();
4703 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4704 tcg_gen_andi_tl(t0, t0, 0xF);
4705 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4706 tcg_temp_free(t0);
4707 #endif
4708 }
4709
4710 #if defined(TARGET_PPC64)
4711 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4712
4713 /* mfsr */
4714 static void gen_mfsr_64b(DisasContext *ctx)
4715 {
4716 #if defined(CONFIG_USER_ONLY)
4717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4718 #else
4719 TCGv t0;
4720 if (unlikely(ctx->pr)) {
4721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4722 return;
4723 }
4724 t0 = tcg_const_tl(SR(ctx->opcode));
4725 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4726 tcg_temp_free(t0);
4727 #endif
4728 }
4729
4730 /* mfsrin */
4731 static void gen_mfsrin_64b(DisasContext *ctx)
4732 {
4733 #if defined(CONFIG_USER_ONLY)
4734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4735 #else
4736 TCGv t0;
4737 if (unlikely(ctx->pr)) {
4738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4739 return;
4740 }
4741 t0 = tcg_temp_new();
4742 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4743 tcg_gen_andi_tl(t0, t0, 0xF);
4744 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4745 tcg_temp_free(t0);
4746 #endif
4747 }
4748
4749 /* mtsr */
4750 static void gen_mtsr_64b(DisasContext *ctx)
4751 {
4752 #if defined(CONFIG_USER_ONLY)
4753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4754 #else
4755 TCGv t0;
4756 if (unlikely(ctx->pr)) {
4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4758 return;
4759 }
4760 t0 = tcg_const_tl(SR(ctx->opcode));
4761 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4762 tcg_temp_free(t0);
4763 #endif
4764 }
4765
4766 /* mtsrin */
4767 static void gen_mtsrin_64b(DisasContext *ctx)
4768 {
4769 #if defined(CONFIG_USER_ONLY)
4770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4771 #else
4772 TCGv t0;
4773 if (unlikely(ctx->pr)) {
4774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4775 return;
4776 }
4777 t0 = tcg_temp_new();
4778 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4779 tcg_gen_andi_tl(t0, t0, 0xF);
4780 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4781 tcg_temp_free(t0);
4782 #endif
4783 }
4784
4785 /* slbmte */
4786 static void gen_slbmte(DisasContext *ctx)
4787 {
4788 #if defined(CONFIG_USER_ONLY)
4789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4790 #else
4791 if (unlikely(ctx->pr)) {
4792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4793 return;
4794 }
4795 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4796 cpu_gpr[rS(ctx->opcode)]);
4797 #endif
4798 }
4799
4800 static void gen_slbmfee(DisasContext *ctx)
4801 {
4802 #if defined(CONFIG_USER_ONLY)
4803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4804 #else
4805 if (unlikely(ctx->pr)) {
4806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4807 return;
4808 }
4809 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4810 cpu_gpr[rB(ctx->opcode)]);
4811 #endif
4812 }
4813
4814 static void gen_slbmfev(DisasContext *ctx)
4815 {
4816 #if defined(CONFIG_USER_ONLY)
4817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4818 #else
4819 if (unlikely(ctx->pr)) {
4820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4821 return;
4822 }
4823 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4824 cpu_gpr[rB(ctx->opcode)]);
4825 #endif
4826 }
4827 #endif /* defined(TARGET_PPC64) */
4828
4829 /*** Lookaside buffer management ***/
4830 /* Optional & supervisor only: */
4831
4832 /* tlbia */
4833 static void gen_tlbia(DisasContext *ctx)
4834 {
4835 #if defined(CONFIG_USER_ONLY)
4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4837 #else
4838 if (unlikely(ctx->pr)) {
4839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4840 return;
4841 }
4842 gen_helper_tlbia(cpu_env);
4843 #endif
4844 }
4845
4846 /* tlbiel */
4847 static void gen_tlbiel(DisasContext *ctx)
4848 {
4849 #if defined(CONFIG_USER_ONLY)
4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4851 #else
4852 if (unlikely(ctx->pr)) {
4853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4854 return;
4855 }
4856 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4857 #endif
4858 }
4859
4860 /* tlbie */
4861 static void gen_tlbie(DisasContext *ctx)
4862 {
4863 #if defined(CONFIG_USER_ONLY)
4864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4865 #else
4866 if (unlikely(ctx->pr)) {
4867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4868 return;
4869 }
4870 if (NARROW_MODE(ctx)) {
4871 TCGv t0 = tcg_temp_new();
4872 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4873 gen_helper_tlbie(cpu_env, t0);
4874 tcg_temp_free(t0);
4875 } else {
4876 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4877 }
4878 #endif
4879 }
4880
4881 /* tlbsync */
4882 static void gen_tlbsync(DisasContext *ctx)
4883 {
4884 #if defined(CONFIG_USER_ONLY)
4885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4886 #else
4887 if (unlikely(ctx->pr)) {
4888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4889 return;
4890 }
4891 /* This has no effect: it should ensure that all previous
4892 * tlbie have completed
4893 */
4894 gen_stop_exception(ctx);
4895 #endif
4896 }
4897
4898 #if defined(TARGET_PPC64)
4899 /* slbia */
4900 static void gen_slbia(DisasContext *ctx)
4901 {
4902 #if defined(CONFIG_USER_ONLY)
4903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4904 #else
4905 if (unlikely(ctx->pr)) {
4906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4907 return;
4908 }
4909 gen_helper_slbia(cpu_env);
4910 #endif
4911 }
4912
4913 /* slbie */
4914 static void gen_slbie(DisasContext *ctx)
4915 {
4916 #if defined(CONFIG_USER_ONLY)
4917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4918 #else
4919 if (unlikely(ctx->pr)) {
4920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4921 return;
4922 }
4923 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4924 #endif
4925 }
4926 #endif
4927
4928 /*** External control ***/
4929 /* Optional: */
4930
4931 /* eciwx */
4932 static void gen_eciwx(DisasContext *ctx)
4933 {
4934 TCGv t0;
4935 /* Should check EAR[E] ! */
4936 gen_set_access_type(ctx, ACCESS_EXT);
4937 t0 = tcg_temp_new();
4938 gen_addr_reg_index(ctx, t0);
4939 gen_check_align(ctx, t0, 0x03);
4940 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4941 tcg_temp_free(t0);
4942 }
4943
4944 /* ecowx */
4945 static void gen_ecowx(DisasContext *ctx)
4946 {
4947 TCGv t0;
4948 /* Should check EAR[E] ! */
4949 gen_set_access_type(ctx, ACCESS_EXT);
4950 t0 = tcg_temp_new();
4951 gen_addr_reg_index(ctx, t0);
4952 gen_check_align(ctx, t0, 0x03);
4953 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4954 tcg_temp_free(t0);
4955 }
4956
4957 /* PowerPC 601 specific instructions */
4958
4959 /* abs - abs. */
4960 static void gen_abs(DisasContext *ctx)
4961 {
4962 TCGLabel *l1 = gen_new_label();
4963 TCGLabel *l2 = gen_new_label();
4964 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4965 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4966 tcg_gen_br(l2);
4967 gen_set_label(l1);
4968 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4969 gen_set_label(l2);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4972 }
4973
4974 /* abso - abso. */
4975 static void gen_abso(DisasContext *ctx)
4976 {
4977 TCGLabel *l1 = gen_new_label();
4978 TCGLabel *l2 = gen_new_label();
4979 TCGLabel *l3 = gen_new_label();
4980 /* Start with XER OV disabled, the most likely case */
4981 tcg_gen_movi_tl(cpu_ov, 0);
4982 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4983 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4984 tcg_gen_movi_tl(cpu_ov, 1);
4985 tcg_gen_movi_tl(cpu_so, 1);
4986 tcg_gen_br(l2);
4987 gen_set_label(l1);
4988 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4989 tcg_gen_br(l3);
4990 gen_set_label(l2);
4991 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4992 gen_set_label(l3);
4993 if (unlikely(Rc(ctx->opcode) != 0))
4994 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4995 }
4996
4997 /* clcs */
4998 static void gen_clcs(DisasContext *ctx)
4999 {
5000 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5001 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5002 tcg_temp_free_i32(t0);
5003 /* Rc=1 sets CR0 to an undefined state */
5004 }
5005
5006 /* div - div. */
5007 static void gen_div(DisasContext *ctx)
5008 {
5009 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5010 cpu_gpr[rB(ctx->opcode)]);
5011 if (unlikely(Rc(ctx->opcode) != 0))
5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5013 }
5014
5015 /* divo - divo. */
5016 static void gen_divo(DisasContext *ctx)
5017 {
5018 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5019 cpu_gpr[rB(ctx->opcode)]);
5020 if (unlikely(Rc(ctx->opcode) != 0))
5021 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5022 }
5023
5024 /* divs - divs. */
5025 static void gen_divs(DisasContext *ctx)
5026 {
5027 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5028 cpu_gpr[rB(ctx->opcode)]);
5029 if (unlikely(Rc(ctx->opcode) != 0))
5030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5031 }
5032
5033 /* divso - divso. */
5034 static void gen_divso(DisasContext *ctx)
5035 {
5036 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5037 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5040 }
5041
5042 /* doz - doz. */
5043 static void gen_doz(DisasContext *ctx)
5044 {
5045 TCGLabel *l1 = gen_new_label();
5046 TCGLabel *l2 = gen_new_label();
5047 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5048 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5049 tcg_gen_br(l2);
5050 gen_set_label(l1);
5051 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5052 gen_set_label(l2);
5053 if (unlikely(Rc(ctx->opcode) != 0))
5054 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5055 }
5056
5057 /* dozo - dozo. */
5058 static void gen_dozo(DisasContext *ctx)
5059 {
5060 TCGLabel *l1 = gen_new_label();
5061 TCGLabel *l2 = gen_new_label();
5062 TCGv t0 = tcg_temp_new();
5063 TCGv t1 = tcg_temp_new();
5064 TCGv t2 = tcg_temp_new();
5065 /* Start with XER OV disabled, the most likely case */
5066 tcg_gen_movi_tl(cpu_ov, 0);
5067 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5068 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5069 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5070 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5071 tcg_gen_andc_tl(t1, t1, t2);
5072 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5073 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5074 tcg_gen_movi_tl(cpu_ov, 1);
5075 tcg_gen_movi_tl(cpu_so, 1);
5076 tcg_gen_br(l2);
5077 gen_set_label(l1);
5078 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5079 gen_set_label(l2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5085 }
5086
5087 /* dozi */
5088 static void gen_dozi(DisasContext *ctx)
5089 {
5090 target_long simm = SIMM(ctx->opcode);
5091 TCGLabel *l1 = gen_new_label();
5092 TCGLabel *l2 = gen_new_label();
5093 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5094 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5095 tcg_gen_br(l2);
5096 gen_set_label(l1);
5097 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5098 gen_set_label(l2);
5099 if (unlikely(Rc(ctx->opcode) != 0))
5100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5101 }
5102
5103 /* lscbx - lscbx. */
5104 static void gen_lscbx(DisasContext *ctx)
5105 {
5106 TCGv t0 = tcg_temp_new();
5107 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5108 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5109 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5110
5111 gen_addr_reg_index(ctx, t0);
5112 /* NIP cannot be restored if the memory exception comes from an helper */
5113 gen_update_nip(ctx, ctx->nip - 4);
5114 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5115 tcg_temp_free_i32(t1);
5116 tcg_temp_free_i32(t2);
5117 tcg_temp_free_i32(t3);
5118 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5119 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, t0);
5122 tcg_temp_free(t0);
5123 }
5124
5125 /* maskg - maskg. */
5126 static void gen_maskg(DisasContext *ctx)
5127 {
5128 TCGLabel *l1 = gen_new_label();
5129 TCGv t0 = tcg_temp_new();
5130 TCGv t1 = tcg_temp_new();
5131 TCGv t2 = tcg_temp_new();
5132 TCGv t3 = tcg_temp_new();
5133 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5134 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5135 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5136 tcg_gen_addi_tl(t2, t0, 1);
5137 tcg_gen_shr_tl(t2, t3, t2);
5138 tcg_gen_shr_tl(t3, t3, t1);
5139 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5140 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5141 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5142 gen_set_label(l1);
5143 tcg_temp_free(t0);
5144 tcg_temp_free(t1);
5145 tcg_temp_free(t2);
5146 tcg_temp_free(t3);
5147 if (unlikely(Rc(ctx->opcode) != 0))
5148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5149 }
5150
5151 /* maskir - maskir. */
5152 static void gen_maskir(DisasContext *ctx)
5153 {
5154 TCGv t0 = tcg_temp_new();
5155 TCGv t1 = tcg_temp_new();
5156 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5157 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5158 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5159 tcg_temp_free(t0);
5160 tcg_temp_free(t1);
5161 if (unlikely(Rc(ctx->opcode) != 0))
5162 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5163 }
5164
5165 /* mul - mul. */
5166 static void gen_mul(DisasContext *ctx)
5167 {
5168 TCGv_i64 t0 = tcg_temp_new_i64();
5169 TCGv_i64 t1 = tcg_temp_new_i64();
5170 TCGv t2 = tcg_temp_new();
5171 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5172 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5173 tcg_gen_mul_i64(t0, t0, t1);
5174 tcg_gen_trunc_i64_tl(t2, t0);
5175 gen_store_spr(SPR_MQ, t2);
5176 tcg_gen_shri_i64(t1, t0, 32);
5177 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5178 tcg_temp_free_i64(t0);
5179 tcg_temp_free_i64(t1);
5180 tcg_temp_free(t2);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5183 }
5184
5185 /* mulo - mulo. */
5186 static void gen_mulo(DisasContext *ctx)
5187 {
5188 TCGLabel *l1 = gen_new_label();
5189 TCGv_i64 t0 = tcg_temp_new_i64();
5190 TCGv_i64 t1 = tcg_temp_new_i64();
5191 TCGv t2 = tcg_temp_new();
5192 /* Start with XER OV disabled, the most likely case */
5193 tcg_gen_movi_tl(cpu_ov, 0);
5194 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5195 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5196 tcg_gen_mul_i64(t0, t0, t1);
5197 tcg_gen_trunc_i64_tl(t2, t0);
5198 gen_store_spr(SPR_MQ, t2);
5199 tcg_gen_shri_i64(t1, t0, 32);
5200 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5201 tcg_gen_ext32s_i64(t1, t0);
5202 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5203 tcg_gen_movi_tl(cpu_ov, 1);
5204 tcg_gen_movi_tl(cpu_so, 1);
5205 gen_set_label(l1);
5206 tcg_temp_free_i64(t0);
5207 tcg_temp_free_i64(t1);
5208 tcg_temp_free(t2);
5209 if (unlikely(Rc(ctx->opcode) != 0))
5210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5211 }
5212
5213 /* nabs - nabs. */
5214 static void gen_nabs(DisasContext *ctx)
5215 {
5216 TCGLabel *l1 = gen_new_label();
5217 TCGLabel *l2 = gen_new_label();
5218 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5219 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5220 tcg_gen_br(l2);
5221 gen_set_label(l1);
5222 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5223 gen_set_label(l2);
5224 if (unlikely(Rc(ctx->opcode) != 0))
5225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5226 }
5227
5228 /* nabso - nabso. */
5229 static void gen_nabso(DisasContext *ctx)
5230 {
5231 TCGLabel *l1 = gen_new_label();
5232 TCGLabel *l2 = gen_new_label();
5233 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5234 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5235 tcg_gen_br(l2);
5236 gen_set_label(l1);
5237 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5238 gen_set_label(l2);
5239 /* nabs never overflows */
5240 tcg_gen_movi_tl(cpu_ov, 0);
5241 if (unlikely(Rc(ctx->opcode) != 0))
5242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5243 }
5244
5245 /* rlmi - rlmi. */
5246 static void gen_rlmi(DisasContext *ctx)
5247 {
5248 uint32_t mb = MB(ctx->opcode);
5249 uint32_t me = ME(ctx->opcode);
5250 TCGv t0 = tcg_temp_new();
5251 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5252 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5253 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5254 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5255 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5256 tcg_temp_free(t0);
5257 if (unlikely(Rc(ctx->opcode) != 0))
5258 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5259 }
5260
5261 /* rrib - rrib. */
5262 static void gen_rrib(DisasContext *ctx)
5263 {
5264 TCGv t0 = tcg_temp_new();
5265 TCGv t1 = tcg_temp_new();
5266 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t1, 0x80000000);
5268 tcg_gen_shr_tl(t1, t1, t0);
5269 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5270 tcg_gen_and_tl(t0, t0, t1);
5271 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5272 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5273 tcg_temp_free(t0);
5274 tcg_temp_free(t1);
5275 if (unlikely(Rc(ctx->opcode) != 0))
5276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5277 }
5278
5279 /* sle - sle. */
5280 static void gen_sle(DisasContext *ctx)
5281 {
5282 TCGv t0 = tcg_temp_new();
5283 TCGv t1 = tcg_temp_new();
5284 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5285 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5286 tcg_gen_subfi_tl(t1, 32, t1);
5287 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5288 tcg_gen_or_tl(t1, t0, t1);
5289 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5290 gen_store_spr(SPR_MQ, t1);
5291 tcg_temp_free(t0);
5292 tcg_temp_free(t1);
5293 if (unlikely(Rc(ctx->opcode) != 0))
5294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5295 }
5296
5297 /* sleq - sleq. */
5298 static void gen_sleq(DisasContext *ctx)
5299 {
5300 TCGv t0 = tcg_temp_new();
5301 TCGv t1 = tcg_temp_new();
5302 TCGv t2 = tcg_temp_new();
5303 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5304 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5305 tcg_gen_shl_tl(t2, t2, t0);
5306 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5307 gen_load_spr(t1, SPR_MQ);
5308 gen_store_spr(SPR_MQ, t0);
5309 tcg_gen_and_tl(t0, t0, t2);
5310 tcg_gen_andc_tl(t1, t1, t2);
5311 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5312 tcg_temp_free(t0);
5313 tcg_temp_free(t1);
5314 tcg_temp_free(t2);
5315 if (unlikely(Rc(ctx->opcode) != 0))
5316 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5317 }
5318
5319 /* sliq - sliq. */
5320 static void gen_sliq(DisasContext *ctx)
5321 {
5322 int sh = SH(ctx->opcode);
5323 TCGv t0 = tcg_temp_new();
5324 TCGv t1 = tcg_temp_new();
5325 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5326 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5327 tcg_gen_or_tl(t1, t0, t1);
5328 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5329 gen_store_spr(SPR_MQ, t1);
5330 tcg_temp_free(t0);
5331 tcg_temp_free(t1);
5332 if (unlikely(Rc(ctx->opcode) != 0))
5333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5334 }
5335
5336 /* slliq - slliq. */
5337 static void gen_slliq(DisasContext *ctx)
5338 {
5339 int sh = SH(ctx->opcode);
5340 TCGv t0 = tcg_temp_new();
5341 TCGv t1 = tcg_temp_new();
5342 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5343 gen_load_spr(t1, SPR_MQ);
5344 gen_store_spr(SPR_MQ, t0);
5345 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5346 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5347 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5348 tcg_temp_free(t0);
5349 tcg_temp_free(t1);
5350 if (unlikely(Rc(ctx->opcode) != 0))
5351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5352 }
5353
5354 /* sllq - sllq. */
5355 static void gen_sllq(DisasContext *ctx)
5356 {
5357 TCGLabel *l1 = gen_new_label();
5358 TCGLabel *l2 = gen_new_label();
5359 TCGv t0 = tcg_temp_local_new();
5360 TCGv t1 = tcg_temp_local_new();
5361 TCGv t2 = tcg_temp_local_new();
5362 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5363 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5364 tcg_gen_shl_tl(t1, t1, t2);
5365 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5366 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5367 gen_load_spr(t0, SPR_MQ);
5368 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5369 tcg_gen_br(l2);
5370 gen_set_label(l1);
5371 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5372 gen_load_spr(t2, SPR_MQ);
5373 tcg_gen_andc_tl(t1, t2, t1);
5374 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5375 gen_set_label(l2);
5376 tcg_temp_free(t0);
5377 tcg_temp_free(t1);
5378 tcg_temp_free(t2);
5379 if (unlikely(Rc(ctx->opcode) != 0))
5380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5381 }
5382
5383 /* slq - slq. */
5384 static void gen_slq(DisasContext *ctx)
5385 {
5386 TCGLabel *l1 = gen_new_label();
5387 TCGv t0 = tcg_temp_new();
5388 TCGv t1 = tcg_temp_new();
5389 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5390 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5391 tcg_gen_subfi_tl(t1, 32, t1);
5392 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5393 tcg_gen_or_tl(t1, t0, t1);
5394 gen_store_spr(SPR_MQ, t1);
5395 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5396 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5397 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5398 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5399 gen_set_label(l1);
5400 tcg_temp_free(t0);
5401 tcg_temp_free(t1);
5402 if (unlikely(Rc(ctx->opcode) != 0))
5403 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5404 }
5405
5406 /* sraiq - sraiq. */
5407 static void gen_sraiq(DisasContext *ctx)
5408 {
5409 int sh = SH(ctx->opcode);
5410 TCGLabel *l1 = gen_new_label();
5411 TCGv t0 = tcg_temp_new();
5412 TCGv t1 = tcg_temp_new();
5413 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5414 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5415 tcg_gen_or_tl(t0, t0, t1);
5416 gen_store_spr(SPR_MQ, t0);
5417 tcg_gen_movi_tl(cpu_ca, 0);
5418 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5419 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5420 tcg_gen_movi_tl(cpu_ca, 1);
5421 gen_set_label(l1);
5422 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5423 tcg_temp_free(t0);
5424 tcg_temp_free(t1);
5425 if (unlikely(Rc(ctx->opcode) != 0))
5426 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5427 }
5428
5429 /* sraq - sraq. */
5430 static void gen_sraq(DisasContext *ctx)
5431 {
5432 TCGLabel *l1 = gen_new_label();
5433 TCGLabel *l2 = gen_new_label();
5434 TCGv t0 = tcg_temp_new();
5435 TCGv t1 = tcg_temp_local_new();
5436 TCGv t2 = tcg_temp_local_new();
5437 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5438 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5439 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5440 tcg_gen_subfi_tl(t2, 32, t2);
5441 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5442 tcg_gen_or_tl(t0, t0, t2);
5443 gen_store_spr(SPR_MQ, t0);
5444 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5445 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5446 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5447 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5448 gen_set_label(l1);
5449 tcg_temp_free(t0);
5450 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5451 tcg_gen_movi_tl(cpu_ca, 0);
5452 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5454 tcg_gen_movi_tl(cpu_ca, 1);
5455 gen_set_label(l2);
5456 tcg_temp_free(t1);
5457 tcg_temp_free(t2);
5458 if (unlikely(Rc(ctx->opcode) != 0))
5459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5460 }
5461
5462 /* sre - sre. */
5463 static void gen_sre(DisasContext *ctx)
5464 {
5465 TCGv t0 = tcg_temp_new();
5466 TCGv t1 = tcg_temp_new();
5467 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5468 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5469 tcg_gen_subfi_tl(t1, 32, t1);
5470 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5471 tcg_gen_or_tl(t1, t0, t1);
5472 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5473 gen_store_spr(SPR_MQ, t1);
5474 tcg_temp_free(t0);
5475 tcg_temp_free(t1);
5476 if (unlikely(Rc(ctx->opcode) != 0))
5477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5478 }
5479
5480 /* srea - srea. */
5481 static void gen_srea(DisasContext *ctx)
5482 {
5483 TCGv t0 = tcg_temp_new();
5484 TCGv t1 = tcg_temp_new();
5485 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5486 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5487 gen_store_spr(SPR_MQ, t0);
5488 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5489 tcg_temp_free(t0);
5490 tcg_temp_free(t1);
5491 if (unlikely(Rc(ctx->opcode) != 0))
5492 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5493 }
5494
5495 /* sreq */
5496 static void gen_sreq(DisasContext *ctx)
5497 {
5498 TCGv t0 = tcg_temp_new();
5499 TCGv t1 = tcg_temp_new();
5500 TCGv t2 = tcg_temp_new();
5501 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5502 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5503 tcg_gen_shr_tl(t1, t1, t0);
5504 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5505 gen_load_spr(t2, SPR_MQ);
5506 gen_store_spr(SPR_MQ, t0);
5507 tcg_gen_and_tl(t0, t0, t1);
5508 tcg_gen_andc_tl(t2, t2, t1);
5509 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5510 tcg_temp_free(t0);
5511 tcg_temp_free(t1);
5512 tcg_temp_free(t2);
5513 if (unlikely(Rc(ctx->opcode) != 0))
5514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5515 }
5516
5517 /* sriq */
5518 static void gen_sriq(DisasContext *ctx)
5519 {
5520 int sh = SH(ctx->opcode);
5521 TCGv t0 = tcg_temp_new();
5522 TCGv t1 = tcg_temp_new();
5523 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5524 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5525 tcg_gen_or_tl(t1, t0, t1);
5526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5527 gen_store_spr(SPR_MQ, t1);
5528 tcg_temp_free(t0);
5529 tcg_temp_free(t1);
5530 if (unlikely(Rc(ctx->opcode) != 0))
5531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5532 }
5533
5534 /* srliq */
5535 static void gen_srliq(DisasContext *ctx)
5536 {
5537 int sh = SH(ctx->opcode);
5538 TCGv t0 = tcg_temp_new();
5539 TCGv t1 = tcg_temp_new();
5540 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5541 gen_load_spr(t1, SPR_MQ);
5542 gen_store_spr(SPR_MQ, t0);
5543 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5544 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5545 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5546 tcg_temp_free(t0);
5547 tcg_temp_free(t1);
5548 if (unlikely(Rc(ctx->opcode) != 0))
5549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5550 }
5551
5552 /* srlq */
5553 static void gen_srlq(DisasContext *ctx)
5554 {
5555 TCGLabel *l1 = gen_new_label();
5556 TCGLabel *l2 = gen_new_label();
5557 TCGv t0 = tcg_temp_local_new();
5558 TCGv t1 = tcg_temp_local_new();
5559 TCGv t2 = tcg_temp_local_new();
5560 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5561 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5562 tcg_gen_shr_tl(t2, t1, t2);
5563 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5564 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5565 gen_load_spr(t0, SPR_MQ);
5566 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5567 tcg_gen_br(l2);
5568 gen_set_label(l1);
5569 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5570 tcg_gen_and_tl(t0, t0, t2);
5571 gen_load_spr(t1, SPR_MQ);
5572 tcg_gen_andc_tl(t1, t1, t2);
5573 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5574 gen_set_label(l2);
5575 tcg_temp_free(t0);
5576 tcg_temp_free(t1);
5577 tcg_temp_free(t2);
5578 if (unlikely(Rc(ctx->opcode) != 0))
5579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5580 }
5581
5582 /* srq */
5583 static void gen_srq(DisasContext *ctx)
5584 {
5585 TCGLabel *l1 = gen_new_label();
5586 TCGv t0 = tcg_temp_new();
5587 TCGv t1 = tcg_temp_new();
5588 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5589 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5590 tcg_gen_subfi_tl(t1, 32, t1);
5591 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5592 tcg_gen_or_tl(t1, t0, t1);
5593 gen_store_spr(SPR_MQ, t1);
5594 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5595 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5596 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5597 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5598 gen_set_label(l1);
5599 tcg_temp_free(t0);
5600 tcg_temp_free(t1);
5601 if (unlikely(Rc(ctx->opcode) != 0))
5602 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5603 }
5604
5605 /* PowerPC 602 specific instructions */
5606
5607 /* dsa */
5608 static void gen_dsa(DisasContext *ctx)
5609 {
5610 /* XXX: TODO */
5611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5612 }
5613
5614 /* esa */
5615 static void gen_esa(DisasContext *ctx)
5616 {
5617 /* XXX: TODO */
5618 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5619 }
5620
5621 /* mfrom */
5622 static void gen_mfrom(DisasContext *ctx)
5623 {
5624 #if defined(CONFIG_USER_ONLY)
5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5626 #else
5627 if (unlikely(ctx->pr)) {
5628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5629 return;
5630 }
5631 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5632 #endif
5633 }
5634
5635 /* 602 - 603 - G2 TLB management */
5636
5637 /* tlbld */
5638 static void gen_tlbld_6xx(DisasContext *ctx)
5639 {
5640 #if defined(CONFIG_USER_ONLY)
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5642 #else
5643 if (unlikely(ctx->pr)) {
5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5645 return;
5646 }
5647 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5648 #endif
5649 }
5650
5651 /* tlbli */
5652 static void gen_tlbli_6xx(DisasContext *ctx)
5653 {
5654 #if defined(CONFIG_USER_ONLY)
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5656 #else
5657 if (unlikely(ctx->pr)) {
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5659 return;
5660 }
5661 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5662 #endif
5663 }
5664
5665 /* 74xx TLB management */
5666
5667 /* tlbld */
5668 static void gen_tlbld_74xx(DisasContext *ctx)
5669 {
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5672 #else
5673 if (unlikely(ctx->pr)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5675 return;
5676 }
5677 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5678 #endif
5679 }
5680
5681 /* tlbli */
5682 static void gen_tlbli_74xx(DisasContext *ctx)
5683 {
5684 #if defined(CONFIG_USER_ONLY)
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5686 #else
5687 if (unlikely(ctx->pr)) {
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5689 return;
5690 }
5691 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5692 #endif
5693 }
5694
5695 /* POWER instructions not in PowerPC 601 */
5696
5697 /* clf */
5698 static void gen_clf(DisasContext *ctx)
5699 {
5700 /* Cache line flush: implemented as no-op */
5701 }
5702
5703 /* cli */
5704 static void gen_cli(DisasContext *ctx)
5705 {
5706 /* Cache line invalidate: privileged and treated as no-op */
5707 #if defined(CONFIG_USER_ONLY)
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5709 #else
5710 if (unlikely(ctx->pr)) {
5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5712 return;
5713 }
5714 #endif
5715 }
5716
5717 /* dclst */
5718 static void gen_dclst(DisasContext *ctx)
5719 {
5720 /* Data cache line store: treated as no-op */
5721 }
5722
5723 static void gen_mfsri(DisasContext *ctx)
5724 {
5725 #if defined(CONFIG_USER_ONLY)
5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5727 #else
5728 int ra = rA(ctx->opcode);
5729 int rd = rD(ctx->opcode);
5730 TCGv t0;
5731 if (unlikely(ctx->pr)) {
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 return;
5734 }
5735 t0 = tcg_temp_new();
5736 gen_addr_reg_index(ctx, t0);
5737 tcg_gen_shri_tl(t0, t0, 28);
5738 tcg_gen_andi_tl(t0, t0, 0xF);
5739 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5740 tcg_temp_free(t0);
5741 if (ra != 0 && ra != rd)
5742 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5743 #endif
5744 }
5745
5746 static void gen_rac(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5750 #else
5751 TCGv t0;
5752 if (unlikely(ctx->pr)) {
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 return;
5755 }
5756 t0 = tcg_temp_new();
5757 gen_addr_reg_index(ctx, t0);
5758 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5759 tcg_temp_free(t0);
5760 #endif
5761 }
5762
5763 static void gen_rfsvc(DisasContext *ctx)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5767 #else
5768 if (unlikely(ctx->pr)) {
5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5770 return;
5771 }
5772 gen_helper_rfsvc(cpu_env);
5773 gen_sync_exception(ctx);
5774 #endif
5775 }
5776
5777 /* svc is not implemented for now */
5778
5779 /* POWER2 specific instructions */
5780 /* Quad manipulation (load/store two floats at a time) */
5781
5782 /* lfq */
5783 static void gen_lfq(DisasContext *ctx)
5784 {
5785 int rd = rD(ctx->opcode);
5786 TCGv t0;
5787 gen_set_access_type(ctx, ACCESS_FLOAT);
5788 t0 = tcg_temp_new();
5789 gen_addr_imm_index(ctx, t0, 0);
5790 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5791 gen_addr_add(ctx, t0, t0, 8);
5792 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5793 tcg_temp_free(t0);
5794 }
5795
5796 /* lfqu */
5797 static void gen_lfqu(DisasContext *ctx)
5798 {
5799 int ra = rA(ctx->opcode);
5800 int rd = rD(ctx->opcode);
5801 TCGv t0, t1;
5802 gen_set_access_type(ctx, ACCESS_FLOAT);
5803 t0 = tcg_temp_new();
5804 t1 = tcg_temp_new();
5805 gen_addr_imm_index(ctx, t0, 0);
5806 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5807 gen_addr_add(ctx, t1, t0, 8);
5808 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5809 if (ra != 0)
5810 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5811 tcg_temp_free(t0);
5812 tcg_temp_free(t1);
5813 }
5814
5815 /* lfqux */
5816 static void gen_lfqux(DisasContext *ctx)
5817 {
5818 int ra = rA(ctx->opcode);
5819 int rd = rD(ctx->opcode);
5820 gen_set_access_type(ctx, ACCESS_FLOAT);
5821 TCGv t0, t1;
5822 t0 = tcg_temp_new();
5823 gen_addr_reg_index(ctx, t0);
5824 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5825 t1 = tcg_temp_new();
5826 gen_addr_add(ctx, t1, t0, 8);
5827 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5828 tcg_temp_free(t1);
5829 if (ra != 0)
5830 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5831 tcg_temp_free(t0);
5832 }
5833
5834 /* lfqx */
5835 static void gen_lfqx(DisasContext *ctx)
5836 {
5837 int rd = rD(ctx->opcode);
5838 TCGv t0;
5839 gen_set_access_type(ctx, ACCESS_FLOAT);
5840 t0 = tcg_temp_new();
5841 gen_addr_reg_index(ctx, t0);
5842 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5843 gen_addr_add(ctx, t0, t0, 8);
5844 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5845 tcg_temp_free(t0);
5846 }
5847
5848 /* stfq */
5849 static void gen_stfq(DisasContext *ctx)
5850 {
5851 int rd = rD(ctx->opcode);
5852 TCGv t0;
5853 gen_set_access_type(ctx, ACCESS_FLOAT);
5854 t0 = tcg_temp_new();
5855 gen_addr_imm_index(ctx, t0, 0);
5856 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5857 gen_addr_add(ctx, t0, t0, 8);
5858 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5859 tcg_temp_free(t0);
5860 }
5861
5862 /* stfqu */
5863 static void gen_stfqu(DisasContext *ctx)
5864 {
5865 int ra = rA(ctx->opcode);
5866 int rd = rD(ctx->opcode);
5867 TCGv t0, t1;
5868 gen_set_access_type(ctx, ACCESS_FLOAT);
5869 t0 = tcg_temp_new();
5870 gen_addr_imm_index(ctx, t0, 0);
5871 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5872 t1 = tcg_temp_new();
5873 gen_addr_add(ctx, t1, t0, 8);
5874 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5875 tcg_temp_free(t1);
5876 if (ra != 0)
5877 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5878 tcg_temp_free(t0);
5879 }
5880
5881 /* stfqux */
5882 static void gen_stfqux(DisasContext *ctx)
5883 {
5884 int ra = rA(ctx->opcode);
5885 int rd = rD(ctx->opcode);
5886 TCGv t0, t1;
5887 gen_set_access_type(ctx, ACCESS_FLOAT);
5888 t0 = tcg_temp_new();
5889 gen_addr_reg_index(ctx, t0);
5890 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5891 t1 = tcg_temp_new();
5892 gen_addr_add(ctx, t1, t0, 8);
5893 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5894 tcg_temp_free(t1);
5895 if (ra != 0)
5896 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5897 tcg_temp_free(t0);
5898 }
5899
5900 /* stfqx */
5901 static void gen_stfqx(DisasContext *ctx)
5902 {
5903 int rd = rD(ctx->opcode);
5904 TCGv t0;
5905 gen_set_access_type(ctx, ACCESS_FLOAT);
5906 t0 = tcg_temp_new();
5907 gen_addr_reg_index(ctx, t0);
5908 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5909 gen_addr_add(ctx, t0, t0, 8);
5910 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5911 tcg_temp_free(t0);
5912 }
5913
5914 /* BookE specific instructions */
5915
5916 /* XXX: not implemented on 440 ? */
5917 static void gen_mfapidi(DisasContext *ctx)
5918 {
5919 /* XXX: TODO */
5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5921 }
5922
5923 /* XXX: not implemented on 440 ? */
5924 static void gen_tlbiva(DisasContext *ctx)
5925 {
5926 #if defined(CONFIG_USER_ONLY)
5927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5928 #else
5929 TCGv t0;
5930 if (unlikely(ctx->pr)) {
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 return;
5933 }
5934 t0 = tcg_temp_new();
5935 gen_addr_reg_index(ctx, t0);
5936 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5937 tcg_temp_free(t0);
5938 #endif
5939 }
5940
5941 /* All 405 MAC instructions are translated here */
5942 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5943 int ra, int rb, int rt, int Rc)
5944 {
5945 TCGv t0, t1;
5946
5947 t0 = tcg_temp_local_new();
5948 t1 = tcg_temp_local_new();
5949
5950 switch (opc3 & 0x0D) {
5951 case 0x05:
5952 /* macchw - macchw. - macchwo - macchwo. */
5953 /* macchws - macchws. - macchwso - macchwso. */
5954 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5955 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5956 /* mulchw - mulchw. */
5957 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5958 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5959 tcg_gen_ext16s_tl(t1, t1);
5960 break;
5961 case 0x04:
5962 /* macchwu - macchwu. - macchwuo - macchwuo. */
5963 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5964 /* mulchwu - mulchwu. */
5965 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5966 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5967 tcg_gen_ext16u_tl(t1, t1);
5968 break;
5969 case 0x01:
5970 /* machhw - machhw. - machhwo - machhwo. */
5971 /* machhws - machhws. - machhwso - machhwso. */
5972 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5973 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5974 /* mulhhw - mulhhw. */
5975 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5976 tcg_gen_ext16s_tl(t0, t0);
5977 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5978 tcg_gen_ext16s_tl(t1, t1);
5979 break;
5980 case 0x00:
5981 /* machhwu - machhwu. - machhwuo - machhwuo. */
5982 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5983 /* mulhhwu - mulhhwu. */
5984 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5985 tcg_gen_ext16u_tl(t0, t0);
5986 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5987 tcg_gen_ext16u_tl(t1, t1);
5988 break;
5989 case 0x0D:
5990 /* maclhw - maclhw. - maclhwo - maclhwo. */
5991 /* maclhws - maclhws. - maclhwso - maclhwso. */
5992 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5993 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5994 /* mullhw - mullhw. */
5995 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5996 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5997 break;
5998 case 0x0C:
5999 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6000 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6001 /* mullhwu - mullhwu. */
6002 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6003 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6004 break;
6005 }
6006 if (opc2 & 0x04) {
6007 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6008 tcg_gen_mul_tl(t1, t0, t1);
6009 if (opc2 & 0x02) {
6010 /* nmultiply-and-accumulate (0x0E) */
6011 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6012 } else {
6013 /* multiply-and-accumulate (0x0C) */
6014 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6015 }
6016
6017 if (opc3 & 0x12) {
6018 /* Check overflow and/or saturate */
6019 TCGLabel *l1 = gen_new_label();
6020
6021 if (opc3 & 0x10) {
6022 /* Start with XER OV disabled, the most likely case */
6023 tcg_gen_movi_tl(cpu_ov, 0);
6024 }
6025 if (opc3 & 0x01) {
6026 /* Signed */
6027 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6028 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6029 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6030 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6031 if (opc3 & 0x02) {
6032 /* Saturate */
6033 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6034 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6035 }
6036 } else {
6037 /* Unsigned */
6038 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6039 if (opc3 & 0x02) {
6040 /* Saturate */
6041 tcg_gen_movi_tl(t0, UINT32_MAX);
6042 }
6043 }
6044 if (opc3 & 0x10) {
6045 /* Check overflow */
6046 tcg_gen_movi_tl(cpu_ov, 1);
6047 tcg_gen_movi_tl(cpu_so, 1);
6048 }
6049 gen_set_label(l1);
6050 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6051 }
6052 } else {
6053 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6054 }
6055 tcg_temp_free(t0);
6056 tcg_temp_free(t1);
6057 if (unlikely(Rc) != 0) {
6058 /* Update Rc0 */
6059 gen_set_Rc0(ctx, cpu_gpr[rt]);
6060 }
6061 }
6062
6063 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6064 static void glue(gen_, name)(DisasContext *ctx) \
6065 { \
6066 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6067 rD(ctx->opcode), Rc(ctx->opcode)); \
6068 }
6069
6070 /* macchw - macchw. */
6071 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6072 /* macchwo - macchwo. */
6073 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6074 /* macchws - macchws. */
6075 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6076 /* macchwso - macchwso. */
6077 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6078 /* macchwsu - macchwsu. */
6079 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6080 /* macchwsuo - macchwsuo. */
6081 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6082 /* macchwu - macchwu. */
6083 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6084 /* macchwuo - macchwuo. */
6085 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6086 /* machhw - machhw. */
6087 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6088 /* machhwo - machhwo. */
6089 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6090 /* machhws - machhws. */
6091 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6092 /* machhwso - machhwso. */
6093 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6094 /* machhwsu - machhwsu. */
6095 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6096 /* machhwsuo - machhwsuo. */
6097 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6098 /* machhwu - machhwu. */
6099 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6100 /* machhwuo - machhwuo. */
6101 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6102 /* maclhw - maclhw. */
6103 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6104 /* maclhwo - maclhwo. */
6105 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6106 /* maclhws - maclhws. */
6107 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6108 /* maclhwso - maclhwso. */
6109 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6110 /* maclhwu - maclhwu. */
6111 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6112 /* maclhwuo - maclhwuo. */
6113 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6114 /* maclhwsu - maclhwsu. */
6115 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6116 /* maclhwsuo - maclhwsuo. */
6117 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6118 /* nmacchw - nmacchw. */
6119 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6120 /* nmacchwo - nmacchwo. */
6121 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6122 /* nmacchws - nmacchws. */
6123 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6124 /* nmacchwso - nmacchwso. */
6125 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6126 /* nmachhw - nmachhw. */
6127 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6128 /* nmachhwo - nmachhwo. */
6129 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6130 /* nmachhws - nmachhws. */
6131 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6132 /* nmachhwso - nmachhwso. */
6133 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6134 /* nmaclhw - nmaclhw. */
6135 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6136 /* nmaclhwo - nmaclhwo. */
6137 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6138 /* nmaclhws - nmaclhws. */
6139 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6140 /* nmaclhwso - nmaclhwso. */
6141 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6142
6143 /* mulchw - mulchw. */
6144 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6145 /* mulchwu - mulchwu. */
6146 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6147 /* mulhhw - mulhhw. */
6148 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6149 /* mulhhwu - mulhhwu. */
6150 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6151 /* mullhw - mullhw. */
6152 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6153 /* mullhwu - mullhwu. */
6154 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6155
6156 /* mfdcr */
6157 static void gen_mfdcr(DisasContext *ctx)
6158 {
6159 #if defined(CONFIG_USER_ONLY)
6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6161 #else
6162 TCGv dcrn;
6163 if (unlikely(ctx->pr)) {
6164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6165 return;
6166 }
6167 /* NIP cannot be restored if the memory exception comes from an helper */
6168 gen_update_nip(ctx, ctx->nip - 4);
6169 dcrn = tcg_const_tl(SPR(ctx->opcode));
6170 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6171 tcg_temp_free(dcrn);
6172 #endif
6173 }
6174
6175 /* mtdcr */
6176 static void gen_mtdcr(DisasContext *ctx)
6177 {
6178 #if defined(CONFIG_USER_ONLY)
6179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6180 #else
6181 TCGv dcrn;
6182 if (unlikely(ctx->pr)) {
6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6184 return;
6185 }
6186 /* NIP cannot be restored if the memory exception comes from an helper */
6187 gen_update_nip(ctx, ctx->nip - 4);
6188 dcrn = tcg_const_tl(SPR(ctx->opcode));
6189 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6190 tcg_temp_free(dcrn);
6191 #endif
6192 }
6193
6194 /* mfdcrx */
6195 /* XXX: not implemented on 440 ? */
6196 static void gen_mfdcrx(DisasContext *ctx)
6197 {
6198 #if defined(CONFIG_USER_ONLY)
6199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6200 #else
6201 if (unlikely(ctx->pr)) {
6202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6203 return;
6204 }
6205 /* NIP cannot be restored if the memory exception comes from an helper */
6206 gen_update_nip(ctx, ctx->nip - 4);
6207 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6208 cpu_gpr[rA(ctx->opcode)]);
6209 /* Note: Rc update flag set leads to undefined state of Rc0 */
6210 #endif
6211 }
6212
6213 /* mtdcrx */
6214 /* XXX: not implemented on 440 ? */
6215 static void gen_mtdcrx(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6219 #else
6220 if (unlikely(ctx->pr)) {
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6222 return;
6223 }
6224 /* NIP cannot be restored if the memory exception comes from an helper */
6225 gen_update_nip(ctx, ctx->nip - 4);
6226 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6227 cpu_gpr[rS(ctx->opcode)]);
6228 /* Note: Rc update flag set leads to undefined state of Rc0 */
6229 #endif
6230 }
6231
6232 /* mfdcrux (PPC 460) : user-mode access to DCR */
6233 static void gen_mfdcrux(DisasContext *ctx)
6234 {
6235 /* NIP cannot be restored if the memory exception comes from an helper */
6236 gen_update_nip(ctx, ctx->nip - 4);
6237 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6238 cpu_gpr[rA(ctx->opcode)]);
6239 /* Note: Rc update flag set leads to undefined state of Rc0 */
6240 }
6241
6242 /* mtdcrux (PPC 460) : user-mode access to DCR */
6243 static void gen_mtdcrux(DisasContext *ctx)
6244 {
6245 /* NIP cannot be restored if the memory exception comes from an helper */
6246 gen_update_nip(ctx, ctx->nip - 4);
6247 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6248 cpu_gpr[rS(ctx->opcode)]);
6249 /* Note: Rc update flag set leads to undefined state of Rc0 */
6250 }
6251
6252 /* dccci */
6253 static void gen_dccci(DisasContext *ctx)
6254 {
6255 #if defined(CONFIG_USER_ONLY)
6256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6257 #else
6258 if (unlikely(ctx->pr)) {
6259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6260 return;
6261 }
6262 /* interpreted as no-op */
6263 #endif
6264 }
6265
6266 /* dcread */
6267 static void gen_dcread(DisasContext *ctx)
6268 {
6269 #if defined(CONFIG_USER_ONLY)
6270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6271 #else
6272 TCGv EA, val;
6273 if (unlikely(ctx->pr)) {
6274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6275 return;
6276 }
6277 gen_set_access_type(ctx, ACCESS_CACHE);
6278 EA = tcg_temp_new();
6279 gen_addr_reg_index(ctx, EA);
6280 val = tcg_temp_new();
6281 gen_qemu_ld32u(ctx, val, EA);
6282 tcg_temp_free(val);
6283 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6284 tcg_temp_free(EA);
6285 #endif
6286 }
6287
6288 /* icbt */
6289 static void gen_icbt_40x(DisasContext *ctx)
6290 {
6291 /* interpreted as no-op */
6292 /* XXX: specification say this is treated as a load by the MMU
6293 * but does not generate any exception
6294 */
6295 }
6296
6297 /* iccci */
6298 static void gen_iccci(DisasContext *ctx)
6299 {
6300 #if defined(CONFIG_USER_ONLY)
6301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6302 #else
6303 if (unlikely(ctx->pr)) {
6304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6305 return;
6306 }
6307 /* interpreted as no-op */
6308 #endif
6309 }
6310
6311 /* icread */
6312 static void gen_icread(DisasContext *ctx)
6313 {
6314 #if defined(CONFIG_USER_ONLY)
6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6316 #else
6317 if (unlikely(ctx->pr)) {
6318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6319 return;
6320 }
6321 /* interpreted as no-op */
6322 #endif
6323 }
6324
6325 /* rfci (supervisor only) */
6326 static void gen_rfci_40x(DisasContext *ctx)
6327 {
6328 #if defined(CONFIG_USER_ONLY)
6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6330 #else
6331 if (unlikely(ctx->pr)) {
6332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6333 return;
6334 }
6335 /* Restore CPU state */
6336 gen_helper_40x_rfci(cpu_env);
6337 gen_sync_exception(ctx);
6338 #endif
6339 }
6340
6341 static void gen_rfci(DisasContext *ctx)
6342 {
6343 #if defined(CONFIG_USER_ONLY)
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 #else
6346 if (unlikely(ctx->pr)) {
6347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6348 return;
6349 }
6350 /* Restore CPU state */
6351 gen_helper_rfci(cpu_env);
6352 gen_sync_exception(ctx);
6353 #endif
6354 }
6355
6356 /* BookE specific */
6357
6358 /* XXX: not implemented on 440 ? */
6359 static void gen_rfdi(DisasContext *ctx)
6360 {
6361 #if defined(CONFIG_USER_ONLY)
6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6363 #else
6364 if (unlikely(ctx->pr)) {
6365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6366 return;
6367 }
6368 /* Restore CPU state */
6369 gen_helper_rfdi(cpu_env);
6370 gen_sync_exception(ctx);
6371 #endif
6372 }
6373
6374 /* XXX: not implemented on 440 ? */
6375 static void gen_rfmci(DisasContext *ctx)
6376 {
6377 #if defined(CONFIG_USER_ONLY)
6378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6379 #else
6380 if (unlikely(ctx->pr)) {
6381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6382 return;
6383 }
6384 /* Restore CPU state */
6385 gen_helper_rfmci(cpu_env);
6386 gen_sync_exception(ctx);
6387 #endif
6388 }
6389
6390 /* TLB management - PowerPC 405 implementation */
6391
6392 /* tlbre */
6393 static void gen_tlbre_40x(DisasContext *ctx)
6394 {
6395 #if defined(CONFIG_USER_ONLY)
6396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6397 #else
6398 if (unlikely(ctx->pr)) {
6399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6400 return;
6401 }
6402 switch (rB(ctx->opcode)) {
6403 case 0:
6404 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6405 cpu_gpr[rA(ctx->opcode)]);
6406 break;
6407 case 1:
6408 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6409 cpu_gpr[rA(ctx->opcode)]);
6410 break;
6411 default:
6412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6413 break;
6414 }
6415 #endif
6416 }
6417
6418 /* tlbsx - tlbsx. */
6419 static void gen_tlbsx_40x(DisasContext *ctx)
6420 {
6421 #if defined(CONFIG_USER_ONLY)
6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6423 #else
6424 TCGv t0;
6425 if (unlikely(ctx->pr)) {
6426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6427 return;
6428 }
6429 t0 = tcg_temp_new();
6430 gen_addr_reg_index(ctx, t0);
6431 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6432 tcg_temp_free(t0);
6433 if (Rc(ctx->opcode)) {
6434 TCGLabel *l1 = gen_new_label();
6435 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6436 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6437 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6438 gen_set_label(l1);
6439 }
6440 #endif
6441 }
6442
6443 /* tlbwe */
6444 static void gen_tlbwe_40x(DisasContext *ctx)
6445 {
6446 #if defined(CONFIG_USER_ONLY)
6447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6448 #else
6449 if (unlikely(ctx->pr)) {
6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6451 return;
6452 }
6453 switch (rB(ctx->opcode)) {
6454 case 0:
6455 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6456 cpu_gpr[rS(ctx->opcode)]);
6457 break;
6458 case 1:
6459 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6460 cpu_gpr[rS(ctx->opcode)]);
6461 break;
6462 default:
6463 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6464 break;
6465 }
6466 #endif
6467 }
6468
6469 /* TLB management - PowerPC 440 implementation */
6470
6471 /* tlbre */
6472 static void gen_tlbre_440(DisasContext *ctx)
6473 {
6474 #if defined(CONFIG_USER_ONLY)
6475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6476 #else
6477 if (unlikely(ctx->pr)) {
6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6479 return;
6480 }
6481 switch (rB(ctx->opcode)) {
6482 case 0:
6483 case 1:
6484 case 2:
6485 {
6486 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6487 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6488 t0, cpu_gpr[rA(ctx->opcode)]);
6489 tcg_temp_free_i32(t0);
6490 }
6491 break;
6492 default:
6493 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6494 break;
6495 }
6496 #endif
6497 }
6498
6499 /* tlbsx - tlbsx. */
6500 static void gen_tlbsx_440(DisasContext *ctx)
6501 {
6502 #if defined(CONFIG_USER_ONLY)
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504 #else
6505 TCGv t0;
6506 if (unlikely(ctx->pr)) {
6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6508 return;
6509 }
6510 t0 = tcg_temp_new();
6511 gen_addr_reg_index(ctx, t0);
6512 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6513 tcg_temp_free(t0);
6514 if (Rc(ctx->opcode)) {
6515 TCGLabel *l1 = gen_new_label();
6516 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6517 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6518 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6519 gen_set_label(l1);
6520 }
6521 #endif
6522 }
6523
6524 /* tlbwe */
6525 static void gen_tlbwe_440(DisasContext *ctx)
6526 {
6527 #if defined(CONFIG_USER_ONLY)
6528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6529 #else
6530 if (unlikely(ctx->pr)) {
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532 return;
6533 }
6534 switch (rB(ctx->opcode)) {
6535 case 0:
6536 case 1:
6537 case 2:
6538 {
6539 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6540 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6541 cpu_gpr[rS(ctx->opcode)]);
6542 tcg_temp_free_i32(t0);
6543 }
6544 break;
6545 default:
6546 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6547 break;
6548 }
6549 #endif
6550 }
6551
6552 /* TLB management - PowerPC BookE 2.06 implementation */
6553
6554 /* tlbre */
6555 static void gen_tlbre_booke206(DisasContext *ctx)
6556 {
6557 #if defined(CONFIG_USER_ONLY)
6558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6559 #else
6560 if (unlikely(ctx->pr)) {
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 return;
6563 }
6564
6565 gen_helper_booke206_tlbre(cpu_env);
6566 #endif
6567 }
6568
6569 /* tlbsx - tlbsx. */
6570 static void gen_tlbsx_booke206(DisasContext *ctx)
6571 {
6572 #if defined(CONFIG_USER_ONLY)
6573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6574 #else
6575 TCGv t0;
6576 if (unlikely(ctx->pr)) {
6577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6578 return;
6579 }
6580
6581 if (rA(ctx->opcode)) {
6582 t0 = tcg_temp_new();
6583 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6584 } else {
6585 t0 = tcg_const_tl(0);
6586 }
6587
6588 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6589 gen_helper_booke206_tlbsx(cpu_env, t0);
6590 tcg_temp_free(t0);
6591 #endif
6592 }
6593
6594 /* tlbwe */
6595 static void gen_tlbwe_booke206(DisasContext *ctx)
6596 {
6597 #if defined(CONFIG_USER_ONLY)
6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599 #else
6600 if (unlikely(ctx->pr)) {
6601 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6602 return;
6603 }
6604 gen_update_nip(ctx, ctx->nip - 4);
6605 gen_helper_booke206_tlbwe(cpu_env);
6606 #endif
6607 }
6608
6609 static void gen_tlbivax_booke206(DisasContext *ctx)
6610 {
6611 #if defined(CONFIG_USER_ONLY)
6612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6613 #else
6614 TCGv t0;
6615 if (unlikely(ctx->pr)) {
6616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6617 return;
6618 }
6619
6620 t0 = tcg_temp_new();
6621 gen_addr_reg_index(ctx, t0);
6622
6623 gen_helper_booke206_tlbivax(cpu_env, t0);
6624 tcg_temp_free(t0);
6625 #endif
6626 }
6627
6628 static void gen_tlbilx_booke206(DisasContext *ctx)
6629 {
6630 #if defined(CONFIG_USER_ONLY)
6631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6632 #else
6633 TCGv t0;
6634 if (unlikely(ctx->pr)) {
6635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6636 return;
6637 }
6638
6639 t0 = tcg_temp_new();
6640 gen_addr_reg_index(ctx, t0);
6641
6642 switch((ctx->opcode >> 21) & 0x3) {
6643 case 0:
6644 gen_helper_booke206_tlbilx0(cpu_env, t0);
6645 break;
6646 case 1:
6647 gen_helper_booke206_tlbilx1(cpu_env, t0);
6648 break;
6649 case 3:
6650 gen_helper_booke206_tlbilx3(cpu_env, t0);
6651 break;
6652 default:
6653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6654 break;
6655 }
6656
6657 tcg_temp_free(t0);
6658 #endif
6659 }
6660
6661
6662 /* wrtee */
6663 static void gen_wrtee(DisasContext *ctx)
6664 {
6665 #if defined(CONFIG_USER_ONLY)
6666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6667 #else
6668 TCGv t0;
6669 if (unlikely(ctx->pr)) {
6670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6671 return;
6672 }
6673 t0 = tcg_temp_new();
6674 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6675 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6676 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6677 tcg_temp_free(t0);
6678 /* Stop translation to have a chance to raise an exception
6679 * if we just set msr_ee to 1
6680 */
6681 gen_stop_exception(ctx);
6682 #endif
6683 }
6684
6685 /* wrteei */
6686 static void gen_wrteei(DisasContext *ctx)
6687 {
6688 #if defined(CONFIG_USER_ONLY)
6689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6690 #else
6691 if (unlikely(ctx->pr)) {
6692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6693 return;
6694 }
6695 if (ctx->opcode & 0x00008000) {
6696 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6697 /* Stop translation to have a chance to raise an exception */
6698 gen_stop_exception(ctx);
6699 } else {
6700 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6701 }
6702 #endif
6703 }
6704
6705 /* PowerPC 440 specific instructions */
6706
6707 /* dlmzb */
6708 static void gen_dlmzb(DisasContext *ctx)
6709 {
6710 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6711 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6712 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6713 tcg_temp_free_i32(t0);
6714 }
6715
6716 /* mbar replaces eieio on 440 */
6717 static void gen_mbar(DisasContext *ctx)
6718 {
6719 /* interpreted as no-op */
6720 }
6721
6722 /* msync replaces sync on 440 */
6723 static void gen_msync_4xx(DisasContext *ctx)
6724 {
6725 /* interpreted as no-op */
6726 }
6727
6728 /* icbt */
6729 static void gen_icbt_440(DisasContext *ctx)
6730 {
6731 /* interpreted as no-op */
6732 /* XXX: specification say this is treated as a load by the MMU
6733 * but does not generate any exception
6734 */
6735 }
6736
6737 /* Embedded.Processor Control */
6738
6739 static void gen_msgclr(DisasContext *ctx)
6740 {
6741 #if defined(CONFIG_USER_ONLY)
6742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6743 #else
6744 if (unlikely(ctx->pr)) {
6745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6746 return;
6747 }
6748
6749 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6750 #endif
6751 }
6752
6753 static void gen_msgsnd(DisasContext *ctx)
6754 {
6755 #if defined(CONFIG_USER_ONLY)
6756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6757 #else
6758 if (unlikely(ctx->pr)) {
6759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6760 return;
6761 }
6762
6763 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6764 #endif
6765 }
6766
6767 /*** Altivec vector extension ***/
6768 /* Altivec registers moves */
6769
6770 static inline TCGv_ptr gen_avr_ptr(int reg)
6771 {
6772 TCGv_ptr r = tcg_temp_new_ptr();
6773 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6774 return r;
6775 }
6776
6777 #define GEN_VR_LDX(name, opc2, opc3) \
6778 static void glue(gen_, name)(DisasContext *ctx) \
6779 { \
6780 TCGv EA; \
6781 if (unlikely(!ctx->altivec_enabled)) { \
6782 gen_exception(ctx, POWERPC_EXCP_VPU); \
6783 return; \
6784 } \
6785 gen_set_access_type(ctx, ACCESS_INT); \
6786 EA = tcg_temp_new(); \
6787 gen_addr_reg_index(ctx, EA); \
6788 tcg_gen_andi_tl(EA, EA, ~0xf); \
6789 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6790 64-bit byteswap already. */ \
6791 if (ctx->le_mode) { \
6792 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6793 tcg_gen_addi_tl(EA, EA, 8); \
6794 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6795 } else { \
6796 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6797 tcg_gen_addi_tl(EA, EA, 8); \
6798 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6799 } \
6800 tcg_temp_free(EA); \
6801 }
6802
6803 #define GEN_VR_STX(name, opc2, opc3) \
6804 static void gen_st##name(DisasContext *ctx) \
6805 { \
6806 TCGv EA; \
6807 if (unlikely(!ctx->altivec_enabled)) { \
6808 gen_exception(ctx, POWERPC_EXCP_VPU); \
6809 return; \
6810 } \
6811 gen_set_access_type(ctx, ACCESS_INT); \
6812 EA = tcg_temp_new(); \
6813 gen_addr_reg_index(ctx, EA); \
6814 tcg_gen_andi_tl(EA, EA, ~0xf); \
6815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6816 64-bit byteswap already. */ \
6817 if (ctx->le_mode) { \
6818 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6819 tcg_gen_addi_tl(EA, EA, 8); \
6820 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6821 } else { \
6822 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6823 tcg_gen_addi_tl(EA, EA, 8); \
6824 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6825 } \
6826 tcg_temp_free(EA); \
6827 }
6828
6829 #define GEN_VR_LVE(name, opc2, opc3, size) \
6830 static void gen_lve##name(DisasContext *ctx) \
6831 { \
6832 TCGv EA; \
6833 TCGv_ptr rs; \
6834 if (unlikely(!ctx->altivec_enabled)) { \
6835 gen_exception(ctx, POWERPC_EXCP_VPU); \
6836 return; \
6837 } \
6838 gen_set_access_type(ctx, ACCESS_INT); \
6839 EA = tcg_temp_new(); \
6840 gen_addr_reg_index(ctx, EA); \
6841 if (size > 1) { \
6842 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6843 } \
6844 rs = gen_avr_ptr(rS(ctx->opcode)); \
6845 gen_helper_lve##name(cpu_env, rs, EA); \
6846 tcg_temp_free(EA); \
6847 tcg_temp_free_ptr(rs); \
6848 }
6849
6850 #define GEN_VR_STVE(name, opc2, opc3, size) \
6851 static void gen_stve##name(DisasContext *ctx) \
6852 { \
6853 TCGv EA; \
6854 TCGv_ptr rs; \
6855 if (unlikely(!ctx->altivec_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_VPU); \
6857 return; \
6858 } \
6859 gen_set_access_type(ctx, ACCESS_INT); \
6860 EA = tcg_temp_new(); \
6861 gen_addr_reg_index(ctx, EA); \
6862 if (size > 1) { \
6863 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6864 } \
6865 rs = gen_avr_ptr(rS(ctx->opcode)); \
6866 gen_helper_stve##name(cpu_env, rs, EA); \
6867 tcg_temp_free(EA); \
6868 tcg_temp_free_ptr(rs); \
6869 }
6870
6871 GEN_VR_LDX(lvx, 0x07, 0x03);
6872 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6873 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6874
6875 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6876 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6877 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6878
6879 GEN_VR_STX(svx, 0x07, 0x07);
6880 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6881 GEN_VR_STX(svxl, 0x07, 0x0F);
6882
6883 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6884 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6885 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6886
6887 static void gen_lvsl(DisasContext *ctx)
6888 {
6889 TCGv_ptr rd;
6890 TCGv EA;
6891 if (unlikely(!ctx->altivec_enabled)) {
6892 gen_exception(ctx, POWERPC_EXCP_VPU);
6893 return;
6894 }
6895 EA = tcg_temp_new();
6896 gen_addr_reg_index(ctx, EA);
6897 rd = gen_avr_ptr(rD(ctx->opcode));
6898 gen_helper_lvsl(rd, EA);
6899 tcg_temp_free(EA);
6900 tcg_temp_free_ptr(rd);
6901 }
6902
6903 static void gen_lvsr(DisasContext *ctx)
6904 {
6905 TCGv_ptr rd;
6906 TCGv EA;
6907 if (unlikely(!ctx->altivec_enabled)) {
6908 gen_exception(ctx, POWERPC_EXCP_VPU);
6909 return;
6910 }
6911 EA = tcg_temp_new();
6912 gen_addr_reg_index(ctx, EA);
6913 rd = gen_avr_ptr(rD(ctx->opcode));
6914 gen_helper_lvsr(rd, EA);
6915 tcg_temp_free(EA);
6916 tcg_temp_free_ptr(rd);
6917 }
6918
6919 static void gen_mfvscr(DisasContext *ctx)
6920 {
6921 TCGv_i32 t;
6922 if (unlikely(!ctx->altivec_enabled)) {
6923 gen_exception(ctx, POWERPC_EXCP_VPU);
6924 return;
6925 }
6926 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6927 t = tcg_temp_new_i32();
6928 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6929 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6930 tcg_temp_free_i32(t);
6931 }
6932
6933 static void gen_mtvscr(DisasContext *ctx)
6934 {
6935 TCGv_ptr p;
6936 if (unlikely(!ctx->altivec_enabled)) {
6937 gen_exception(ctx, POWERPC_EXCP_VPU);
6938 return;
6939 }
6940 p = gen_avr_ptr(rB(ctx->opcode));
6941 gen_helper_mtvscr(cpu_env, p);
6942 tcg_temp_free_ptr(p);
6943 }
6944
6945 /* Logical operations */
6946 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6947 static void glue(gen_, name)(DisasContext *ctx) \
6948 { \
6949 if (unlikely(!ctx->altivec_enabled)) { \
6950 gen_exception(ctx, POWERPC_EXCP_VPU); \
6951 return; \
6952 } \
6953 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6954 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6955 }
6956
6957 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6958 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6959 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6960 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6961 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6962 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6963 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6964 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6965
6966 #define GEN_VXFORM(name, opc2, opc3) \
6967 static void glue(gen_, name)(DisasContext *ctx) \
6968 { \
6969 TCGv_ptr ra, rb, rd; \
6970 if (unlikely(!ctx->altivec_enabled)) { \
6971 gen_exception(ctx, POWERPC_EXCP_VPU); \
6972 return; \
6973 } \
6974 ra = gen_avr_ptr(rA(ctx->opcode)); \
6975 rb = gen_avr_ptr(rB(ctx->opcode)); \
6976 rd = gen_avr_ptr(rD(ctx->opcode)); \
6977 gen_helper_##name (rd, ra, rb); \
6978 tcg_temp_free_ptr(ra); \
6979 tcg_temp_free_ptr(rb); \
6980 tcg_temp_free_ptr(rd); \
6981 }
6982
6983 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6984 static void glue(gen_, name)(DisasContext *ctx) \
6985 { \
6986 TCGv_ptr ra, rb, rd; \
6987 if (unlikely(!ctx->altivec_enabled)) { \
6988 gen_exception(ctx, POWERPC_EXCP_VPU); \
6989 return; \
6990 } \
6991 ra = gen_avr_ptr(rA(ctx->opcode)); \
6992 rb = gen_avr_ptr(rB(ctx->opcode)); \
6993 rd = gen_avr_ptr(rD(ctx->opcode)); \
6994 gen_helper_##name(cpu_env, rd, ra, rb); \
6995 tcg_temp_free_ptr(ra); \
6996 tcg_temp_free_ptr(rb); \
6997 tcg_temp_free_ptr(rd); \
6998 }
6999
7000 #define GEN_VXFORM3(name, opc2, opc3) \
7001 static void glue(gen_, name)(DisasContext *ctx) \
7002 { \
7003 TCGv_ptr ra, rb, rc, rd; \
7004 if (unlikely(!ctx->altivec_enabled)) { \
7005 gen_exception(ctx, POWERPC_EXCP_VPU); \
7006 return; \
7007 } \
7008 ra = gen_avr_ptr(rA(ctx->opcode)); \
7009 rb = gen_avr_ptr(rB(ctx->opcode)); \
7010 rc = gen_avr_ptr(rC(ctx->opcode)); \
7011 rd = gen_avr_ptr(rD(ctx->opcode)); \
7012 gen_helper_##name(rd, ra, rb, rc); \
7013 tcg_temp_free_ptr(ra); \
7014 tcg_temp_free_ptr(rb); \
7015 tcg_temp_free_ptr(rc); \
7016 tcg_temp_free_ptr(rd); \
7017 }
7018
7019 /*
7020 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7021 * an opcode bit. In general, these pairs come from different
7022 * versions of the ISA, so we must also support a pair of flags for
7023 * each instruction.
7024 */
7025 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7026 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7027 { \
7028 if ((Rc(ctx->opcode) == 0) && \
7029 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7030 gen_##name0(ctx); \
7031 } else if ((Rc(ctx->opcode) == 1) && \
7032 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7033 gen_##name1(ctx); \
7034 } else { \
7035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7036 } \
7037 }
7038
7039 GEN_VXFORM(vaddubm, 0, 0);
7040 GEN_VXFORM(vadduhm, 0, 1);
7041 GEN_VXFORM(vadduwm, 0, 2);
7042 GEN_VXFORM(vaddudm, 0, 3);
7043 GEN_VXFORM(vsububm, 0, 16);
7044 GEN_VXFORM(vsubuhm, 0, 17);
7045 GEN_VXFORM(vsubuwm, 0, 18);
7046 GEN_VXFORM(vsubudm, 0, 19);
7047 GEN_VXFORM(vmaxub, 1, 0);
7048 GEN_VXFORM(vmaxuh, 1, 1);
7049 GEN_VXFORM(vmaxuw, 1, 2);
7050 GEN_VXFORM(vmaxud, 1, 3);
7051 GEN_VXFORM(vmaxsb, 1, 4);
7052 GEN_VXFORM(vmaxsh, 1, 5);
7053 GEN_VXFORM(vmaxsw, 1, 6);
7054 GEN_VXFORM(vmaxsd, 1, 7);
7055 GEN_VXFORM(vminub, 1, 8);
7056 GEN_VXFORM(vminuh, 1, 9);
7057 GEN_VXFORM(vminuw, 1, 10);
7058 GEN_VXFORM(vminud, 1, 11);
7059 GEN_VXFORM(vminsb, 1, 12);
7060 GEN_VXFORM(vminsh, 1, 13);
7061 GEN_VXFORM(vminsw, 1, 14);
7062 GEN_VXFORM(vminsd, 1, 15);
7063 GEN_VXFORM(vavgub, 1, 16);
7064 GEN_VXFORM(vavguh, 1, 17);
7065 GEN_VXFORM(vavguw, 1, 18);
7066 GEN_VXFORM(vavgsb, 1, 20);
7067 GEN_VXFORM(vavgsh, 1, 21);
7068 GEN_VXFORM(vavgsw, 1, 22);
7069 GEN_VXFORM(vmrghb, 6, 0);
7070 GEN_VXFORM(vmrghh, 6, 1);
7071 GEN_VXFORM(vmrghw, 6, 2);
7072 GEN_VXFORM(vmrglb, 6, 4);
7073 GEN_VXFORM(vmrglh, 6, 5);
7074 GEN_VXFORM(vmrglw, 6, 6);
7075
7076 static void gen_vmrgew(DisasContext *ctx)
7077 {
7078 TCGv_i64 tmp;
7079 int VT, VA, VB;
7080 if (unlikely(!ctx->altivec_enabled)) {
7081 gen_exception(ctx, POWERPC_EXCP_VPU);
7082 return;
7083 }
7084 VT = rD(ctx->opcode);
7085 VA = rA(ctx->opcode);
7086 VB = rB(ctx->opcode);
7087 tmp = tcg_temp_new_i64();
7088 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7089 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7090 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7091 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7092 tcg_temp_free_i64(tmp);
7093 }
7094
7095 static void gen_vmrgow(DisasContext *ctx)
7096 {
7097 int VT, VA, VB;
7098 if (unlikely(!ctx->altivec_enabled)) {
7099 gen_exception(ctx, POWERPC_EXCP_VPU);
7100 return;
7101 }
7102 VT = rD(ctx->opcode);
7103 VA = rA(ctx->opcode);
7104 VB = rB(ctx->opcode);
7105
7106 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7107 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7108 }
7109
7110 GEN_VXFORM(vmuloub, 4, 0);
7111 GEN_VXFORM(vmulouh, 4, 1);
7112 GEN_VXFORM(vmulouw, 4, 2);
7113 GEN_VXFORM(vmuluwm, 4, 2);
7114 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7115 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7116 GEN_VXFORM(vmulosb, 4, 4);
7117 GEN_VXFORM(vmulosh, 4, 5);
7118 GEN_VXFORM(vmulosw, 4, 6);
7119 GEN_VXFORM(vmuleub, 4, 8);
7120 GEN_VXFORM(vmuleuh, 4, 9);
7121 GEN_VXFORM(vmuleuw, 4, 10);
7122 GEN_VXFORM(vmulesb, 4, 12);
7123 GEN_VXFORM(vmulesh, 4, 13);
7124 GEN_VXFORM(vmulesw, 4, 14);
7125 GEN_VXFORM(vslb, 2, 4);
7126 GEN_VXFORM(vslh, 2, 5);
7127 GEN_VXFORM(vslw, 2, 6);
7128 GEN_VXFORM(vsld, 2, 23);
7129 GEN_VXFORM(vsrb, 2, 8);
7130 GEN_VXFORM(vsrh, 2, 9);
7131 GEN_VXFORM(vsrw, 2, 10);
7132 GEN_VXFORM(vsrd, 2, 27);
7133 GEN_VXFORM(vsrab, 2, 12);
7134 GEN_VXFORM(vsrah, 2, 13);
7135 GEN_VXFORM(vsraw, 2, 14);
7136 GEN_VXFORM(vsrad, 2, 15);
7137 GEN_VXFORM(vslo, 6, 16);
7138 GEN_VXFORM(vsro, 6, 17);
7139 GEN_VXFORM(vaddcuw, 0, 6);
7140 GEN_VXFORM(vsubcuw, 0, 22);
7141 GEN_VXFORM_ENV(vaddubs, 0, 8);
7142 GEN_VXFORM_ENV(vadduhs, 0, 9);
7143 GEN_VXFORM_ENV(vadduws, 0, 10);
7144 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7145 GEN_VXFORM_ENV(vaddshs, 0, 13);
7146 GEN_VXFORM_ENV(vaddsws, 0, 14);
7147 GEN_VXFORM_ENV(vsububs, 0, 24);
7148 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7149 GEN_VXFORM_ENV(vsubuws, 0, 26);
7150 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7151 GEN_VXFORM_ENV(vsubshs, 0, 29);
7152 GEN_VXFORM_ENV(vsubsws, 0, 30);
7153 GEN_VXFORM(vadduqm, 0, 4);
7154 GEN_VXFORM(vaddcuq, 0, 5);
7155 GEN_VXFORM3(vaddeuqm, 30, 0);
7156 GEN_VXFORM3(vaddecuq, 30, 0);
7157 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7158 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7159 GEN_VXFORM(vsubuqm, 0, 20);
7160 GEN_VXFORM(vsubcuq, 0, 21);
7161 GEN_VXFORM3(vsubeuqm, 31, 0);
7162 GEN_VXFORM3(vsubecuq, 31, 0);
7163 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7164 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7165 GEN_VXFORM(vrlb, 2, 0);
7166 GEN_VXFORM(vrlh, 2, 1);
7167 GEN_VXFORM(vrlw, 2, 2);
7168 GEN_VXFORM(vrld, 2, 3);
7169 GEN_VXFORM(vsl, 2, 7);
7170 GEN_VXFORM(vsr, 2, 11);
7171 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7172 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7173 GEN_VXFORM_ENV(vpkudum, 7, 17);
7174 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7175 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7176 GEN_VXFORM_ENV(vpkudus, 7, 19);
7177 GEN_VXFORM_ENV(vpkshus, 7, 4);
7178 GEN_VXFORM_ENV(vpkswus, 7, 5);
7179 GEN_VXFORM_ENV(vpksdus, 7, 21);
7180 GEN_VXFORM_ENV(vpkshss, 7, 6);
7181 GEN_VXFORM_ENV(vpkswss, 7, 7);
7182 GEN_VXFORM_ENV(vpksdss, 7, 23);
7183 GEN_VXFORM(vpkpx, 7, 12);
7184 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7185 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7186 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7187 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7188 GEN_VXFORM_ENV(vsumsws, 4, 30);
7189 GEN_VXFORM_ENV(vaddfp, 5, 0);
7190 GEN_VXFORM_ENV(vsubfp, 5, 1);
7191 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7192 GEN_VXFORM_ENV(vminfp, 5, 17);
7193
7194 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7195 static void glue(gen_, name)(DisasContext *ctx) \
7196 { \
7197 TCGv_ptr ra, rb, rd; \
7198 if (unlikely(!ctx->altivec_enabled)) { \
7199 gen_exception(ctx, POWERPC_EXCP_VPU); \
7200 return; \
7201 } \
7202 ra = gen_avr_ptr(rA(ctx->opcode)); \
7203 rb = gen_avr_ptr(rB(ctx->opcode)); \
7204 rd = gen_avr_ptr(rD(ctx->opcode)); \
7205 gen_helper_##opname(cpu_env, rd, ra, rb); \
7206 tcg_temp_free_ptr(ra); \
7207 tcg_temp_free_ptr(rb); \
7208 tcg_temp_free_ptr(rd); \
7209 }
7210
7211 #define GEN_VXRFORM(name, opc2, opc3) \
7212 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7213 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7214
7215 /*
7216 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7217 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7218 * come from different versions of the ISA, so we must also support a
7219 * pair of flags for each instruction.
7220 */
7221 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7222 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7223 { \
7224 if ((Rc(ctx->opcode) == 0) && \
7225 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7226 if (Rc21(ctx->opcode) == 0) { \
7227 gen_##name0(ctx); \
7228 } else { \
7229 gen_##name0##_(ctx); \
7230 } \
7231 } else if ((Rc(ctx->opcode) == 1) && \
7232 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7233 if (Rc21(ctx->opcode) == 0) { \
7234 gen_##name1(ctx); \
7235 } else { \
7236 gen_##name1##_(ctx); \
7237 } \
7238 } else { \
7239 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7240 } \
7241 }
7242
7243 GEN_VXRFORM(vcmpequb, 3, 0)
7244 GEN_VXRFORM(vcmpequh, 3, 1)
7245 GEN_VXRFORM(vcmpequw, 3, 2)
7246 GEN_VXRFORM(vcmpequd, 3, 3)
7247 GEN_VXRFORM(vcmpgtsb, 3, 12)
7248 GEN_VXRFORM(vcmpgtsh, 3, 13)
7249 GEN_VXRFORM(vcmpgtsw, 3, 14)
7250 GEN_VXRFORM(vcmpgtsd, 3, 15)
7251 GEN_VXRFORM(vcmpgtub, 3, 8)
7252 GEN_VXRFORM(vcmpgtuh, 3, 9)
7253 GEN_VXRFORM(vcmpgtuw, 3, 10)
7254 GEN_VXRFORM(vcmpgtud, 3, 11)
7255 GEN_VXRFORM(vcmpeqfp, 3, 3)
7256 GEN_VXRFORM(vcmpgefp, 3, 7)
7257 GEN_VXRFORM(vcmpgtfp, 3, 11)
7258 GEN_VXRFORM(vcmpbfp, 3, 15)
7259
7260 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7261 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7262 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7263 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7264 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7265 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7266
7267 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7268 static void glue(gen_, name)(DisasContext *ctx) \
7269 { \
7270 TCGv_ptr rd; \
7271 TCGv_i32 simm; \
7272 if (unlikely(!ctx->altivec_enabled)) { \
7273 gen_exception(ctx, POWERPC_EXCP_VPU); \
7274 return; \
7275 } \
7276 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7277 rd = gen_avr_ptr(rD(ctx->opcode)); \
7278 gen_helper_##name (rd, simm); \
7279 tcg_temp_free_i32(simm); \
7280 tcg_temp_free_ptr(rd); \
7281 }
7282
7283 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7284 GEN_VXFORM_SIMM(vspltish, 6, 13);
7285 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7286
7287 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7288 static void glue(gen_, name)(DisasContext *ctx) \
7289 { \
7290 TCGv_ptr rb, rd; \
7291 if (unlikely(!ctx->altivec_enabled)) { \
7292 gen_exception(ctx, POWERPC_EXCP_VPU); \
7293 return; \
7294 } \
7295 rb = gen_avr_ptr(rB(ctx->opcode)); \
7296 rd = gen_avr_ptr(rD(ctx->opcode)); \
7297 gen_helper_##name (rd, rb); \
7298 tcg_temp_free_ptr(rb); \
7299 tcg_temp_free_ptr(rd); \
7300 }
7301
7302 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7303 static void glue(gen_, name)(DisasContext *ctx) \
7304 { \
7305 TCGv_ptr rb, rd; \
7306 \
7307 if (unlikely(!ctx->altivec_enabled)) { \
7308 gen_exception(ctx, POWERPC_EXCP_VPU); \
7309 return; \
7310 } \
7311 rb = gen_avr_ptr(rB(ctx->opcode)); \
7312 rd = gen_avr_ptr(rD(ctx->opcode)); \
7313 gen_helper_##name(cpu_env, rd, rb); \
7314 tcg_temp_free_ptr(rb); \
7315 tcg_temp_free_ptr(rd); \
7316 }
7317
7318 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7319 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7320 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7321 GEN_VXFORM_NOA(vupklsb, 7, 10);
7322 GEN_VXFORM_NOA(vupklsh, 7, 11);
7323 GEN_VXFORM_NOA(vupklsw, 7, 27);
7324 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7325 GEN_VXFORM_NOA(vupklpx, 7, 15);
7326 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7327 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7328 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7329 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7330 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7331 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7332 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7333 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7334
7335 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7336 static void glue(gen_, name)(DisasContext *ctx) \
7337 { \
7338 TCGv_ptr rd; \
7339 TCGv_i32 simm; \
7340 if (unlikely(!ctx->altivec_enabled)) { \
7341 gen_exception(ctx, POWERPC_EXCP_VPU); \
7342 return; \
7343 } \
7344 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7345 rd = gen_avr_ptr(rD(ctx->opcode)); \
7346 gen_helper_##name (rd, simm); \
7347 tcg_temp_free_i32(simm); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
7351 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7352 static void glue(gen_, name)(DisasContext *ctx) \
7353 { \
7354 TCGv_ptr rb, rd; \
7355 TCGv_i32 uimm; \
7356 if (unlikely(!ctx->altivec_enabled)) { \
7357 gen_exception(ctx, POWERPC_EXCP_VPU); \
7358 return; \
7359 } \
7360 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7361 rb = gen_avr_ptr(rB(ctx->opcode)); \
7362 rd = gen_avr_ptr(rD(ctx->opcode)); \
7363 gen_helper_##name (rd, rb, uimm); \
7364 tcg_temp_free_i32(uimm); \
7365 tcg_temp_free_ptr(rb); \
7366 tcg_temp_free_ptr(rd); \
7367 }
7368
7369 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7370 static void glue(gen_, name)(DisasContext *ctx) \
7371 { \
7372 TCGv_ptr rb, rd; \
7373 TCGv_i32 uimm; \
7374 \
7375 if (unlikely(!ctx->altivec_enabled)) { \
7376 gen_exception(ctx, POWERPC_EXCP_VPU); \
7377 return; \
7378 } \
7379 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7380 rb = gen_avr_ptr(rB(ctx->opcode)); \
7381 rd = gen_avr_ptr(rD(ctx->opcode)); \
7382 gen_helper_##name(cpu_env, rd, rb, uimm); \
7383 tcg_temp_free_i32(uimm); \
7384 tcg_temp_free_ptr(rb); \
7385 tcg_temp_free_ptr(rd); \
7386 }
7387
7388 GEN_VXFORM_UIMM(vspltb, 6, 8);
7389 GEN_VXFORM_UIMM(vsplth, 6, 9);
7390 GEN_VXFORM_UIMM(vspltw, 6, 10);
7391 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7392 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7393 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7394 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7395
7396 static void gen_vsldoi(DisasContext *ctx)
7397 {
7398 TCGv_ptr ra, rb, rd;
7399 TCGv_i32 sh;
7400 if (unlikely(!ctx->altivec_enabled)) {
7401 gen_exception(ctx, POWERPC_EXCP_VPU);
7402 return;
7403 }
7404 ra = gen_avr_ptr(rA(ctx->opcode));
7405 rb = gen_avr_ptr(rB(ctx->opcode));
7406 rd = gen_avr_ptr(rD(ctx->opcode));
7407 sh = tcg_const_i32(VSH(ctx->opcode));
7408 gen_helper_vsldoi (rd, ra, rb, sh);
7409 tcg_temp_free_ptr(ra);
7410 tcg_temp_free_ptr(rb);
7411 tcg_temp_free_ptr(rd);
7412 tcg_temp_free_i32(sh);
7413 }
7414
7415 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7416 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7417 { \
7418 TCGv_ptr ra, rb, rc, rd; \
7419 if (unlikely(!ctx->altivec_enabled)) { \
7420 gen_exception(ctx, POWERPC_EXCP_VPU); \
7421 return; \
7422 } \
7423 ra = gen_avr_ptr(rA(ctx->opcode)); \
7424 rb = gen_avr_ptr(rB(ctx->opcode)); \
7425 rc = gen_avr_ptr(rC(ctx->opcode)); \
7426 rd = gen_avr_ptr(rD(ctx->opcode)); \
7427 if (Rc(ctx->opcode)) { \
7428 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7429 } else { \
7430 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7431 } \
7432 tcg_temp_free_ptr(ra); \
7433 tcg_temp_free_ptr(rb); \
7434 tcg_temp_free_ptr(rc); \
7435 tcg_temp_free_ptr(rd); \
7436 }
7437
7438 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7439
7440 static void gen_vmladduhm(DisasContext *ctx)
7441 {
7442 TCGv_ptr ra, rb, rc, rd;
7443 if (unlikely(!ctx->altivec_enabled)) {
7444 gen_exception(ctx, POWERPC_EXCP_VPU);
7445 return;
7446 }
7447 ra = gen_avr_ptr(rA(ctx->opcode));
7448 rb = gen_avr_ptr(rB(ctx->opcode));
7449 rc = gen_avr_ptr(rC(ctx->opcode));
7450 rd = gen_avr_ptr(rD(ctx->opcode));
7451 gen_helper_vmladduhm(rd, ra, rb, rc);
7452 tcg_temp_free_ptr(ra);
7453 tcg_temp_free_ptr(rb);
7454 tcg_temp_free_ptr(rc);
7455 tcg_temp_free_ptr(rd);
7456 }
7457
7458 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7459 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7460 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7461 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7462 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7463
7464 GEN_VXFORM_NOA(vclzb, 1, 28)
7465 GEN_VXFORM_NOA(vclzh, 1, 29)
7466 GEN_VXFORM_NOA(vclzw, 1, 30)
7467 GEN_VXFORM_NOA(vclzd, 1, 31)
7468 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7469 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7470 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7471 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7472 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7473 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7474 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7475 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7476 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7477 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7478 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7479 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7480 GEN_VXFORM(vbpermq, 6, 21);
7481 GEN_VXFORM_NOA(vgbbd, 6, 20);
7482 GEN_VXFORM(vpmsumb, 4, 16)
7483 GEN_VXFORM(vpmsumh, 4, 17)
7484 GEN_VXFORM(vpmsumw, 4, 18)
7485 GEN_VXFORM(vpmsumd, 4, 19)
7486
7487 #define GEN_BCD(op) \
7488 static void gen_##op(DisasContext *ctx) \
7489 { \
7490 TCGv_ptr ra, rb, rd; \
7491 TCGv_i32 ps; \
7492 \
7493 if (unlikely(!ctx->altivec_enabled)) { \
7494 gen_exception(ctx, POWERPC_EXCP_VPU); \
7495 return; \
7496 } \
7497 \
7498 ra = gen_avr_ptr(rA(ctx->opcode)); \
7499 rb = gen_avr_ptr(rB(ctx->opcode)); \
7500 rd = gen_avr_ptr(rD(ctx->opcode)); \
7501 \
7502 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7503 \
7504 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7505 \
7506 tcg_temp_free_ptr(ra); \
7507 tcg_temp_free_ptr(rb); \
7508 tcg_temp_free_ptr(rd); \
7509 tcg_temp_free_i32(ps); \
7510 }
7511
7512 GEN_BCD(bcdadd)
7513 GEN_BCD(bcdsub)
7514
7515 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7516 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7517 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7518 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7519 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7520 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7521 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7522 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7523
7524 static void gen_vsbox(DisasContext *ctx)
7525 {
7526 TCGv_ptr ra, rd;
7527 if (unlikely(!ctx->altivec_enabled)) {
7528 gen_exception(ctx, POWERPC_EXCP_VPU);
7529 return;
7530 }
7531 ra = gen_avr_ptr(rA(ctx->opcode));
7532 rd = gen_avr_ptr(rD(ctx->opcode));
7533 gen_helper_vsbox(rd, ra);
7534 tcg_temp_free_ptr(ra);
7535 tcg_temp_free_ptr(rd);
7536 }
7537
7538 GEN_VXFORM(vcipher, 4, 20)
7539 GEN_VXFORM(vcipherlast, 4, 20)
7540 GEN_VXFORM(vncipher, 4, 21)
7541 GEN_VXFORM(vncipherlast, 4, 21)
7542
7543 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7544 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7545 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7546 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7547
7548 #define VSHASIGMA(op) \
7549 static void gen_##op(DisasContext *ctx) \
7550 { \
7551 TCGv_ptr ra, rd; \
7552 TCGv_i32 st_six; \
7553 if (unlikely(!ctx->altivec_enabled)) { \
7554 gen_exception(ctx, POWERPC_EXCP_VPU); \
7555 return; \
7556 } \
7557 ra = gen_avr_ptr(rA(ctx->opcode)); \
7558 rd = gen_avr_ptr(rD(ctx->opcode)); \
7559 st_six = tcg_const_i32(rB(ctx->opcode)); \
7560 gen_helper_##op(rd, ra, st_six); \
7561 tcg_temp_free_ptr(ra); \
7562 tcg_temp_free_ptr(rd); \
7563 tcg_temp_free_i32(st_six); \
7564 }
7565
7566 VSHASIGMA(vshasigmaw)
7567 VSHASIGMA(vshasigmad)
7568
7569 GEN_VXFORM3(vpermxor, 22, 0xFF)
7570 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7571 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7572
7573 /*** VSX extension ***/
7574
7575 static inline TCGv_i64 cpu_vsrh(int n)
7576 {
7577 if (n < 32) {
7578 return cpu_fpr[n];
7579 } else {
7580 return cpu_avrh[n-32];
7581 }
7582 }
7583
7584 static inline TCGv_i64 cpu_vsrl(int n)
7585 {
7586 if (n < 32) {
7587 return cpu_vsr[n];
7588 } else {
7589 return cpu_avrl[n-32];
7590 }
7591 }
7592
7593 #define VSX_LOAD_SCALAR(name, operation) \
7594 static void gen_##name(DisasContext *ctx) \
7595 { \
7596 TCGv EA; \
7597 if (unlikely(!ctx->vsx_enabled)) { \
7598 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7599 return; \
7600 } \
7601 gen_set_access_type(ctx, ACCESS_INT); \
7602 EA = tcg_temp_new(); \
7603 gen_addr_reg_index(ctx, EA); \
7604 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7605 /* NOTE: cpu_vsrl is undefined */ \
7606 tcg_temp_free(EA); \
7607 }
7608
7609 VSX_LOAD_SCALAR(lxsdx, ld64)
7610 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7611 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7612 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7613
7614 static void gen_lxvd2x(DisasContext *ctx)
7615 {
7616 TCGv EA;
7617 if (unlikely(!ctx->vsx_enabled)) {
7618 gen_exception(ctx, POWERPC_EXCP_VSXU);
7619 return;
7620 }
7621 gen_set_access_type(ctx, ACCESS_INT);
7622 EA = tcg_temp_new();
7623 gen_addr_reg_index(ctx, EA);
7624 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7625 tcg_gen_addi_tl(EA, EA, 8);
7626 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7627 tcg_temp_free(EA);
7628 }
7629
7630 static void gen_lxvdsx(DisasContext *ctx)
7631 {
7632 TCGv EA;
7633 if (unlikely(!ctx->vsx_enabled)) {
7634 gen_exception(ctx, POWERPC_EXCP_VSXU);
7635 return;
7636 }
7637 gen_set_access_type(ctx, ACCESS_INT);
7638 EA = tcg_temp_new();
7639 gen_addr_reg_index(ctx, EA);
7640 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7641 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7642 tcg_temp_free(EA);
7643 }
7644
7645 static void gen_lxvw4x(DisasContext *ctx)
7646 {
7647 TCGv EA;
7648 TCGv_i64 tmp;
7649 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7650 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7651 if (unlikely(!ctx->vsx_enabled)) {
7652 gen_exception(ctx, POWERPC_EXCP_VSXU);
7653 return;
7654 }
7655 gen_set_access_type(ctx, ACCESS_INT);
7656 EA = tcg_temp_new();
7657 tmp = tcg_temp_new_i64();
7658
7659 gen_addr_reg_index(ctx, EA);
7660 gen_qemu_ld32u_i64(ctx, tmp, EA);
7661 tcg_gen_addi_tl(EA, EA, 4);
7662 gen_qemu_ld32u_i64(ctx, xth, EA);
7663 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7664
7665 tcg_gen_addi_tl(EA, EA, 4);
7666 gen_qemu_ld32u_i64(ctx, tmp, EA);
7667 tcg_gen_addi_tl(EA, EA, 4);
7668 gen_qemu_ld32u_i64(ctx, xtl, EA);
7669 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7670
7671 tcg_temp_free(EA);
7672 tcg_temp_free_i64(tmp);
7673 }
7674
7675 #define VSX_STORE_SCALAR(name, operation) \
7676 static void gen_##name(DisasContext *ctx) \
7677 { \
7678 TCGv EA; \
7679 if (unlikely(!ctx->vsx_enabled)) { \
7680 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7681 return; \
7682 } \
7683 gen_set_access_type(ctx, ACCESS_INT); \
7684 EA = tcg_temp_new(); \
7685 gen_addr_reg_index(ctx, EA); \
7686 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7687 tcg_temp_free(EA); \
7688 }
7689
7690 VSX_STORE_SCALAR(stxsdx, st64)
7691 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7692 VSX_STORE_SCALAR(stxsspx, st32fs)
7693
7694 static void gen_stxvd2x(DisasContext *ctx)
7695 {
7696 TCGv EA;
7697 if (unlikely(!ctx->vsx_enabled)) {
7698 gen_exception(ctx, POWERPC_EXCP_VSXU);
7699 return;
7700 }
7701 gen_set_access_type(ctx, ACCESS_INT);
7702 EA = tcg_temp_new();
7703 gen_addr_reg_index(ctx, EA);
7704 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7705 tcg_gen_addi_tl(EA, EA, 8);
7706 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7707 tcg_temp_free(EA);
7708 }
7709
7710 static void gen_stxvw4x(DisasContext *ctx)
7711 {
7712 TCGv_i64 tmp;
7713 TCGv EA;
7714 if (unlikely(!ctx->vsx_enabled)) {
7715 gen_exception(ctx, POWERPC_EXCP_VSXU);
7716 return;
7717 }
7718 gen_set_access_type(ctx, ACCESS_INT);
7719 EA = tcg_temp_new();
7720 gen_addr_reg_index(ctx, EA);
7721 tmp = tcg_temp_new_i64();
7722
7723 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7724 gen_qemu_st32_i64(ctx, tmp, EA);
7725 tcg_gen_addi_tl(EA, EA, 4);
7726 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7727
7728 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7729 tcg_gen_addi_tl(EA, EA, 4);
7730 gen_qemu_st32_i64(ctx, tmp, EA);
7731 tcg_gen_addi_tl(EA, EA, 4);
7732 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7733
7734 tcg_temp_free(EA);
7735 tcg_temp_free_i64(tmp);
7736 }
7737
7738 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7739 static void gen_##name(DisasContext *ctx) \
7740 { \
7741 if (xS(ctx->opcode) < 32) { \
7742 if (unlikely(!ctx->fpu_enabled)) { \
7743 gen_exception(ctx, POWERPC_EXCP_FPU); \
7744 return; \
7745 } \
7746 } else { \
7747 if (unlikely(!ctx->altivec_enabled)) { \
7748 gen_exception(ctx, POWERPC_EXCP_VPU); \
7749 return; \
7750 } \
7751 } \
7752 TCGv_i64 tmp = tcg_temp_new_i64(); \
7753 tcg_gen_##tcgop1(tmp, source); \
7754 tcg_gen_##tcgop2(target, tmp); \
7755 tcg_temp_free_i64(tmp); \
7756 }
7757
7758
7759 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7760 cpu_vsrh(xS(ctx->opcode)))
7761 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7762 cpu_gpr[rA(ctx->opcode)])
7763 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7764 cpu_gpr[rA(ctx->opcode)])
7765
7766 #if defined(TARGET_PPC64)
7767 #define MV_VSRD(name, target, source) \
7768 static void gen_##name(DisasContext *ctx) \
7769 { \
7770 if (xS(ctx->opcode) < 32) { \
7771 if (unlikely(!ctx->fpu_enabled)) { \
7772 gen_exception(ctx, POWERPC_EXCP_FPU); \
7773 return; \
7774 } \
7775 } else { \
7776 if (unlikely(!ctx->altivec_enabled)) { \
7777 gen_exception(ctx, POWERPC_EXCP_VPU); \
7778 return; \
7779 } \
7780 } \
7781 tcg_gen_mov_i64(target, source); \
7782 }
7783
7784 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7785 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7786
7787 #endif
7788
7789 static void gen_xxpermdi(DisasContext *ctx)
7790 {
7791 if (unlikely(!ctx->vsx_enabled)) {
7792 gen_exception(ctx, POWERPC_EXCP_VSXU);
7793 return;
7794 }
7795
7796 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7797 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7798 TCGv_i64 xh, xl;
7799
7800 xh = tcg_temp_new_i64();
7801 xl = tcg_temp_new_i64();
7802
7803 if ((DM(ctx->opcode) & 2) == 0) {
7804 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7805 } else {
7806 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7807 }
7808 if ((DM(ctx->opcode) & 1) == 0) {
7809 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7810 } else {
7811 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7812 }
7813
7814 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7815 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7816
7817 tcg_temp_free_i64(xh);
7818 tcg_temp_free_i64(xl);
7819 } else {
7820 if ((DM(ctx->opcode) & 2) == 0) {
7821 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7822 } else {
7823 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7824 }
7825 if ((DM(ctx->opcode) & 1) == 0) {
7826 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7827 } else {
7828 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7829 }
7830 }
7831 }
7832
7833 #define OP_ABS 1
7834 #define OP_NABS 2
7835 #define OP_NEG 3
7836 #define OP_CPSGN 4
7837 #define SGN_MASK_DP 0x8000000000000000ull
7838 #define SGN_MASK_SP 0x8000000080000000ull
7839
7840 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7841 static void glue(gen_, name)(DisasContext * ctx) \
7842 { \
7843 TCGv_i64 xb, sgm; \
7844 if (unlikely(!ctx->vsx_enabled)) { \
7845 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7846 return; \
7847 } \
7848 xb = tcg_temp_new_i64(); \
7849 sgm = tcg_temp_new_i64(); \
7850 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7851 tcg_gen_movi_i64(sgm, sgn_mask); \
7852 switch (op) { \
7853 case OP_ABS: { \
7854 tcg_gen_andc_i64(xb, xb, sgm); \
7855 break; \
7856 } \
7857 case OP_NABS: { \
7858 tcg_gen_or_i64(xb, xb, sgm); \
7859 break; \
7860 } \
7861 case OP_NEG: { \
7862 tcg_gen_xor_i64(xb, xb, sgm); \
7863 break; \
7864 } \
7865 case OP_CPSGN: { \
7866 TCGv_i64 xa = tcg_temp_new_i64(); \
7867 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7868 tcg_gen_and_i64(xa, xa, sgm); \
7869 tcg_gen_andc_i64(xb, xb, sgm); \
7870 tcg_gen_or_i64(xb, xb, xa); \
7871 tcg_temp_free_i64(xa); \
7872 break; \
7873 } \
7874 } \
7875 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7876 tcg_temp_free_i64(xb); \
7877 tcg_temp_free_i64(sgm); \
7878 }
7879
7880 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7881 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7882 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7883 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7884
7885 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7886 static void glue(gen_, name)(DisasContext * ctx) \
7887 { \
7888 TCGv_i64 xbh, xbl, sgm; \
7889 if (unlikely(!ctx->vsx_enabled)) { \
7890 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7891 return; \
7892 } \
7893 xbh = tcg_temp_new_i64(); \
7894 xbl = tcg_temp_new_i64(); \
7895 sgm = tcg_temp_new_i64(); \
7896 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7897 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7898 tcg_gen_movi_i64(sgm, sgn_mask); \
7899 switch (op) { \
7900 case OP_ABS: { \
7901 tcg_gen_andc_i64(xbh, xbh, sgm); \
7902 tcg_gen_andc_i64(xbl, xbl, sgm); \
7903 break; \
7904 } \
7905 case OP_NABS: { \
7906 tcg_gen_or_i64(xbh, xbh, sgm); \
7907 tcg_gen_or_i64(xbl, xbl, sgm); \
7908 break; \
7909 } \
7910 case OP_NEG: { \
7911 tcg_gen_xor_i64(xbh, xbh, sgm); \
7912 tcg_gen_xor_i64(xbl, xbl, sgm); \
7913 break; \
7914 } \
7915 case OP_CPSGN: { \
7916 TCGv_i64 xah = tcg_temp_new_i64(); \
7917 TCGv_i64 xal = tcg_temp_new_i64(); \
7918 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7919 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7920 tcg_gen_and_i64(xah, xah, sgm); \
7921 tcg_gen_and_i64(xal, xal, sgm); \
7922 tcg_gen_andc_i64(xbh, xbh, sgm); \
7923 tcg_gen_andc_i64(xbl, xbl, sgm); \
7924 tcg_gen_or_i64(xbh, xbh, xah); \
7925 tcg_gen_or_i64(xbl, xbl, xal); \
7926 tcg_temp_free_i64(xah); \
7927 tcg_temp_free_i64(xal); \
7928 break; \
7929 } \
7930 } \
7931 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7932 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7933 tcg_temp_free_i64(xbh); \
7934 tcg_temp_free_i64(xbl); \
7935 tcg_temp_free_i64(sgm); \
7936 }
7937
7938 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7939 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7940 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7941 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7942 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7943 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7944 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7945 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7946
7947 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7948 static void gen_##name(DisasContext * ctx) \
7949 { \
7950 TCGv_i32 opc; \
7951 if (unlikely(!ctx->vsx_enabled)) { \
7952 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7953 return; \
7954 } \
7955 /* NIP cannot be restored if the memory exception comes from an helper */ \
7956 gen_update_nip(ctx, ctx->nip - 4); \
7957 opc = tcg_const_i32(ctx->opcode); \
7958 gen_helper_##name(cpu_env, opc); \
7959 tcg_temp_free_i32(opc); \
7960 }
7961
7962 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7963 static void gen_##name(DisasContext * ctx) \
7964 { \
7965 if (unlikely(!ctx->vsx_enabled)) { \
7966 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7967 return; \
7968 } \
7969 /* NIP cannot be restored if the exception comes */ \
7970 /* from a helper. */ \
7971 gen_update_nip(ctx, ctx->nip - 4); \
7972 \
7973 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7974 cpu_vsrh(xB(ctx->opcode))); \
7975 }
7976
7977 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8000 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8002 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8014
8015 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8016 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8017 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8018 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8019 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8020 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8021 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8022 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8023 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8024 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8025 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8026 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8027 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8028 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8029 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8030 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8031 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8032
8033 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8069
8070 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8106
8107 #define VSX_LOGICAL(name, tcg_op) \
8108 static void glue(gen_, name)(DisasContext * ctx) \
8109 { \
8110 if (unlikely(!ctx->vsx_enabled)) { \
8111 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8112 return; \
8113 } \
8114 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8115 cpu_vsrh(xB(ctx->opcode))); \
8116 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8117 cpu_vsrl(xB(ctx->opcode))); \
8118 }
8119
8120 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8121 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8122 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8123 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8124 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8125 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8126 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8127 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8128
8129 #define VSX_XXMRG(name, high) \
8130 static void glue(gen_, name)(DisasContext * ctx) \
8131 { \
8132 TCGv_i64 a0, a1, b0, b1; \
8133 if (unlikely(!ctx->vsx_enabled)) { \
8134 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8135 return; \
8136 } \
8137 a0 = tcg_temp_new_i64(); \
8138 a1 = tcg_temp_new_i64(); \
8139 b0 = tcg_temp_new_i64(); \
8140 b1 = tcg_temp_new_i64(); \
8141 if (high) { \
8142 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8143 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8144 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8145 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8146 } else { \
8147 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8148 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8149 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8150 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8151 } \
8152 tcg_gen_shri_i64(a0, a0, 32); \
8153 tcg_gen_shri_i64(b0, b0, 32); \
8154 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8155 b0, a0, 32, 32); \
8156 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8157 b1, a1, 32, 32); \
8158 tcg_temp_free_i64(a0); \
8159 tcg_temp_free_i64(a1); \
8160 tcg_temp_free_i64(b0); \
8161 tcg_temp_free_i64(b1); \
8162 }
8163
8164 VSX_XXMRG(xxmrghw, 1)
8165 VSX_XXMRG(xxmrglw, 0)
8166
8167 static void gen_xxsel(DisasContext * ctx)
8168 {
8169 TCGv_i64 a, b, c;
8170 if (unlikely(!ctx->vsx_enabled)) {
8171 gen_exception(ctx, POWERPC_EXCP_VSXU);
8172 return;
8173 }
8174 a = tcg_temp_new_i64();
8175 b = tcg_temp_new_i64();
8176 c = tcg_temp_new_i64();
8177
8178 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8179 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8180 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8181
8182 tcg_gen_and_i64(b, b, c);
8183 tcg_gen_andc_i64(a, a, c);
8184 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8185
8186 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8187 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8188 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8189
8190 tcg_gen_and_i64(b, b, c);
8191 tcg_gen_andc_i64(a, a, c);
8192 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8193
8194 tcg_temp_free_i64(a);
8195 tcg_temp_free_i64(b);
8196 tcg_temp_free_i64(c);
8197 }
8198
8199 static void gen_xxspltw(DisasContext *ctx)
8200 {
8201 TCGv_i64 b, b2;
8202 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8203 cpu_vsrl(xB(ctx->opcode)) :
8204 cpu_vsrh(xB(ctx->opcode));
8205
8206 if (unlikely(!ctx->vsx_enabled)) {
8207 gen_exception(ctx, POWERPC_EXCP_VSXU);
8208 return;
8209 }
8210
8211 b = tcg_temp_new_i64();
8212 b2 = tcg_temp_new_i64();
8213
8214 if (UIM(ctx->opcode) & 1) {
8215 tcg_gen_ext32u_i64(b, vsr);
8216 } else {
8217 tcg_gen_shri_i64(b, vsr, 32);
8218 }
8219
8220 tcg_gen_shli_i64(b2, b, 32);
8221 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8222 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8223
8224 tcg_temp_free_i64(b);
8225 tcg_temp_free_i64(b2);
8226 }
8227
8228 static void gen_xxsldwi(DisasContext *ctx)
8229 {
8230 TCGv_i64 xth, xtl;
8231 if (unlikely(!ctx->vsx_enabled)) {
8232 gen_exception(ctx, POWERPC_EXCP_VSXU);
8233 return;
8234 }
8235 xth = tcg_temp_new_i64();
8236 xtl = tcg_temp_new_i64();
8237
8238 switch (SHW(ctx->opcode)) {
8239 case 0: {
8240 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8241 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8242 break;
8243 }
8244 case 1: {
8245 TCGv_i64 t0 = tcg_temp_new_i64();
8246 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8247 tcg_gen_shli_i64(xth, xth, 32);
8248 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8249 tcg_gen_shri_i64(t0, t0, 32);
8250 tcg_gen_or_i64(xth, xth, t0);
8251 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8252 tcg_gen_shli_i64(xtl, xtl, 32);
8253 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8254 tcg_gen_shri_i64(t0, t0, 32);
8255 tcg_gen_or_i64(xtl, xtl, t0);
8256 tcg_temp_free_i64(t0);
8257 break;
8258 }
8259 case 2: {
8260 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8261 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8262 break;
8263 }
8264 case 3: {
8265 TCGv_i64 t0 = tcg_temp_new_i64();
8266 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8267 tcg_gen_shli_i64(xth, xth, 32);
8268 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8269 tcg_gen_shri_i64(t0, t0, 32);
8270 tcg_gen_or_i64(xth, xth, t0);
8271 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8272 tcg_gen_shli_i64(xtl, xtl, 32);
8273 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8274 tcg_gen_shri_i64(t0, t0, 32);
8275 tcg_gen_or_i64(xtl, xtl, t0);
8276 tcg_temp_free_i64(t0);
8277 break;
8278 }
8279 }
8280
8281 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8282 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8283
8284 tcg_temp_free_i64(xth);
8285 tcg_temp_free_i64(xtl);
8286 }
8287
8288 /*** Decimal Floating Point ***/
8289
8290 static inline TCGv_ptr gen_fprp_ptr(int reg)
8291 {
8292 TCGv_ptr r = tcg_temp_new_ptr();
8293 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8294 return r;
8295 }
8296
8297 #define GEN_DFP_T_A_B_Rc(name) \
8298 static void gen_##name(DisasContext *ctx) \
8299 { \
8300 TCGv_ptr rd, ra, rb; \
8301 if (unlikely(!ctx->fpu_enabled)) { \
8302 gen_exception(ctx, POWERPC_EXCP_FPU); \
8303 return; \
8304 } \
8305 gen_update_nip(ctx, ctx->nip - 4); \
8306 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8307 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8308 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8309 gen_helper_##name(cpu_env, rd, ra, rb); \
8310 if (unlikely(Rc(ctx->opcode) != 0)) { \
8311 gen_set_cr1_from_fpscr(ctx); \
8312 } \
8313 tcg_temp_free_ptr(rd); \
8314 tcg_temp_free_ptr(ra); \
8315 tcg_temp_free_ptr(rb); \
8316 }
8317
8318 #define GEN_DFP_BF_A_B(name) \
8319 static void gen_##name(DisasContext *ctx) \
8320 { \
8321 TCGv_ptr ra, rb; \
8322 if (unlikely(!ctx->fpu_enabled)) { \
8323 gen_exception(ctx, POWERPC_EXCP_FPU); \
8324 return; \
8325 } \
8326 gen_update_nip(ctx, ctx->nip - 4); \
8327 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8328 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8329 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8330 cpu_env, ra, rb); \
8331 tcg_temp_free_ptr(ra); \
8332 tcg_temp_free_ptr(rb); \
8333 }
8334
8335 #define GEN_DFP_BF_A_DCM(name) \
8336 static void gen_##name(DisasContext *ctx) \
8337 { \
8338 TCGv_ptr ra; \
8339 TCGv_i32 dcm; \
8340 if (unlikely(!ctx->fpu_enabled)) { \
8341 gen_exception(ctx, POWERPC_EXCP_FPU); \
8342 return; \
8343 } \
8344 gen_update_nip(ctx, ctx->nip - 4); \
8345 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8346 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8347 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8348 cpu_env, ra, dcm); \
8349 tcg_temp_free_ptr(ra); \
8350 tcg_temp_free_i32(dcm); \
8351 }
8352
8353 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8354 static void gen_##name(DisasContext *ctx) \
8355 { \
8356 TCGv_ptr rt, rb; \
8357 TCGv_i32 u32_1, u32_2; \
8358 if (unlikely(!ctx->fpu_enabled)) { \
8359 gen_exception(ctx, POWERPC_EXCP_FPU); \
8360 return; \
8361 } \
8362 gen_update_nip(ctx, ctx->nip - 4); \
8363 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8364 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8365 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8366 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8367 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8368 if (unlikely(Rc(ctx->opcode) != 0)) { \
8369 gen_set_cr1_from_fpscr(ctx); \
8370 } \
8371 tcg_temp_free_ptr(rt); \
8372 tcg_temp_free_ptr(rb); \
8373 tcg_temp_free_i32(u32_1); \
8374 tcg_temp_free_i32(u32_2); \
8375 }
8376
8377 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8378 static void gen_##name(DisasContext *ctx) \
8379 { \
8380 TCGv_ptr rt, ra, rb; \
8381 TCGv_i32 i32; \
8382 if (unlikely(!ctx->fpu_enabled)) { \
8383 gen_exception(ctx, POWERPC_EXCP_FPU); \
8384 return; \
8385 } \
8386 gen_update_nip(ctx, ctx->nip - 4); \
8387 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8388 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8389 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8390 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8391 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8392 if (unlikely(Rc(ctx->opcode) != 0)) { \
8393 gen_set_cr1_from_fpscr(ctx); \
8394 } \
8395 tcg_temp_free_ptr(rt); \
8396 tcg_temp_free_ptr(rb); \
8397 tcg_temp_free_ptr(ra); \
8398 tcg_temp_free_i32(i32); \
8399 }
8400
8401 #define GEN_DFP_T_B_Rc(name) \
8402 static void gen_##name(DisasContext *ctx) \
8403 { \
8404 TCGv_ptr rt, rb; \
8405 if (unlikely(!ctx->fpu_enabled)) { \
8406 gen_exception(ctx, POWERPC_EXCP_FPU); \
8407 return; \
8408 } \
8409 gen_update_nip(ctx, ctx->nip - 4); \
8410 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8411 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8412 gen_helper_##name(cpu_env, rt, rb); \
8413 if (unlikely(Rc(ctx->opcode) != 0)) { \
8414 gen_set_cr1_from_fpscr(ctx); \
8415 } \
8416 tcg_temp_free_ptr(rt); \
8417 tcg_temp_free_ptr(rb); \
8418 }
8419
8420 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8421 static void gen_##name(DisasContext *ctx) \
8422 { \
8423 TCGv_ptr rt, rs; \
8424 TCGv_i32 i32; \
8425 if (unlikely(!ctx->fpu_enabled)) { \
8426 gen_exception(ctx, POWERPC_EXCP_FPU); \
8427 return; \
8428 } \
8429 gen_update_nip(ctx, ctx->nip - 4); \
8430 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8431 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8432 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8433 gen_helper_##name(cpu_env, rt, rs, i32); \
8434 if (unlikely(Rc(ctx->opcode) != 0)) { \
8435 gen_set_cr1_from_fpscr(ctx); \
8436 } \
8437 tcg_temp_free_ptr(rt); \
8438 tcg_temp_free_ptr(rs); \
8439 tcg_temp_free_i32(i32); \
8440 }
8441
8442 GEN_DFP_T_A_B_Rc(dadd)
8443 GEN_DFP_T_A_B_Rc(daddq)
8444 GEN_DFP_T_A_B_Rc(dsub)
8445 GEN_DFP_T_A_B_Rc(dsubq)
8446 GEN_DFP_T_A_B_Rc(dmul)
8447 GEN_DFP_T_A_B_Rc(dmulq)
8448 GEN_DFP_T_A_B_Rc(ddiv)
8449 GEN_DFP_T_A_B_Rc(ddivq)
8450 GEN_DFP_BF_A_B(dcmpu)
8451 GEN_DFP_BF_A_B(dcmpuq)
8452 GEN_DFP_BF_A_B(dcmpo)
8453 GEN_DFP_BF_A_B(dcmpoq)
8454 GEN_DFP_BF_A_DCM(dtstdc)
8455 GEN_DFP_BF_A_DCM(dtstdcq)
8456 GEN_DFP_BF_A_DCM(dtstdg)
8457 GEN_DFP_BF_A_DCM(dtstdgq)
8458 GEN_DFP_BF_A_B(dtstex)
8459 GEN_DFP_BF_A_B(dtstexq)
8460 GEN_DFP_BF_A_B(dtstsf)
8461 GEN_DFP_BF_A_B(dtstsfq)
8462 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8463 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8464 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8465 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8466 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8467 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8468 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8469 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8470 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8471 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8472 GEN_DFP_T_B_Rc(dctdp)
8473 GEN_DFP_T_B_Rc(dctqpq)
8474 GEN_DFP_T_B_Rc(drsp)
8475 GEN_DFP_T_B_Rc(drdpq)
8476 GEN_DFP_T_B_Rc(dcffix)
8477 GEN_DFP_T_B_Rc(dcffixq)
8478 GEN_DFP_T_B_Rc(dctfix)
8479 GEN_DFP_T_B_Rc(dctfixq)
8480 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8481 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8482 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8483 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8484 GEN_DFP_T_B_Rc(dxex)
8485 GEN_DFP_T_B_Rc(dxexq)
8486 GEN_DFP_T_A_B_Rc(diex)
8487 GEN_DFP_T_A_B_Rc(diexq)
8488 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8489 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8490 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8491 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8492
8493 /*** SPE extension ***/
8494 /* Register moves */
8495
8496 static inline void gen_evmra(DisasContext *ctx)
8497 {
8498
8499 if (unlikely(!ctx->spe_enabled)) {
8500 gen_exception(ctx, POWERPC_EXCP_SPEU);
8501 return;
8502 }
8503
8504 TCGv_i64 tmp = tcg_temp_new_i64();
8505
8506 /* tmp := rA_lo + rA_hi << 32 */
8507 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8508
8509 /* spe_acc := tmp */
8510 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8511 tcg_temp_free_i64(tmp);
8512
8513 /* rD := rA */
8514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8515 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8516 }
8517
8518 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8519 {
8520 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8521 }
8522
8523 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8524 {
8525 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8526 }
8527
8528 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8529 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8530 { \
8531 if (Rc(ctx->opcode)) \
8532 gen_##name1(ctx); \
8533 else \
8534 gen_##name0(ctx); \
8535 }
8536
8537 /* Handler for undefined SPE opcodes */
8538 static inline void gen_speundef(DisasContext *ctx)
8539 {
8540 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8541 }
8542
8543 /* SPE logic */
8544 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8545 static inline void gen_##name(DisasContext *ctx) \
8546 { \
8547 if (unlikely(!ctx->spe_enabled)) { \
8548 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8549 return; \
8550 } \
8551 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8552 cpu_gpr[rB(ctx->opcode)]); \
8553 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8554 cpu_gprh[rB(ctx->opcode)]); \
8555 }
8556
8557 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8558 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8559 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8560 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8561 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8562 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8563 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8564 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8565
8566 /* SPE logic immediate */
8567 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8568 static inline void gen_##name(DisasContext *ctx) \
8569 { \
8570 TCGv_i32 t0; \
8571 if (unlikely(!ctx->spe_enabled)) { \
8572 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8573 return; \
8574 } \
8575 t0 = tcg_temp_new_i32(); \
8576 \
8577 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8578 tcg_opi(t0, t0, rB(ctx->opcode)); \
8579 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8580 \
8581 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8582 tcg_opi(t0, t0, rB(ctx->opcode)); \
8583 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8584 \
8585 tcg_temp_free_i32(t0); \
8586 }
8587 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8588 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8589 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8590 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8591
8592 /* SPE arithmetic */
8593 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8594 static inline void gen_##name(DisasContext *ctx) \
8595 { \
8596 TCGv_i32 t0; \
8597 if (unlikely(!ctx->spe_enabled)) { \
8598 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8599 return; \
8600 } \
8601 t0 = tcg_temp_new_i32(); \
8602 \
8603 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8604 tcg_op(t0, t0); \
8605 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8606 \
8607 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8608 tcg_op(t0, t0); \
8609 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8610 \
8611 tcg_temp_free_i32(t0); \
8612 }
8613
8614 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8615 {
8616 TCGLabel *l1 = gen_new_label();
8617 TCGLabel *l2 = gen_new_label();
8618
8619 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8620 tcg_gen_neg_i32(ret, arg1);
8621 tcg_gen_br(l2);
8622 gen_set_label(l1);
8623 tcg_gen_mov_i32(ret, arg1);
8624 gen_set_label(l2);
8625 }
8626 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8627 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8628 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8629 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8630 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8631 {
8632 tcg_gen_addi_i32(ret, arg1, 0x8000);
8633 tcg_gen_ext16u_i32(ret, ret);
8634 }
8635 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8636 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8637 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8638
8639 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8640 static inline void gen_##name(DisasContext *ctx) \
8641 { \
8642 TCGv_i32 t0, t1; \
8643 if (unlikely(!ctx->spe_enabled)) { \
8644 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8645 return; \
8646 } \
8647 t0 = tcg_temp_new_i32(); \
8648 t1 = tcg_temp_new_i32(); \
8649 \
8650 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8651 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8652 tcg_op(t0, t0, t1); \
8653 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8654 \
8655 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8656 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8657 tcg_op(t0, t0, t1); \
8658 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8659 \
8660 tcg_temp_free_i32(t0); \
8661 tcg_temp_free_i32(t1); \
8662 }
8663
8664 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8665 {
8666 TCGLabel *l1 = gen_new_label();
8667 TCGLabel *l2 = gen_new_label();
8668 TCGv_i32 t0 = tcg_temp_local_new_i32();
8669
8670 /* No error here: 6 bits are used */
8671 tcg_gen_andi_i32(t0, arg2, 0x3F);
8672 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8673 tcg_gen_shr_i32(ret, arg1, t0);
8674 tcg_gen_br(l2);
8675 gen_set_label(l1);
8676 tcg_gen_movi_i32(ret, 0);
8677 gen_set_label(l2);
8678 tcg_temp_free_i32(t0);
8679 }
8680 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8681 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8682 {
8683 TCGLabel *l1 = gen_new_label();
8684 TCGLabel *l2 = gen_new_label();
8685 TCGv_i32 t0 = tcg_temp_local_new_i32();
8686
8687 /* No error here: 6 bits are used */
8688 tcg_gen_andi_i32(t0, arg2, 0x3F);
8689 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8690 tcg_gen_sar_i32(ret, arg1, t0);
8691 tcg_gen_br(l2);
8692 gen_set_label(l1);
8693 tcg_gen_movi_i32(ret, 0);
8694 gen_set_label(l2);
8695 tcg_temp_free_i32(t0);
8696 }
8697 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8698 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8699 {
8700 TCGLabel *l1 = gen_new_label();
8701 TCGLabel *l2 = gen_new_label();
8702 TCGv_i32 t0 = tcg_temp_local_new_i32();
8703
8704 /* No error here: 6 bits are used */
8705 tcg_gen_andi_i32(t0, arg2, 0x3F);
8706 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8707 tcg_gen_shl_i32(ret, arg1, t0);
8708 tcg_gen_br(l2);
8709 gen_set_label(l1);
8710 tcg_gen_movi_i32(ret, 0);
8711 gen_set_label(l2);
8712 tcg_temp_free_i32(t0);
8713 }
8714 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8715 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8716 {
8717 TCGv_i32 t0 = tcg_temp_new_i32();
8718 tcg_gen_andi_i32(t0, arg2, 0x1F);
8719 tcg_gen_rotl_i32(ret, arg1, t0);
8720 tcg_temp_free_i32(t0);
8721 }
8722 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8723 static inline void gen_evmergehi(DisasContext *ctx)
8724 {
8725 if (unlikely(!ctx->spe_enabled)) {
8726 gen_exception(ctx, POWERPC_EXCP_SPEU);
8727 return;
8728 }
8729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8730 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8731 }
8732 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8733 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8734 {
8735 tcg_gen_sub_i32(ret, arg2, arg1);
8736 }
8737 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8738
8739 /* SPE arithmetic immediate */
8740 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8741 static inline void gen_##name(DisasContext *ctx) \
8742 { \
8743 TCGv_i32 t0; \
8744 if (unlikely(!ctx->spe_enabled)) { \
8745 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8746 return; \
8747 } \
8748 t0 = tcg_temp_new_i32(); \
8749 \
8750 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8751 tcg_op(t0, t0, rA(ctx->opcode)); \
8752 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8753 \
8754 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8755 tcg_op(t0, t0, rA(ctx->opcode)); \
8756 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8757 \
8758 tcg_temp_free_i32(t0); \
8759 }
8760 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8761 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8762
8763 /* SPE comparison */
8764 #define GEN_SPEOP_COMP(name, tcg_cond) \
8765 static inline void gen_##name(DisasContext *ctx) \
8766 { \
8767 if (unlikely(!ctx->spe_enabled)) { \
8768 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8769 return; \
8770 } \
8771 TCGLabel *l1 = gen_new_label(); \
8772 TCGLabel *l2 = gen_new_label(); \
8773 TCGLabel *l3 = gen_new_label(); \
8774 TCGLabel *l4 = gen_new_label(); \
8775 \
8776 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8777 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8778 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8779 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8780 \
8781 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8782 cpu_gpr[rB(ctx->opcode)], l1); \
8783 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8784 tcg_gen_br(l2); \
8785 gen_set_label(l1); \
8786 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8787 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8788 gen_set_label(l2); \
8789 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8790 cpu_gprh[rB(ctx->opcode)], l3); \
8791 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8792 ~(CRF_CH | CRF_CH_AND_CL)); \
8793 tcg_gen_br(l4); \
8794 gen_set_label(l3); \
8795 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8796 CRF_CH | CRF_CH_OR_CL); \
8797 gen_set_label(l4); \
8798 }
8799 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8800 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8801 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8802 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8803 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8804
8805 /* SPE misc */
8806 static inline void gen_brinc(DisasContext *ctx)
8807 {
8808 /* Note: brinc is usable even if SPE is disabled */
8809 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8810 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8811 }
8812 static inline void gen_evmergelo(DisasContext *ctx)
8813 {
8814 if (unlikely(!ctx->spe_enabled)) {
8815 gen_exception(ctx, POWERPC_EXCP_SPEU);
8816 return;
8817 }
8818 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8819 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8820 }
8821 static inline void gen_evmergehilo(DisasContext *ctx)
8822 {
8823 if (unlikely(!ctx->spe_enabled)) {
8824 gen_exception(ctx, POWERPC_EXCP_SPEU);
8825 return;
8826 }
8827 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8828 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8829 }
8830 static inline void gen_evmergelohi(DisasContext *ctx)
8831 {
8832 if (unlikely(!ctx->spe_enabled)) {
8833 gen_exception(ctx, POWERPC_EXCP_SPEU);
8834 return;
8835 }
8836 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8837 TCGv tmp = tcg_temp_new();
8838 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8840 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8841 tcg_temp_free(tmp);
8842 } else {
8843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8844 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8845 }
8846 }
8847 static inline void gen_evsplati(DisasContext *ctx)
8848 {
8849 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8850
8851 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8852 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8853 }
8854 static inline void gen_evsplatfi(DisasContext *ctx)
8855 {
8856 uint64_t imm = rA(ctx->opcode) << 27;
8857
8858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8859 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8860 }
8861
8862 static inline void gen_evsel(DisasContext *ctx)
8863 {
8864 TCGLabel *l1 = gen_new_label();
8865 TCGLabel *l2 = gen_new_label();
8866 TCGLabel *l3 = gen_new_label();
8867 TCGLabel *l4 = gen_new_label();
8868 TCGv_i32 t0 = tcg_temp_local_new_i32();
8869
8870 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8871 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8872 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8873 tcg_gen_br(l2);
8874 gen_set_label(l1);
8875 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8876 gen_set_label(l2);
8877 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8878 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8880 tcg_gen_br(l4);
8881 gen_set_label(l3);
8882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8883 gen_set_label(l4);
8884 tcg_temp_free_i32(t0);
8885 }
8886
8887 static void gen_evsel0(DisasContext *ctx)
8888 {
8889 gen_evsel(ctx);
8890 }
8891
8892 static void gen_evsel1(DisasContext *ctx)
8893 {
8894 gen_evsel(ctx);
8895 }
8896
8897 static void gen_evsel2(DisasContext *ctx)
8898 {
8899 gen_evsel(ctx);
8900 }
8901
8902 static void gen_evsel3(DisasContext *ctx)
8903 {
8904 gen_evsel(ctx);
8905 }
8906
8907 /* Multiply */
8908
8909 static inline void gen_evmwumi(DisasContext *ctx)
8910 {
8911 TCGv_i64 t0, t1;
8912
8913 if (unlikely(!ctx->spe_enabled)) {
8914 gen_exception(ctx, POWERPC_EXCP_SPEU);
8915 return;
8916 }
8917
8918 t0 = tcg_temp_new_i64();
8919 t1 = tcg_temp_new_i64();
8920
8921 /* t0 := rA; t1 := rB */
8922 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8923 tcg_gen_ext32u_i64(t0, t0);
8924 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8925 tcg_gen_ext32u_i64(t1, t1);
8926
8927 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8928
8929 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8930
8931 tcg_temp_free_i64(t0);
8932 tcg_temp_free_i64(t1);
8933 }
8934
8935 static inline void gen_evmwumia(DisasContext *ctx)
8936 {
8937 TCGv_i64 tmp;
8938
8939 if (unlikely(!ctx->spe_enabled)) {
8940 gen_exception(ctx, POWERPC_EXCP_SPEU);
8941 return;
8942 }
8943
8944 gen_evmwumi(ctx); /* rD := rA * rB */
8945
8946 tmp = tcg_temp_new_i64();
8947
8948 /* acc := rD */
8949 gen_load_gpr64(tmp, rD(ctx->opcode));
8950 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8951 tcg_temp_free_i64(tmp);
8952 }
8953
8954 static inline void gen_evmwumiaa(DisasContext *ctx)
8955 {
8956 TCGv_i64 acc;
8957 TCGv_i64 tmp;
8958
8959 if (unlikely(!ctx->spe_enabled)) {
8960 gen_exception(ctx, POWERPC_EXCP_SPEU);
8961 return;
8962 }
8963
8964 gen_evmwumi(ctx); /* rD := rA * rB */
8965
8966 acc = tcg_temp_new_i64();
8967 tmp = tcg_temp_new_i64();
8968
8969 /* tmp := rD */
8970 gen_load_gpr64(tmp, rD(ctx->opcode));
8971
8972 /* Load acc */
8973 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8974
8975 /* acc := tmp + acc */
8976 tcg_gen_add_i64(acc, acc, tmp);
8977
8978 /* Store acc */
8979 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8980
8981 /* rD := acc */
8982 gen_store_gpr64(rD(ctx->opcode), acc);
8983
8984 tcg_temp_free_i64(acc);
8985 tcg_temp_free_i64(tmp);
8986 }
8987
8988 static inline void gen_evmwsmi(DisasContext *ctx)
8989 {
8990 TCGv_i64 t0, t1;
8991
8992 if (unlikely(!ctx->spe_enabled)) {
8993 gen_exception(ctx, POWERPC_EXCP_SPEU);
8994 return;
8995 }
8996
8997 t0 = tcg_temp_new_i64();
8998 t1 = tcg_temp_new_i64();
8999
9000 /* t0 := rA; t1 := rB */
9001 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9002 tcg_gen_ext32s_i64(t0, t0);
9003 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9004 tcg_gen_ext32s_i64(t1, t1);
9005
9006 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9007
9008 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9009
9010 tcg_temp_free_i64(t0);
9011 tcg_temp_free_i64(t1);
9012 }
9013
9014 static inline void gen_evmwsmia(DisasContext *ctx)
9015 {
9016 TCGv_i64 tmp;
9017
9018 gen_evmwsmi(ctx); /* rD := rA * rB */
9019
9020 tmp = tcg_temp_new_i64();
9021
9022 /* acc := rD */
9023 gen_load_gpr64(tmp, rD(ctx->opcode));
9024 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9025
9026 tcg_temp_free_i64(tmp);
9027 }
9028
9029 static inline void gen_evmwsmiaa(DisasContext *ctx)
9030 {
9031 TCGv_i64 acc = tcg_temp_new_i64();
9032 TCGv_i64 tmp = tcg_temp_new_i64();
9033
9034 gen_evmwsmi(ctx); /* rD := rA * rB */
9035
9036 acc = tcg_temp_new_i64();
9037 tmp = tcg_temp_new_i64();
9038
9039 /* tmp := rD */
9040 gen_load_gpr64(tmp, rD(ctx->opcode));
9041
9042 /* Load acc */
9043 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9044
9045 /* acc := tmp + acc */
9046 tcg_gen_add_i64(acc, acc, tmp);
9047
9048 /* Store acc */
9049 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9050
9051 /* rD := acc */
9052 gen_store_gpr64(rD(ctx->opcode), acc);
9053
9054 tcg_temp_free_i64(acc);
9055 tcg_temp_free_i64(tmp);
9056 }
9057
9058 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9059 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9060 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9061 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9062 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9063 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9064 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9065 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9066 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9067 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9068 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9069 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9070 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9071 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9072 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9073 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9074 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9075 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9076 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9077 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9078 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9079 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9080 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9081 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9082 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9083 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9084 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9085 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9086 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9087
9088 /* SPE load and stores */
9089 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9090 {
9091 target_ulong uimm = rB(ctx->opcode);
9092
9093 if (rA(ctx->opcode) == 0) {
9094 tcg_gen_movi_tl(EA, uimm << sh);
9095 } else {
9096 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9097 if (NARROW_MODE(ctx)) {
9098 tcg_gen_ext32u_tl(EA, EA);
9099 }
9100 }
9101 }
9102
9103 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9104 {
9105 TCGv_i64 t0 = tcg_temp_new_i64();
9106 gen_qemu_ld64(ctx, t0, addr);
9107 gen_store_gpr64(rD(ctx->opcode), t0);
9108 tcg_temp_free_i64(t0);
9109 }
9110
9111 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9112 {
9113 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9114 gen_addr_add(ctx, addr, addr, 4);
9115 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9116 }
9117
9118 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9119 {
9120 TCGv t0 = tcg_temp_new();
9121 gen_qemu_ld16u(ctx, t0, addr);
9122 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9123 gen_addr_add(ctx, addr, addr, 2);
9124 gen_qemu_ld16u(ctx, t0, addr);
9125 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9126 gen_addr_add(ctx, addr, addr, 2);
9127 gen_qemu_ld16u(ctx, t0, addr);
9128 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9129 gen_addr_add(ctx, addr, addr, 2);
9130 gen_qemu_ld16u(ctx, t0, addr);
9131 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9132 tcg_temp_free(t0);
9133 }
9134
9135 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9136 {
9137 TCGv t0 = tcg_temp_new();
9138 gen_qemu_ld16u(ctx, t0, addr);
9139 tcg_gen_shli_tl(t0, t0, 16);
9140 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9141 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9142 tcg_temp_free(t0);
9143 }
9144
9145 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9146 {
9147 TCGv t0 = tcg_temp_new();
9148 gen_qemu_ld16u(ctx, t0, addr);
9149 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9150 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9151 tcg_temp_free(t0);
9152 }
9153
9154 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9155 {
9156 TCGv t0 = tcg_temp_new();
9157 gen_qemu_ld16s(ctx, t0, addr);
9158 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9159 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9160 tcg_temp_free(t0);
9161 }
9162
9163 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9164 {
9165 TCGv t0 = tcg_temp_new();
9166 gen_qemu_ld16u(ctx, t0, addr);
9167 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9168 gen_addr_add(ctx, addr, addr, 2);
9169 gen_qemu_ld16u(ctx, t0, addr);
9170 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9171 tcg_temp_free(t0);
9172 }
9173
9174 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9175 {
9176 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9177 gen_addr_add(ctx, addr, addr, 2);
9178 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9179 }
9180
9181 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9182 {
9183 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9184 gen_addr_add(ctx, addr, addr, 2);
9185 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9186 }
9187
9188 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9189 {
9190 TCGv t0 = tcg_temp_new();
9191 gen_qemu_ld32u(ctx, t0, addr);
9192 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9194 tcg_temp_free(t0);
9195 }
9196
9197 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9198 {
9199 TCGv t0 = tcg_temp_new();
9200 gen_qemu_ld16u(ctx, t0, addr);
9201 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9202 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9203 gen_addr_add(ctx, addr, addr, 2);
9204 gen_qemu_ld16u(ctx, t0, addr);
9205 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9206 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9207 tcg_temp_free(t0);
9208 }
9209
9210 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9211 {
9212 TCGv_i64 t0 = tcg_temp_new_i64();
9213 gen_load_gpr64(t0, rS(ctx->opcode));
9214 gen_qemu_st64(ctx, t0, addr);
9215 tcg_temp_free_i64(t0);
9216 }
9217
9218 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9219 {
9220 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9221 gen_addr_add(ctx, addr, addr, 4);
9222 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9223 }
9224
9225 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9226 {
9227 TCGv t0 = tcg_temp_new();
9228 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9229 gen_qemu_st16(ctx, t0, addr);
9230 gen_addr_add(ctx, addr, addr, 2);
9231 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9232 gen_addr_add(ctx, addr, addr, 2);
9233 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9234 gen_qemu_st16(ctx, t0, addr);
9235 tcg_temp_free(t0);
9236 gen_addr_add(ctx, addr, addr, 2);
9237 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9238 }
9239
9240 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9241 {
9242 TCGv t0 = tcg_temp_new();
9243 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9244 gen_qemu_st16(ctx, t0, addr);
9245 gen_addr_add(ctx, addr, addr, 2);
9246 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9247 gen_qemu_st16(ctx, t0, addr);
9248 tcg_temp_free(t0);
9249 }
9250
9251 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9252 {
9253 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9254 gen_addr_add(ctx, addr, addr, 2);
9255 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9256 }
9257
9258 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9259 {
9260 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9261 }
9262
9263 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9264 {
9265 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9266 }
9267
9268 #define GEN_SPEOP_LDST(name, opc2, sh) \
9269 static void glue(gen_, name)(DisasContext *ctx) \
9270 { \
9271 TCGv t0; \
9272 if (unlikely(!ctx->spe_enabled)) { \
9273 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9274 return; \
9275 } \
9276 gen_set_access_type(ctx, ACCESS_INT); \
9277 t0 = tcg_temp_new(); \
9278 if (Rc(ctx->opcode)) { \
9279 gen_addr_spe_imm_index(ctx, t0, sh); \
9280 } else { \
9281 gen_addr_reg_index(ctx, t0); \
9282 } \
9283 gen_op_##name(ctx, t0); \
9284 tcg_temp_free(t0); \
9285 }
9286
9287 GEN_SPEOP_LDST(evldd, 0x00, 3);
9288 GEN_SPEOP_LDST(evldw, 0x01, 3);
9289 GEN_SPEOP_LDST(evldh, 0x02, 3);
9290 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9291 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9292 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9293 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9294 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9295 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9296 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9297 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9298
9299 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9300 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9301 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9302 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9303 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9304 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9305 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9306
9307 /* Multiply and add - TODO */
9308 #if 0
9309 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9310 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9314 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9324 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9330 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9331 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9336 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9337 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9338 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9339 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9340
9341 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9346 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9347 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9348 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9349 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9350 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9351 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9352 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9353
9354 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9355 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9356 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358
9359 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9360 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9361 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9362 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9363 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9364 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9365 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9366 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9370 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9371
9372 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9373 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9374 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9376 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377 #endif
9378
9379 /*** SPE floating-point extension ***/
9380 #define GEN_SPEFPUOP_CONV_32_32(name) \
9381 static inline void gen_##name(DisasContext *ctx) \
9382 { \
9383 TCGv_i32 t0 = tcg_temp_new_i32(); \
9384 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9385 gen_helper_##name(t0, cpu_env, t0); \
9386 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9387 tcg_temp_free_i32(t0); \
9388 }
9389 #define GEN_SPEFPUOP_CONV_32_64(name) \
9390 static inline void gen_##name(DisasContext *ctx) \
9391 { \
9392 TCGv_i64 t0 = tcg_temp_new_i64(); \
9393 TCGv_i32 t1 = tcg_temp_new_i32(); \
9394 gen_load_gpr64(t0, rB(ctx->opcode)); \
9395 gen_helper_##name(t1, cpu_env, t0); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9397 tcg_temp_free_i64(t0); \
9398 tcg_temp_free_i32(t1); \
9399 }
9400 #define GEN_SPEFPUOP_CONV_64_32(name) \
9401 static inline void gen_##name(DisasContext *ctx) \
9402 { \
9403 TCGv_i64 t0 = tcg_temp_new_i64(); \
9404 TCGv_i32 t1 = tcg_temp_new_i32(); \
9405 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9406 gen_helper_##name(t0, cpu_env, t1); \
9407 gen_store_gpr64(rD(ctx->opcode), t0); \
9408 tcg_temp_free_i64(t0); \
9409 tcg_temp_free_i32(t1); \
9410 }
9411 #define GEN_SPEFPUOP_CONV_64_64(name) \
9412 static inline void gen_##name(DisasContext *ctx) \
9413 { \
9414 TCGv_i64 t0 = tcg_temp_new_i64(); \
9415 gen_load_gpr64(t0, rB(ctx->opcode)); \
9416 gen_helper_##name(t0, cpu_env, t0); \
9417 gen_store_gpr64(rD(ctx->opcode), t0); \
9418 tcg_temp_free_i64(t0); \
9419 }
9420 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9421 static inline void gen_##name(DisasContext *ctx) \
9422 { \
9423 TCGv_i32 t0, t1; \
9424 if (unlikely(!ctx->spe_enabled)) { \
9425 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9426 return; \
9427 } \
9428 t0 = tcg_temp_new_i32(); \
9429 t1 = tcg_temp_new_i32(); \
9430 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9431 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9432 gen_helper_##name(t0, cpu_env, t0, t1); \
9433 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9434 \
9435 tcg_temp_free_i32(t0); \
9436 tcg_temp_free_i32(t1); \
9437 }
9438 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9439 static inline void gen_##name(DisasContext *ctx) \
9440 { \
9441 TCGv_i64 t0, t1; \
9442 if (unlikely(!ctx->spe_enabled)) { \
9443 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9444 return; \
9445 } \
9446 t0 = tcg_temp_new_i64(); \
9447 t1 = tcg_temp_new_i64(); \
9448 gen_load_gpr64(t0, rA(ctx->opcode)); \
9449 gen_load_gpr64(t1, rB(ctx->opcode)); \
9450 gen_helper_##name(t0, cpu_env, t0, t1); \
9451 gen_store_gpr64(rD(ctx->opcode), t0); \
9452 tcg_temp_free_i64(t0); \
9453 tcg_temp_free_i64(t1); \
9454 }
9455 #define GEN_SPEFPUOP_COMP_32(name) \
9456 static inline void gen_##name(DisasContext *ctx) \
9457 { \
9458 TCGv_i32 t0, t1; \
9459 if (unlikely(!ctx->spe_enabled)) { \
9460 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9461 return; \
9462 } \
9463 t0 = tcg_temp_new_i32(); \
9464 t1 = tcg_temp_new_i32(); \
9465 \
9466 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9467 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9468 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9469 \
9470 tcg_temp_free_i32(t0); \
9471 tcg_temp_free_i32(t1); \
9472 }
9473 #define GEN_SPEFPUOP_COMP_64(name) \
9474 static inline void gen_##name(DisasContext *ctx) \
9475 { \
9476 TCGv_i64 t0, t1; \
9477 if (unlikely(!ctx->spe_enabled)) { \
9478 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9479 return; \
9480 } \
9481 t0 = tcg_temp_new_i64(); \
9482 t1 = tcg_temp_new_i64(); \
9483 gen_load_gpr64(t0, rA(ctx->opcode)); \
9484 gen_load_gpr64(t1, rB(ctx->opcode)); \
9485 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9486 tcg_temp_free_i64(t0); \
9487 tcg_temp_free_i64(t1); \
9488 }
9489
9490 /* Single precision floating-point vectors operations */
9491 /* Arithmetic */
9492 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9493 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9494 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9495 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9496 static inline void gen_evfsabs(DisasContext *ctx)
9497 {
9498 if (unlikely(!ctx->spe_enabled)) {
9499 gen_exception(ctx, POWERPC_EXCP_SPEU);
9500 return;
9501 }
9502 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9503 ~0x80000000);
9504 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9505 ~0x80000000);
9506 }
9507 static inline void gen_evfsnabs(DisasContext *ctx)
9508 {
9509 if (unlikely(!ctx->spe_enabled)) {
9510 gen_exception(ctx, POWERPC_EXCP_SPEU);
9511 return;
9512 }
9513 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9514 0x80000000);
9515 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9516 0x80000000);
9517 }
9518 static inline void gen_evfsneg(DisasContext *ctx)
9519 {
9520 if (unlikely(!ctx->spe_enabled)) {
9521 gen_exception(ctx, POWERPC_EXCP_SPEU);
9522 return;
9523 }
9524 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9525 0x80000000);
9526 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9527 0x80000000);
9528 }
9529
9530 /* Conversion */
9531 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9532 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9533 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9534 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9535 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9536 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9537 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9538 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9539 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9540 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9541
9542 /* Comparison */
9543 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9544 GEN_SPEFPUOP_COMP_64(evfscmplt);
9545 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9546 GEN_SPEFPUOP_COMP_64(evfststgt);
9547 GEN_SPEFPUOP_COMP_64(evfststlt);
9548 GEN_SPEFPUOP_COMP_64(evfststeq);
9549
9550 /* Opcodes definitions */
9551 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9552 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9553 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9554 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9555 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9556 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9557 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9558 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9559 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9560 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9561 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9562 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9563 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9564 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9565
9566 /* Single precision floating-point operations */
9567 /* Arithmetic */
9568 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9569 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9570 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9571 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9572 static inline void gen_efsabs(DisasContext *ctx)
9573 {
9574 if (unlikely(!ctx->spe_enabled)) {
9575 gen_exception(ctx, POWERPC_EXCP_SPEU);
9576 return;
9577 }
9578 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9579 }
9580 static inline void gen_efsnabs(DisasContext *ctx)
9581 {
9582 if (unlikely(!ctx->spe_enabled)) {
9583 gen_exception(ctx, POWERPC_EXCP_SPEU);
9584 return;
9585 }
9586 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9587 }
9588 static inline void gen_efsneg(DisasContext *ctx)
9589 {
9590 if (unlikely(!ctx->spe_enabled)) {
9591 gen_exception(ctx, POWERPC_EXCP_SPEU);
9592 return;
9593 }
9594 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9595 }
9596
9597 /* Conversion */
9598 GEN_SPEFPUOP_CONV_32_32(efscfui);
9599 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9600 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9601 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9602 GEN_SPEFPUOP_CONV_32_32(efsctui);
9603 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9604 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9605 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9606 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9607 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9608 GEN_SPEFPUOP_CONV_32_64(efscfd);
9609
9610 /* Comparison */
9611 GEN_SPEFPUOP_COMP_32(efscmpgt);
9612 GEN_SPEFPUOP_COMP_32(efscmplt);
9613 GEN_SPEFPUOP_COMP_32(efscmpeq);
9614 GEN_SPEFPUOP_COMP_32(efststgt);
9615 GEN_SPEFPUOP_COMP_32(efststlt);
9616 GEN_SPEFPUOP_COMP_32(efststeq);
9617
9618 /* Opcodes definitions */
9619 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9620 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9621 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9622 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9623 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9624 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9625 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9626 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9627 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9628 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9629 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9630 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9631 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9632 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9633
9634 /* Double precision floating-point operations */
9635 /* Arithmetic */
9636 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9637 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9638 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9639 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9640 static inline void gen_efdabs(DisasContext *ctx)
9641 {
9642 if (unlikely(!ctx->spe_enabled)) {
9643 gen_exception(ctx, POWERPC_EXCP_SPEU);
9644 return;
9645 }
9646 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9647 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9648 ~0x80000000);
9649 }
9650 static inline void gen_efdnabs(DisasContext *ctx)
9651 {
9652 if (unlikely(!ctx->spe_enabled)) {
9653 gen_exception(ctx, POWERPC_EXCP_SPEU);
9654 return;
9655 }
9656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9657 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9658 0x80000000);
9659 }
9660 static inline void gen_efdneg(DisasContext *ctx)
9661 {
9662 if (unlikely(!ctx->spe_enabled)) {
9663 gen_exception(ctx, POWERPC_EXCP_SPEU);
9664 return;
9665 }
9666 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9667 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9668 0x80000000);
9669 }
9670
9671 /* Conversion */
9672 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9673 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9674 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9675 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9676 GEN_SPEFPUOP_CONV_32_64(efdctui);
9677 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9678 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9679 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9680 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9681 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9682 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9683 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9684 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9685 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9686 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9687
9688 /* Comparison */
9689 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9690 GEN_SPEFPUOP_COMP_64(efdcmplt);
9691 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9692 GEN_SPEFPUOP_COMP_64(efdtstgt);
9693 GEN_SPEFPUOP_COMP_64(efdtstlt);
9694 GEN_SPEFPUOP_COMP_64(efdtsteq);
9695
9696 /* Opcodes definitions */
9697 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9698 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9699 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9700 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9701 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9702 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9703 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9704 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9705 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9706 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9707 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9708 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9709 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9710 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9711 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9712 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9713
9714 static void gen_tbegin(DisasContext *ctx)
9715 {
9716 if (unlikely(!ctx->tm_enabled)) {
9717 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9718 return;
9719 }
9720 gen_helper_tbegin(cpu_env);
9721 }
9722
9723 #define GEN_TM_NOOP(name) \
9724 static inline void gen_##name(DisasContext *ctx) \
9725 { \
9726 if (unlikely(!ctx->tm_enabled)) { \
9727 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9728 return; \
9729 } \
9730 /* Because tbegin always fails in QEMU, these user \
9731 * space instructions all have a simple implementation: \
9732 * \
9733 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9734 * = 0b0 || 0b00 || 0b0 \
9735 */ \
9736 tcg_gen_movi_i32(cpu_crf[0], 0); \
9737 }
9738
9739 GEN_TM_NOOP(tend);
9740 GEN_TM_NOOP(tabort);
9741 GEN_TM_NOOP(tabortwc);
9742 GEN_TM_NOOP(tabortwci);
9743 GEN_TM_NOOP(tabortdc);
9744 GEN_TM_NOOP(tabortdci);
9745 GEN_TM_NOOP(tsr);
9746
9747 static void gen_tcheck(DisasContext *ctx)
9748 {
9749 if (unlikely(!ctx->tm_enabled)) {
9750 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9751 return;
9752 }
9753 /* Because tbegin always fails, the tcheck implementation
9754 * is simple:
9755 *
9756 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9757 * = 0b1 || 0b00 || 0b0
9758 */
9759 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9760 }
9761
9762 #if defined(CONFIG_USER_ONLY)
9763 #define GEN_TM_PRIV_NOOP(name) \
9764 static inline void gen_##name(DisasContext *ctx) \
9765 { \
9766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9767 }
9768
9769 #else
9770
9771 #define GEN_TM_PRIV_NOOP(name) \
9772 static inline void gen_##name(DisasContext *ctx) \
9773 { \
9774 if (unlikely(ctx->pr)) { \
9775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9776 return; \
9777 } \
9778 if (unlikely(!ctx->tm_enabled)) { \
9779 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9780 return; \
9781 } \
9782 /* Because tbegin always fails, the implementation is \
9783 * simple: \
9784 * \
9785 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9786 * = 0b0 || 0b00 | 0b0 \
9787 */ \
9788 tcg_gen_movi_i32(cpu_crf[0], 0); \
9789 }
9790
9791 #endif
9792
9793 GEN_TM_PRIV_NOOP(treclaim);
9794 GEN_TM_PRIV_NOOP(trechkpt);
9795
9796 static opcode_t opcodes[] = {
9797 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9798 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9799 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9800 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9801 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9802 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9803 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9804 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9805 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9806 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9807 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9808 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9809 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9810 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9811 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9812 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9813 #if defined(TARGET_PPC64)
9814 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9815 #endif
9816 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9817 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9818 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9819 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9820 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9821 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9822 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9823 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9824 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9825 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9826 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9827 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9828 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9829 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9830 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9831 #if defined(TARGET_PPC64)
9832 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9833 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9834 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9835 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9836 #endif
9837 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9840 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9841 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9842 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9843 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9844 #if defined(TARGET_PPC64)
9845 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9846 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9847 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9848 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9849 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9850 #endif
9851 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9852 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9853 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9854 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9855 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9856 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9857 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9858 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9859 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9860 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9861 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9862 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9863 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9864 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9865 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9866 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9867 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9868 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9869 #if defined(TARGET_PPC64)
9870 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9871 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9872 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9873 #endif
9874 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9877 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9878 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9879 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9880 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9881 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9882 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9883 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9884 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9885 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9886 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9887 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9888 #if defined(TARGET_PPC64)
9889 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9890 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9891 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9892 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9893 #endif
9894 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9895 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9896 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9897 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9898 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9899 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9900 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9901 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9902 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9903 #if defined(TARGET_PPC64)
9904 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9905 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9906 #endif
9907 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9908 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9909 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9910 #if defined(TARGET_PPC64)
9911 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9912 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9913 #endif
9914 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9915 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9916 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9917 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9918 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9919 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9920 #if defined(TARGET_PPC64)
9921 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9922 #endif
9923 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9924 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9925 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9926 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9927 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9928 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9929 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9930 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9931 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9932 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9933 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9934 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9935 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9936 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9937 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9938 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9939 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9940 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9941 #if defined(TARGET_PPC64)
9942 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9943 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9944 PPC_SEGMENT_64B),
9945 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9946 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9947 PPC_SEGMENT_64B),
9948 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9949 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9950 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9951 #endif
9952 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9953 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9954 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9955 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9956 #if defined(TARGET_PPC64)
9957 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9958 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9959 #endif
9960 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9961 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9962 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9963 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9964 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9965 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9966 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9967 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9968 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9969 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9970 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9971 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9972 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9973 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9974 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9975 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9976 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9977 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9978 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9979 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9980 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9981 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9982 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9983 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9984 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9985 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9986 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9987 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9988 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9989 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9990 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9991 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9992 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9993 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9994 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9995 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9996 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9997 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9998 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9999 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10000 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10001 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10002 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10003 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10004 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10005 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10006 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10007 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10008 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10009 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10010 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10011 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10012 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10013 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10014 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10015 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10016 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10017 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10018 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10019 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10020 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10021 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10022 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10023 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10024 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10025 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10026 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10027 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10028 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10029 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10030 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10031 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10032 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10033 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10034 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10035 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10036 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10037 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10038 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10039 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10040 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10041 PPC_NONE, PPC2_BOOKE206),
10042 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10043 PPC_NONE, PPC2_BOOKE206),
10044 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10045 PPC_NONE, PPC2_BOOKE206),
10046 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10047 PPC_NONE, PPC2_BOOKE206),
10048 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10049 PPC_NONE, PPC2_BOOKE206),
10050 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10051 PPC_NONE, PPC2_PRCNTL),
10052 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10053 PPC_NONE, PPC2_PRCNTL),
10054 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10055 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10056 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10057 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10058 PPC_BOOKE, PPC2_BOOKE206),
10059 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10060 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10061 PPC_BOOKE, PPC2_BOOKE206),
10062 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10063 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10064 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10065 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10066 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10067 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10068 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10069 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10070 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10071
10072 #undef GEN_INT_ARITH_ADD
10073 #undef GEN_INT_ARITH_ADD_CONST
10074 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10075 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10076 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10077 add_ca, compute_ca, compute_ov) \
10078 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10079 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10080 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10081 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10082 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10083 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10084 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10085 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10086 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10087 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10088 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10089
10090 #undef GEN_INT_ARITH_DIVW
10091 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10092 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10093 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10094 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10095 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10096 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10097 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10098 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10099 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10100 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10101
10102 #if defined(TARGET_PPC64)
10103 #undef GEN_INT_ARITH_DIVD
10104 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10105 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10106 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10107 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10108 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10109 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10110
10111 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10112 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10113 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10114 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10115
10116 #undef GEN_INT_ARITH_MUL_HELPER
10117 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10118 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10119 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10120 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10121 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10122 #endif
10123
10124 #undef GEN_INT_ARITH_SUBF
10125 #undef GEN_INT_ARITH_SUBF_CONST
10126 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10127 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10128 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10129 add_ca, compute_ca, compute_ov) \
10130 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10131 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10132 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10133 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10134 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10135 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10136 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10137 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10138 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10139 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10140 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10141
10142 #undef GEN_LOGICAL1
10143 #undef GEN_LOGICAL2
10144 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10145 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10146 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10147 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10148 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10149 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10150 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10151 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10152 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10153 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10154 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10155 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10156 #if defined(TARGET_PPC64)
10157 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10158 #endif
10159
10160 #if defined(TARGET_PPC64)
10161 #undef GEN_PPC64_R2
10162 #undef GEN_PPC64_R4
10163 #define GEN_PPC64_R2(name, opc1, opc2) \
10164 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10165 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10166 PPC_64B)
10167 #define GEN_PPC64_R4(name, opc1, opc2) \
10168 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10169 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10170 PPC_64B), \
10171 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10172 PPC_64B), \
10173 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10174 PPC_64B)
10175 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10176 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10177 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10178 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10179 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10180 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10181 #endif
10182
10183 #undef _GEN_FLOAT_ACB
10184 #undef GEN_FLOAT_ACB
10185 #undef _GEN_FLOAT_AB
10186 #undef GEN_FLOAT_AB
10187 #undef _GEN_FLOAT_AC
10188 #undef GEN_FLOAT_AC
10189 #undef GEN_FLOAT_B
10190 #undef GEN_FLOAT_BS
10191 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10192 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10193 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10194 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10195 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10196 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10197 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10198 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10199 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10200 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10201 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10202 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10203 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10204 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10205 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10206 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10207 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10208 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10209 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10210
10211 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10212 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10213 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10214 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10215 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10216 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10217 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10218 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10219 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10220 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10221 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10222 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10223 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10224 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10225 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10226 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10227 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10228 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10229 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10230 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10231 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10232 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10233 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10234 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10235 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10236 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10237 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10238 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10239 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10240 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10241 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10242
10243 #undef GEN_LD
10244 #undef GEN_LDU
10245 #undef GEN_LDUX
10246 #undef GEN_LDX_E
10247 #undef GEN_LDS
10248 #define GEN_LD(name, ldop, opc, type) \
10249 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10250 #define GEN_LDU(name, ldop, opc, type) \
10251 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10252 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10253 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10254 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10255 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10256 #define GEN_LDS(name, ldop, op, type) \
10257 GEN_LD(name, ldop, op | 0x20, type) \
10258 GEN_LDU(name, ldop, op | 0x21, type) \
10259 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10260 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10261
10262 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10263 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10264 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10265 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10266 #if defined(TARGET_PPC64)
10267 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10268 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10269 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10270 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10271 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10272 #endif
10273 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10274 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10275
10276 #undef GEN_ST
10277 #undef GEN_STU
10278 #undef GEN_STUX
10279 #undef GEN_STX_E
10280 #undef GEN_STS
10281 #define GEN_ST(name, stop, opc, type) \
10282 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10283 #define GEN_STU(name, stop, opc, type) \
10284 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10285 #define GEN_STUX(name, stop, opc2, opc3, type) \
10286 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10287 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10288 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10289 #define GEN_STS(name, stop, op, type) \
10290 GEN_ST(name, stop, op | 0x20, type) \
10291 GEN_STU(name, stop, op | 0x21, type) \
10292 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10293 GEN_STX(name, stop, 0x17, op | 0x00, type)
10294
10295 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10296 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10297 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10298 #if defined(TARGET_PPC64)
10299 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10300 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10301 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10302 #endif
10303 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10304 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10305
10306 #undef GEN_LDF
10307 #undef GEN_LDUF
10308 #undef GEN_LDUXF
10309 #undef GEN_LDXF
10310 #undef GEN_LDFS
10311 #define GEN_LDF(name, ldop, opc, type) \
10312 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10313 #define GEN_LDUF(name, ldop, opc, type) \
10314 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10315 #define GEN_LDUXF(name, ldop, opc, type) \
10316 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10317 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10318 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10319 #define GEN_LDFS(name, ldop, op, type) \
10320 GEN_LDF(name, ldop, op | 0x20, type) \
10321 GEN_LDUF(name, ldop, op | 0x21, type) \
10322 GEN_LDUXF(name, ldop, op | 0x01, type) \
10323 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10324
10325 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10326 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10327 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10328 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10329 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10330 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10331
10332 #undef GEN_STF
10333 #undef GEN_STUF
10334 #undef GEN_STUXF
10335 #undef GEN_STXF
10336 #undef GEN_STFS
10337 #define GEN_STF(name, stop, opc, type) \
10338 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10339 #define GEN_STUF(name, stop, opc, type) \
10340 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10341 #define GEN_STUXF(name, stop, opc, type) \
10342 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10343 #define GEN_STXF(name, stop, opc2, opc3, type) \
10344 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10345 #define GEN_STFS(name, stop, op, type) \
10346 GEN_STF(name, stop, op | 0x20, type) \
10347 GEN_STUF(name, stop, op | 0x21, type) \
10348 GEN_STUXF(name, stop, op | 0x01, type) \
10349 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10350
10351 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10352 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10353 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10354 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10355 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10356
10357 #undef GEN_CRLOGIC
10358 #define GEN_CRLOGIC(name, tcg_op, opc) \
10359 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10360 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10361 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10362 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10363 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10364 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10365 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10366 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10367 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10368
10369 #undef GEN_MAC_HANDLER
10370 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10371 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10372 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10373 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10374 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10375 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10376 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10377 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10378 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10379 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10380 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10381 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10382 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10383 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10384 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10385 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10386 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10387 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10388 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10389 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10390 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10391 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10392 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10393 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10394 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10395 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10396 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10397 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10398 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10399 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10400 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10401 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10402 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10403 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10404 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10405 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10406 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10407 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10408 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10409 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10410 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10411 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10412 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10413 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10414
10415 #undef GEN_VR_LDX
10416 #undef GEN_VR_STX
10417 #undef GEN_VR_LVE
10418 #undef GEN_VR_STVE
10419 #define GEN_VR_LDX(name, opc2, opc3) \
10420 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10421 #define GEN_VR_STX(name, opc2, opc3) \
10422 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10423 #define GEN_VR_LVE(name, opc2, opc3) \
10424 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10425 #define GEN_VR_STVE(name, opc2, opc3) \
10426 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10427 GEN_VR_LDX(lvx, 0x07, 0x03),
10428 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10429 GEN_VR_LVE(bx, 0x07, 0x00),
10430 GEN_VR_LVE(hx, 0x07, 0x01),
10431 GEN_VR_LVE(wx, 0x07, 0x02),
10432 GEN_VR_STX(svx, 0x07, 0x07),
10433 GEN_VR_STX(svxl, 0x07, 0x0F),
10434 GEN_VR_STVE(bx, 0x07, 0x04),
10435 GEN_VR_STVE(hx, 0x07, 0x05),
10436 GEN_VR_STVE(wx, 0x07, 0x06),
10437
10438 #undef GEN_VX_LOGICAL
10439 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10440 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10441
10442 #undef GEN_VX_LOGICAL_207
10443 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10444 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10445
10446 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10447 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10448 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10449 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10450 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10451 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10452 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10453 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10454
10455 #undef GEN_VXFORM
10456 #define GEN_VXFORM(name, opc2, opc3) \
10457 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10458
10459 #undef GEN_VXFORM_207
10460 #define GEN_VXFORM_207(name, opc2, opc3) \
10461 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10462
10463 #undef GEN_VXFORM_DUAL
10464 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10465 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10466
10467 #undef GEN_VXRFORM_DUAL
10468 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10469 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10470 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10471
10472 GEN_VXFORM(vaddubm, 0, 0),
10473 GEN_VXFORM(vadduhm, 0, 1),
10474 GEN_VXFORM(vadduwm, 0, 2),
10475 GEN_VXFORM_207(vaddudm, 0, 3),
10476 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10477 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10478 GEN_VXFORM(vsubuwm, 0, 18),
10479 GEN_VXFORM_207(vsubudm, 0, 19),
10480 GEN_VXFORM(vmaxub, 1, 0),
10481 GEN_VXFORM(vmaxuh, 1, 1),
10482 GEN_VXFORM(vmaxuw, 1, 2),
10483 GEN_VXFORM_207(vmaxud, 1, 3),
10484 GEN_VXFORM(vmaxsb, 1, 4),
10485 GEN_VXFORM(vmaxsh, 1, 5),
10486 GEN_VXFORM(vmaxsw, 1, 6),
10487 GEN_VXFORM_207(vmaxsd, 1, 7),
10488 GEN_VXFORM(vminub, 1, 8),
10489 GEN_VXFORM(vminuh, 1, 9),
10490 GEN_VXFORM(vminuw, 1, 10),
10491 GEN_VXFORM_207(vminud, 1, 11),
10492 GEN_VXFORM(vminsb, 1, 12),
10493 GEN_VXFORM(vminsh, 1, 13),
10494 GEN_VXFORM(vminsw, 1, 14),
10495 GEN_VXFORM_207(vminsd, 1, 15),
10496 GEN_VXFORM(vavgub, 1, 16),
10497 GEN_VXFORM(vavguh, 1, 17),
10498 GEN_VXFORM(vavguw, 1, 18),
10499 GEN_VXFORM(vavgsb, 1, 20),
10500 GEN_VXFORM(vavgsh, 1, 21),
10501 GEN_VXFORM(vavgsw, 1, 22),
10502 GEN_VXFORM(vmrghb, 6, 0),
10503 GEN_VXFORM(vmrghh, 6, 1),
10504 GEN_VXFORM(vmrghw, 6, 2),
10505 GEN_VXFORM(vmrglb, 6, 4),
10506 GEN_VXFORM(vmrglh, 6, 5),
10507 GEN_VXFORM(vmrglw, 6, 6),
10508 GEN_VXFORM_207(vmrgew, 6, 30),
10509 GEN_VXFORM_207(vmrgow, 6, 26),
10510 GEN_VXFORM(vmuloub, 4, 0),
10511 GEN_VXFORM(vmulouh, 4, 1),
10512 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10513 GEN_VXFORM(vmulosb, 4, 4),
10514 GEN_VXFORM(vmulosh, 4, 5),
10515 GEN_VXFORM_207(vmulosw, 4, 6),
10516 GEN_VXFORM(vmuleub, 4, 8),
10517 GEN_VXFORM(vmuleuh, 4, 9),
10518 GEN_VXFORM_207(vmuleuw, 4, 10),
10519 GEN_VXFORM(vmulesb, 4, 12),
10520 GEN_VXFORM(vmulesh, 4, 13),
10521 GEN_VXFORM_207(vmulesw, 4, 14),
10522 GEN_VXFORM(vslb, 2, 4),
10523 GEN_VXFORM(vslh, 2, 5),
10524 GEN_VXFORM(vslw, 2, 6),
10525 GEN_VXFORM_207(vsld, 2, 23),
10526 GEN_VXFORM(vsrb, 2, 8),
10527 GEN_VXFORM(vsrh, 2, 9),
10528 GEN_VXFORM(vsrw, 2, 10),
10529 GEN_VXFORM_207(vsrd, 2, 27),
10530 GEN_VXFORM(vsrab, 2, 12),
10531 GEN_VXFORM(vsrah, 2, 13),
10532 GEN_VXFORM(vsraw, 2, 14),
10533 GEN_VXFORM_207(vsrad, 2, 15),
10534 GEN_VXFORM(vslo, 6, 16),
10535 GEN_VXFORM(vsro, 6, 17),
10536 GEN_VXFORM(vaddcuw, 0, 6),
10537 GEN_VXFORM(vsubcuw, 0, 22),
10538 GEN_VXFORM(vaddubs, 0, 8),
10539 GEN_VXFORM(vadduhs, 0, 9),
10540 GEN_VXFORM(vadduws, 0, 10),
10541 GEN_VXFORM(vaddsbs, 0, 12),
10542 GEN_VXFORM(vaddshs, 0, 13),
10543 GEN_VXFORM(vaddsws, 0, 14),
10544 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10545 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10546 GEN_VXFORM(vsubuws, 0, 26),
10547 GEN_VXFORM(vsubsbs, 0, 28),
10548 GEN_VXFORM(vsubshs, 0, 29),
10549 GEN_VXFORM(vsubsws, 0, 30),
10550 GEN_VXFORM_207(vadduqm, 0, 4),
10551 GEN_VXFORM_207(vaddcuq, 0, 5),
10552 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10553 GEN_VXFORM_207(vsubuqm, 0, 20),
10554 GEN_VXFORM_207(vsubcuq, 0, 21),
10555 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10556 GEN_VXFORM(vrlb, 2, 0),
10557 GEN_VXFORM(vrlh, 2, 1),
10558 GEN_VXFORM(vrlw, 2, 2),
10559 GEN_VXFORM_207(vrld, 2, 3),
10560 GEN_VXFORM(vsl, 2, 7),
10561 GEN_VXFORM(vsr, 2, 11),
10562 GEN_VXFORM(vpkuhum, 7, 0),
10563 GEN_VXFORM(vpkuwum, 7, 1),
10564 GEN_VXFORM_207(vpkudum, 7, 17),
10565 GEN_VXFORM(vpkuhus, 7, 2),
10566 GEN_VXFORM(vpkuwus, 7, 3),
10567 GEN_VXFORM_207(vpkudus, 7, 19),
10568 GEN_VXFORM(vpkshus, 7, 4),
10569 GEN_VXFORM(vpkswus, 7, 5),
10570 GEN_VXFORM_207(vpksdus, 7, 21),
10571 GEN_VXFORM(vpkshss, 7, 6),
10572 GEN_VXFORM(vpkswss, 7, 7),
10573 GEN_VXFORM_207(vpksdss, 7, 23),
10574 GEN_VXFORM(vpkpx, 7, 12),
10575 GEN_VXFORM(vsum4ubs, 4, 24),
10576 GEN_VXFORM(vsum4sbs, 4, 28),
10577 GEN_VXFORM(vsum4shs, 4, 25),
10578 GEN_VXFORM(vsum2sws, 4, 26),
10579 GEN_VXFORM(vsumsws, 4, 30),
10580 GEN_VXFORM(vaddfp, 5, 0),
10581 GEN_VXFORM(vsubfp, 5, 1),
10582 GEN_VXFORM(vmaxfp, 5, 16),
10583 GEN_VXFORM(vminfp, 5, 17),
10584
10585 #undef GEN_VXRFORM1
10586 #undef GEN_VXRFORM
10587 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10588 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10589 #define GEN_VXRFORM(name, opc2, opc3) \
10590 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10591 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10592 GEN_VXRFORM(vcmpequb, 3, 0)
10593 GEN_VXRFORM(vcmpequh, 3, 1)
10594 GEN_VXRFORM(vcmpequw, 3, 2)
10595 GEN_VXRFORM(vcmpgtsb, 3, 12)
10596 GEN_VXRFORM(vcmpgtsh, 3, 13)
10597 GEN_VXRFORM(vcmpgtsw, 3, 14)
10598 GEN_VXRFORM(vcmpgtub, 3, 8)
10599 GEN_VXRFORM(vcmpgtuh, 3, 9)
10600 GEN_VXRFORM(vcmpgtuw, 3, 10)
10601 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10602 GEN_VXRFORM(vcmpgefp, 3, 7)
10603 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10604 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10605
10606 #undef GEN_VXFORM_SIMM
10607 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10608 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10609 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10610 GEN_VXFORM_SIMM(vspltish, 6, 13),
10611 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10612
10613 #undef GEN_VXFORM_NOA
10614 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10615 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10616 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10617 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10618 GEN_VXFORM_207(vupkhsw, 7, 25),
10619 GEN_VXFORM_NOA(vupklsb, 7, 10),
10620 GEN_VXFORM_NOA(vupklsh, 7, 11),
10621 GEN_VXFORM_207(vupklsw, 7, 27),
10622 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10623 GEN_VXFORM_NOA(vupklpx, 7, 15),
10624 GEN_VXFORM_NOA(vrefp, 5, 4),
10625 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10626 GEN_VXFORM_NOA(vexptefp, 5, 6),
10627 GEN_VXFORM_NOA(vlogefp, 5, 7),
10628 GEN_VXFORM_NOA(vrfim, 5, 11),
10629 GEN_VXFORM_NOA(vrfin, 5, 8),
10630 GEN_VXFORM_NOA(vrfip, 5, 10),
10631 GEN_VXFORM_NOA(vrfiz, 5, 9),
10632
10633 #undef GEN_VXFORM_UIMM
10634 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10635 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10636 GEN_VXFORM_UIMM(vspltb, 6, 8),
10637 GEN_VXFORM_UIMM(vsplth, 6, 9),
10638 GEN_VXFORM_UIMM(vspltw, 6, 10),
10639 GEN_VXFORM_UIMM(vcfux, 5, 12),
10640 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10641 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10642 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10643
10644 #undef GEN_VAFORM_PAIRED
10645 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10646 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10647 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10648 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10649 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10650 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10651 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10652 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10653
10654 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10655 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10656 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10657 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10658
10659 GEN_VXFORM_207(vbpermq, 6, 21),
10660 GEN_VXFORM_207(vgbbd, 6, 20),
10661 GEN_VXFORM_207(vpmsumb, 4, 16),
10662 GEN_VXFORM_207(vpmsumh, 4, 17),
10663 GEN_VXFORM_207(vpmsumw, 4, 18),
10664 GEN_VXFORM_207(vpmsumd, 4, 19),
10665
10666 GEN_VXFORM_207(vsbox, 4, 23),
10667
10668 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10669 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10670
10671 GEN_VXFORM_207(vshasigmaw, 1, 26),
10672 GEN_VXFORM_207(vshasigmad, 1, 27),
10673
10674 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10675
10676 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10677 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10678 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10679 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10680 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10681 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10682 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10683
10684 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10685 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10686 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10687 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10688 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10689
10690 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10691 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10692 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10693 #if defined(TARGET_PPC64)
10694 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10695 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10696 #endif
10697
10698 #undef GEN_XX2FORM
10699 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10702
10703 #undef GEN_XX3FORM
10704 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10709
10710 #undef GEN_XX2IFORM
10711 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10712 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10714 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10715 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10716
10717 #undef GEN_XX3_RC_FORM
10718 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10719 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10720 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10721 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10724 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10727
10728 #undef GEN_XX3FORM_DM
10729 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10730 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10731 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10733 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10735 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10736 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10737 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10738 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10739 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10740 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10741 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10742 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10743 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10744 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10745 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10746
10747 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10748 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10749 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10750 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10751
10752 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10753 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10754 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10755 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10756 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10757 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10758 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10759 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10760
10761 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10762 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10763 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10764 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10765 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10766 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10767 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10768 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10769 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10770 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10771 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10772 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10773 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10774 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10775 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10776 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10777 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10778 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10779 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10780 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10781 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10782 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10783 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10784 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10785 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10786 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10787 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10788 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10789 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10790 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10791 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10792 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10793 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10794 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10795 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10796 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10797
10798 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10799 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10800 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10801 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10802 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10803 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10804 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10805 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10806 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10807 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10808 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10809 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10810 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10811 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10812 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10813 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10814 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10815 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10816
10817 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10818 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10819 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10820 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10821 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10822 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10823 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10824 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10825 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10826 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10827 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10828 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10829 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10830 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10831 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10832 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10833 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10834 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10835 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10836 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10837 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10838 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10839 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10840 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10841 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10842 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10843 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10844 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10845 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10846 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10847 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10848 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10849 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10850 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10851 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10852 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10853
10854 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10855 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10856 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10857 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10858 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10859 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10860 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10861 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10862 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10863 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10864 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10865 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10866 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10867 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10868 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10869 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10870 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10871 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10872 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10873 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10874 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10875 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10876 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10877 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10878 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10879 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10880 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10881 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10882 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10883 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10884 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10885 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10886 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10887 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10888 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10889 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10890
10891 #undef VSX_LOGICAL
10892 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10893 GEN_XX3FORM(name, opc2, opc3, fl2)
10894
10895 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10896 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10897 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10898 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10899 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10900 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10901 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10902 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10903 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10904 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10905 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10906 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10907
10908 #define GEN_XXSEL_ROW(opc3) \
10909 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10910 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10911 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10912 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10913 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10914 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10915 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10916 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10917
10918 GEN_XXSEL_ROW(0x00)
10919 GEN_XXSEL_ROW(0x01)
10920 GEN_XXSEL_ROW(0x02)
10921 GEN_XXSEL_ROW(0x03)
10922 GEN_XXSEL_ROW(0x04)
10923 GEN_XXSEL_ROW(0x05)
10924 GEN_XXSEL_ROW(0x06)
10925 GEN_XXSEL_ROW(0x07)
10926 GEN_XXSEL_ROW(0x08)
10927 GEN_XXSEL_ROW(0x09)
10928 GEN_XXSEL_ROW(0x0A)
10929 GEN_XXSEL_ROW(0x0B)
10930 GEN_XXSEL_ROW(0x0C)
10931 GEN_XXSEL_ROW(0x0D)
10932 GEN_XXSEL_ROW(0x0E)
10933 GEN_XXSEL_ROW(0x0F)
10934 GEN_XXSEL_ROW(0x10)
10935 GEN_XXSEL_ROW(0x11)
10936 GEN_XXSEL_ROW(0x12)
10937 GEN_XXSEL_ROW(0x13)
10938 GEN_XXSEL_ROW(0x14)
10939 GEN_XXSEL_ROW(0x15)
10940 GEN_XXSEL_ROW(0x16)
10941 GEN_XXSEL_ROW(0x17)
10942 GEN_XXSEL_ROW(0x18)
10943 GEN_XXSEL_ROW(0x19)
10944 GEN_XXSEL_ROW(0x1A)
10945 GEN_XXSEL_ROW(0x1B)
10946 GEN_XXSEL_ROW(0x1C)
10947 GEN_XXSEL_ROW(0x1D)
10948 GEN_XXSEL_ROW(0x1E)
10949 GEN_XXSEL_ROW(0x1F)
10950
10951 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10952
10953 #undef GEN_DFP_T_A_B_Rc
10954 #undef GEN_DFP_BF_A_B
10955 #undef GEN_DFP_BF_A_DCM
10956 #undef GEN_DFP_T_B_U32_U32_Rc
10957 #undef GEN_DFP_T_A_B_I32_Rc
10958 #undef GEN_DFP_T_B_Rc
10959 #undef GEN_DFP_T_FPR_I32_Rc
10960
10961 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10962 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10963
10964 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10965 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10966 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10967
10968 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10969 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10970 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10971 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10972 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10973
10974 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10975 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10976
10977 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10978 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10979 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10980
10981 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10982 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10983 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10984 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10985 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10986
10987 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10988 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10989
10990 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10991 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10992
10993 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10994 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10995
10996 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10997 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10998
10999 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11000 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11001
11002 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11003 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11004
11005 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11006 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11007
11008 #define GEN_DFP_BF_A_B(name, op1, op2) \
11009 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11010
11011 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11012 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11013
11014 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11015 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11016
11017 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11018 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11019
11020 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11021 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11022
11023 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11024 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11025
11026 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11027 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11028
11029 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11030 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11031
11032 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11033 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11034
11035 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11036 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11037
11038 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11039 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11040
11041 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11042 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11043
11044 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11045 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11046
11047 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11048 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11049
11050 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11051 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11052
11053 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11054 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11055
11056 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11057 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11058
11059 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11060 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11061
11062 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11063 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11064 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11065 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11066 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11067 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11068 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11069 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11070 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11071 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11072 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11073 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11074 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11075 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11076 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11077 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11078 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11079 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11080 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11081 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11082 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11083 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11084 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11085 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11086 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11087 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11088 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11089 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11090 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11091 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11092 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11093 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11094 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11095 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11096 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11097 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11098 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11099 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11100 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11101 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11102 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11103 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11104 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11105 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11106 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11107 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11108 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11109 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11110 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11111 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11112
11113 #undef GEN_SPE
11114 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11115 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11116 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11117 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11118 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11119 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11120 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11121 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11122 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11123 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11124 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11125 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11126 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11127 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11128 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11129 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11130 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11131 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11132 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11133 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11134 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11135 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11136 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11137 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11138 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11139 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11140 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11141 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11142 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11143 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11144 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11145
11146 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11147 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11148 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11149 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11150 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11151 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11152 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11153 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11154 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11155 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11156 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11157 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11158 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11159 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11160
11161 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11162 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11163 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11164 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11165 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11166 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11167 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11168 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11169 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11170 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11171 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11172 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11173 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11174 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11175
11176 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11177 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11178 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11179 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11180 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11181 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11182 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11183 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11184 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11185 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11186 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11187 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11188 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11189 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11190 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11191 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11192
11193 #undef GEN_SPEOP_LDST
11194 #define GEN_SPEOP_LDST(name, opc2, sh) \
11195 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11196 GEN_SPEOP_LDST(evldd, 0x00, 3),
11197 GEN_SPEOP_LDST(evldw, 0x01, 3),
11198 GEN_SPEOP_LDST(evldh, 0x02, 3),
11199 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11200 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11201 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11202 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11203 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11204 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11205 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11206 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11207
11208 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11209 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11210 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11211 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11212 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11213 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11214 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11215
11216 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11217 PPC_NONE, PPC2_TM),
11218 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11219 PPC_NONE, PPC2_TM),
11220 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11221 PPC_NONE, PPC2_TM),
11222 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11223 PPC_NONE, PPC2_TM),
11224 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11225 PPC_NONE, PPC2_TM),
11226 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11227 PPC_NONE, PPC2_TM),
11228 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11229 PPC_NONE, PPC2_TM),
11230 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11231 PPC_NONE, PPC2_TM),
11232 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11233 PPC_NONE, PPC2_TM),
11234 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11235 PPC_NONE, PPC2_TM),
11236 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11237 PPC_NONE, PPC2_TM),
11238 };
11239
11240 #include "helper_regs.h"
11241 #include "translate_init.c"
11242
11243 /*****************************************************************************/
11244 /* Misc PowerPC helpers */
11245 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11246 int flags)
11247 {
11248 #define RGPL 4
11249 #define RFPL 4
11250
11251 PowerPCCPU *cpu = POWERPC_CPU(cs);
11252 CPUPPCState *env = &cpu->env;
11253 int i;
11254
11255 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11256 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11257 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11258 cs->cpu_index);
11259 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11260 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11261 env->hflags, env->mmu_idx);
11262 #if !defined(NO_TIMER_DUMP)
11263 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11264 #if !defined(CONFIG_USER_ONLY)
11265 " DECR %08" PRIu32
11266 #endif
11267 "\n",
11268 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11269 #if !defined(CONFIG_USER_ONLY)
11270 , cpu_ppc_load_decr(env)
11271 #endif
11272 );
11273 #endif
11274 for (i = 0; i < 32; i++) {
11275 if ((i & (RGPL - 1)) == 0)
11276 cpu_fprintf(f, "GPR%02d", i);
11277 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11278 if ((i & (RGPL - 1)) == (RGPL - 1))
11279 cpu_fprintf(f, "\n");
11280 }
11281 cpu_fprintf(f, "CR ");
11282 for (i = 0; i < 8; i++)
11283 cpu_fprintf(f, "%01x", env->crf[i]);
11284 cpu_fprintf(f, " [");
11285 for (i = 0; i < 8; i++) {
11286 char a = '-';
11287 if (env->crf[i] & 0x08)
11288 a = 'L';
11289 else if (env->crf[i] & 0x04)
11290 a = 'G';
11291 else if (env->crf[i] & 0x02)
11292 a = 'E';
11293 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11294 }
11295 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11296 env->reserve_addr);
11297 for (i = 0; i < 32; i++) {
11298 if ((i & (RFPL - 1)) == 0)
11299 cpu_fprintf(f, "FPR%02d", i);
11300 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11301 if ((i & (RFPL - 1)) == (RFPL - 1))
11302 cpu_fprintf(f, "\n");
11303 }
11304 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11305 #if !defined(CONFIG_USER_ONLY)
11306 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11307 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11308 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11309 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11310
11311 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11312 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11313 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11314 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11315
11316 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11317 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11318 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11319 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11320
11321 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11322 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11323 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11324 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11325 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11326
11327 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11328 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11329 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11330 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11331
11332 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11333 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11334 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11335 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11336
11337 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11338 " EPR " TARGET_FMT_lx "\n",
11339 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11340 env->spr[SPR_BOOKE_EPR]);
11341
11342 /* FSL-specific */
11343 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11344 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11345 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11346 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11347
11348 /*
11349 * IVORs are left out as they are large and do not change often --
11350 * they can be read with "p $ivor0", "p $ivor1", etc.
11351 */
11352 }
11353
11354 #if defined(TARGET_PPC64)
11355 if (env->flags & POWERPC_FLAG_CFAR) {
11356 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11357 }
11358 #endif
11359
11360 switch (env->mmu_model) {
11361 case POWERPC_MMU_32B:
11362 case POWERPC_MMU_601:
11363 case POWERPC_MMU_SOFT_6xx:
11364 case POWERPC_MMU_SOFT_74xx:
11365 #if defined(TARGET_PPC64)
11366 case POWERPC_MMU_64B:
11367 case POWERPC_MMU_2_03:
11368 case POWERPC_MMU_2_06:
11369 case POWERPC_MMU_2_06a:
11370 case POWERPC_MMU_2_07:
11371 case POWERPC_MMU_2_07a:
11372 #endif
11373 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11374 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11375 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11376 break;
11377 case POWERPC_MMU_BOOKE206:
11378 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11379 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11380 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11381 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11382
11383 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11384 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11385 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11386 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11387
11388 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11389 " TLB1CFG " TARGET_FMT_lx "\n",
11390 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11391 env->spr[SPR_BOOKE_TLB1CFG]);
11392 break;
11393 default:
11394 break;
11395 }
11396 #endif
11397
11398 #undef RGPL
11399 #undef RFPL
11400 }
11401
11402 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11403 fprintf_function cpu_fprintf, int flags)
11404 {
11405 #if defined(DO_PPC_STATISTICS)
11406 PowerPCCPU *cpu = POWERPC_CPU(cs);
11407 opc_handler_t **t1, **t2, **t3, *handler;
11408 int op1, op2, op3;
11409
11410 t1 = cpu->env.opcodes;
11411 for (op1 = 0; op1 < 64; op1++) {
11412 handler = t1[op1];
11413 if (is_indirect_opcode(handler)) {
11414 t2 = ind_table(handler);
11415 for (op2 = 0; op2 < 32; op2++) {
11416 handler = t2[op2];
11417 if (is_indirect_opcode(handler)) {
11418 t3 = ind_table(handler);
11419 for (op3 = 0; op3 < 32; op3++) {
11420 handler = t3[op3];
11421 if (handler->count == 0)
11422 continue;
11423 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11424 "%016" PRIx64 " %" PRId64 "\n",
11425 op1, op2, op3, op1, (op3 << 5) | op2,
11426 handler->oname,
11427 handler->count, handler->count);
11428 }
11429 } else {
11430 if (handler->count == 0)
11431 continue;
11432 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11433 "%016" PRIx64 " %" PRId64 "\n",
11434 op1, op2, op1, op2, handler->oname,
11435 handler->count, handler->count);
11436 }
11437 }
11438 } else {
11439 if (handler->count == 0)
11440 continue;
11441 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11442 " %" PRId64 "\n",
11443 op1, op1, handler->oname,
11444 handler->count, handler->count);
11445 }
11446 }
11447 #endif
11448 }
11449
11450 /*****************************************************************************/
11451 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11452 {
11453 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11454 CPUState *cs = CPU(cpu);
11455 DisasContext ctx, *ctxp = &ctx;
11456 opc_handler_t **table, *handler;
11457 target_ulong pc_start;
11458 int num_insns;
11459 int max_insns;
11460
11461 pc_start = tb->pc;
11462 ctx.nip = pc_start;
11463 ctx.tb = tb;
11464 ctx.exception = POWERPC_EXCP_NONE;
11465 ctx.spr_cb = env->spr_cb;
11466 ctx.pr = msr_pr;
11467 ctx.hv = !msr_pr && msr_hv;
11468 ctx.mem_idx = env->mmu_idx;
11469 ctx.insns_flags = env->insns_flags;
11470 ctx.insns_flags2 = env->insns_flags2;
11471 ctx.access_type = -1;
11472 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11473 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11474 #if defined(TARGET_PPC64)
11475 ctx.sf_mode = msr_is_64bit(env, env->msr);
11476 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11477 #endif
11478 ctx.fpu_enabled = msr_fp;
11479 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11480 ctx.spe_enabled = msr_spe;
11481 else
11482 ctx.spe_enabled = 0;
11483 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11484 ctx.altivec_enabled = msr_vr;
11485 else
11486 ctx.altivec_enabled = 0;
11487 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11488 ctx.vsx_enabled = msr_vsx;
11489 } else {
11490 ctx.vsx_enabled = 0;
11491 }
11492 #if defined(TARGET_PPC64)
11493 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11494 ctx.tm_enabled = msr_tm;
11495 } else {
11496 ctx.tm_enabled = 0;
11497 }
11498 #endif
11499 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11500 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11501 else
11502 ctx.singlestep_enabled = 0;
11503 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11504 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11505 if (unlikely(cs->singlestep_enabled)) {
11506 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11507 }
11508 #if defined (DO_SINGLE_STEP) && 0
11509 /* Single step trace mode */
11510 msr_se = 1;
11511 #endif
11512 num_insns = 0;
11513 max_insns = tb->cflags & CF_COUNT_MASK;
11514 if (max_insns == 0) {
11515 max_insns = CF_COUNT_MASK;
11516 }
11517 if (max_insns > TCG_MAX_INSNS) {
11518 max_insns = TCG_MAX_INSNS;
11519 }
11520
11521 gen_tb_start(tb);
11522 tcg_clear_temp_count();
11523 /* Set env in case of segfault during code fetch */
11524 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11525 tcg_gen_insn_start(ctx.nip);
11526 num_insns++;
11527
11528 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11529 gen_debug_exception(ctxp);
11530 /* The address covered by the breakpoint must be included in
11531 [tb->pc, tb->pc + tb->size) in order to for it to be
11532 properly cleared -- thus we increment the PC here so that
11533 the logic setting tb->size below does the right thing. */
11534 ctx.nip += 4;
11535 break;
11536 }
11537
11538 LOG_DISAS("----------------\n");
11539 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11540 ctx.nip, ctx.mem_idx, (int)msr_ir);
11541 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11542 gen_io_start();
11543 if (unlikely(need_byteswap(&ctx))) {
11544 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11545 } else {
11546 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11547 }
11548 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11549 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11550 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11551 ctx.nip += 4;
11552 table = env->opcodes;
11553 handler = table[opc1(ctx.opcode)];
11554 if (is_indirect_opcode(handler)) {
11555 table = ind_table(handler);
11556 handler = table[opc2(ctx.opcode)];
11557 if (is_indirect_opcode(handler)) {
11558 table = ind_table(handler);
11559 handler = table[opc3(ctx.opcode)];
11560 }
11561 }
11562 /* Is opcode *REALLY* valid ? */
11563 if (unlikely(handler->handler == &gen_invalid)) {
11564 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11565 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11566 opc1(ctx.opcode), opc2(ctx.opcode),
11567 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11568 } else {
11569 uint32_t inval;
11570
11571 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11572 inval = handler->inval2;
11573 } else {
11574 inval = handler->inval1;
11575 }
11576
11577 if (unlikely((ctx.opcode & inval) != 0)) {
11578 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11579 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11580 ctx.opcode & inval, opc1(ctx.opcode),
11581 opc2(ctx.opcode), opc3(ctx.opcode),
11582 ctx.opcode, ctx.nip - 4);
11583 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11584 break;
11585 }
11586 }
11587 (*(handler->handler))(&ctx);
11588 #if defined(DO_PPC_STATISTICS)
11589 handler->count++;
11590 #endif
11591 /* Check trace mode exceptions */
11592 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11593 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11594 ctx.exception != POWERPC_SYSCALL &&
11595 ctx.exception != POWERPC_EXCP_TRAP &&
11596 ctx.exception != POWERPC_EXCP_BRANCH)) {
11597 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11598 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11599 (cs->singlestep_enabled) ||
11600 singlestep ||
11601 num_insns >= max_insns)) {
11602 /* if we reach a page boundary or are single stepping, stop
11603 * generation
11604 */
11605 break;
11606 }
11607 if (tcg_check_temp_count()) {
11608 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11609 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11610 ctx.opcode);
11611 exit(1);
11612 }
11613 }
11614 if (tb->cflags & CF_LAST_IO)
11615 gen_io_end();
11616 if (ctx.exception == POWERPC_EXCP_NONE) {
11617 gen_goto_tb(&ctx, 0, ctx.nip);
11618 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11619 if (unlikely(cs->singlestep_enabled)) {
11620 gen_debug_exception(ctxp);
11621 }
11622 /* Generate the return instruction */
11623 tcg_gen_exit_tb(0);
11624 }
11625 gen_tb_end(tb, num_insns);
11626
11627 tb->size = ctx.nip - pc_start;
11628 tb->icount = num_insns;
11629
11630 #if defined(DEBUG_DISAS)
11631 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11632 int flags;
11633 flags = env->bfd_mach;
11634 flags |= ctx.le_mode << 16;
11635 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11636 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11637 qemu_log("\n");
11638 }
11639 #endif
11640 }
11641
11642 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11643 target_ulong *data)
11644 {
11645 env->nip = data[0];
11646 }
AR7 emulation for QEMU