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target-s390x: fix s390_cpu_initial_reset
[qemu/ar7.git] / linux-user / main.c
blobc855bccadcdb0deeb8432f0be87315e4b624dec8
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cpu.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36
37 char *exec_path;
38
39 int singlestep;
40 const char *filename;
41 const char *argv0;
42 int gdbstub_port;
43 envlist_t *envlist;
44 static const char *cpu_model;
45 unsigned long mmap_min_addr;
46 #if defined(CONFIG_USE_GUEST_BASE)
47 unsigned long guest_base;
48 int have_guest_base;
49 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
50 /*
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
53 *
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
56 */
57 # ifdef TARGET_MIPS
58 /* MIPS only supports 31 bits of virtual address space for user space */
59 unsigned long reserved_va = 0x77000000;
60 # else
61 unsigned long reserved_va = 0xf7000000;
62 # endif
63 #else
64 unsigned long reserved_va;
65 #endif
66 #endif
67
68 static void usage(void);
69
70 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
71 const char *qemu_uname_release;
72
73 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
76 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
77
78 void gemu_log(const char *fmt, ...)
79 {
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85 }
86
87 #if defined(TARGET_I386)
88 int cpu_get_pic_interrupt(CPUX86State *env)
89 {
90 return -1;
91 }
92 #endif
93
94 /***********************************************************/
95 /* Helper routines for implementing atomic operations. */
96
97 /* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
101 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
102 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
103 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
104 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
105 static int pending_cpus;
106
107 /* Make sure everything is in a consistent state for calling fork(). */
108 void fork_start(void)
109 {
110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
111 pthread_mutex_lock(&exclusive_lock);
112 mmap_fork_start();
113 }
114
115 void fork_end(int child)
116 {
117 mmap_fork_end(child);
118 if (child) {
119 CPUState *cpu, *next_cpu;
120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
122 CPU_FOREACH_SAFE(cpu, next_cpu) {
123 if (cpu != thread_cpu) {
124 QTAILQ_REMOVE(&cpus, thread_cpu, node);
125 }
126 }
127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
129 pthread_mutex_init(&cpu_list_mutex, NULL);
130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
133 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
137 }
138 }
139
140 /* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142 static inline void exclusive_idle(void)
143 {
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147 }
148
149 /* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151 static inline void start_exclusive(void)
152 {
153 CPUState *other_cpu;
154
155 pthread_mutex_lock(&exclusive_lock);
156 exclusive_idle();
157
158 pending_cpus = 1;
159 /* Make all other cpus stop executing. */
160 CPU_FOREACH(other_cpu) {
161 if (other_cpu->running) {
162 pending_cpus++;
163 cpu_exit(other_cpu);
164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169 }
170
171 /* Finish an exclusive operation. */
172 static inline void __attribute__((unused)) end_exclusive(void)
173 {
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177 }
178
179 /* Wait for exclusive ops to finish, and begin cpu execution. */
180 static inline void cpu_exec_start(CPUState *cpu)
181 {
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
184 cpu->running = true;
185 pthread_mutex_unlock(&exclusive_lock);
186 }
187
188 /* Mark cpu as not executing, and release pending exclusive ops. */
189 static inline void cpu_exec_end(CPUState *cpu)
190 {
191 pthread_mutex_lock(&exclusive_lock);
192 cpu->running = false;
193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201 }
202
203 void cpu_list_lock(void)
204 {
205 pthread_mutex_lock(&cpu_list_mutex);
206 }
207
208 void cpu_list_unlock(void)
209 {
210 pthread_mutex_unlock(&cpu_list_mutex);
211 }
212
213
214 #ifdef TARGET_I386
215 /***********************************************************/
216 /* CPUX86 core interface */
217
218 uint64_t cpu_get_tsc(CPUX86State *env)
219 {
220 return cpu_get_real_ticks();
221 }
222
223 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
224 int flags)
225 {
226 unsigned int e1, e2;
227 uint32_t *p;
228 e1 = (addr << 16) | (limit & 0xffff);
229 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
230 e2 |= flags;
231 p = ptr;
232 p[0] = tswap32(e1);
233 p[1] = tswap32(e2);
234 }
235
236 static uint64_t *idt_table;
237 #ifdef TARGET_X86_64
238 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
239 uint64_t addr, unsigned int sel)
240 {
241 uint32_t *p, e1, e2;
242 e1 = (addr & 0xffff) | (sel << 16);
243 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
244 p = ptr;
245 p[0] = tswap32(e1);
246 p[1] = tswap32(e2);
247 p[2] = tswap32(addr >> 32);
248 p[3] = 0;
249 }
250 /* only dpl matters as we do only user space emulation */
251 static void set_idt(int n, unsigned int dpl)
252 {
253 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
254 }
255 #else
256 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
257 uint32_t addr, unsigned int sel)
258 {
259 uint32_t *p, e1, e2;
260 e1 = (addr & 0xffff) | (sel << 16);
261 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
262 p = ptr;
263 p[0] = tswap32(e1);
264 p[1] = tswap32(e2);
265 }
266
267 /* only dpl matters as we do only user space emulation */
268 static void set_idt(int n, unsigned int dpl)
269 {
270 set_gate(idt_table + n, 0, dpl, 0, 0);
271 }
272 #endif
273
274 void cpu_loop(CPUX86State *env)
275 {
276 CPUState *cs = CPU(x86_env_get_cpu(env));
277 int trapnr;
278 abi_ulong pc;
279 target_siginfo_t info;
280
281 for(;;) {
282 cpu_exec_start(cs);
283 trapnr = cpu_x86_exec(env);
284 cpu_exec_end(cs);
285 switch(trapnr) {
286 case 0x80:
287 /* linux syscall from int $0x80 */
288 env->regs[R_EAX] = do_syscall(env,
289 env->regs[R_EAX],
290 env->regs[R_EBX],
291 env->regs[R_ECX],
292 env->regs[R_EDX],
293 env->regs[R_ESI],
294 env->regs[R_EDI],
295 env->regs[R_EBP],
296 0, 0);
297 break;
298 #ifndef TARGET_ABI32
299 case EXCP_SYSCALL:
300 /* linux syscall from syscall instruction */
301 env->regs[R_EAX] = do_syscall(env,
302 env->regs[R_EAX],
303 env->regs[R_EDI],
304 env->regs[R_ESI],
305 env->regs[R_EDX],
306 env->regs[10],
307 env->regs[8],
308 env->regs[9],
309 0, 0);
310 break;
311 #endif
312 case EXCP0B_NOSEG:
313 case EXCP0C_STACK:
314 info.si_signo = TARGET_SIGBUS;
315 info.si_errno = 0;
316 info.si_code = TARGET_SI_KERNEL;
317 info._sifields._sigfault._addr = 0;
318 queue_signal(env, info.si_signo, &info);
319 break;
320 case EXCP0D_GPF:
321 /* XXX: potential problem if ABI32 */
322 #ifndef TARGET_X86_64
323 if (env->eflags & VM_MASK) {
324 handle_vm86_fault(env);
325 } else
326 #endif
327 {
328 info.si_signo = TARGET_SIGSEGV;
329 info.si_errno = 0;
330 info.si_code = TARGET_SI_KERNEL;
331 info._sifields._sigfault._addr = 0;
332 queue_signal(env, info.si_signo, &info);
333 }
334 break;
335 case EXCP0E_PAGE:
336 info.si_signo = TARGET_SIGSEGV;
337 info.si_errno = 0;
338 if (!(env->error_code & 1))
339 info.si_code = TARGET_SEGV_MAPERR;
340 else
341 info.si_code = TARGET_SEGV_ACCERR;
342 info._sifields._sigfault._addr = env->cr[2];
343 queue_signal(env, info.si_signo, &info);
344 break;
345 case EXCP00_DIVZ:
346 #ifndef TARGET_X86_64
347 if (env->eflags & VM_MASK) {
348 handle_vm86_trap(env, trapnr);
349 } else
350 #endif
351 {
352 /* division by zero */
353 info.si_signo = TARGET_SIGFPE;
354 info.si_errno = 0;
355 info.si_code = TARGET_FPE_INTDIV;
356 info._sifields._sigfault._addr = env->eip;
357 queue_signal(env, info.si_signo, &info);
358 }
359 break;
360 case EXCP01_DB:
361 case EXCP03_INT3:
362 #ifndef TARGET_X86_64
363 if (env->eflags & VM_MASK) {
364 handle_vm86_trap(env, trapnr);
365 } else
366 #endif
367 {
368 info.si_signo = TARGET_SIGTRAP;
369 info.si_errno = 0;
370 if (trapnr == EXCP01_DB) {
371 info.si_code = TARGET_TRAP_BRKPT;
372 info._sifields._sigfault._addr = env->eip;
373 } else {
374 info.si_code = TARGET_SI_KERNEL;
375 info._sifields._sigfault._addr = 0;
376 }
377 queue_signal(env, info.si_signo, &info);
378 }
379 break;
380 case EXCP04_INTO:
381 case EXCP05_BOUND:
382 #ifndef TARGET_X86_64
383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
385 } else
386 #endif
387 {
388 info.si_signo = TARGET_SIGSEGV;
389 info.si_errno = 0;
390 info.si_code = TARGET_SI_KERNEL;
391 info._sifields._sigfault._addr = 0;
392 queue_signal(env, info.si_signo, &info);
393 }
394 break;
395 case EXCP06_ILLOP:
396 info.si_signo = TARGET_SIGILL;
397 info.si_errno = 0;
398 info.si_code = TARGET_ILL_ILLOPN;
399 info._sifields._sigfault._addr = env->eip;
400 queue_signal(env, info.si_signo, &info);
401 break;
402 case EXCP_INTERRUPT:
403 /* just indicate that signals should be handled asap */
404 break;
405 case EXCP_DEBUG:
406 {
407 int sig;
408
409 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
410 if (sig)
411 {
412 info.si_signo = sig;
413 info.si_errno = 0;
414 info.si_code = TARGET_TRAP_BRKPT;
415 queue_signal(env, info.si_signo, &info);
416 }
417 }
418 break;
419 default:
420 pc = env->segs[R_CS].base + env->eip;
421 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
422 (long)pc, trapnr);
423 abort();
424 }
425 process_pending_signals(env);
426 }
427 }
428 #endif
429
430 #ifdef TARGET_ARM
431
432 #define get_user_code_u32(x, gaddr, doswap) \
433 ({ abi_long __r = get_user_u32((x), (gaddr)); \
434 if (!__r && (doswap)) { \
435 (x) = bswap32(x); \
436 } \
437 __r; \
438 })
439
440 #define get_user_code_u16(x, gaddr, doswap) \
441 ({ abi_long __r = get_user_u16((x), (gaddr)); \
442 if (!__r && (doswap)) { \
443 (x) = bswap16(x); \
444 } \
445 __r; \
446 })
447
448 #ifdef TARGET_ABI32
449 /* Commpage handling -- there is no commpage for AArch64 */
450
451 /*
452 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
453 * Input:
454 * r0 = pointer to oldval
455 * r1 = pointer to newval
456 * r2 = pointer to target value
457 *
458 * Output:
459 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
460 * C set if *ptr was changed, clear if no exchange happened
461 *
462 * Note segv's in kernel helpers are a bit tricky, we can set the
463 * data address sensibly but the PC address is just the entry point.
464 */
465 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
466 {
467 uint64_t oldval, newval, val;
468 uint32_t addr, cpsr;
469 target_siginfo_t info;
470
471 /* Based on the 32 bit code in do_kernel_trap */
472
473 /* XXX: This only works between threads, not between processes.
474 It's probably possible to implement this with native host
475 operations. However things like ldrex/strex are much harder so
476 there's not much point trying. */
477 start_exclusive();
478 cpsr = cpsr_read(env);
479 addr = env->regs[2];
480
481 if (get_user_u64(oldval, env->regs[0])) {
482 env->exception.vaddress = env->regs[0];
483 goto segv;
484 };
485
486 if (get_user_u64(newval, env->regs[1])) {
487 env->exception.vaddress = env->regs[1];
488 goto segv;
489 };
490
491 if (get_user_u64(val, addr)) {
492 env->exception.vaddress = addr;
493 goto segv;
494 }
495
496 if (val == oldval) {
497 val = newval;
498
499 if (put_user_u64(val, addr)) {
500 env->exception.vaddress = addr;
501 goto segv;
502 };
503
504 env->regs[0] = 0;
505 cpsr |= CPSR_C;
506 } else {
507 env->regs[0] = -1;
508 cpsr &= ~CPSR_C;
509 }
510 cpsr_write(env, cpsr, CPSR_C);
511 end_exclusive();
512 return;
513
514 segv:
515 end_exclusive();
516 /* We get the PC of the entry address - which is as good as anything,
517 on a real kernel what you get depends on which mode it uses. */
518 info.si_signo = TARGET_SIGSEGV;
519 info.si_errno = 0;
520 /* XXX: check env->error_code */
521 info.si_code = TARGET_SEGV_MAPERR;
522 info._sifields._sigfault._addr = env->exception.vaddress;
523 queue_signal(env, info.si_signo, &info);
524 }
525
526 /* Handle a jump to the kernel code page. */
527 static int
528 do_kernel_trap(CPUARMState *env)
529 {
530 uint32_t addr;
531 uint32_t cpsr;
532 uint32_t val;
533
534 switch (env->regs[15]) {
535 case 0xffff0fa0: /* __kernel_memory_barrier */
536 /* ??? No-op. Will need to do better for SMP. */
537 break;
538 case 0xffff0fc0: /* __kernel_cmpxchg */
539 /* XXX: This only works between threads, not between processes.
540 It's probably possible to implement this with native host
541 operations. However things like ldrex/strex are much harder so
542 there's not much point trying. */
543 start_exclusive();
544 cpsr = cpsr_read(env);
545 addr = env->regs[2];
546 /* FIXME: This should SEGV if the access fails. */
547 if (get_user_u32(val, addr))
548 val = ~env->regs[0];
549 if (val == env->regs[0]) {
550 val = env->regs[1];
551 /* FIXME: Check for segfaults. */
552 put_user_u32(val, addr);
553 env->regs[0] = 0;
554 cpsr |= CPSR_C;
555 } else {
556 env->regs[0] = -1;
557 cpsr &= ~CPSR_C;
558 }
559 cpsr_write(env, cpsr, CPSR_C);
560 end_exclusive();
561 break;
562 case 0xffff0fe0: /* __kernel_get_tls */
563 env->regs[0] = cpu_get_tls(env);
564 break;
565 case 0xffff0f60: /* __kernel_cmpxchg64 */
566 arm_kernel_cmpxchg64_helper(env);
567 break;
568
569 default:
570 return 1;
571 }
572 /* Jump back to the caller. */
573 addr = env->regs[14];
574 if (addr & 1) {
575 env->thumb = 1;
576 addr &= ~1;
577 }
578 env->regs[15] = addr;
579
580 return 0;
581 }
582
583 /* Store exclusive handling for AArch32 */
584 static int do_strex(CPUARMState *env)
585 {
586 uint64_t val;
587 int size;
588 int rc = 1;
589 int segv = 0;
590 uint32_t addr;
591 start_exclusive();
592 if (env->exclusive_addr != env->exclusive_test) {
593 goto fail;
594 }
595 /* We know we're always AArch32 so the address is in uint32_t range
596 * unless it was the -1 exclusive-monitor-lost value (which won't
597 * match exclusive_test above).
598 */
599 assert(extract64(env->exclusive_addr, 32, 32) == 0);
600 addr = env->exclusive_addr;
601 size = env->exclusive_info & 0xf;
602 switch (size) {
603 case 0:
604 segv = get_user_u8(val, addr);
605 break;
606 case 1:
607 segv = get_user_u16(val, addr);
608 break;
609 case 2:
610 case 3:
611 segv = get_user_u32(val, addr);
612 break;
613 default:
614 abort();
615 }
616 if (segv) {
617 env->exception.vaddress = addr;
618 goto done;
619 }
620 if (size == 3) {
621 uint32_t valhi;
622 segv = get_user_u32(valhi, addr + 4);
623 if (segv) {
624 env->exception.vaddress = addr + 4;
625 goto done;
626 }
627 val = deposit64(val, 32, 32, valhi);
628 }
629 if (val != env->exclusive_val) {
630 goto fail;
631 }
632
633 val = env->regs[(env->exclusive_info >> 8) & 0xf];
634 switch (size) {
635 case 0:
636 segv = put_user_u8(val, addr);
637 break;
638 case 1:
639 segv = put_user_u16(val, addr);
640 break;
641 case 2:
642 case 3:
643 segv = put_user_u32(val, addr);
644 break;
645 }
646 if (segv) {
647 env->exception.vaddress = addr;
648 goto done;
649 }
650 if (size == 3) {
651 val = env->regs[(env->exclusive_info >> 12) & 0xf];
652 segv = put_user_u32(val, addr + 4);
653 if (segv) {
654 env->exception.vaddress = addr + 4;
655 goto done;
656 }
657 }
658 rc = 0;
659 fail:
660 env->regs[15] += 4;
661 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
662 done:
663 end_exclusive();
664 return segv;
665 }
666
667 void cpu_loop(CPUARMState *env)
668 {
669 CPUState *cs = CPU(arm_env_get_cpu(env));
670 int trapnr;
671 unsigned int n, insn;
672 target_siginfo_t info;
673 uint32_t addr;
674
675 for(;;) {
676 cpu_exec_start(cs);
677 trapnr = cpu_arm_exec(env);
678 cpu_exec_end(cs);
679 switch(trapnr) {
680 case EXCP_UDEF:
681 {
682 TaskState *ts = cs->opaque;
683 uint32_t opcode;
684 int rc;
685
686 /* we handle the FPU emulation here, as Linux */
687 /* we get the opcode */
688 /* FIXME - what to do if get_user() fails? */
689 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
690
691 rc = EmulateAll(opcode, &ts->fpa, env);
692 if (rc == 0) { /* illegal instruction */
693 info.si_signo = TARGET_SIGILL;
694 info.si_errno = 0;
695 info.si_code = TARGET_ILL_ILLOPN;
696 info._sifields._sigfault._addr = env->regs[15];
697 queue_signal(env, info.si_signo, &info);
698 } else if (rc < 0) { /* FP exception */
699 int arm_fpe=0;
700
701 /* translate softfloat flags to FPSR flags */
702 if (-rc & float_flag_invalid)
703 arm_fpe |= BIT_IOC;
704 if (-rc & float_flag_divbyzero)
705 arm_fpe |= BIT_DZC;
706 if (-rc & float_flag_overflow)
707 arm_fpe |= BIT_OFC;
708 if (-rc & float_flag_underflow)
709 arm_fpe |= BIT_UFC;
710 if (-rc & float_flag_inexact)
711 arm_fpe |= BIT_IXC;
712
713 FPSR fpsr = ts->fpa.fpsr;
714 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
715
716 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
717 info.si_signo = TARGET_SIGFPE;
718 info.si_errno = 0;
719
720 /* ordered by priority, least first */
721 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
722 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
723 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
724 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
725 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
726
727 info._sifields._sigfault._addr = env->regs[15];
728 queue_signal(env, info.si_signo, &info);
729 } else {
730 env->regs[15] += 4;
731 }
732
733 /* accumulate unenabled exceptions */
734 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
735 fpsr |= BIT_IXC;
736 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
737 fpsr |= BIT_UFC;
738 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
739 fpsr |= BIT_OFC;
740 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
741 fpsr |= BIT_DZC;
742 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
743 fpsr |= BIT_IOC;
744 ts->fpa.fpsr=fpsr;
745 } else { /* everything OK */
746 /* increment PC */
747 env->regs[15] += 4;
748 }
749 }
750 break;
751 case EXCP_SWI:
752 case EXCP_BKPT:
753 {
754 env->eabi = 1;
755 /* system call */
756 if (trapnr == EXCP_BKPT) {
757 if (env->thumb) {
758 /* FIXME - what to do if get_user() fails? */
759 get_user_code_u16(insn, env->regs[15], env->bswap_code);
760 n = insn & 0xff;
761 env->regs[15] += 2;
762 } else {
763 /* FIXME - what to do if get_user() fails? */
764 get_user_code_u32(insn, env->regs[15], env->bswap_code);
765 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
766 env->regs[15] += 4;
767 }
768 } else {
769 if (env->thumb) {
770 /* FIXME - what to do if get_user() fails? */
771 get_user_code_u16(insn, env->regs[15] - 2,
772 env->bswap_code);
773 n = insn & 0xff;
774 } else {
775 /* FIXME - what to do if get_user() fails? */
776 get_user_code_u32(insn, env->regs[15] - 4,
777 env->bswap_code);
778 n = insn & 0xffffff;
779 }
780 }
781
782 if (n == ARM_NR_cacheflush) {
783 /* nop */
784 } else if (n == ARM_NR_semihosting
785 || n == ARM_NR_thumb_semihosting) {
786 env->regs[0] = do_arm_semihosting (env);
787 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
788 /* linux syscall */
789 if (env->thumb || n == 0) {
790 n = env->regs[7];
791 } else {
792 n -= ARM_SYSCALL_BASE;
793 env->eabi = 0;
794 }
795 if ( n > ARM_NR_BASE) {
796 switch (n) {
797 case ARM_NR_cacheflush:
798 /* nop */
799 break;
800 case ARM_NR_set_tls:
801 cpu_set_tls(env, env->regs[0]);
802 env->regs[0] = 0;
803 break;
804 case ARM_NR_breakpoint:
805 env->regs[15] -= env->thumb ? 2 : 4;
806 goto excp_debug;
807 default:
808 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
809 n);
810 env->regs[0] = -TARGET_ENOSYS;
811 break;
812 }
813 } else {
814 env->regs[0] = do_syscall(env,
815 n,
816 env->regs[0],
817 env->regs[1],
818 env->regs[2],
819 env->regs[3],
820 env->regs[4],
821 env->regs[5],
822 0, 0);
823 }
824 } else {
825 goto error;
826 }
827 }
828 break;
829 case EXCP_INTERRUPT:
830 /* just indicate that signals should be handled asap */
831 break;
832 case EXCP_STREX:
833 if (!do_strex(env)) {
834 break;
835 }
836 /* fall through for segv */
837 case EXCP_PREFETCH_ABORT:
838 case EXCP_DATA_ABORT:
839 addr = env->exception.vaddress;
840 {
841 info.si_signo = TARGET_SIGSEGV;
842 info.si_errno = 0;
843 /* XXX: check env->error_code */
844 info.si_code = TARGET_SEGV_MAPERR;
845 info._sifields._sigfault._addr = addr;
846 queue_signal(env, info.si_signo, &info);
847 }
848 break;
849 case EXCP_DEBUG:
850 excp_debug:
851 {
852 int sig;
853
854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
860 queue_signal(env, info.si_signo, &info);
861 }
862 }
863 break;
864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
868 default:
869 error:
870 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
871 trapnr);
872 cpu_dump_state(cs, stderr, fprintf, 0);
873 abort();
874 }
875 process_pending_signals(env);
876 }
877 }
878
879 #else
880
881 /*
882 * Handle AArch64 store-release exclusive
883 *
884 * rs = gets the status result of store exclusive
885 * rt = is the register that is stored
886 * rt2 = is the second register store (in STP)
887 *
888 */
889 static int do_strex_a64(CPUARMState *env)
890 {
891 uint64_t val;
892 int size;
893 bool is_pair;
894 int rc = 1;
895 int segv = 0;
896 uint64_t addr;
897 int rs, rt, rt2;
898
899 start_exclusive();
900 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
901 size = extract32(env->exclusive_info, 0, 2);
902 is_pair = extract32(env->exclusive_info, 2, 1);
903 rs = extract32(env->exclusive_info, 4, 5);
904 rt = extract32(env->exclusive_info, 9, 5);
905 rt2 = extract32(env->exclusive_info, 14, 5);
906
907 addr = env->exclusive_addr;
908
909 if (addr != env->exclusive_test) {
910 goto finish;
911 }
912
913 switch (size) {
914 case 0:
915 segv = get_user_u8(val, addr);
916 break;
917 case 1:
918 segv = get_user_u16(val, addr);
919 break;
920 case 2:
921 segv = get_user_u32(val, addr);
922 break;
923 case 3:
924 segv = get_user_u64(val, addr);
925 break;
926 default:
927 abort();
928 }
929 if (segv) {
930 env->exception.vaddress = addr;
931 goto error;
932 }
933 if (val != env->exclusive_val) {
934 goto finish;
935 }
936 if (is_pair) {
937 if (size == 2) {
938 segv = get_user_u32(val, addr + 4);
939 } else {
940 segv = get_user_u64(val, addr + 8);
941 }
942 if (segv) {
943 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
944 goto error;
945 }
946 if (val != env->exclusive_high) {
947 goto finish;
948 }
949 }
950 /* handle the zero register */
951 val = rt == 31 ? 0 : env->xregs[rt];
952 switch (size) {
953 case 0:
954 segv = put_user_u8(val, addr);
955 break;
956 case 1:
957 segv = put_user_u16(val, addr);
958 break;
959 case 2:
960 segv = put_user_u32(val, addr);
961 break;
962 case 3:
963 segv = put_user_u64(val, addr);
964 break;
965 }
966 if (segv) {
967 goto error;
968 }
969 if (is_pair) {
970 /* handle the zero register */
971 val = rt2 == 31 ? 0 : env->xregs[rt2];
972 if (size == 2) {
973 segv = put_user_u32(val, addr + 4);
974 } else {
975 segv = put_user_u64(val, addr + 8);
976 }
977 if (segv) {
978 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
979 goto error;
980 }
981 }
982 rc = 0;
983 finish:
984 env->pc += 4;
985 /* rs == 31 encodes a write to the ZR, thus throwing away
986 * the status return. This is rather silly but valid.
987 */
988 if (rs < 31) {
989 env->xregs[rs] = rc;
990 }
991 error:
992 /* instruction faulted, PC does not advance */
993 /* either way a strex releases any exclusive lock we have */
994 env->exclusive_addr = -1;
995 end_exclusive();
996 return segv;
997 }
998
999 /* AArch64 main loop */
1000 void cpu_loop(CPUARMState *env)
1001 {
1002 CPUState *cs = CPU(arm_env_get_cpu(env));
1003 int trapnr, sig;
1004 target_siginfo_t info;
1005
1006 for (;;) {
1007 cpu_exec_start(cs);
1008 trapnr = cpu_arm_exec(env);
1009 cpu_exec_end(cs);
1010
1011 switch (trapnr) {
1012 case EXCP_SWI:
1013 env->xregs[0] = do_syscall(env,
1014 env->xregs[8],
1015 env->xregs[0],
1016 env->xregs[1],
1017 env->xregs[2],
1018 env->xregs[3],
1019 env->xregs[4],
1020 env->xregs[5],
1021 0, 0);
1022 break;
1023 case EXCP_INTERRUPT:
1024 /* just indicate that signals should be handled asap */
1025 break;
1026 case EXCP_UDEF:
1027 info.si_signo = TARGET_SIGILL;
1028 info.si_errno = 0;
1029 info.si_code = TARGET_ILL_ILLOPN;
1030 info._sifields._sigfault._addr = env->pc;
1031 queue_signal(env, info.si_signo, &info);
1032 break;
1033 case EXCP_STREX:
1034 if (!do_strex_a64(env)) {
1035 break;
1036 }
1037 /* fall through for segv */
1038 case EXCP_PREFETCH_ABORT:
1039 case EXCP_DATA_ABORT:
1040 info.si_signo = TARGET_SIGSEGV;
1041 info.si_errno = 0;
1042 /* XXX: check env->error_code */
1043 info.si_code = TARGET_SEGV_MAPERR;
1044 info._sifields._sigfault._addr = env->exception.vaddress;
1045 queue_signal(env, info.si_signo, &info);
1046 break;
1047 case EXCP_DEBUG:
1048 case EXCP_BKPT:
1049 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1050 if (sig) {
1051 info.si_signo = sig;
1052 info.si_errno = 0;
1053 info.si_code = TARGET_TRAP_BRKPT;
1054 queue_signal(env, info.si_signo, &info);
1055 }
1056 break;
1057 default:
1058 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1059 trapnr);
1060 cpu_dump_state(cs, stderr, fprintf, 0);
1061 abort();
1062 }
1063 process_pending_signals(env);
1064 /* Exception return on AArch64 always clears the exclusive monitor,
1065 * so any return to running guest code implies this.
1066 * A strex (successful or otherwise) also clears the monitor, so
1067 * we don't need to specialcase EXCP_STREX.
1068 */
1069 env->exclusive_addr = -1;
1070 }
1071 }
1072 #endif /* ndef TARGET_ABI32 */
1073
1074 #endif
1075
1076 #ifdef TARGET_UNICORE32
1077
1078 void cpu_loop(CPUUniCore32State *env)
1079 {
1080 CPUState *cs = CPU(uc32_env_get_cpu(env));
1081 int trapnr;
1082 unsigned int n, insn;
1083 target_siginfo_t info;
1084
1085 for (;;) {
1086 cpu_exec_start(cs);
1087 trapnr = uc32_cpu_exec(env);
1088 cpu_exec_end(cs);
1089 switch (trapnr) {
1090 case UC32_EXCP_PRIV:
1091 {
1092 /* system call */
1093 get_user_u32(insn, env->regs[31] - 4);
1094 n = insn & 0xffffff;
1095
1096 if (n >= UC32_SYSCALL_BASE) {
1097 /* linux syscall */
1098 n -= UC32_SYSCALL_BASE;
1099 if (n == UC32_SYSCALL_NR_set_tls) {
1100 cpu_set_tls(env, env->regs[0]);
1101 env->regs[0] = 0;
1102 } else {
1103 env->regs[0] = do_syscall(env,
1104 n,
1105 env->regs[0],
1106 env->regs[1],
1107 env->regs[2],
1108 env->regs[3],
1109 env->regs[4],
1110 env->regs[5],
1111 0, 0);
1112 }
1113 } else {
1114 goto error;
1115 }
1116 }
1117 break;
1118 case UC32_EXCP_DTRAP:
1119 case UC32_EXCP_ITRAP:
1120 info.si_signo = TARGET_SIGSEGV;
1121 info.si_errno = 0;
1122 /* XXX: check env->error_code */
1123 info.si_code = TARGET_SEGV_MAPERR;
1124 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1125 queue_signal(env, info.si_signo, &info);
1126 break;
1127 case EXCP_INTERRUPT:
1128 /* just indicate that signals should be handled asap */
1129 break;
1130 case EXCP_DEBUG:
1131 {
1132 int sig;
1133
1134 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1135 if (sig) {
1136 info.si_signo = sig;
1137 info.si_errno = 0;
1138 info.si_code = TARGET_TRAP_BRKPT;
1139 queue_signal(env, info.si_signo, &info);
1140 }
1141 }
1142 break;
1143 default:
1144 goto error;
1145 }
1146 process_pending_signals(env);
1147 }
1148
1149 error:
1150 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1151 cpu_dump_state(cs, stderr, fprintf, 0);
1152 abort();
1153 }
1154 #endif
1155
1156 #ifdef TARGET_SPARC
1157 #define SPARC64_STACK_BIAS 2047
1158
1159 //#define DEBUG_WIN
1160
1161 /* WARNING: dealing with register windows _is_ complicated. More info
1162 can be found at http://www.sics.se/~psm/sparcstack.html */
1163 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1164 {
1165 index = (index + cwp * 16) % (16 * env->nwindows);
1166 /* wrap handling : if cwp is on the last window, then we use the
1167 registers 'after' the end */
1168 if (index < 8 && env->cwp == env->nwindows - 1)
1169 index += 16 * env->nwindows;
1170 return index;
1171 }
1172
1173 /* save the register window 'cwp1' */
1174 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1175 {
1176 unsigned int i;
1177 abi_ulong sp_ptr;
1178
1179 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1180 #ifdef TARGET_SPARC64
1181 if (sp_ptr & 3)
1182 sp_ptr += SPARC64_STACK_BIAS;
1183 #endif
1184 #if defined(DEBUG_WIN)
1185 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1186 sp_ptr, cwp1);
1187 #endif
1188 for(i = 0; i < 16; i++) {
1189 /* FIXME - what to do if put_user() fails? */
1190 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1191 sp_ptr += sizeof(abi_ulong);
1192 }
1193 }
1194
1195 static void save_window(CPUSPARCState *env)
1196 {
1197 #ifndef TARGET_SPARC64
1198 unsigned int new_wim;
1199 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1200 ((1LL << env->nwindows) - 1);
1201 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1202 env->wim = new_wim;
1203 #else
1204 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1205 env->cansave++;
1206 env->canrestore--;
1207 #endif
1208 }
1209
1210 static void restore_window(CPUSPARCState *env)
1211 {
1212 #ifndef TARGET_SPARC64
1213 unsigned int new_wim;
1214 #endif
1215 unsigned int i, cwp1;
1216 abi_ulong sp_ptr;
1217
1218 #ifndef TARGET_SPARC64
1219 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1220 ((1LL << env->nwindows) - 1);
1221 #endif
1222
1223 /* restore the invalid window */
1224 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1225 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1226 #ifdef TARGET_SPARC64
1227 if (sp_ptr & 3)
1228 sp_ptr += SPARC64_STACK_BIAS;
1229 #endif
1230 #if defined(DEBUG_WIN)
1231 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1232 sp_ptr, cwp1);
1233 #endif
1234 for(i = 0; i < 16; i++) {
1235 /* FIXME - what to do if get_user() fails? */
1236 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1237 sp_ptr += sizeof(abi_ulong);
1238 }
1239 #ifdef TARGET_SPARC64
1240 env->canrestore++;
1241 if (env->cleanwin < env->nwindows - 1)
1242 env->cleanwin++;
1243 env->cansave--;
1244 #else
1245 env->wim = new_wim;
1246 #endif
1247 }
1248
1249 static void flush_windows(CPUSPARCState *env)
1250 {
1251 int offset, cwp1;
1252
1253 offset = 1;
1254 for(;;) {
1255 /* if restore would invoke restore_window(), then we can stop */
1256 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1257 #ifndef TARGET_SPARC64
1258 if (env->wim & (1 << cwp1))
1259 break;
1260 #else
1261 if (env->canrestore == 0)
1262 break;
1263 env->cansave++;
1264 env->canrestore--;
1265 #endif
1266 save_window_offset(env, cwp1);
1267 offset++;
1268 }
1269 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1270 #ifndef TARGET_SPARC64
1271 /* set wim so that restore will reload the registers */
1272 env->wim = 1 << cwp1;
1273 #endif
1274 #if defined(DEBUG_WIN)
1275 printf("flush_windows: nb=%d\n", offset - 1);
1276 #endif
1277 }
1278
1279 void cpu_loop (CPUSPARCState *env)
1280 {
1281 CPUState *cs = CPU(sparc_env_get_cpu(env));
1282 int trapnr;
1283 abi_long ret;
1284 target_siginfo_t info;
1285
1286 while (1) {
1287 cpu_exec_start(cs);
1288 trapnr = cpu_sparc_exec (env);
1289 cpu_exec_end(cs);
1290
1291 /* Compute PSR before exposing state. */
1292 if (env->cc_op != CC_OP_FLAGS) {
1293 cpu_get_psr(env);
1294 }
1295
1296 switch (trapnr) {
1297 #ifndef TARGET_SPARC64
1298 case 0x88:
1299 case 0x90:
1300 #else
1301 case 0x110:
1302 case 0x16d:
1303 #endif
1304 ret = do_syscall (env, env->gregs[1],
1305 env->regwptr[0], env->regwptr[1],
1306 env->regwptr[2], env->regwptr[3],
1307 env->regwptr[4], env->regwptr[5],
1308 0, 0);
1309 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1310 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1311 env->xcc |= PSR_CARRY;
1312 #else
1313 env->psr |= PSR_CARRY;
1314 #endif
1315 ret = -ret;
1316 } else {
1317 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1318 env->xcc &= ~PSR_CARRY;
1319 #else
1320 env->psr &= ~PSR_CARRY;
1321 #endif
1322 }
1323 env->regwptr[0] = ret;
1324 /* next instruction */
1325 env->pc = env->npc;
1326 env->npc = env->npc + 4;
1327 break;
1328 case 0x83: /* flush windows */
1329 #ifdef TARGET_ABI32
1330 case 0x103:
1331 #endif
1332 flush_windows(env);
1333 /* next instruction */
1334 env->pc = env->npc;
1335 env->npc = env->npc + 4;
1336 break;
1337 #ifndef TARGET_SPARC64
1338 case TT_WIN_OVF: /* window overflow */
1339 save_window(env);
1340 break;
1341 case TT_WIN_UNF: /* window underflow */
1342 restore_window(env);
1343 break;
1344 case TT_TFAULT:
1345 case TT_DFAULT:
1346 {
1347 info.si_signo = TARGET_SIGSEGV;
1348 info.si_errno = 0;
1349 /* XXX: check env->error_code */
1350 info.si_code = TARGET_SEGV_MAPERR;
1351 info._sifields._sigfault._addr = env->mmuregs[4];
1352 queue_signal(env, info.si_signo, &info);
1353 }
1354 break;
1355 #else
1356 case TT_SPILL: /* window overflow */
1357 save_window(env);
1358 break;
1359 case TT_FILL: /* window underflow */
1360 restore_window(env);
1361 break;
1362 case TT_TFAULT:
1363 case TT_DFAULT:
1364 {
1365 info.si_signo = TARGET_SIGSEGV;
1366 info.si_errno = 0;
1367 /* XXX: check env->error_code */
1368 info.si_code = TARGET_SEGV_MAPERR;
1369 if (trapnr == TT_DFAULT)
1370 info._sifields._sigfault._addr = env->dmmuregs[4];
1371 else
1372 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1373 queue_signal(env, info.si_signo, &info);
1374 }
1375 break;
1376 #ifndef TARGET_ABI32
1377 case 0x16e:
1378 flush_windows(env);
1379 sparc64_get_context(env);
1380 break;
1381 case 0x16f:
1382 flush_windows(env);
1383 sparc64_set_context(env);
1384 break;
1385 #endif
1386 #endif
1387 case EXCP_INTERRUPT:
1388 /* just indicate that signals should be handled asap */
1389 break;
1390 case TT_ILL_INSN:
1391 {
1392 info.si_signo = TARGET_SIGILL;
1393 info.si_errno = 0;
1394 info.si_code = TARGET_ILL_ILLOPC;
1395 info._sifields._sigfault._addr = env->pc;
1396 queue_signal(env, info.si_signo, &info);
1397 }
1398 break;
1399 case EXCP_DEBUG:
1400 {
1401 int sig;
1402
1403 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1404 if (sig)
1405 {
1406 info.si_signo = sig;
1407 info.si_errno = 0;
1408 info.si_code = TARGET_TRAP_BRKPT;
1409 queue_signal(env, info.si_signo, &info);
1410 }
1411 }
1412 break;
1413 default:
1414 printf ("Unhandled trap: 0x%x\n", trapnr);
1415 cpu_dump_state(cs, stderr, fprintf, 0);
1416 exit (1);
1417 }
1418 process_pending_signals (env);
1419 }
1420 }
1421
1422 #endif
1423
1424 #ifdef TARGET_PPC
1425 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1426 {
1427 /* TO FIX */
1428 return 0;
1429 }
1430
1431 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1432 {
1433 return cpu_ppc_get_tb(env);
1434 }
1435
1436 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1437 {
1438 return cpu_ppc_get_tb(env) >> 32;
1439 }
1440
1441 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1442 {
1443 return cpu_ppc_get_tb(env);
1444 }
1445
1446 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1447 {
1448 return cpu_ppc_get_tb(env) >> 32;
1449 }
1450
1451 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1452 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1453
1454 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1455 {
1456 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1457 }
1458
1459 /* XXX: to be fixed */
1460 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1461 {
1462 return -1;
1463 }
1464
1465 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1466 {
1467 return -1;
1468 }
1469
1470 #define EXCP_DUMP(env, fmt, ...) \
1471 do { \
1472 CPUState *cs = ENV_GET_CPU(env); \
1473 fprintf(stderr, fmt , ## __VA_ARGS__); \
1474 cpu_dump_state(cs, stderr, fprintf, 0); \
1475 qemu_log(fmt, ## __VA_ARGS__); \
1476 if (qemu_log_enabled()) { \
1477 log_cpu_state(cs, 0); \
1478 } \
1479 } while (0)
1480
1481 static int do_store_exclusive(CPUPPCState *env)
1482 {
1483 target_ulong addr;
1484 target_ulong page_addr;
1485 target_ulong val, val2 __attribute__((unused)) = 0;
1486 int flags;
1487 int segv = 0;
1488
1489 addr = env->reserve_ea;
1490 page_addr = addr & TARGET_PAGE_MASK;
1491 start_exclusive();
1492 mmap_lock();
1493 flags = page_get_flags(page_addr);
1494 if ((flags & PAGE_READ) == 0) {
1495 segv = 1;
1496 } else {
1497 int reg = env->reserve_info & 0x1f;
1498 int size = env->reserve_info >> 5;
1499 int stored = 0;
1500
1501 if (addr == env->reserve_addr) {
1502 switch (size) {
1503 case 1: segv = get_user_u8(val, addr); break;
1504 case 2: segv = get_user_u16(val, addr); break;
1505 case 4: segv = get_user_u32(val, addr); break;
1506 #if defined(TARGET_PPC64)
1507 case 8: segv = get_user_u64(val, addr); break;
1508 case 16: {
1509 segv = get_user_u64(val, addr);
1510 if (!segv) {
1511 segv = get_user_u64(val2, addr + 8);
1512 }
1513 break;
1514 }
1515 #endif
1516 default: abort();
1517 }
1518 if (!segv && val == env->reserve_val) {
1519 val = env->gpr[reg];
1520 switch (size) {
1521 case 1: segv = put_user_u8(val, addr); break;
1522 case 2: segv = put_user_u16(val, addr); break;
1523 case 4: segv = put_user_u32(val, addr); break;
1524 #if defined(TARGET_PPC64)
1525 case 8: segv = put_user_u64(val, addr); break;
1526 case 16: {
1527 if (val2 == env->reserve_val2) {
1528 if (msr_le) {
1529 val2 = val;
1530 val = env->gpr[reg+1];
1531 } else {
1532 val2 = env->gpr[reg+1];
1533 }
1534 segv = put_user_u64(val, addr);
1535 if (!segv) {
1536 segv = put_user_u64(val2, addr + 8);
1537 }
1538 }
1539 break;
1540 }
1541 #endif
1542 default: abort();
1543 }
1544 if (!segv) {
1545 stored = 1;
1546 }
1547 }
1548 }
1549 env->crf[0] = (stored << 1) | xer_so;
1550 env->reserve_addr = (target_ulong)-1;
1551 }
1552 if (!segv) {
1553 env->nip += 4;
1554 }
1555 mmap_unlock();
1556 end_exclusive();
1557 return segv;
1558 }
1559
1560 void cpu_loop(CPUPPCState *env)
1561 {
1562 CPUState *cs = CPU(ppc_env_get_cpu(env));
1563 target_siginfo_t info;
1564 int trapnr;
1565 target_ulong ret;
1566
1567 for(;;) {
1568 cpu_exec_start(cs);
1569 trapnr = cpu_ppc_exec(env);
1570 cpu_exec_end(cs);
1571 switch(trapnr) {
1572 case POWERPC_EXCP_NONE:
1573 /* Just go on */
1574 break;
1575 case POWERPC_EXCP_CRITICAL: /* Critical input */
1576 cpu_abort(cs, "Critical interrupt while in user mode. "
1577 "Aborting\n");
1578 break;
1579 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1580 cpu_abort(cs, "Machine check exception while in user mode. "
1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_DSI: /* Data storage exception */
1584 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1585 env->spr[SPR_DAR]);
1586 /* XXX: check this. Seems bugged */
1587 switch (env->error_code & 0xFF000000) {
1588 case 0x40000000:
1589 info.si_signo = TARGET_SIGSEGV;
1590 info.si_errno = 0;
1591 info.si_code = TARGET_SEGV_MAPERR;
1592 break;
1593 case 0x04000000:
1594 info.si_signo = TARGET_SIGILL;
1595 info.si_errno = 0;
1596 info.si_code = TARGET_ILL_ILLADR;
1597 break;
1598 case 0x08000000:
1599 info.si_signo = TARGET_SIGSEGV;
1600 info.si_errno = 0;
1601 info.si_code = TARGET_SEGV_ACCERR;
1602 break;
1603 default:
1604 /* Let's send a regular segfault... */
1605 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1606 env->error_code);
1607 info.si_signo = TARGET_SIGSEGV;
1608 info.si_errno = 0;
1609 info.si_code = TARGET_SEGV_MAPERR;
1610 break;
1611 }
1612 info._sifields._sigfault._addr = env->nip;
1613 queue_signal(env, info.si_signo, &info);
1614 break;
1615 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1616 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1617 "\n", env->spr[SPR_SRR0]);
1618 /* XXX: check this */
1619 switch (env->error_code & 0xFF000000) {
1620 case 0x40000000:
1621 info.si_signo = TARGET_SIGSEGV;
1622 info.si_errno = 0;
1623 info.si_code = TARGET_SEGV_MAPERR;
1624 break;
1625 case 0x10000000:
1626 case 0x08000000:
1627 info.si_signo = TARGET_SIGSEGV;
1628 info.si_errno = 0;
1629 info.si_code = TARGET_SEGV_ACCERR;
1630 break;
1631 default:
1632 /* Let's send a regular segfault... */
1633 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1634 env->error_code);
1635 info.si_signo = TARGET_SIGSEGV;
1636 info.si_errno = 0;
1637 info.si_code = TARGET_SEGV_MAPERR;
1638 break;
1639 }
1640 info._sifields._sigfault._addr = env->nip - 4;
1641 queue_signal(env, info.si_signo, &info);
1642 break;
1643 case POWERPC_EXCP_EXTERNAL: /* External input */
1644 cpu_abort(cs, "External interrupt while in user mode. "
1645 "Aborting\n");
1646 break;
1647 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1648 EXCP_DUMP(env, "Unaligned memory access\n");
1649 /* XXX: check this */
1650 info.si_signo = TARGET_SIGBUS;
1651 info.si_errno = 0;
1652 info.si_code = TARGET_BUS_ADRALN;
1653 info._sifields._sigfault._addr = env->nip - 4;
1654 queue_signal(env, info.si_signo, &info);
1655 break;
1656 case POWERPC_EXCP_PROGRAM: /* Program exception */
1657 /* XXX: check this */
1658 switch (env->error_code & ~0xF) {
1659 case POWERPC_EXCP_FP:
1660 EXCP_DUMP(env, "Floating point program exception\n");
1661 info.si_signo = TARGET_SIGFPE;
1662 info.si_errno = 0;
1663 switch (env->error_code & 0xF) {
1664 case POWERPC_EXCP_FP_OX:
1665 info.si_code = TARGET_FPE_FLTOVF;
1666 break;
1667 case POWERPC_EXCP_FP_UX:
1668 info.si_code = TARGET_FPE_FLTUND;
1669 break;
1670 case POWERPC_EXCP_FP_ZX:
1671 case POWERPC_EXCP_FP_VXZDZ:
1672 info.si_code = TARGET_FPE_FLTDIV;
1673 break;
1674 case POWERPC_EXCP_FP_XX:
1675 info.si_code = TARGET_FPE_FLTRES;
1676 break;
1677 case POWERPC_EXCP_FP_VXSOFT:
1678 info.si_code = TARGET_FPE_FLTINV;
1679 break;
1680 case POWERPC_EXCP_FP_VXSNAN:
1681 case POWERPC_EXCP_FP_VXISI:
1682 case POWERPC_EXCP_FP_VXIDI:
1683 case POWERPC_EXCP_FP_VXIMZ:
1684 case POWERPC_EXCP_FP_VXVC:
1685 case POWERPC_EXCP_FP_VXSQRT:
1686 case POWERPC_EXCP_FP_VXCVI:
1687 info.si_code = TARGET_FPE_FLTSUB;
1688 break;
1689 default:
1690 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1691 env->error_code);
1692 break;
1693 }
1694 break;
1695 case POWERPC_EXCP_INVAL:
1696 EXCP_DUMP(env, "Invalid instruction\n");
1697 info.si_signo = TARGET_SIGILL;
1698 info.si_errno = 0;
1699 switch (env->error_code & 0xF) {
1700 case POWERPC_EXCP_INVAL_INVAL:
1701 info.si_code = TARGET_ILL_ILLOPC;
1702 break;
1703 case POWERPC_EXCP_INVAL_LSWX:
1704 info.si_code = TARGET_ILL_ILLOPN;
1705 break;
1706 case POWERPC_EXCP_INVAL_SPR:
1707 info.si_code = TARGET_ILL_PRVREG;
1708 break;
1709 case POWERPC_EXCP_INVAL_FP:
1710 info.si_code = TARGET_ILL_COPROC;
1711 break;
1712 default:
1713 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1714 env->error_code & 0xF);
1715 info.si_code = TARGET_ILL_ILLADR;
1716 break;
1717 }
1718 break;
1719 case POWERPC_EXCP_PRIV:
1720 EXCP_DUMP(env, "Privilege violation\n");
1721 info.si_signo = TARGET_SIGILL;
1722 info.si_errno = 0;
1723 switch (env->error_code & 0xF) {
1724 case POWERPC_EXCP_PRIV_OPC:
1725 info.si_code = TARGET_ILL_PRVOPC;
1726 break;
1727 case POWERPC_EXCP_PRIV_REG:
1728 info.si_code = TARGET_ILL_PRVREG;
1729 break;
1730 default:
1731 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1732 env->error_code & 0xF);
1733 info.si_code = TARGET_ILL_PRVOPC;
1734 break;
1735 }
1736 break;
1737 case POWERPC_EXCP_TRAP:
1738 cpu_abort(cs, "Tried to call a TRAP\n");
1739 break;
1740 default:
1741 /* Should not happen ! */
1742 cpu_abort(cs, "Unknown program exception (%02x)\n",
1743 env->error_code);
1744 break;
1745 }
1746 info._sifields._sigfault._addr = env->nip - 4;
1747 queue_signal(env, info.si_signo, &info);
1748 break;
1749 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1750 EXCP_DUMP(env, "No floating point allowed\n");
1751 info.si_signo = TARGET_SIGILL;
1752 info.si_errno = 0;
1753 info.si_code = TARGET_ILL_COPROC;
1754 info._sifields._sigfault._addr = env->nip - 4;
1755 queue_signal(env, info.si_signo, &info);
1756 break;
1757 case POWERPC_EXCP_SYSCALL: /* System call exception */
1758 cpu_abort(cs, "Syscall exception while in user mode. "
1759 "Aborting\n");
1760 break;
1761 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1762 EXCP_DUMP(env, "No APU instruction allowed\n");
1763 info.si_signo = TARGET_SIGILL;
1764 info.si_errno = 0;
1765 info.si_code = TARGET_ILL_COPROC;
1766 info._sifields._sigfault._addr = env->nip - 4;
1767 queue_signal(env, info.si_signo, &info);
1768 break;
1769 case POWERPC_EXCP_DECR: /* Decrementer exception */
1770 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1771 "Aborting\n");
1772 break;
1773 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1774 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1775 "Aborting\n");
1776 break;
1777 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1778 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_DTLB: /* Data TLB error */
1782 cpu_abort(cs, "Data TLB exception while in user mode. "
1783 "Aborting\n");
1784 break;
1785 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1786 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1787 "Aborting\n");
1788 break;
1789 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1790 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1791 info.si_signo = TARGET_SIGILL;
1792 info.si_errno = 0;
1793 info.si_code = TARGET_ILL_COPROC;
1794 info._sifields._sigfault._addr = env->nip - 4;
1795 queue_signal(env, info.si_signo, &info);
1796 break;
1797 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1798 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1799 break;
1800 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1801 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1802 break;
1803 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1804 cpu_abort(cs, "Performance monitor exception not handled\n");
1805 break;
1806 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1807 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1811 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_RESET: /* System reset exception */
1815 cpu_abort(cs, "Reset interrupt while in user mode. "
1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_DSEG: /* Data segment exception */
1819 cpu_abort(cs, "Data segment exception while in user mode. "
1820 "Aborting\n");
1821 break;
1822 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1823 cpu_abort(cs, "Instruction segment exception "
1824 "while in user mode. Aborting\n");
1825 break;
1826 /* PowerPC 64 with hypervisor mode support */
1827 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1828 cpu_abort(cs, "Hypervisor decrementer interrupt "
1829 "while in user mode. Aborting\n");
1830 break;
1831 case POWERPC_EXCP_TRACE: /* Trace exception */
1832 /* Nothing to do:
1833 * we use this exception to emulate step-by-step execution mode.
1834 */
1835 break;
1836 /* PowerPC 64 with hypervisor mode support */
1837 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1838 cpu_abort(cs, "Hypervisor data storage exception "
1839 "while in user mode. Aborting\n");
1840 break;
1841 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1842 cpu_abort(cs, "Hypervisor instruction storage exception "
1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1846 cpu_abort(cs, "Hypervisor data segment exception "
1847 "while in user mode. Aborting\n");
1848 break;
1849 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1850 cpu_abort(cs, "Hypervisor instruction segment exception "
1851 "while in user mode. Aborting\n");
1852 break;
1853 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1854 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1855 info.si_signo = TARGET_SIGILL;
1856 info.si_errno = 0;
1857 info.si_code = TARGET_ILL_COPROC;
1858 info._sifields._sigfault._addr = env->nip - 4;
1859 queue_signal(env, info.si_signo, &info);
1860 break;
1861 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1862 cpu_abort(cs, "Programmable interval timer interrupt "
1863 "while in user mode. Aborting\n");
1864 break;
1865 case POWERPC_EXCP_IO: /* IO error exception */
1866 cpu_abort(cs, "IO error exception while in user mode. "
1867 "Aborting\n");
1868 break;
1869 case POWERPC_EXCP_RUNM: /* Run mode exception */
1870 cpu_abort(cs, "Run mode exception while in user mode. "
1871 "Aborting\n");
1872 break;
1873 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1874 cpu_abort(cs, "Emulation trap exception not handled\n");
1875 break;
1876 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1877 cpu_abort(cs, "Instruction fetch TLB exception "
1878 "while in user-mode. Aborting");
1879 break;
1880 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1881 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1882 "Aborting");
1883 break;
1884 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1885 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1886 "Aborting");
1887 break;
1888 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1889 cpu_abort(cs, "Floating-point assist exception not handled\n");
1890 break;
1891 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1892 cpu_abort(cs, "Instruction address breakpoint exception "
1893 "not handled\n");
1894 break;
1895 case POWERPC_EXCP_SMI: /* System management interrupt */
1896 cpu_abort(cs, "System management interrupt while in user mode. "
1897 "Aborting\n");
1898 break;
1899 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1900 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1904 cpu_abort(cs, "Performance monitor exception not handled\n");
1905 break;
1906 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1907 cpu_abort(cs, "Vector assist exception not handled\n");
1908 break;
1909 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1910 cpu_abort(cs, "Soft patch exception not handled\n");
1911 break;
1912 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1913 cpu_abort(cs, "Maintenance exception while in user mode. "
1914 "Aborting\n");
1915 break;
1916 case POWERPC_EXCP_STOP: /* stop translation */
1917 /* We did invalidate the instruction cache. Go on */
1918 break;
1919 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1920 /* We just stopped because of a branch. Go on */
1921 break;
1922 case POWERPC_EXCP_SYSCALL_USER:
1923 /* system call in user-mode emulation */
1924 /* WARNING:
1925 * PPC ABI uses overflow flag in cr0 to signal an error
1926 * in syscalls.
1927 */
1928 env->crf[0] &= ~0x1;
1929 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1930 env->gpr[5], env->gpr[6], env->gpr[7],
1931 env->gpr[8], 0, 0);
1932 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1933 /* Returning from a successful sigreturn syscall.
1934 Avoid corrupting register state. */
1935 break;
1936 }
1937 if (ret > (target_ulong)(-515)) {
1938 env->crf[0] |= 0x1;
1939 ret = -ret;
1940 }
1941 env->gpr[3] = ret;
1942 break;
1943 case POWERPC_EXCP_STCX:
1944 if (do_store_exclusive(env)) {
1945 info.si_signo = TARGET_SIGSEGV;
1946 info.si_errno = 0;
1947 info.si_code = TARGET_SEGV_MAPERR;
1948 info._sifields._sigfault._addr = env->nip;
1949 queue_signal(env, info.si_signo, &info);
1950 }
1951 break;
1952 case EXCP_DEBUG:
1953 {
1954 int sig;
1955
1956 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1957 if (sig) {
1958 info.si_signo = sig;
1959 info.si_errno = 0;
1960 info.si_code = TARGET_TRAP_BRKPT;
1961 queue_signal(env, info.si_signo, &info);
1962 }
1963 }
1964 break;
1965 case EXCP_INTERRUPT:
1966 /* just indicate that signals should be handled asap */
1967 break;
1968 default:
1969 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
1970 break;
1971 }
1972 process_pending_signals(env);
1973 }
1974 }
1975 #endif
1976
1977 #ifdef TARGET_MIPS
1978
1979 # ifdef TARGET_ABI_MIPSO32
1980 # define MIPS_SYS(name, args) args,
1981 static const uint8_t mips_syscall_args[] = {
1982 MIPS_SYS(sys_syscall , 8) /* 4000 */
1983 MIPS_SYS(sys_exit , 1)
1984 MIPS_SYS(sys_fork , 0)
1985 MIPS_SYS(sys_read , 3)
1986 MIPS_SYS(sys_write , 3)
1987 MIPS_SYS(sys_open , 3) /* 4005 */
1988 MIPS_SYS(sys_close , 1)
1989 MIPS_SYS(sys_waitpid , 3)
1990 MIPS_SYS(sys_creat , 2)
1991 MIPS_SYS(sys_link , 2)
1992 MIPS_SYS(sys_unlink , 1) /* 4010 */
1993 MIPS_SYS(sys_execve , 0)
1994 MIPS_SYS(sys_chdir , 1)
1995 MIPS_SYS(sys_time , 1)
1996 MIPS_SYS(sys_mknod , 3)
1997 MIPS_SYS(sys_chmod , 2) /* 4015 */
1998 MIPS_SYS(sys_lchown , 3)
1999 MIPS_SYS(sys_ni_syscall , 0)
2000 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2001 MIPS_SYS(sys_lseek , 3)
2002 MIPS_SYS(sys_getpid , 0) /* 4020 */
2003 MIPS_SYS(sys_mount , 5)
2004 MIPS_SYS(sys_umount , 1)
2005 MIPS_SYS(sys_setuid , 1)
2006 MIPS_SYS(sys_getuid , 0)
2007 MIPS_SYS(sys_stime , 1) /* 4025 */
2008 MIPS_SYS(sys_ptrace , 4)
2009 MIPS_SYS(sys_alarm , 1)
2010 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2011 MIPS_SYS(sys_pause , 0)
2012 MIPS_SYS(sys_utime , 2) /* 4030 */
2013 MIPS_SYS(sys_ni_syscall , 0)
2014 MIPS_SYS(sys_ni_syscall , 0)
2015 MIPS_SYS(sys_access , 2)
2016 MIPS_SYS(sys_nice , 1)
2017 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2018 MIPS_SYS(sys_sync , 0)
2019 MIPS_SYS(sys_kill , 2)
2020 MIPS_SYS(sys_rename , 2)
2021 MIPS_SYS(sys_mkdir , 2)
2022 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2023 MIPS_SYS(sys_dup , 1)
2024 MIPS_SYS(sys_pipe , 0)
2025 MIPS_SYS(sys_times , 1)
2026 MIPS_SYS(sys_ni_syscall , 0)
2027 MIPS_SYS(sys_brk , 1) /* 4045 */
2028 MIPS_SYS(sys_setgid , 1)
2029 MIPS_SYS(sys_getgid , 0)
2030 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2031 MIPS_SYS(sys_geteuid , 0)
2032 MIPS_SYS(sys_getegid , 0) /* 4050 */
2033 MIPS_SYS(sys_acct , 0)
2034 MIPS_SYS(sys_umount2 , 2)
2035 MIPS_SYS(sys_ni_syscall , 0)
2036 MIPS_SYS(sys_ioctl , 3)
2037 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2038 MIPS_SYS(sys_ni_syscall , 2)
2039 MIPS_SYS(sys_setpgid , 2)
2040 MIPS_SYS(sys_ni_syscall , 0)
2041 MIPS_SYS(sys_olduname , 1)
2042 MIPS_SYS(sys_umask , 1) /* 4060 */
2043 MIPS_SYS(sys_chroot , 1)
2044 MIPS_SYS(sys_ustat , 2)
2045 MIPS_SYS(sys_dup2 , 2)
2046 MIPS_SYS(sys_getppid , 0)
2047 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2048 MIPS_SYS(sys_setsid , 0)
2049 MIPS_SYS(sys_sigaction , 3)
2050 MIPS_SYS(sys_sgetmask , 0)
2051 MIPS_SYS(sys_ssetmask , 1)
2052 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2053 MIPS_SYS(sys_setregid , 2)
2054 MIPS_SYS(sys_sigsuspend , 0)
2055 MIPS_SYS(sys_sigpending , 1)
2056 MIPS_SYS(sys_sethostname , 2)
2057 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2058 MIPS_SYS(sys_getrlimit , 2)
2059 MIPS_SYS(sys_getrusage , 2)
2060 MIPS_SYS(sys_gettimeofday, 2)
2061 MIPS_SYS(sys_settimeofday, 2)
2062 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2063 MIPS_SYS(sys_setgroups , 2)
2064 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2065 MIPS_SYS(sys_symlink , 2)
2066 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2067 MIPS_SYS(sys_readlink , 3) /* 4085 */
2068 MIPS_SYS(sys_uselib , 1)
2069 MIPS_SYS(sys_swapon , 2)
2070 MIPS_SYS(sys_reboot , 3)
2071 MIPS_SYS(old_readdir , 3)
2072 MIPS_SYS(old_mmap , 6) /* 4090 */
2073 MIPS_SYS(sys_munmap , 2)
2074 MIPS_SYS(sys_truncate , 2)
2075 MIPS_SYS(sys_ftruncate , 2)
2076 MIPS_SYS(sys_fchmod , 2)
2077 MIPS_SYS(sys_fchown , 3) /* 4095 */
2078 MIPS_SYS(sys_getpriority , 2)
2079 MIPS_SYS(sys_setpriority , 3)
2080 MIPS_SYS(sys_ni_syscall , 0)
2081 MIPS_SYS(sys_statfs , 2)
2082 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2083 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2084 MIPS_SYS(sys_socketcall , 2)
2085 MIPS_SYS(sys_syslog , 3)
2086 MIPS_SYS(sys_setitimer , 3)
2087 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2088 MIPS_SYS(sys_newstat , 2)
2089 MIPS_SYS(sys_newlstat , 2)
2090 MIPS_SYS(sys_newfstat , 2)
2091 MIPS_SYS(sys_uname , 1)
2092 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2093 MIPS_SYS(sys_vhangup , 0)
2094 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2095 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2096 MIPS_SYS(sys_wait4 , 4)
2097 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2098 MIPS_SYS(sys_sysinfo , 1)
2099 MIPS_SYS(sys_ipc , 6)
2100 MIPS_SYS(sys_fsync , 1)
2101 MIPS_SYS(sys_sigreturn , 0)
2102 MIPS_SYS(sys_clone , 6) /* 4120 */
2103 MIPS_SYS(sys_setdomainname, 2)
2104 MIPS_SYS(sys_newuname , 1)
2105 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2106 MIPS_SYS(sys_adjtimex , 1)
2107 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2108 MIPS_SYS(sys_sigprocmask , 3)
2109 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2110 MIPS_SYS(sys_init_module , 5)
2111 MIPS_SYS(sys_delete_module, 1)
2112 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2113 MIPS_SYS(sys_quotactl , 0)
2114 MIPS_SYS(sys_getpgid , 1)
2115 MIPS_SYS(sys_fchdir , 1)
2116 MIPS_SYS(sys_bdflush , 2)
2117 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2118 MIPS_SYS(sys_personality , 1)
2119 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2120 MIPS_SYS(sys_setfsuid , 1)
2121 MIPS_SYS(sys_setfsgid , 1)
2122 MIPS_SYS(sys_llseek , 5) /* 4140 */
2123 MIPS_SYS(sys_getdents , 3)
2124 MIPS_SYS(sys_select , 5)
2125 MIPS_SYS(sys_flock , 2)
2126 MIPS_SYS(sys_msync , 3)
2127 MIPS_SYS(sys_readv , 3) /* 4145 */
2128 MIPS_SYS(sys_writev , 3)
2129 MIPS_SYS(sys_cacheflush , 3)
2130 MIPS_SYS(sys_cachectl , 3)
2131 MIPS_SYS(sys_sysmips , 4)
2132 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2133 MIPS_SYS(sys_getsid , 1)
2134 MIPS_SYS(sys_fdatasync , 0)
2135 MIPS_SYS(sys_sysctl , 1)
2136 MIPS_SYS(sys_mlock , 2)
2137 MIPS_SYS(sys_munlock , 2) /* 4155 */
2138 MIPS_SYS(sys_mlockall , 1)
2139 MIPS_SYS(sys_munlockall , 0)
2140 MIPS_SYS(sys_sched_setparam, 2)
2141 MIPS_SYS(sys_sched_getparam, 2)
2142 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2143 MIPS_SYS(sys_sched_getscheduler, 1)
2144 MIPS_SYS(sys_sched_yield , 0)
2145 MIPS_SYS(sys_sched_get_priority_max, 1)
2146 MIPS_SYS(sys_sched_get_priority_min, 1)
2147 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2148 MIPS_SYS(sys_nanosleep, 2)
2149 MIPS_SYS(sys_mremap , 5)
2150 MIPS_SYS(sys_accept , 3)
2151 MIPS_SYS(sys_bind , 3)
2152 MIPS_SYS(sys_connect , 3) /* 4170 */
2153 MIPS_SYS(sys_getpeername , 3)
2154 MIPS_SYS(sys_getsockname , 3)
2155 MIPS_SYS(sys_getsockopt , 5)
2156 MIPS_SYS(sys_listen , 2)
2157 MIPS_SYS(sys_recv , 4) /* 4175 */
2158 MIPS_SYS(sys_recvfrom , 6)
2159 MIPS_SYS(sys_recvmsg , 3)
2160 MIPS_SYS(sys_send , 4)
2161 MIPS_SYS(sys_sendmsg , 3)
2162 MIPS_SYS(sys_sendto , 6) /* 4180 */
2163 MIPS_SYS(sys_setsockopt , 5)
2164 MIPS_SYS(sys_shutdown , 2)
2165 MIPS_SYS(sys_socket , 3)
2166 MIPS_SYS(sys_socketpair , 4)
2167 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2168 MIPS_SYS(sys_getresuid , 3)
2169 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2170 MIPS_SYS(sys_poll , 3)
2171 MIPS_SYS(sys_nfsservctl , 3)
2172 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2173 MIPS_SYS(sys_getresgid , 3)
2174 MIPS_SYS(sys_prctl , 5)
2175 MIPS_SYS(sys_rt_sigreturn, 0)
2176 MIPS_SYS(sys_rt_sigaction, 4)
2177 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2178 MIPS_SYS(sys_rt_sigpending, 2)
2179 MIPS_SYS(sys_rt_sigtimedwait, 4)
2180 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2181 MIPS_SYS(sys_rt_sigsuspend, 0)
2182 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2183 MIPS_SYS(sys_pwrite64 , 6)
2184 MIPS_SYS(sys_chown , 3)
2185 MIPS_SYS(sys_getcwd , 2)
2186 MIPS_SYS(sys_capget , 2)
2187 MIPS_SYS(sys_capset , 2) /* 4205 */
2188 MIPS_SYS(sys_sigaltstack , 2)
2189 MIPS_SYS(sys_sendfile , 4)
2190 MIPS_SYS(sys_ni_syscall , 0)
2191 MIPS_SYS(sys_ni_syscall , 0)
2192 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2193 MIPS_SYS(sys_truncate64 , 4)
2194 MIPS_SYS(sys_ftruncate64 , 4)
2195 MIPS_SYS(sys_stat64 , 2)
2196 MIPS_SYS(sys_lstat64 , 2)
2197 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2198 MIPS_SYS(sys_pivot_root , 2)
2199 MIPS_SYS(sys_mincore , 3)
2200 MIPS_SYS(sys_madvise , 3)
2201 MIPS_SYS(sys_getdents64 , 3)
2202 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2203 MIPS_SYS(sys_ni_syscall , 0)
2204 MIPS_SYS(sys_gettid , 0)
2205 MIPS_SYS(sys_readahead , 5)
2206 MIPS_SYS(sys_setxattr , 5)
2207 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2208 MIPS_SYS(sys_fsetxattr , 5)
2209 MIPS_SYS(sys_getxattr , 4)
2210 MIPS_SYS(sys_lgetxattr , 4)
2211 MIPS_SYS(sys_fgetxattr , 4)
2212 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2213 MIPS_SYS(sys_llistxattr , 3)
2214 MIPS_SYS(sys_flistxattr , 3)
2215 MIPS_SYS(sys_removexattr , 2)
2216 MIPS_SYS(sys_lremovexattr, 2)
2217 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2218 MIPS_SYS(sys_tkill , 2)
2219 MIPS_SYS(sys_sendfile64 , 5)
2220 MIPS_SYS(sys_futex , 6)
2221 MIPS_SYS(sys_sched_setaffinity, 3)
2222 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2223 MIPS_SYS(sys_io_setup , 2)
2224 MIPS_SYS(sys_io_destroy , 1)
2225 MIPS_SYS(sys_io_getevents, 5)
2226 MIPS_SYS(sys_io_submit , 3)
2227 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2228 MIPS_SYS(sys_exit_group , 1)
2229 MIPS_SYS(sys_lookup_dcookie, 3)
2230 MIPS_SYS(sys_epoll_create, 1)
2231 MIPS_SYS(sys_epoll_ctl , 4)
2232 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2233 MIPS_SYS(sys_remap_file_pages, 5)
2234 MIPS_SYS(sys_set_tid_address, 1)
2235 MIPS_SYS(sys_restart_syscall, 0)
2236 MIPS_SYS(sys_fadvise64_64, 7)
2237 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2238 MIPS_SYS(sys_fstatfs64 , 2)
2239 MIPS_SYS(sys_timer_create, 3)
2240 MIPS_SYS(sys_timer_settime, 4)
2241 MIPS_SYS(sys_timer_gettime, 2)
2242 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2243 MIPS_SYS(sys_timer_delete, 1)
2244 MIPS_SYS(sys_clock_settime, 2)
2245 MIPS_SYS(sys_clock_gettime, 2)
2246 MIPS_SYS(sys_clock_getres, 2)
2247 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2248 MIPS_SYS(sys_tgkill , 3)
2249 MIPS_SYS(sys_utimes , 2)
2250 MIPS_SYS(sys_mbind , 4)
2251 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2252 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2253 MIPS_SYS(sys_mq_open , 4)
2254 MIPS_SYS(sys_mq_unlink , 1)
2255 MIPS_SYS(sys_mq_timedsend, 5)
2256 MIPS_SYS(sys_mq_timedreceive, 5)
2257 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2258 MIPS_SYS(sys_mq_getsetattr, 3)
2259 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2260 MIPS_SYS(sys_waitid , 4)
2261 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2262 MIPS_SYS(sys_add_key , 5)
2263 MIPS_SYS(sys_request_key, 4)
2264 MIPS_SYS(sys_keyctl , 5)
2265 MIPS_SYS(sys_set_thread_area, 1)
2266 MIPS_SYS(sys_inotify_init, 0)
2267 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2268 MIPS_SYS(sys_inotify_rm_watch, 2)
2269 MIPS_SYS(sys_migrate_pages, 4)
2270 MIPS_SYS(sys_openat, 4)
2271 MIPS_SYS(sys_mkdirat, 3)
2272 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2273 MIPS_SYS(sys_fchownat, 5)
2274 MIPS_SYS(sys_futimesat, 3)
2275 MIPS_SYS(sys_fstatat64, 4)
2276 MIPS_SYS(sys_unlinkat, 3)
2277 MIPS_SYS(sys_renameat, 4) /* 4295 */
2278 MIPS_SYS(sys_linkat, 5)
2279 MIPS_SYS(sys_symlinkat, 3)
2280 MIPS_SYS(sys_readlinkat, 4)
2281 MIPS_SYS(sys_fchmodat, 3)
2282 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2283 MIPS_SYS(sys_pselect6, 6)
2284 MIPS_SYS(sys_ppoll, 5)
2285 MIPS_SYS(sys_unshare, 1)
2286 MIPS_SYS(sys_splice, 6)
2287 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2288 MIPS_SYS(sys_tee, 4)
2289 MIPS_SYS(sys_vmsplice, 4)
2290 MIPS_SYS(sys_move_pages, 6)
2291 MIPS_SYS(sys_set_robust_list, 2)
2292 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2293 MIPS_SYS(sys_kexec_load, 4)
2294 MIPS_SYS(sys_getcpu, 3)
2295 MIPS_SYS(sys_epoll_pwait, 6)
2296 MIPS_SYS(sys_ioprio_set, 3)
2297 MIPS_SYS(sys_ioprio_get, 2)
2298 MIPS_SYS(sys_utimensat, 4)
2299 MIPS_SYS(sys_signalfd, 3)
2300 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2301 MIPS_SYS(sys_eventfd, 1)
2302 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2303 MIPS_SYS(sys_timerfd_create, 2)
2304 MIPS_SYS(sys_timerfd_gettime, 2)
2305 MIPS_SYS(sys_timerfd_settime, 4)
2306 MIPS_SYS(sys_signalfd4, 4)
2307 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2308 MIPS_SYS(sys_epoll_create1, 1)
2309 MIPS_SYS(sys_dup3, 3)
2310 MIPS_SYS(sys_pipe2, 2)
2311 MIPS_SYS(sys_inotify_init1, 1)
2312 MIPS_SYS(sys_preadv, 6) /* 4330 */
2313 MIPS_SYS(sys_pwritev, 6)
2314 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2315 MIPS_SYS(sys_perf_event_open, 5)
2316 MIPS_SYS(sys_accept4, 4)
2317 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2318 MIPS_SYS(sys_fanotify_init, 2)
2319 MIPS_SYS(sys_fanotify_mark, 6)
2320 MIPS_SYS(sys_prlimit64, 4)
2321 MIPS_SYS(sys_name_to_handle_at, 5)
2322 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2323 MIPS_SYS(sys_clock_adjtime, 2)
2324 MIPS_SYS(sys_syncfs, 1)
2325 };
2326 # undef MIPS_SYS
2327 # endif /* O32 */
2328
2329 static int do_store_exclusive(CPUMIPSState *env)
2330 {
2331 target_ulong addr;
2332 target_ulong page_addr;
2333 target_ulong val;
2334 int flags;
2335 int segv = 0;
2336 int reg;
2337 int d;
2338
2339 addr = env->lladdr;
2340 page_addr = addr & TARGET_PAGE_MASK;
2341 start_exclusive();
2342 mmap_lock();
2343 flags = page_get_flags(page_addr);
2344 if ((flags & PAGE_READ) == 0) {
2345 segv = 1;
2346 } else {
2347 reg = env->llreg & 0x1f;
2348 d = (env->llreg & 0x20) != 0;
2349 if (d) {
2350 segv = get_user_s64(val, addr);
2351 } else {
2352 segv = get_user_s32(val, addr);
2353 }
2354 if (!segv) {
2355 if (val != env->llval) {
2356 env->active_tc.gpr[reg] = 0;
2357 } else {
2358 if (d) {
2359 segv = put_user_u64(env->llnewval, addr);
2360 } else {
2361 segv = put_user_u32(env->llnewval, addr);
2362 }
2363 if (!segv) {
2364 env->active_tc.gpr[reg] = 1;
2365 }
2366 }
2367 }
2368 }
2369 env->lladdr = -1;
2370 if (!segv) {
2371 env->active_tc.PC += 4;
2372 }
2373 mmap_unlock();
2374 end_exclusive();
2375 return segv;
2376 }
2377
2378 /* Break codes */
2379 enum {
2380 BRK_OVERFLOW = 6,
2381 BRK_DIVZERO = 7
2382 };
2383
2384 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2385 unsigned int code)
2386 {
2387 int ret = -1;
2388
2389 switch (code) {
2390 case BRK_OVERFLOW:
2391 case BRK_DIVZERO:
2392 info->si_signo = TARGET_SIGFPE;
2393 info->si_errno = 0;
2394 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2395 queue_signal(env, info->si_signo, &*info);
2396 ret = 0;
2397 break;
2398 default:
2399 info->si_signo = TARGET_SIGTRAP;
2400 info->si_errno = 0;
2401 queue_signal(env, info->si_signo, &*info);
2402 ret = 0;
2403 break;
2404 }
2405
2406 return ret;
2407 }
2408
2409 void cpu_loop(CPUMIPSState *env)
2410 {
2411 CPUState *cs = CPU(mips_env_get_cpu(env));
2412 target_siginfo_t info;
2413 int trapnr;
2414 abi_long ret;
2415 # ifdef TARGET_ABI_MIPSO32
2416 unsigned int syscall_num;
2417 # endif
2418
2419 for(;;) {
2420 cpu_exec_start(cs);
2421 trapnr = cpu_mips_exec(env);
2422 cpu_exec_end(cs);
2423 switch(trapnr) {
2424 case EXCP_SYSCALL:
2425 env->active_tc.PC += 4;
2426 # ifdef TARGET_ABI_MIPSO32
2427 syscall_num = env->active_tc.gpr[2] - 4000;
2428 if (syscall_num >= sizeof(mips_syscall_args)) {
2429 ret = -TARGET_ENOSYS;
2430 } else {
2431 int nb_args;
2432 abi_ulong sp_reg;
2433 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2434
2435 nb_args = mips_syscall_args[syscall_num];
2436 sp_reg = env->active_tc.gpr[29];
2437 switch (nb_args) {
2438 /* these arguments are taken from the stack */
2439 case 8:
2440 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2441 goto done_syscall;
2442 }
2443 case 7:
2444 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 6:
2448 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2449 goto done_syscall;
2450 }
2451 case 5:
2452 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2453 goto done_syscall;
2454 }
2455 default:
2456 break;
2457 }
2458 ret = do_syscall(env, env->active_tc.gpr[2],
2459 env->active_tc.gpr[4],
2460 env->active_tc.gpr[5],
2461 env->active_tc.gpr[6],
2462 env->active_tc.gpr[7],
2463 arg5, arg6, arg7, arg8);
2464 }
2465 done_syscall:
2466 # else
2467 ret = do_syscall(env, env->active_tc.gpr[2],
2468 env->active_tc.gpr[4], env->active_tc.gpr[5],
2469 env->active_tc.gpr[6], env->active_tc.gpr[7],
2470 env->active_tc.gpr[8], env->active_tc.gpr[9],
2471 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2472 # endif /* O32 */
2473 if (ret == -TARGET_QEMU_ESIGRETURN) {
2474 /* Returning from a successful sigreturn syscall.
2475 Avoid clobbering register state. */
2476 break;
2477 }
2478 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2479 env->active_tc.gpr[7] = 1; /* error flag */
2480 ret = -ret;
2481 } else {
2482 env->active_tc.gpr[7] = 0; /* error flag */
2483 }
2484 env->active_tc.gpr[2] = ret;
2485 break;
2486 case EXCP_TLBL:
2487 case EXCP_TLBS:
2488 case EXCP_AdEL:
2489 case EXCP_AdES:
2490 info.si_signo = TARGET_SIGSEGV;
2491 info.si_errno = 0;
2492 /* XXX: check env->error_code */
2493 info.si_code = TARGET_SEGV_MAPERR;
2494 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2495 queue_signal(env, info.si_signo, &info);
2496 break;
2497 case EXCP_CpU:
2498 case EXCP_RI:
2499 info.si_signo = TARGET_SIGILL;
2500 info.si_errno = 0;
2501 info.si_code = 0;
2502 queue_signal(env, info.si_signo, &info);
2503 break;
2504 case EXCP_INTERRUPT:
2505 /* just indicate that signals should be handled asap */
2506 break;
2507 case EXCP_DEBUG:
2508 {
2509 int sig;
2510
2511 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2512 if (sig)
2513 {
2514 info.si_signo = sig;
2515 info.si_errno = 0;
2516 info.si_code = TARGET_TRAP_BRKPT;
2517 queue_signal(env, info.si_signo, &info);
2518 }
2519 }
2520 break;
2521 case EXCP_SC:
2522 if (do_store_exclusive(env)) {
2523 info.si_signo = TARGET_SIGSEGV;
2524 info.si_errno = 0;
2525 info.si_code = TARGET_SEGV_MAPERR;
2526 info._sifields._sigfault._addr = env->active_tc.PC;
2527 queue_signal(env, info.si_signo, &info);
2528 }
2529 break;
2530 case EXCP_DSPDIS:
2531 info.si_signo = TARGET_SIGILL;
2532 info.si_errno = 0;
2533 info.si_code = TARGET_ILL_ILLOPC;
2534 queue_signal(env, info.si_signo, &info);
2535 break;
2536 /* The code below was inspired by the MIPS Linux kernel trap
2537 * handling code in arch/mips/kernel/traps.c.
2538 */
2539 case EXCP_BREAK:
2540 {
2541 abi_ulong trap_instr;
2542 unsigned int code;
2543
2544 if (env->hflags & MIPS_HFLAG_M16) {
2545 if (env->insn_flags & ASE_MICROMIPS) {
2546 /* microMIPS mode */
2547 ret = get_user_u16(trap_instr, env->active_tc.PC);
2548 if (ret != 0) {
2549 goto error;
2550 }
2551
2552 if ((trap_instr >> 10) == 0x11) {
2553 /* 16-bit instruction */
2554 code = trap_instr & 0xf;
2555 } else {
2556 /* 32-bit instruction */
2557 abi_ulong instr_lo;
2558
2559 ret = get_user_u16(instr_lo,
2560 env->active_tc.PC + 2);
2561 if (ret != 0) {
2562 goto error;
2563 }
2564 trap_instr = (trap_instr << 16) | instr_lo;
2565 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2566 /* Unfortunately, microMIPS also suffers from
2567 the old assembler bug... */
2568 if (code >= (1 << 10)) {
2569 code >>= 10;
2570 }
2571 }
2572 } else {
2573 /* MIPS16e mode */
2574 ret = get_user_u16(trap_instr, env->active_tc.PC);
2575 if (ret != 0) {
2576 goto error;
2577 }
2578 code = (trap_instr >> 6) & 0x3f;
2579 }
2580 } else {
2581 ret = get_user_ual(trap_instr, env->active_tc.PC);
2582 if (ret != 0) {
2583 goto error;
2584 }
2585
2586 /* As described in the original Linux kernel code, the
2587 * below checks on 'code' are to work around an old
2588 * assembly bug.
2589 */
2590 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2591 if (code >= (1 << 10)) {
2592 code >>= 10;
2593 }
2594 }
2595
2596 if (do_break(env, &info, code) != 0) {
2597 goto error;
2598 }
2599 }
2600 break;
2601 case EXCP_TRAP:
2602 {
2603 abi_ulong trap_instr;
2604 unsigned int code = 0;
2605
2606 if (env->hflags & MIPS_HFLAG_M16) {
2607 /* microMIPS mode */
2608 abi_ulong instr[2];
2609
2610 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2611 get_user_u16(instr[1], env->active_tc.PC + 2);
2612
2613 trap_instr = (instr[0] << 16) | instr[1];
2614 } else {
2615 ret = get_user_ual(trap_instr, env->active_tc.PC);
2616 }
2617
2618 if (ret != 0) {
2619 goto error;
2620 }
2621
2622 /* The immediate versions don't provide a code. */
2623 if (!(trap_instr & 0xFC000000)) {
2624 if (env->hflags & MIPS_HFLAG_M16) {
2625 /* microMIPS mode */
2626 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2627 } else {
2628 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2629 }
2630 }
2631
2632 if (do_break(env, &info, code) != 0) {
2633 goto error;
2634 }
2635 }
2636 break;
2637 default:
2638 error:
2639 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2640 trapnr);
2641 cpu_dump_state(cs, stderr, fprintf, 0);
2642 abort();
2643 }
2644 process_pending_signals(env);
2645 }
2646 }
2647 #endif
2648
2649 #ifdef TARGET_OPENRISC
2650
2651 void cpu_loop(CPUOpenRISCState *env)
2652 {
2653 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2654 int trapnr, gdbsig;
2655
2656 for (;;) {
2657 cpu_exec_start(cs);
2658 trapnr = cpu_exec(env);
2659 cpu_exec_end(cs);
2660 gdbsig = 0;
2661
2662 switch (trapnr) {
2663 case EXCP_RESET:
2664 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2665 exit(1);
2666 break;
2667 case EXCP_BUSERR:
2668 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2669 gdbsig = TARGET_SIGBUS;
2670 break;
2671 case EXCP_DPF:
2672 case EXCP_IPF:
2673 cpu_dump_state(cs, stderr, fprintf, 0);
2674 gdbsig = TARGET_SIGSEGV;
2675 break;
2676 case EXCP_TICK:
2677 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2678 break;
2679 case EXCP_ALIGN:
2680 qemu_log("\nAlignment pc is %#x\n", env->pc);
2681 gdbsig = TARGET_SIGBUS;
2682 break;
2683 case EXCP_ILLEGAL:
2684 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2685 gdbsig = TARGET_SIGILL;
2686 break;
2687 case EXCP_INT:
2688 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2689 break;
2690 case EXCP_DTLBMISS:
2691 case EXCP_ITLBMISS:
2692 qemu_log("\nTLB miss\n");
2693 break;
2694 case EXCP_RANGE:
2695 qemu_log("\nRange\n");
2696 gdbsig = TARGET_SIGSEGV;
2697 break;
2698 case EXCP_SYSCALL:
2699 env->pc += 4; /* 0xc00; */
2700 env->gpr[11] = do_syscall(env,
2701 env->gpr[11], /* return value */
2702 env->gpr[3], /* r3 - r7 are params */
2703 env->gpr[4],
2704 env->gpr[5],
2705 env->gpr[6],
2706 env->gpr[7],
2707 env->gpr[8], 0, 0);
2708 break;
2709 case EXCP_FPE:
2710 qemu_log("\nFloating point error\n");
2711 break;
2712 case EXCP_TRAP:
2713 qemu_log("\nTrap\n");
2714 gdbsig = TARGET_SIGTRAP;
2715 break;
2716 case EXCP_NR:
2717 qemu_log("\nNR\n");
2718 break;
2719 default:
2720 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2721 trapnr);
2722 cpu_dump_state(cs, stderr, fprintf, 0);
2723 gdbsig = TARGET_SIGILL;
2724 break;
2725 }
2726 if (gdbsig) {
2727 gdb_handlesig(cs, gdbsig);
2728 if (gdbsig != TARGET_SIGTRAP) {
2729 exit(1);
2730 }
2731 }
2732
2733 process_pending_signals(env);
2734 }
2735 }
2736
2737 #endif /* TARGET_OPENRISC */
2738
2739 #ifdef TARGET_SH4
2740 void cpu_loop(CPUSH4State *env)
2741 {
2742 CPUState *cs = CPU(sh_env_get_cpu(env));
2743 int trapnr, ret;
2744 target_siginfo_t info;
2745
2746 while (1) {
2747 cpu_exec_start(cs);
2748 trapnr = cpu_sh4_exec (env);
2749 cpu_exec_end(cs);
2750
2751 switch (trapnr) {
2752 case 0x160:
2753 env->pc += 2;
2754 ret = do_syscall(env,
2755 env->gregs[3],
2756 env->gregs[4],
2757 env->gregs[5],
2758 env->gregs[6],
2759 env->gregs[7],
2760 env->gregs[0],
2761 env->gregs[1],
2762 0, 0);
2763 env->gregs[0] = ret;
2764 break;
2765 case EXCP_INTERRUPT:
2766 /* just indicate that signals should be handled asap */
2767 break;
2768 case EXCP_DEBUG:
2769 {
2770 int sig;
2771
2772 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2773 if (sig)
2774 {
2775 info.si_signo = sig;
2776 info.si_errno = 0;
2777 info.si_code = TARGET_TRAP_BRKPT;
2778 queue_signal(env, info.si_signo, &info);
2779 }
2780 }
2781 break;
2782 case 0xa0:
2783 case 0xc0:
2784 info.si_signo = TARGET_SIGSEGV;
2785 info.si_errno = 0;
2786 info.si_code = TARGET_SEGV_MAPERR;
2787 info._sifields._sigfault._addr = env->tea;
2788 queue_signal(env, info.si_signo, &info);
2789 break;
2790
2791 default:
2792 printf ("Unhandled trap: 0x%x\n", trapnr);
2793 cpu_dump_state(cs, stderr, fprintf, 0);
2794 exit (1);
2795 }
2796 process_pending_signals (env);
2797 }
2798 }
2799 #endif
2800
2801 #ifdef TARGET_CRIS
2802 void cpu_loop(CPUCRISState *env)
2803 {
2804 CPUState *cs = CPU(cris_env_get_cpu(env));
2805 int trapnr, ret;
2806 target_siginfo_t info;
2807
2808 while (1) {
2809 cpu_exec_start(cs);
2810 trapnr = cpu_cris_exec (env);
2811 cpu_exec_end(cs);
2812 switch (trapnr) {
2813 case 0xaa:
2814 {
2815 info.si_signo = TARGET_SIGSEGV;
2816 info.si_errno = 0;
2817 /* XXX: check env->error_code */
2818 info.si_code = TARGET_SEGV_MAPERR;
2819 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2820 queue_signal(env, info.si_signo, &info);
2821 }
2822 break;
2823 case EXCP_INTERRUPT:
2824 /* just indicate that signals should be handled asap */
2825 break;
2826 case EXCP_BREAK:
2827 ret = do_syscall(env,
2828 env->regs[9],
2829 env->regs[10],
2830 env->regs[11],
2831 env->regs[12],
2832 env->regs[13],
2833 env->pregs[7],
2834 env->pregs[11],
2835 0, 0);
2836 env->regs[10] = ret;
2837 break;
2838 case EXCP_DEBUG:
2839 {
2840 int sig;
2841
2842 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2843 if (sig)
2844 {
2845 info.si_signo = sig;
2846 info.si_errno = 0;
2847 info.si_code = TARGET_TRAP_BRKPT;
2848 queue_signal(env, info.si_signo, &info);
2849 }
2850 }
2851 break;
2852 default:
2853 printf ("Unhandled trap: 0x%x\n", trapnr);
2854 cpu_dump_state(cs, stderr, fprintf, 0);
2855 exit (1);
2856 }
2857 process_pending_signals (env);
2858 }
2859 }
2860 #endif
2861
2862 #ifdef TARGET_MICROBLAZE
2863 void cpu_loop(CPUMBState *env)
2864 {
2865 CPUState *cs = CPU(mb_env_get_cpu(env));
2866 int trapnr, ret;
2867 target_siginfo_t info;
2868
2869 while (1) {
2870 cpu_exec_start(cs);
2871 trapnr = cpu_mb_exec (env);
2872 cpu_exec_end(cs);
2873 switch (trapnr) {
2874 case 0xaa:
2875 {
2876 info.si_signo = TARGET_SIGSEGV;
2877 info.si_errno = 0;
2878 /* XXX: check env->error_code */
2879 info.si_code = TARGET_SEGV_MAPERR;
2880 info._sifields._sigfault._addr = 0;
2881 queue_signal(env, info.si_signo, &info);
2882 }
2883 break;
2884 case EXCP_INTERRUPT:
2885 /* just indicate that signals should be handled asap */
2886 break;
2887 case EXCP_BREAK:
2888 /* Return address is 4 bytes after the call. */
2889 env->regs[14] += 4;
2890 env->sregs[SR_PC] = env->regs[14];
2891 ret = do_syscall(env,
2892 env->regs[12],
2893 env->regs[5],
2894 env->regs[6],
2895 env->regs[7],
2896 env->regs[8],
2897 env->regs[9],
2898 env->regs[10],
2899 0, 0);
2900 env->regs[3] = ret;
2901 break;
2902 case EXCP_HW_EXCP:
2903 env->regs[17] = env->sregs[SR_PC] + 4;
2904 if (env->iflags & D_FLAG) {
2905 env->sregs[SR_ESR] |= 1 << 12;
2906 env->sregs[SR_PC] -= 4;
2907 /* FIXME: if branch was immed, replay the imm as well. */
2908 }
2909
2910 env->iflags &= ~(IMM_FLAG | D_FLAG);
2911
2912 switch (env->sregs[SR_ESR] & 31) {
2913 case ESR_EC_DIVZERO:
2914 info.si_signo = TARGET_SIGFPE;
2915 info.si_errno = 0;
2916 info.si_code = TARGET_FPE_FLTDIV;
2917 info._sifields._sigfault._addr = 0;
2918 queue_signal(env, info.si_signo, &info);
2919 break;
2920 case ESR_EC_FPU:
2921 info.si_signo = TARGET_SIGFPE;
2922 info.si_errno = 0;
2923 if (env->sregs[SR_FSR] & FSR_IO) {
2924 info.si_code = TARGET_FPE_FLTINV;
2925 }
2926 if (env->sregs[SR_FSR] & FSR_DZ) {
2927 info.si_code = TARGET_FPE_FLTDIV;
2928 }
2929 info._sifields._sigfault._addr = 0;
2930 queue_signal(env, info.si_signo, &info);
2931 break;
2932 default:
2933 printf ("Unhandled hw-exception: 0x%x\n",
2934 env->sregs[SR_ESR] & ESR_EC_MASK);
2935 cpu_dump_state(cs, stderr, fprintf, 0);
2936 exit (1);
2937 break;
2938 }
2939 break;
2940 case EXCP_DEBUG:
2941 {
2942 int sig;
2943
2944 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2945 if (sig)
2946 {
2947 info.si_signo = sig;
2948 info.si_errno = 0;
2949 info.si_code = TARGET_TRAP_BRKPT;
2950 queue_signal(env, info.si_signo, &info);
2951 }
2952 }
2953 break;
2954 default:
2955 printf ("Unhandled trap: 0x%x\n", trapnr);
2956 cpu_dump_state(cs, stderr, fprintf, 0);
2957 exit (1);
2958 }
2959 process_pending_signals (env);
2960 }
2961 }
2962 #endif
2963
2964 #ifdef TARGET_M68K
2965
2966 void cpu_loop(CPUM68KState *env)
2967 {
2968 CPUState *cs = CPU(m68k_env_get_cpu(env));
2969 int trapnr;
2970 unsigned int n;
2971 target_siginfo_t info;
2972 TaskState *ts = cs->opaque;
2973
2974 for(;;) {
2975 cpu_exec_start(cs);
2976 trapnr = cpu_m68k_exec(env);
2977 cpu_exec_end(cs);
2978 switch(trapnr) {
2979 case EXCP_ILLEGAL:
2980 {
2981 if (ts->sim_syscalls) {
2982 uint16_t nr;
2983 get_user_u16(nr, env->pc + 2);
2984 env->pc += 4;
2985 do_m68k_simcall(env, nr);
2986 } else {
2987 goto do_sigill;
2988 }
2989 }
2990 break;
2991 case EXCP_HALT_INSN:
2992 /* Semihosing syscall. */
2993 env->pc += 4;
2994 do_m68k_semihosting(env, env->dregs[0]);
2995 break;
2996 case EXCP_LINEA:
2997 case EXCP_LINEF:
2998 case EXCP_UNSUPPORTED:
2999 do_sigill:
3000 info.si_signo = TARGET_SIGILL;
3001 info.si_errno = 0;
3002 info.si_code = TARGET_ILL_ILLOPN;
3003 info._sifields._sigfault._addr = env->pc;
3004 queue_signal(env, info.si_signo, &info);
3005 break;
3006 case EXCP_TRAP0:
3007 {
3008 ts->sim_syscalls = 0;
3009 n = env->dregs[0];
3010 env->pc += 2;
3011 env->dregs[0] = do_syscall(env,
3012 n,
3013 env->dregs[1],
3014 env->dregs[2],
3015 env->dregs[3],
3016 env->dregs[4],
3017 env->dregs[5],
3018 env->aregs[0],
3019 0, 0);
3020 }
3021 break;
3022 case EXCP_INTERRUPT:
3023 /* just indicate that signals should be handled asap */
3024 break;
3025 case EXCP_ACCESS:
3026 {
3027 info.si_signo = TARGET_SIGSEGV;
3028 info.si_errno = 0;
3029 /* XXX: check env->error_code */
3030 info.si_code = TARGET_SEGV_MAPERR;
3031 info._sifields._sigfault._addr = env->mmu.ar;
3032 queue_signal(env, info.si_signo, &info);
3033 }
3034 break;
3035 case EXCP_DEBUG:
3036 {
3037 int sig;
3038
3039 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3040 if (sig)
3041 {
3042 info.si_signo = sig;
3043 info.si_errno = 0;
3044 info.si_code = TARGET_TRAP_BRKPT;
3045 queue_signal(env, info.si_signo, &info);
3046 }
3047 }
3048 break;
3049 default:
3050 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3051 trapnr);
3052 cpu_dump_state(cs, stderr, fprintf, 0);
3053 abort();
3054 }
3055 process_pending_signals(env);
3056 }
3057 }
3058 #endif /* TARGET_M68K */
3059
3060 #ifdef TARGET_ALPHA
3061 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3062 {
3063 target_ulong addr, val, tmp;
3064 target_siginfo_t info;
3065 int ret = 0;
3066
3067 addr = env->lock_addr;
3068 tmp = env->lock_st_addr;
3069 env->lock_addr = -1;
3070 env->lock_st_addr = 0;
3071
3072 start_exclusive();
3073 mmap_lock();
3074
3075 if (addr == tmp) {
3076 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3077 goto do_sigsegv;
3078 }
3079
3080 if (val == env->lock_value) {
3081 tmp = env->ir[reg];
3082 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3083 goto do_sigsegv;
3084 }
3085 ret = 1;
3086 }
3087 }
3088 env->ir[reg] = ret;
3089 env->pc += 4;
3090
3091 mmap_unlock();
3092 end_exclusive();
3093 return;
3094
3095 do_sigsegv:
3096 mmap_unlock();
3097 end_exclusive();
3098
3099 info.si_signo = TARGET_SIGSEGV;
3100 info.si_errno = 0;
3101 info.si_code = TARGET_SEGV_MAPERR;
3102 info._sifields._sigfault._addr = addr;
3103 queue_signal(env, TARGET_SIGSEGV, &info);
3104 }
3105
3106 void cpu_loop(CPUAlphaState *env)
3107 {
3108 CPUState *cs = CPU(alpha_env_get_cpu(env));
3109 int trapnr;
3110 target_siginfo_t info;
3111 abi_long sysret;
3112
3113 while (1) {
3114 cpu_exec_start(cs);
3115 trapnr = cpu_alpha_exec (env);
3116 cpu_exec_end(cs);
3117
3118 /* All of the traps imply a transition through PALcode, which
3119 implies an REI instruction has been executed. Which means
3120 that the intr_flag should be cleared. */
3121 env->intr_flag = 0;
3122
3123 switch (trapnr) {
3124 case EXCP_RESET:
3125 fprintf(stderr, "Reset requested. Exit\n");
3126 exit(1);
3127 break;
3128 case EXCP_MCHK:
3129 fprintf(stderr, "Machine check exception. Exit\n");
3130 exit(1);
3131 break;
3132 case EXCP_SMP_INTERRUPT:
3133 case EXCP_CLK_INTERRUPT:
3134 case EXCP_DEV_INTERRUPT:
3135 fprintf(stderr, "External interrupt. Exit\n");
3136 exit(1);
3137 break;
3138 case EXCP_MMFAULT:
3139 env->lock_addr = -1;
3140 info.si_signo = TARGET_SIGSEGV;
3141 info.si_errno = 0;
3142 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3143 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3144 info._sifields._sigfault._addr = env->trap_arg0;
3145 queue_signal(env, info.si_signo, &info);
3146 break;
3147 case EXCP_UNALIGN:
3148 env->lock_addr = -1;
3149 info.si_signo = TARGET_SIGBUS;
3150 info.si_errno = 0;
3151 info.si_code = TARGET_BUS_ADRALN;
3152 info._sifields._sigfault._addr = env->trap_arg0;
3153 queue_signal(env, info.si_signo, &info);
3154 break;
3155 case EXCP_OPCDEC:
3156 do_sigill:
3157 env->lock_addr = -1;
3158 info.si_signo = TARGET_SIGILL;
3159 info.si_errno = 0;
3160 info.si_code = TARGET_ILL_ILLOPC;
3161 info._sifields._sigfault._addr = env->pc;
3162 queue_signal(env, info.si_signo, &info);
3163 break;
3164 case EXCP_ARITH:
3165 env->lock_addr = -1;
3166 info.si_signo = TARGET_SIGFPE;
3167 info.si_errno = 0;
3168 info.si_code = TARGET_FPE_FLTINV;
3169 info._sifields._sigfault._addr = env->pc;
3170 queue_signal(env, info.si_signo, &info);
3171 break;
3172 case EXCP_FEN:
3173 /* No-op. Linux simply re-enables the FPU. */
3174 break;
3175 case EXCP_CALL_PAL:
3176 env->lock_addr = -1;
3177 switch (env->error_code) {
3178 case 0x80:
3179 /* BPT */
3180 info.si_signo = TARGET_SIGTRAP;
3181 info.si_errno = 0;
3182 info.si_code = TARGET_TRAP_BRKPT;
3183 info._sifields._sigfault._addr = env->pc;
3184 queue_signal(env, info.si_signo, &info);
3185 break;
3186 case 0x81:
3187 /* BUGCHK */
3188 info.si_signo = TARGET_SIGTRAP;
3189 info.si_errno = 0;
3190 info.si_code = 0;
3191 info._sifields._sigfault._addr = env->pc;
3192 queue_signal(env, info.si_signo, &info);
3193 break;
3194 case 0x83:
3195 /* CALLSYS */
3196 trapnr = env->ir[IR_V0];
3197 sysret = do_syscall(env, trapnr,
3198 env->ir[IR_A0], env->ir[IR_A1],
3199 env->ir[IR_A2], env->ir[IR_A3],
3200 env->ir[IR_A4], env->ir[IR_A5],
3201 0, 0);
3202 if (trapnr == TARGET_NR_sigreturn
3203 || trapnr == TARGET_NR_rt_sigreturn) {
3204 break;
3205 }
3206 /* Syscall writes 0 to V0 to bypass error check, similar
3207 to how this is handled internal to Linux kernel.
3208 (Ab)use trapnr temporarily as boolean indicating error. */
3209 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3210 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3211 env->ir[IR_A3] = trapnr;
3212 break;
3213 case 0x86:
3214 /* IMB */
3215 /* ??? We can probably elide the code using page_unprotect
3216 that is checking for self-modifying code. Instead we
3217 could simply call tb_flush here. Until we work out the
3218 changes required to turn off the extra write protection,
3219 this can be a no-op. */
3220 break;
3221 case 0x9E:
3222 /* RDUNIQUE */
3223 /* Handled in the translator for usermode. */
3224 abort();
3225 case 0x9F:
3226 /* WRUNIQUE */
3227 /* Handled in the translator for usermode. */
3228 abort();
3229 case 0xAA:
3230 /* GENTRAP */
3231 info.si_signo = TARGET_SIGFPE;
3232 switch (env->ir[IR_A0]) {
3233 case TARGET_GEN_INTOVF:
3234 info.si_code = TARGET_FPE_INTOVF;
3235 break;
3236 case TARGET_GEN_INTDIV:
3237 info.si_code = TARGET_FPE_INTDIV;
3238 break;
3239 case TARGET_GEN_FLTOVF:
3240 info.si_code = TARGET_FPE_FLTOVF;
3241 break;
3242 case TARGET_GEN_FLTUND:
3243 info.si_code = TARGET_FPE_FLTUND;
3244 break;
3245 case TARGET_GEN_FLTINV:
3246 info.si_code = TARGET_FPE_FLTINV;
3247 break;
3248 case TARGET_GEN_FLTINE:
3249 info.si_code = TARGET_FPE_FLTRES;
3250 break;
3251 case TARGET_GEN_ROPRAND:
3252 info.si_code = 0;
3253 break;
3254 default:
3255 info.si_signo = TARGET_SIGTRAP;
3256 info.si_code = 0;
3257 break;
3258 }
3259 info.si_errno = 0;
3260 info._sifields._sigfault._addr = env->pc;
3261 queue_signal(env, info.si_signo, &info);
3262 break;
3263 default:
3264 goto do_sigill;
3265 }
3266 break;
3267 case EXCP_DEBUG:
3268 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3269 if (info.si_signo) {
3270 env->lock_addr = -1;
3271 info.si_errno = 0;
3272 info.si_code = TARGET_TRAP_BRKPT;
3273 queue_signal(env, info.si_signo, &info);
3274 }
3275 break;
3276 case EXCP_STL_C:
3277 case EXCP_STQ_C:
3278 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3279 break;
3280 case EXCP_INTERRUPT:
3281 /* Just indicate that signals should be handled asap. */
3282 break;
3283 default:
3284 printf ("Unhandled trap: 0x%x\n", trapnr);
3285 cpu_dump_state(cs, stderr, fprintf, 0);
3286 exit (1);
3287 }
3288 process_pending_signals (env);
3289 }
3290 }
3291 #endif /* TARGET_ALPHA */
3292
3293 #ifdef TARGET_S390X
3294 void cpu_loop(CPUS390XState *env)
3295 {
3296 CPUState *cs = CPU(s390_env_get_cpu(env));
3297 int trapnr, n, sig;
3298 target_siginfo_t info;
3299 target_ulong addr;
3300
3301 while (1) {
3302 cpu_exec_start(cs);
3303 trapnr = cpu_s390x_exec(env);
3304 cpu_exec_end(cs);
3305 switch (trapnr) {
3306 case EXCP_INTERRUPT:
3307 /* Just indicate that signals should be handled asap. */
3308 break;
3309
3310 case EXCP_SVC:
3311 n = env->int_svc_code;
3312 if (!n) {
3313 /* syscalls > 255 */
3314 n = env->regs[1];
3315 }
3316 env->psw.addr += env->int_svc_ilen;
3317 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3318 env->regs[4], env->regs[5],
3319 env->regs[6], env->regs[7], 0, 0);
3320 break;
3321
3322 case EXCP_DEBUG:
3323 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3324 if (sig) {
3325 n = TARGET_TRAP_BRKPT;
3326 goto do_signal_pc;
3327 }
3328 break;
3329 case EXCP_PGM:
3330 n = env->int_pgm_code;
3331 switch (n) {
3332 case PGM_OPERATION:
3333 case PGM_PRIVILEGED:
3334 sig = TARGET_SIGILL;
3335 n = TARGET_ILL_ILLOPC;
3336 goto do_signal_pc;
3337 case PGM_PROTECTION:
3338 case PGM_ADDRESSING:
3339 sig = TARGET_SIGSEGV;
3340 /* XXX: check env->error_code */
3341 n = TARGET_SEGV_MAPERR;
3342 addr = env->__excp_addr;
3343 goto do_signal;
3344 case PGM_EXECUTE:
3345 case PGM_SPECIFICATION:
3346 case PGM_SPECIAL_OP:
3347 case PGM_OPERAND:
3348 do_sigill_opn:
3349 sig = TARGET_SIGILL;
3350 n = TARGET_ILL_ILLOPN;
3351 goto do_signal_pc;
3352
3353 case PGM_FIXPT_OVERFLOW:
3354 sig = TARGET_SIGFPE;
3355 n = TARGET_FPE_INTOVF;
3356 goto do_signal_pc;
3357 case PGM_FIXPT_DIVIDE:
3358 sig = TARGET_SIGFPE;
3359 n = TARGET_FPE_INTDIV;
3360 goto do_signal_pc;
3361
3362 case PGM_DATA:
3363 n = (env->fpc >> 8) & 0xff;
3364 if (n == 0xff) {
3365 /* compare-and-trap */
3366 goto do_sigill_opn;
3367 } else {
3368 /* An IEEE exception, simulated or otherwise. */
3369 if (n & 0x80) {
3370 n = TARGET_FPE_FLTINV;
3371 } else if (n & 0x40) {
3372 n = TARGET_FPE_FLTDIV;
3373 } else if (n & 0x20) {
3374 n = TARGET_FPE_FLTOVF;
3375 } else if (n & 0x10) {
3376 n = TARGET_FPE_FLTUND;
3377 } else if (n & 0x08) {
3378 n = TARGET_FPE_FLTRES;
3379 } else {
3380 /* ??? Quantum exception; BFP, DFP error. */
3381 goto do_sigill_opn;
3382 }
3383 sig = TARGET_SIGFPE;
3384 goto do_signal_pc;
3385 }
3386
3387 default:
3388 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3389 cpu_dump_state(cs, stderr, fprintf, 0);
3390 exit(1);
3391 }
3392 break;
3393
3394 do_signal_pc:
3395 addr = env->psw.addr;
3396 do_signal:
3397 info.si_signo = sig;
3398 info.si_errno = 0;
3399 info.si_code = n;
3400 info._sifields._sigfault._addr = addr;
3401 queue_signal(env, info.si_signo, &info);
3402 break;
3403
3404 default:
3405 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3406 cpu_dump_state(cs, stderr, fprintf, 0);
3407 exit(1);
3408 }
3409 process_pending_signals (env);
3410 }
3411 }
3412
3413 #endif /* TARGET_S390X */
3414
3415 THREAD CPUState *thread_cpu;
3416
3417 void task_settid(TaskState *ts)
3418 {
3419 if (ts->ts_tid == 0) {
3420 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3421 }
3422 }
3423
3424 void stop_all_tasks(void)
3425 {
3426 /*
3427 * We trust that when using NPTL, start_exclusive()
3428 * handles thread stopping correctly.
3429 */
3430 start_exclusive();
3431 }
3432
3433 /* Assumes contents are already zeroed. */
3434 void init_task_state(TaskState *ts)
3435 {
3436 int i;
3437
3438 ts->used = 1;
3439 ts->first_free = ts->sigqueue_table;
3440 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3441 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3442 }
3443 ts->sigqueue_table[i].next = NULL;
3444 }
3445
3446 CPUArchState *cpu_copy(CPUArchState *env)
3447 {
3448 CPUState *cpu = ENV_GET_CPU(env);
3449 CPUState *new_cpu = cpu_init(cpu_model);
3450 CPUArchState *new_env = new_cpu->env_ptr;
3451 CPUBreakpoint *bp;
3452 CPUWatchpoint *wp;
3453
3454 /* Reset non arch specific state */
3455 cpu_reset(new_cpu);
3456
3457 memcpy(new_env, env, sizeof(CPUArchState));
3458
3459 /* Clone all break/watchpoints.
3460 Note: Once we support ptrace with hw-debug register access, make sure
3461 BP_CPU break/watchpoints are handled correctly on clone. */
3462 QTAILQ_INIT(&new_cpu->breakpoints);
3463 QTAILQ_INIT(&new_cpu->watchpoints);
3464 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3465 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3466 }
3467 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3468 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3469 }
3470
3471 return new_env;
3472 }
3473
3474 static void handle_arg_help(const char *arg)
3475 {
3476 usage();
3477 }
3478
3479 static void handle_arg_log(const char *arg)
3480 {
3481 int mask;
3482
3483 mask = qemu_str_to_log_mask(arg);
3484 if (!mask) {
3485 qemu_print_log_usage(stdout);
3486 exit(1);
3487 }
3488 qemu_set_log(mask);
3489 }
3490
3491 static void handle_arg_log_filename(const char *arg)
3492 {
3493 qemu_set_log_filename(arg);
3494 }
3495
3496 static void handle_arg_set_env(const char *arg)
3497 {
3498 char *r, *p, *token;
3499 r = p = strdup(arg);
3500 while ((token = strsep(&p, ",")) != NULL) {
3501 if (envlist_setenv(envlist, token) != 0) {
3502 usage();
3503 }
3504 }
3505 free(r);
3506 }
3507
3508 static void handle_arg_unset_env(const char *arg)
3509 {
3510 char *r, *p, *token;
3511 r = p = strdup(arg);
3512 while ((token = strsep(&p, ",")) != NULL) {
3513 if (envlist_unsetenv(envlist, token) != 0) {
3514 usage();
3515 }
3516 }
3517 free(r);
3518 }
3519
3520 static void handle_arg_argv0(const char *arg)
3521 {
3522 argv0 = strdup(arg);
3523 }
3524
3525 static void handle_arg_stack_size(const char *arg)
3526 {
3527 char *p;
3528 guest_stack_size = strtoul(arg, &p, 0);
3529 if (guest_stack_size == 0) {
3530 usage();
3531 }
3532
3533 if (*p == 'M') {
3534 guest_stack_size *= 1024 * 1024;
3535 } else if (*p == 'k' || *p == 'K') {
3536 guest_stack_size *= 1024;
3537 }
3538 }
3539
3540 static void handle_arg_ld_prefix(const char *arg)
3541 {
3542 interp_prefix = strdup(arg);
3543 }
3544
3545 static void handle_arg_pagesize(const char *arg)
3546 {
3547 qemu_host_page_size = atoi(arg);
3548 if (qemu_host_page_size == 0 ||
3549 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3550 fprintf(stderr, "page size must be a power of two\n");
3551 exit(1);
3552 }
3553 }
3554
3555 static void handle_arg_randseed(const char *arg)
3556 {
3557 unsigned long long seed;
3558
3559 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3560 fprintf(stderr, "Invalid seed number: %s\n", arg);
3561 exit(1);
3562 }
3563 srand(seed);
3564 }
3565
3566 static void handle_arg_gdb(const char *arg)
3567 {
3568 gdbstub_port = atoi(arg);
3569 }
3570
3571 static void handle_arg_uname(const char *arg)
3572 {
3573 qemu_uname_release = strdup(arg);
3574 }
3575
3576 static void handle_arg_cpu(const char *arg)
3577 {
3578 cpu_model = strdup(arg);
3579 if (cpu_model == NULL || is_help_option(cpu_model)) {
3580 /* XXX: implement xxx_cpu_list for targets that still miss it */
3581 #if defined(cpu_list)
3582 cpu_list(stdout, &fprintf);
3583 #endif
3584 exit(1);
3585 }
3586 }
3587
3588 #if defined(CONFIG_USE_GUEST_BASE)
3589 static void handle_arg_guest_base(const char *arg)
3590 {
3591 guest_base = strtol(arg, NULL, 0);
3592 have_guest_base = 1;
3593 }
3594
3595 static void handle_arg_reserved_va(const char *arg)
3596 {
3597 char *p;
3598 int shift = 0;
3599 reserved_va = strtoul(arg, &p, 0);
3600 switch (*p) {
3601 case 'k':
3602 case 'K':
3603 shift = 10;
3604 break;
3605 case 'M':
3606 shift = 20;
3607 break;
3608 case 'G':
3609 shift = 30;
3610 break;
3611 }
3612 if (shift) {
3613 unsigned long unshifted = reserved_va;
3614 p++;
3615 reserved_va <<= shift;
3616 if (((reserved_va >> shift) != unshifted)
3617 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3618 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3619 #endif
3620 ) {
3621 fprintf(stderr, "Reserved virtual address too big\n");
3622 exit(1);
3623 }
3624 }
3625 if (*p) {
3626 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3627 exit(1);
3628 }
3629 }
3630 #endif
3631
3632 static void handle_arg_singlestep(const char *arg)
3633 {
3634 singlestep = 1;
3635 }
3636
3637 static void handle_arg_strace(const char *arg)
3638 {
3639 do_strace = 1;
3640 }
3641
3642 static void handle_arg_version(const char *arg)
3643 {
3644 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3645 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3646 exit(0);
3647 }
3648
3649 struct qemu_argument {
3650 const char *argv;
3651 const char *env;
3652 bool has_arg;
3653 void (*handle_opt)(const char *arg);
3654 const char *example;
3655 const char *help;
3656 };
3657
3658 static const struct qemu_argument arg_table[] = {
3659 {"h", "", false, handle_arg_help,
3660 "", "print this help"},
3661 {"g", "QEMU_GDB", true, handle_arg_gdb,
3662 "port", "wait gdb connection to 'port'"},
3663 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3664 "path", "set the elf interpreter prefix to 'path'"},
3665 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3666 "size", "set the stack size to 'size' bytes"},
3667 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3668 "model", "select CPU (-cpu help for list)"},
3669 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3670 "var=value", "sets targets environment variable (see below)"},
3671 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3672 "var", "unsets targets environment variable (see below)"},
3673 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3674 "argv0", "forces target process argv[0] to be 'argv0'"},
3675 {"r", "QEMU_UNAME", true, handle_arg_uname,
3676 "uname", "set qemu uname release string to 'uname'"},
3677 #if defined(CONFIG_USE_GUEST_BASE)
3678 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3679 "address", "set guest_base address to 'address'"},
3680 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3681 "size", "reserve 'size' bytes for guest virtual address space"},
3682 #endif
3683 {"d", "QEMU_LOG", true, handle_arg_log,
3684 "item[,...]", "enable logging of specified items "
3685 "(use '-d help' for a list of items)"},
3686 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3687 "logfile", "write logs to 'logfile' (default stderr)"},
3688 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3689 "pagesize", "set the host page size to 'pagesize'"},
3690 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3691 "", "run in singlestep mode"},
3692 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3693 "", "log system calls"},
3694 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3695 "", "Seed for pseudo-random number generator"},
3696 {"version", "QEMU_VERSION", false, handle_arg_version,
3697 "", "display version information and exit"},
3698 {NULL, NULL, false, NULL, NULL, NULL}
3699 };
3700
3701 static void usage(void)
3702 {
3703 const struct qemu_argument *arginfo;
3704 int maxarglen;
3705 int maxenvlen;
3706
3707 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3708 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3709 "\n"
3710 "Options and associated environment variables:\n"
3711 "\n");
3712
3713 /* Calculate column widths. We must always have at least enough space
3714 * for the column header.
3715 */
3716 maxarglen = strlen("Argument");
3717 maxenvlen = strlen("Env-variable");
3718
3719 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3720 int arglen = strlen(arginfo->argv);
3721 if (arginfo->has_arg) {
3722 arglen += strlen(arginfo->example) + 1;
3723 }
3724 if (strlen(arginfo->env) > maxenvlen) {
3725 maxenvlen = strlen(arginfo->env);
3726 }
3727 if (arglen > maxarglen) {
3728 maxarglen = arglen;
3729 }
3730 }
3731
3732 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3733 maxenvlen, "Env-variable");
3734
3735 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3736 if (arginfo->has_arg) {
3737 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3738 (int)(maxarglen - strlen(arginfo->argv) - 1),
3739 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3740 } else {
3741 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3742 maxenvlen, arginfo->env,
3743 arginfo->help);
3744 }
3745 }
3746
3747 printf("\n"
3748 "Defaults:\n"
3749 "QEMU_LD_PREFIX = %s\n"
3750 "QEMU_STACK_SIZE = %ld byte\n",
3751 interp_prefix,
3752 guest_stack_size);
3753
3754 printf("\n"
3755 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3756 "QEMU_UNSET_ENV environment variables to set and unset\n"
3757 "environment variables for the target process.\n"
3758 "It is possible to provide several variables by separating them\n"
3759 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3760 "provide the -E and -U options multiple times.\n"
3761 "The following lines are equivalent:\n"
3762 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3763 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3764 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3765 "Note that if you provide several changes to a single variable\n"
3766 "the last change will stay in effect.\n");
3767
3768 exit(1);
3769 }
3770
3771 static int parse_args(int argc, char **argv)
3772 {
3773 const char *r;
3774 int optind;
3775 const struct qemu_argument *arginfo;
3776
3777 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3778 if (arginfo->env == NULL) {
3779 continue;
3780 }
3781
3782 r = getenv(arginfo->env);
3783 if (r != NULL) {
3784 arginfo->handle_opt(r);
3785 }
3786 }
3787
3788 optind = 1;
3789 for (;;) {
3790 if (optind >= argc) {
3791 break;
3792 }
3793 r = argv[optind];
3794 if (r[0] != '-') {
3795 break;
3796 }
3797 optind++;
3798 r++;
3799 if (!strcmp(r, "-")) {
3800 break;
3801 }
3802
3803 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3804 if (!strcmp(r, arginfo->argv)) {
3805 if (arginfo->has_arg) {
3806 if (optind >= argc) {
3807 usage();
3808 }
3809 arginfo->handle_opt(argv[optind]);
3810 optind++;
3811 } else {
3812 arginfo->handle_opt(NULL);
3813 }
3814 break;
3815 }
3816 }
3817
3818 /* no option matched the current argv */
3819 if (arginfo->handle_opt == NULL) {
3820 usage();
3821 }
3822 }
3823
3824 if (optind >= argc) {
3825 usage();
3826 }
3827
3828 filename = argv[optind];
3829 exec_path = argv[optind];
3830
3831 return optind;
3832 }
3833
3834 int main(int argc, char **argv, char **envp)
3835 {
3836 struct target_pt_regs regs1, *regs = &regs1;
3837 struct image_info info1, *info = &info1;
3838 struct linux_binprm bprm;
3839 TaskState *ts;
3840 CPUArchState *env;
3841 CPUState *cpu;
3842 int optind;
3843 char **target_environ, **wrk;
3844 char **target_argv;
3845 int target_argc;
3846 int i;
3847 int ret;
3848 int execfd;
3849
3850 module_call_init(MODULE_INIT_QOM);
3851
3852 if ((envlist = envlist_create()) == NULL) {
3853 (void) fprintf(stderr, "Unable to allocate envlist\n");
3854 exit(1);
3855 }
3856
3857 /* add current environment into the list */
3858 for (wrk = environ; *wrk != NULL; wrk++) {
3859 (void) envlist_setenv(envlist, *wrk);
3860 }
3861
3862 /* Read the stack limit from the kernel. If it's "unlimited",
3863 then we can do little else besides use the default. */
3864 {
3865 struct rlimit lim;
3866 if (getrlimit(RLIMIT_STACK, &lim) == 0
3867 && lim.rlim_cur != RLIM_INFINITY
3868 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3869 guest_stack_size = lim.rlim_cur;
3870 }
3871 }
3872
3873 cpu_model = NULL;
3874 #if defined(cpudef_setup)
3875 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3876 #endif
3877
3878 srand(time(NULL));
3879
3880 optind = parse_args(argc, argv);
3881
3882 /* Zero out regs */
3883 memset(regs, 0, sizeof(struct target_pt_regs));
3884
3885 /* Zero out image_info */
3886 memset(info, 0, sizeof(struct image_info));
3887
3888 memset(&bprm, 0, sizeof (bprm));
3889
3890 /* Scan interp_prefix dir for replacement files. */
3891 init_paths(interp_prefix);
3892
3893 init_qemu_uname_release();
3894
3895 if (cpu_model == NULL) {
3896 #if defined(TARGET_I386)
3897 #ifdef TARGET_X86_64
3898 cpu_model = "qemu64";
3899 #else
3900 cpu_model = "qemu32";
3901 #endif
3902 #elif defined(TARGET_ARM)
3903 cpu_model = "any";
3904 #elif defined(TARGET_UNICORE32)
3905 cpu_model = "any";
3906 #elif defined(TARGET_M68K)
3907 cpu_model = "any";
3908 #elif defined(TARGET_SPARC)
3909 #ifdef TARGET_SPARC64
3910 cpu_model = "TI UltraSparc II";
3911 #else
3912 cpu_model = "Fujitsu MB86904";
3913 #endif
3914 #elif defined(TARGET_MIPS)
3915 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3916 cpu_model = "5KEf";
3917 #else
3918 cpu_model = "24Kf";
3919 #endif
3920 #elif defined TARGET_OPENRISC
3921 cpu_model = "or1200";
3922 #elif defined(TARGET_PPC)
3923 # ifdef TARGET_PPC64
3924 cpu_model = "POWER7";
3925 # else
3926 cpu_model = "750";
3927 # endif
3928 #elif defined TARGET_SH4
3929 cpu_model = TYPE_SH7785_CPU;
3930 #else
3931 cpu_model = "any";
3932 #endif
3933 }
3934 tcg_exec_init(0);
3935 /* NOTE: we need to init the CPU at this stage to get
3936 qemu_host_page_size */
3937 cpu = cpu_init(cpu_model);
3938 if (!cpu) {
3939 fprintf(stderr, "Unable to find CPU definition\n");
3940 exit(1);
3941 }
3942 env = cpu->env_ptr;
3943 cpu_reset(cpu);
3944
3945 thread_cpu = cpu;
3946
3947 if (getenv("QEMU_STRACE")) {
3948 do_strace = 1;
3949 }
3950
3951 if (getenv("QEMU_RAND_SEED")) {
3952 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3953 }
3954
3955 target_environ = envlist_to_environ(envlist, NULL);
3956 envlist_free(envlist);
3957
3958 #if defined(CONFIG_USE_GUEST_BASE)
3959 /*
3960 * Now that page sizes are configured in cpu_init() we can do
3961 * proper page alignment for guest_base.
3962 */
3963 guest_base = HOST_PAGE_ALIGN(guest_base);
3964
3965 if (reserved_va || have_guest_base) {
3966 guest_base = init_guest_space(guest_base, reserved_va, 0,
3967 have_guest_base);
3968 if (guest_base == (unsigned long)-1) {
3969 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3970 "space for use as guest address space (check your virtual "
3971 "memory ulimit setting or reserve less using -R option)\n",
3972 reserved_va);
3973 exit(1);
3974 }
3975
3976 if (reserved_va) {
3977 mmap_next_start = reserved_va;
3978 }
3979 }
3980 #endif /* CONFIG_USE_GUEST_BASE */
3981
3982 /*
3983 * Read in mmap_min_addr kernel parameter. This value is used
3984 * When loading the ELF image to determine whether guest_base
3985 * is needed. It is also used in mmap_find_vma.
3986 */
3987 {
3988 FILE *fp;
3989
3990 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3991 unsigned long tmp;
3992 if (fscanf(fp, "%lu", &tmp) == 1) {
3993 mmap_min_addr = tmp;
3994 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3995 }
3996 fclose(fp);
3997 }
3998 }
3999
4000 /*
4001 * Prepare copy of argv vector for target.
4002 */
4003 target_argc = argc - optind;
4004 target_argv = calloc(target_argc + 1, sizeof (char *));
4005 if (target_argv == NULL) {
4006 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4007 exit(1);
4008 }
4009
4010 /*
4011 * If argv0 is specified (using '-0' switch) we replace
4012 * argv[0] pointer with the given one.
4013 */
4014 i = 0;
4015 if (argv0 != NULL) {
4016 target_argv[i++] = strdup(argv0);
4017 }
4018 for (; i < target_argc; i++) {
4019 target_argv[i] = strdup(argv[optind + i]);
4020 }
4021 target_argv[target_argc] = NULL;
4022
4023 ts = g_malloc0 (sizeof(TaskState));
4024 init_task_state(ts);
4025 /* build Task State */
4026 ts->info = info;
4027 ts->bprm = &bprm;
4028 cpu->opaque = ts;
4029 task_settid(ts);
4030
4031 execfd = qemu_getauxval(AT_EXECFD);
4032 if (execfd == 0) {
4033 execfd = open(filename, O_RDONLY);
4034 if (execfd < 0) {
4035 printf("Error while loading %s: %s\n", filename, strerror(errno));
4036 _exit(1);
4037 }
4038 }
4039
4040 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4041 info, &bprm);
4042 if (ret != 0) {
4043 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4044 _exit(1);
4045 }
4046
4047 for (wrk = target_environ; *wrk; wrk++) {
4048 free(*wrk);
4049 }
4050
4051 free(target_environ);
4052
4053 if (qemu_log_enabled()) {
4054 #if defined(CONFIG_USE_GUEST_BASE)
4055 qemu_log("guest_base 0x%lx\n", guest_base);
4056 #endif
4057 log_page_dump();
4058
4059 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4060 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4061 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4062 info->start_code);
4063 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4064 info->start_data);
4065 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4066 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4067 info->start_stack);
4068 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4069 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4070 }
4071
4072 target_set_brk(info->brk);
4073 syscall_init();
4074 signal_init();
4075
4076 #if defined(CONFIG_USE_GUEST_BASE)
4077 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4078 generating the prologue until now so that the prologue can take
4079 the real value of GUEST_BASE into account. */
4080 tcg_prologue_init(&tcg_ctx);
4081 #endif
4082
4083 #if defined(TARGET_I386)
4084 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4085 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4086 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4087 env->cr[4] |= CR4_OSFXSR_MASK;
4088 env->hflags |= HF_OSFXSR_MASK;
4089 }
4090 #ifndef TARGET_ABI32
4091 /* enable 64 bit mode if possible */
4092 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4093 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4094 exit(1);
4095 }
4096 env->cr[4] |= CR4_PAE_MASK;
4097 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4098 env->hflags |= HF_LMA_MASK;
4099 #endif
4100
4101 /* flags setup : we activate the IRQs by default as in user mode */
4102 env->eflags |= IF_MASK;
4103
4104 /* linux register setup */
4105 #ifndef TARGET_ABI32
4106 env->regs[R_EAX] = regs->rax;
4107 env->regs[R_EBX] = regs->rbx;
4108 env->regs[R_ECX] = regs->rcx;
4109 env->regs[R_EDX] = regs->rdx;
4110 env->regs[R_ESI] = regs->rsi;
4111 env->regs[R_EDI] = regs->rdi;
4112 env->regs[R_EBP] = regs->rbp;
4113 env->regs[R_ESP] = regs->rsp;
4114 env->eip = regs->rip;
4115 #else
4116 env->regs[R_EAX] = regs->eax;
4117 env->regs[R_EBX] = regs->ebx;
4118 env->regs[R_ECX] = regs->ecx;
4119 env->regs[R_EDX] = regs->edx;
4120 env->regs[R_ESI] = regs->esi;
4121 env->regs[R_EDI] = regs->edi;
4122 env->regs[R_EBP] = regs->ebp;
4123 env->regs[R_ESP] = regs->esp;
4124 env->eip = regs->eip;
4125 #endif
4126
4127 /* linux interrupt setup */
4128 #ifndef TARGET_ABI32
4129 env->idt.limit = 511;
4130 #else
4131 env->idt.limit = 255;
4132 #endif
4133 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4134 PROT_READ|PROT_WRITE,
4135 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4136 idt_table = g2h(env->idt.base);
4137 set_idt(0, 0);
4138 set_idt(1, 0);
4139 set_idt(2, 0);
4140 set_idt(3, 3);
4141 set_idt(4, 3);
4142 set_idt(5, 0);
4143 set_idt(6, 0);
4144 set_idt(7, 0);
4145 set_idt(8, 0);
4146 set_idt(9, 0);
4147 set_idt(10, 0);
4148 set_idt(11, 0);
4149 set_idt(12, 0);
4150 set_idt(13, 0);
4151 set_idt(14, 0);
4152 set_idt(15, 0);
4153 set_idt(16, 0);
4154 set_idt(17, 0);
4155 set_idt(18, 0);
4156 set_idt(19, 0);
4157 set_idt(0x80, 3);
4158
4159 /* linux segment setup */
4160 {
4161 uint64_t *gdt_table;
4162 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4163 PROT_READ|PROT_WRITE,
4164 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4165 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4166 gdt_table = g2h(env->gdt.base);
4167 #ifdef TARGET_ABI32
4168 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4169 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4170 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4171 #else
4172 /* 64 bit code segment */
4173 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4174 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4175 DESC_L_MASK |
4176 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4177 #endif
4178 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4180 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4181 }
4182 cpu_x86_load_seg(env, R_CS, __USER_CS);
4183 cpu_x86_load_seg(env, R_SS, __USER_DS);
4184 #ifdef TARGET_ABI32
4185 cpu_x86_load_seg(env, R_DS, __USER_DS);
4186 cpu_x86_load_seg(env, R_ES, __USER_DS);
4187 cpu_x86_load_seg(env, R_FS, __USER_DS);
4188 cpu_x86_load_seg(env, R_GS, __USER_DS);
4189 /* This hack makes Wine work... */
4190 env->segs[R_FS].selector = 0;
4191 #else
4192 cpu_x86_load_seg(env, R_DS, 0);
4193 cpu_x86_load_seg(env, R_ES, 0);
4194 cpu_x86_load_seg(env, R_FS, 0);
4195 cpu_x86_load_seg(env, R_GS, 0);
4196 #endif
4197 #elif defined(TARGET_AARCH64)
4198 {
4199 int i;
4200
4201 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4202 fprintf(stderr,
4203 "The selected ARM CPU does not support 64 bit mode\n");
4204 exit(1);
4205 }
4206
4207 for (i = 0; i < 31; i++) {
4208 env->xregs[i] = regs->regs[i];
4209 }
4210 env->pc = regs->pc;
4211 env->xregs[31] = regs->sp;
4212 }
4213 #elif defined(TARGET_ARM)
4214 {
4215 int i;
4216 cpsr_write(env, regs->uregs[16], 0xffffffff);
4217 for(i = 0; i < 16; i++) {
4218 env->regs[i] = regs->uregs[i];
4219 }
4220 /* Enable BE8. */
4221 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4222 && (info->elf_flags & EF_ARM_BE8)) {
4223 env->bswap_code = 1;
4224 }
4225 }
4226 #elif defined(TARGET_UNICORE32)
4227 {
4228 int i;
4229 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4230 for (i = 0; i < 32; i++) {
4231 env->regs[i] = regs->uregs[i];
4232 }
4233 }
4234 #elif defined(TARGET_SPARC)
4235 {
4236 int i;
4237 env->pc = regs->pc;
4238 env->npc = regs->npc;
4239 env->y = regs->y;
4240 for(i = 0; i < 8; i++)
4241 env->gregs[i] = regs->u_regs[i];
4242 for(i = 0; i < 8; i++)
4243 env->regwptr[i] = regs->u_regs[i + 8];
4244 }
4245 #elif defined(TARGET_PPC)
4246 {
4247 int i;
4248
4249 #if defined(TARGET_PPC64)
4250 #if defined(TARGET_ABI32)
4251 env->msr &= ~((target_ulong)1 << MSR_SF);
4252 #else
4253 env->msr |= (target_ulong)1 << MSR_SF;
4254 #endif
4255 #endif
4256 env->nip = regs->nip;
4257 for(i = 0; i < 32; i++) {
4258 env->gpr[i] = regs->gpr[i];
4259 }
4260 }
4261 #elif defined(TARGET_M68K)
4262 {
4263 env->pc = regs->pc;
4264 env->dregs[0] = regs->d0;
4265 env->dregs[1] = regs->d1;
4266 env->dregs[2] = regs->d2;
4267 env->dregs[3] = regs->d3;
4268 env->dregs[4] = regs->d4;
4269 env->dregs[5] = regs->d5;
4270 env->dregs[6] = regs->d6;
4271 env->dregs[7] = regs->d7;
4272 env->aregs[0] = regs->a0;
4273 env->aregs[1] = regs->a1;
4274 env->aregs[2] = regs->a2;
4275 env->aregs[3] = regs->a3;
4276 env->aregs[4] = regs->a4;
4277 env->aregs[5] = regs->a5;
4278 env->aregs[6] = regs->a6;
4279 env->aregs[7] = regs->usp;
4280 env->sr = regs->sr;
4281 ts->sim_syscalls = 1;
4282 }
4283 #elif defined(TARGET_MICROBLAZE)
4284 {
4285 env->regs[0] = regs->r0;
4286 env->regs[1] = regs->r1;
4287 env->regs[2] = regs->r2;
4288 env->regs[3] = regs->r3;
4289 env->regs[4] = regs->r4;
4290 env->regs[5] = regs->r5;
4291 env->regs[6] = regs->r6;
4292 env->regs[7] = regs->r7;
4293 env->regs[8] = regs->r8;
4294 env->regs[9] = regs->r9;
4295 env->regs[10] = regs->r10;
4296 env->regs[11] = regs->r11;
4297 env->regs[12] = regs->r12;
4298 env->regs[13] = regs->r13;
4299 env->regs[14] = regs->r14;
4300 env->regs[15] = regs->r15;
4301 env->regs[16] = regs->r16;
4302 env->regs[17] = regs->r17;
4303 env->regs[18] = regs->r18;
4304 env->regs[19] = regs->r19;
4305 env->regs[20] = regs->r20;
4306 env->regs[21] = regs->r21;
4307 env->regs[22] = regs->r22;
4308 env->regs[23] = regs->r23;
4309 env->regs[24] = regs->r24;
4310 env->regs[25] = regs->r25;
4311 env->regs[26] = regs->r26;
4312 env->regs[27] = regs->r27;
4313 env->regs[28] = regs->r28;
4314 env->regs[29] = regs->r29;
4315 env->regs[30] = regs->r30;
4316 env->regs[31] = regs->r31;
4317 env->sregs[SR_PC] = regs->pc;
4318 }
4319 #elif defined(TARGET_MIPS)
4320 {
4321 int i;
4322
4323 for(i = 0; i < 32; i++) {
4324 env->active_tc.gpr[i] = regs->regs[i];
4325 }
4326 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4327 if (regs->cp0_epc & 1) {
4328 env->hflags |= MIPS_HFLAG_M16;
4329 }
4330 }
4331 #elif defined(TARGET_OPENRISC)
4332 {
4333 int i;
4334
4335 for (i = 0; i < 32; i++) {
4336 env->gpr[i] = regs->gpr[i];
4337 }
4338
4339 env->sr = regs->sr;
4340 env->pc = regs->pc;
4341 }
4342 #elif defined(TARGET_SH4)
4343 {
4344 int i;
4345
4346 for(i = 0; i < 16; i++) {
4347 env->gregs[i] = regs->regs[i];
4348 }
4349 env->pc = regs->pc;
4350 }
4351 #elif defined(TARGET_ALPHA)
4352 {
4353 int i;
4354
4355 for(i = 0; i < 28; i++) {
4356 env->ir[i] = ((abi_ulong *)regs)[i];
4357 }
4358 env->ir[IR_SP] = regs->usp;
4359 env->pc = regs->pc;
4360 }
4361 #elif defined(TARGET_CRIS)
4362 {
4363 env->regs[0] = regs->r0;
4364 env->regs[1] = regs->r1;
4365 env->regs[2] = regs->r2;
4366 env->regs[3] = regs->r3;
4367 env->regs[4] = regs->r4;
4368 env->regs[5] = regs->r5;
4369 env->regs[6] = regs->r6;
4370 env->regs[7] = regs->r7;
4371 env->regs[8] = regs->r8;
4372 env->regs[9] = regs->r9;
4373 env->regs[10] = regs->r10;
4374 env->regs[11] = regs->r11;
4375 env->regs[12] = regs->r12;
4376 env->regs[13] = regs->r13;
4377 env->regs[14] = info->start_stack;
4378 env->regs[15] = regs->acr;
4379 env->pc = regs->erp;
4380 }
4381 #elif defined(TARGET_S390X)
4382 {
4383 int i;
4384 for (i = 0; i < 16; i++) {
4385 env->regs[i] = regs->gprs[i];
4386 }
4387 env->psw.mask = regs->psw.mask;
4388 env->psw.addr = regs->psw.addr;
4389 }
4390 #else
4391 #error unsupported target CPU
4392 #endif
4393
4394 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4395 ts->stack_base = info->start_stack;
4396 ts->heap_base = info->brk;
4397 /* This will be filled in on the first SYS_HEAPINFO call. */
4398 ts->heap_limit = 0;
4399 #endif
4400
4401 if (gdbstub_port) {
4402 if (gdbserver_start(gdbstub_port) < 0) {
4403 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4404 gdbstub_port);
4405 exit(1);
4406 }
4407 gdb_handlesig(cpu, 0);
4408 }
4409 cpu_loop(env);
4410 /* never exits */
4411 return 0;
4412 }
AR7 emulation for QEMU