include/hw/s390x/css.h

   1 /*
   2  * Channel subsystem structures and definitions.
   3  *
   4  * Copyright 2012 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #ifndef CSS_H
  13 #define CSS_H
  14
  15 #include "cpu.h"
  16 #include "hw/s390x/adapter.h"
  17 #include "hw/s390x/s390_flic.h"
  18 #include "hw/s390x/ioinst.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/s390x/cpu-qom.h"
  21
  22 /* Channel subsystem constants. */
  23 #define MAX_DEVNO 65535
  24 #define MAX_SCHID 65535
  25 #define MAX_SSID 3
  26 #define MAX_CSSID 255
  27 #define MAX_CHPID 255
  28
  29 #define MAX_ISC 7
  30
  31 #define MAX_CIWS 62
  32
  33 #define VIRTUAL_CSSID 0xfe
  34 #define VIRTIO_CCW_CHPID 0   /* used by convention */
  35
  36 typedef struct CIW {
  37     uint8_t type;
  38     uint8_t command;
  39     uint16_t count;
  40 } QEMU_PACKED CIW;
  41
  42 typedef struct SenseId {
  43     /* common part */
  44     uint8_t reserved;        /* always 0x'FF' */
  45     uint16_t cu_type;        /* control unit type */
  46     uint8_t cu_model;        /* control unit model */
  47     uint16_t dev_type;       /* device type */
  48     uint8_t dev_model;       /* device model */
  49     uint8_t unused;          /* padding byte */
  50     /* extended part */
  51     CIW ciw[MAX_CIWS];       /* variable # of CIWs */
  52 } SenseId;                   /* Note: No QEMU_PACKED due to unaligned members */
  53
  54 /* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
  55 typedef struct CMB {
  56     uint16_t ssch_rsch_count;
  57     uint16_t sample_count;
  58     uint32_t device_connect_time;
  59     uint32_t function_pending_time;
  60     uint32_t device_disconnect_time;
  61     uint32_t control_unit_queuing_time;
  62     uint32_t device_active_only_time;
  63     uint32_t reserved[2];
  64 } QEMU_PACKED CMB;
  65
  66 typedef struct CMBE {
  67     uint32_t ssch_rsch_count;
  68     uint32_t sample_count;
  69     uint32_t device_connect_time;
  70     uint32_t function_pending_time;
  71     uint32_t device_disconnect_time;
  72     uint32_t control_unit_queuing_time;
  73     uint32_t device_active_only_time;
  74     uint32_t device_busy_time;
  75     uint32_t initial_command_response_time;
  76     uint32_t reserved[7];
  77 } QEMU_PACKED CMBE;
  78
  79 typedef enum CcwDataStreamOp {
  80     CDS_OP_R = 0, /* read, false when used as is_write */
  81     CDS_OP_W = 1, /* write, true when used as is_write */
  82     CDS_OP_A = 2  /* advance, should not be used as is_write */
  83 } CcwDataStreamOp;
  84
  85 /* normal usage is via SuchchDev.cds instead of instantiating */
  86 typedef struct CcwDataStream {
  87 #define CDS_F_IDA   0x01
  88 #define CDS_F_MIDA  0x02
  89 #define CDS_F_I2K   0x04
  90 #define CDS_F_C64   0x08
  91 #define CDS_F_FMT   0x10 /* CCW format-1 */
  92 #define CDS_F_STREAM_BROKEN  0x80
  93     uint8_t flags;
  94     uint8_t at_idaw;
  95     uint16_t at_byte;
  96     uint16_t count;
  97     uint32_t cda_orig;
  98     int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
  99                       CcwDataStreamOp op);
 100     hwaddr cda;
 101     bool do_skip;
 102 } CcwDataStream;
 103
 104 /*
 105  * IO instructions conclude according to this. Currently we have only
 106  * cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
 107  * IO instructions is described briefly. For more details consult the PoP.
 108  */
 109 typedef enum IOInstEnding {
 110     /* produced expected result */
 111     IOINST_CC_EXPECTED = 0,
 112     /* status conditions were present or produced alternate result */
 113     IOINST_CC_STATUS_PRESENT = 1,
 114     /* inst. ineffective because busy with previously initiated function */
 115     IOINST_CC_BUSY = 2,
 116     /* inst. ineffective because not operational */
 117     IOINST_CC_NOT_OPERATIONAL = 3
 118 } IOInstEnding;
 119
 120 typedef struct SubchDev SubchDev;
 121 struct SubchDev {
 122     /* channel-subsystem related things: */
 123     SCHIB curr_status;           /* Needs alignment and thus must come first */
 124     ORB orb;
 125     uint8_t cssid;
 126     uint8_t ssid;
 127     uint16_t schid;
 128     uint16_t devno;
 129     uint8_t sense_data[32];
 130     hwaddr channel_prog;
 131     CCW1 last_cmd;
 132     bool last_cmd_valid;
 133     bool ccw_fmt_1;
 134     bool thinint_active;
 135     uint8_t ccw_no_data_cnt;
 136     uint16_t migrated_schid; /* used for mismatch detection */
 137     CcwDataStream cds;
 138     /* transport-provided data: */
 139     int (*ccw_cb) (SubchDev *, CCW1);
 140     void (*disable_cb)(SubchDev *);
 141     IOInstEnding (*do_subchannel_work) (SubchDev *);
 142     SenseId id;
 143     void *driver_data;
 144 };
 145
 146 static inline void sch_gen_unit_exception(SubchDev *sch)
 147 {
 148     sch->curr_status.scsw.ctrl &= ~SCSW_ACTL_START_PEND;
 149     sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY |
 150                                   SCSW_STCTL_SECONDARY |
 151                                   SCSW_STCTL_ALERT |
 152                                   SCSW_STCTL_STATUS_PEND;
 153     sch->curr_status.scsw.cpa = sch->channel_prog + 8;
 154     sch->curr_status.scsw.dstat =  SCSW_DSTAT_UNIT_EXCEP;
 155 }
 156
 157 extern const VMStateDescription vmstate_subch_dev;
 158
 159 /*
 160  * Identify a device within the channel subsystem.
 161  * Note that this can be used to identify either the subchannel or
 162  * the attached I/O device, as there's always one I/O device per
 163  * subchannel.
 164  */
 165 typedef struct CssDevId {
 166     uint8_t cssid;
 167     uint8_t ssid;
 168     uint16_t devid;
 169     bool valid;
 170 } CssDevId;
 171
 172 extern const PropertyInfo css_devid_propinfo;
 173
 174 #define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
 175     DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
 176
 177 typedef struct IndAddr {
 178     hwaddr addr;
 179     uint64_t map;
 180     unsigned long refcnt;
 181     int32_t len;
 182     QTAILQ_ENTRY(IndAddr) sibling;
 183 } IndAddr;
 184
 185 extern const VMStateDescription vmstate_ind_addr;
 186
 187 #define VMSTATE_PTR_TO_IND_ADDR(_f, _s)                                   \
 188     VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
 189
 190 IndAddr *get_indicator(hwaddr ind_addr, int len);
 191 void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
 192 int map_indicator(AdapterInfo *adapter, IndAddr *indicator);
 193
 194 typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
 195                                        uint16_t schid);
 196 int css_create_css_image(uint8_t cssid, bool default_image);
 197 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
 198 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
 199                       uint16_t devno, SubchDev *sch);
 200 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
 201 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
 202 unsigned int css_find_free_chpid(uint8_t cssid);
 203 uint16_t css_build_subchannel_id(SubchDev *sch);
 204 void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
 205 void css_inject_io_interrupt(SubchDev *sch);
 206 void css_reset(void);
 207 void css_reset_sch(SubchDev *sch);
 208 void css_crw_add_to_queue(CRW crw);
 209 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
 210                    int chain, uint16_t rsid);
 211 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
 212                            int hotplugged, int add);
 213 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
 214 void css_generate_css_crws(uint8_t cssid);
 215 void css_clear_sei_pending(void);
 216 IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
 217 IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
 218 IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);
 219
 220 int s390_ccw_halt(SubchDev *sch);
 221 int s390_ccw_clear(SubchDev *sch);
 222 IOInstEnding s390_ccw_store(SubchDev *sch);
 223
 224 typedef enum {
 225     CSS_IO_ADAPTER_VIRTIO = 0,
 226     CSS_IO_ADAPTER_PCI = 1,
 227     CSS_IO_ADAPTER_TYPE_NUMS,
 228 } CssIoAdapterType;
 229
 230 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
 231 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
 232 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
 233 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
 234                               uint8_t flags, Error **errp);
 235
 236 #ifndef CONFIG_KVM
 237 #define S390_ADAPTER_SUPPRESSIBLE 0x01
 238 #else
 239 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
 240 #endif
 241
 242 #ifndef CONFIG_USER_ONLY
 243 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 244                          uint16_t schid);
 245 bool css_subch_visible(SubchDev *sch);
 246 void css_conditional_io_interrupt(SubchDev *sch);
 247 IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib);
 248 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 249 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib);
 250 IOInstEnding css_do_xsch(SubchDev *sch);
 251 IOInstEnding css_do_csch(SubchDev *sch);
 252 IOInstEnding css_do_hsch(SubchDev *sch);
 253 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb);
 254 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 255 void css_do_tsch_update_subch(SubchDev *sch);
 256 int css_do_stcrw(CRW *crw);
 257 void css_undo_stcrw(CRW *crw);
 258 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 259                          int rfmt, void *buf);
 260 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 261 int css_enable_mcsse(void);
 262 int css_enable_mss(void);
 263 IOInstEnding css_do_rsch(SubchDev *sch);
 264 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 265 bool css_present(uint8_t cssid);
 266 #endif
 267
 268 extern const PropertyInfo css_devid_ro_propinfo;
 269
 270 #define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
 271     DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
 272
 273 /**
 274  * Create a subchannel for the given bus id.
 275  *
 276  * If @p bus_id is valid, verify that it is not already in use, and find a
 277  * free devno for it.
 278  * If @p bus_id is not valid find a free subchannel id and device number
 279  * across all subchannel sets and all css images starting from the default
 280  * css image.
 281  *
 282  * If either of the former actions succeed, allocate a subchannel structure,
 283  * initialise it with the bus id, subchannel id and device number, register
 284  * it with the CSS and return it. Otherwise return NULL.
 285  *
 286  * The caller becomes owner of the returned subchannel structure and
 287  * is responsible for unregistering and freeing it.
 288  */
 289 SubchDev *css_create_sch(CssDevId bus_id, Error **errp);
 290
 291 /** Turn on css migration */
 292 void css_register_vmstate(void);
 293
 294
 295 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);
 296
 297 static inline void ccw_dstream_rewind(CcwDataStream *cds)
 298 {
 299     cds->at_byte = 0;
 300     cds->at_idaw = 0;
 301     cds->cda = cds->cda_orig;
 302 }
 303
 304 static inline bool ccw_dstream_good(CcwDataStream *cds)
 305 {
 306     return !(cds->flags & CDS_F_STREAM_BROKEN);
 307 }
 308
 309 static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
 310 {
 311     return cds->count - cds->at_byte;
 312 }
 313
 314 static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
 315 {
 316     return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
 317 }
 318
 319 static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
 320 {
 321     return cds->op_handler(cds, NULL, len, CDS_OP_A);
 322 }
 323
 324 static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
 325 {
 326     return cds->op_handler(cds, buff, len, CDS_OP_W);
 327 }
 328
 329 static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
 330 {
 331     return cds->op_handler(cds, buff, len, CDS_OP_R);
 332 }
 333
 334 #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
 335 #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
 336
 337 #endif