2 * OSTimer device simulation in PKUnity SoC
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include "hw/sysbus.h"
15 #include "hw/ptimer.h"
16 #include "qemu/module.h"
19 #include "hw/unicore32/puv3.h"
21 #define TYPE_PUV3_OST "puv3_ost"
22 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
24 /* puv3 ostimer implementation. */
25 typedef struct PUV3OSTState
{
26 SysBusDevice parent_obj
;
38 static uint64_t puv3_ost_read(void *opaque
, hwaddr offset
,
41 PUV3OSTState
*s
= opaque
;
45 case 0x10: /* Counter Register */
46 ret
= s
->reg_OSMR0
- (uint32_t)ptimer_get_count(s
->ptimer
);
48 case 0x14: /* Status Register */
51 case 0x1c: /* Interrupt Enable Register */
55 DPRINTF("Bad offset %x\n", (int)offset
);
57 DPRINTF("offset 0x%x, value 0x%x\n", offset
, ret
);
61 static void puv3_ost_write(void *opaque
, hwaddr offset
,
62 uint64_t value
, unsigned size
)
64 PUV3OSTState
*s
= opaque
;
66 DPRINTF("offset 0x%x, value 0x%x\n", offset
, value
);
68 case 0x00: /* Match Register 0 */
69 ptimer_transaction_begin(s
->ptimer
);
71 if (s
->reg_OSMR0
> s
->reg_OSCR
) {
72 ptimer_set_count(s
->ptimer
, s
->reg_OSMR0
- s
->reg_OSCR
);
74 ptimer_set_count(s
->ptimer
, s
->reg_OSMR0
+
75 (0xffffffff - s
->reg_OSCR
));
77 ptimer_run(s
->ptimer
, 2);
78 ptimer_transaction_commit(s
->ptimer
);
80 case 0x14: /* Status Register */
84 qemu_irq_lower(s
->irq
);
87 case 0x1c: /* Interrupt Enable Register */
91 DPRINTF("Bad offset %x\n", (int)offset
);
95 static const MemoryRegionOps puv3_ost_ops
= {
96 .read
= puv3_ost_read
,
97 .write
= puv3_ost_write
,
100 .max_access_size
= 4,
102 .endianness
= DEVICE_NATIVE_ENDIAN
,
105 static void puv3_ost_tick(void *opaque
)
107 PUV3OSTState
*s
= opaque
;
109 DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
110 s
->reg_OSCR
, s
->reg_OSMR0
);
112 s
->reg_OSCR
= s
->reg_OSMR0
;
115 qemu_irq_raise(s
->irq
);
119 static void puv3_ost_realize(DeviceState
*dev
, Error
**errp
)
121 PUV3OSTState
*s
= PUV3_OST(dev
);
122 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
129 sysbus_init_irq(sbd
, &s
->irq
);
131 s
->ptimer
= ptimer_init(puv3_ost_tick
, s
, PTIMER_POLICY_DEFAULT
);
132 ptimer_transaction_begin(s
->ptimer
);
133 ptimer_set_freq(s
->ptimer
, 50 * 1000 * 1000);
134 ptimer_transaction_commit(s
->ptimer
);
136 memory_region_init_io(&s
->iomem
, OBJECT(s
), &puv3_ost_ops
, s
, "puv3_ost",
138 sysbus_init_mmio(sbd
, &s
->iomem
);
141 static void puv3_ost_class_init(ObjectClass
*klass
, void *data
)
143 DeviceClass
*dc
= DEVICE_CLASS(klass
);
145 dc
->realize
= puv3_ost_realize
;
148 static const TypeInfo puv3_ost_info
= {
149 .name
= TYPE_PUV3_OST
,
150 .parent
= TYPE_SYS_BUS_DEVICE
,
151 .instance_size
= sizeof(PUV3OSTState
),
152 .class_init
= puv3_ost_class_init
,
155 static void puv3_ost_register_type(void)
157 type_register_static(&puv3_ost_info
);
160 type_init(puv3_ost_register_type
)