hw/misc/mps2-scc.c

   1 /*
   2  * ARM MPS2 SCC emulation
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* This is a model of the SCC (Serial Communication Controller)
  13  * found in the FPGA images of MPS2 development boards.
  14  *
  15  * Documentation of it can be found in the MPS2 TRM:
  16  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
  17  * and also in the Application Notes documenting individual FPGA images.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/module.h"
  23 #include "trace.h"
  24 #include "hw/sysbus.h"
  25 #include "migration/vmstate.h"
  26 #include "hw/registerfields.h"
  27 #include "hw/misc/mps2-scc.h"
  28 #include "hw/qdev-properties.h"
  29
  30 REG32(CFG0, 0)
  31 REG32(CFG1, 4)
  32 REG32(CFG3, 0xc)
  33 REG32(CFG4, 0x10)
  34 REG32(CFGDATA_RTN, 0xa0)
  35 REG32(CFGDATA_OUT, 0xa4)
  36 REG32(CFGCTRL, 0xa8)
  37     FIELD(CFGCTRL, DEVICE, 0, 12)
  38     FIELD(CFGCTRL, RES1, 12, 8)
  39     FIELD(CFGCTRL, FUNCTION, 20, 6)
  40     FIELD(CFGCTRL, RES2, 26, 4)
  41     FIELD(CFGCTRL, WRITE, 30, 1)
  42     FIELD(CFGCTRL, START, 31, 1)
  43 REG32(CFGSTAT, 0xac)
  44     FIELD(CFGSTAT, DONE, 0, 1)
  45     FIELD(CFGSTAT, ERROR, 1, 1)
  46 REG32(DLL, 0x100)
  47 REG32(AID, 0xFF8)
  48 REG32(ID, 0xFFC)
  49
  50 /* Handle a write via the SYS_CFG channel to the specified function/device.
  51  * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
  52  */
  53 static bool scc_cfg_write(MPS2SCC *s, unsigned function,
  54                           unsigned device, uint32_t value)
  55 {
  56     trace_mps2_scc_cfg_write(function, device, value);
  57
  58     if (function != 1 || device >= NUM_OSCCLK) {
  59         qemu_log_mask(LOG_GUEST_ERROR,
  60                       "MPS2 SCC config write: bad function %d device %d\n",
  61                       function, device);
  62         return false;
  63     }
  64
  65     s->oscclk[device] = value;
  66     return true;
  67 }
  68
  69 /* Handle a read via the SYS_CFG channel to the specified function/device.
  70  * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit),
  71  * or set *value on success.
  72  */
  73 static bool scc_cfg_read(MPS2SCC *s, unsigned function,
  74                          unsigned device, uint32_t *value)
  75 {
  76     if (function != 1 || device >= NUM_OSCCLK) {
  77         qemu_log_mask(LOG_GUEST_ERROR,
  78                       "MPS2 SCC config read: bad function %d device %d\n",
  79                       function, device);
  80         return false;
  81     }
  82
  83     *value = s->oscclk[device];
  84
  85     trace_mps2_scc_cfg_read(function, device, *value);
  86     return true;
  87 }
  88
  89 static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
  90 {
  91     MPS2SCC *s = MPS2_SCC(opaque);
  92     uint64_t r;
  93
  94     switch (offset) {
  95     case A_CFG0:
  96         r = s->cfg0;
  97         break;
  98     case A_CFG1:
  99         r = s->cfg1;
 100         break;
 101     case A_CFG3:
 102         /* These are user-settable DIP switches on the board. We don't
 103          * model that, so just return zeroes.
 104          */
 105         r = 0;
 106         break;
 107     case A_CFG4:
 108         r = s->cfg4;
 109         break;
 110     case A_CFGDATA_RTN:
 111         r = s->cfgdata_rtn;
 112         break;
 113     case A_CFGDATA_OUT:
 114         r = s->cfgdata_out;
 115         break;
 116     case A_CFGCTRL:
 117         r = s->cfgctrl;
 118         break;
 119     case A_CFGSTAT:
 120         r = s->cfgstat;
 121         break;
 122     case A_DLL:
 123         r = s->dll;
 124         break;
 125     case A_AID:
 126         r = s->aid;
 127         break;
 128     case A_ID:
 129         r = s->id;
 130         break;
 131     default:
 132         qemu_log_mask(LOG_GUEST_ERROR,
 133                       "MPS2 SCC read: bad offset %x\n", (int) offset);
 134         r = 0;
 135         break;
 136     }
 137
 138     trace_mps2_scc_read(offset, r, size);
 139     return r;
 140 }
 141
 142 static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
 143                            unsigned size)
 144 {
 145     MPS2SCC *s = MPS2_SCC(opaque);
 146
 147     trace_mps2_scc_write(offset, value, size);
 148
 149     switch (offset) {
 150     case A_CFG0:
 151         /* TODO on some boards bit 0 controls RAM remapping */
 152         s->cfg0 = value;
 153         break;
 154     case A_CFG1:
 155         /* CFG1 bits [7:0] control the board LEDs. We don't currently have
 156          * a mechanism for displaying this graphically, so use a trace event.
 157          */
 158         trace_mps2_scc_leds(value & 0x80 ? '*' : '.',
 159                             value & 0x40 ? '*' : '.',
 160                             value & 0x20 ? '*' : '.',
 161                             value & 0x10 ? '*' : '.',
 162                             value & 0x08 ? '*' : '.',
 163                             value & 0x04 ? '*' : '.',
 164                             value & 0x02 ? '*' : '.',
 165                             value & 0x01 ? '*' : '.');
 166         s->cfg1 = value;
 167         break;
 168     case A_CFGDATA_OUT:
 169         s->cfgdata_out = value;
 170         break;
 171     case A_CFGCTRL:
 172         /* Writing to CFGCTRL clears SYS_CFGSTAT */
 173         s->cfgstat = 0;
 174         s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK |
 175                                R_CFGCTRL_RES2_MASK |
 176                                R_CFGCTRL_START_MASK);
 177
 178         if (value & R_CFGCTRL_START_MASK) {
 179             /* Start bit set -- do a read or write (instantaneously) */
 180             int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT,
 181                                    R_CFGCTRL_DEVICE_LENGTH);
 182             int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT,
 183                                      R_CFGCTRL_FUNCTION_LENGTH);
 184
 185             s->cfgstat = R_CFGSTAT_DONE_MASK;
 186             if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) {
 187                 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) {
 188                     s->cfgstat |= R_CFGSTAT_ERROR_MASK;
 189                 }
 190             } else {
 191                 uint32_t result;
 192                 if (!scc_cfg_read(s, function, device, &result)) {
 193                     s->cfgstat |= R_CFGSTAT_ERROR_MASK;
 194                 } else {
 195                     s->cfgdata_rtn = result;
 196                 }
 197             }
 198         }
 199         break;
 200     case A_DLL:
 201         /* DLL stands for Digital Locked Loop.
 202          * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a
 203          * mask of which of the DLL_LOCKED bits [16:23] should be ORed
 204          * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0].
 205          * For QEMU, our DLLs are always locked, so we can leave bit 0
 206          * as 1 always and don't need to recalculate it.
 207          */
 208         s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));
 209         break;
 210     default:
 211         qemu_log_mask(LOG_GUEST_ERROR,
 212                       "MPS2 SCC write: bad offset 0x%x\n", (int) offset);
 213         break;
 214     }
 215 }
 216
 217 static const MemoryRegionOps mps2_scc_ops = {
 218     .read = mps2_scc_read,
 219     .write = mps2_scc_write,
 220     .endianness = DEVICE_LITTLE_ENDIAN,
 221 };
 222
 223 static void mps2_scc_reset(DeviceState *dev)
 224 {
 225     MPS2SCC *s = MPS2_SCC(dev);
 226     int i;
 227
 228     trace_mps2_scc_reset();
 229     s->cfg0 = 0;
 230     s->cfg1 = 0;
 231     s->cfgdata_rtn = 0;
 232     s->cfgdata_out = 0;
 233     s->cfgctrl = 0x100000;
 234     s->cfgstat = 0;
 235     s->dll = 0xffff0001;
 236     for (i = 0; i < NUM_OSCCLK; i++) {
 237         s->oscclk[i] = s->oscclk_reset[i];
 238     }
 239 }
 240
 241 static void mps2_scc_init(Object *obj)
 242 {
 243     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 244     MPS2SCC *s = MPS2_SCC(obj);
 245
 246     memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);
 247     sysbus_init_mmio(sbd, &s->iomem);
 248 }
 249
 250 static void mps2_scc_realize(DeviceState *dev, Error **errp)
 251 {
 252 }
 253
 254 static const VMStateDescription mps2_scc_vmstate = {
 255     .name = "mps2-scc",
 256     .version_id = 1,
 257     .minimum_version_id = 1,
 258     .fields = (VMStateField[]) {
 259         VMSTATE_UINT32(cfg0, MPS2SCC),
 260         VMSTATE_UINT32(cfg1, MPS2SCC),
 261         VMSTATE_UINT32(cfgdata_rtn, MPS2SCC),
 262         VMSTATE_UINT32(cfgdata_out, MPS2SCC),
 263         VMSTATE_UINT32(cfgctrl, MPS2SCC),
 264         VMSTATE_UINT32(cfgstat, MPS2SCC),
 265         VMSTATE_UINT32(dll, MPS2SCC),
 266         VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK),
 267         VMSTATE_END_OF_LIST()
 268     }
 269 };
 270
 271 static Property mps2_scc_properties[] = {
 272     /* Values for various read-only ID registers (which are specific
 273      * to the board model or FPGA image)
 274      */
 275     DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
 276     DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
 277     DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
 278     /* These are the initial settings for the source clocks on the board.
 279      * In hardware they can be configured via a config file read by the
 280      * motherboard configuration controller to suit the FPGA image.
 281      * These default values are used by most of the standard FPGA images.
 282      */
 283     DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000),
 284     DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000),
 285     DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000),
 286     DEFINE_PROP_END_OF_LIST(),
 287 };
 288
 289 static void mps2_scc_class_init(ObjectClass *klass, void *data)
 290 {
 291     DeviceClass *dc = DEVICE_CLASS(klass);
 292
 293     dc->realize = mps2_scc_realize;
 294     dc->vmsd = &mps2_scc_vmstate;
 295     dc->reset = mps2_scc_reset;
 296     device_class_set_props(dc, mps2_scc_properties);
 297 }
 298
 299 static const TypeInfo mps2_scc_info = {
 300     .name = TYPE_MPS2_SCC,
 301     .parent = TYPE_SYS_BUS_DEVICE,
 302     .instance_size = sizeof(MPS2SCC),
 303     .instance_init = mps2_scc_init,
 304     .class_init = mps2_scc_class_init,
 305 };
 306
 307 static void mps2_scc_register_types(void)
 308 {
 309     type_register_static(&mps2_scc_info);
 310 }
 311
 312 type_init(mps2_scc_register_types);