hw/intc/etraxfs_pic.c

   1 /*
   2  * QEMU ETRAX Interrupt Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "qemu/module.h"
  28 #include "hw/irq.h"
  29 #include "hw/qdev-properties.h"
  30
  31 #define D(x)
  32
  33 #define R_RW_MASK   0
  34 #define R_R_VECT    1
  35 #define R_R_MASKED_VECT 2
  36 #define R_R_NMI     3
  37 #define R_R_GURU    4
  38 #define R_MAX       5
  39
  40 #define TYPE_ETRAX_FS_PIC "etraxfs,pic"
  41 #define ETRAX_FS_PIC(obj) \
  42     OBJECT_CHECK(struct etrax_pic, (obj), TYPE_ETRAX_FS_PIC)
  43
  44 struct etrax_pic
  45 {
  46     SysBusDevice parent_obj;
  47
  48     MemoryRegion mmio;
  49     qemu_irq parent_irq;
  50     qemu_irq parent_nmi;
  51     uint32_t regs[R_MAX];
  52 };
  53
  54 static void pic_update(struct etrax_pic *fs)
  55 {
  56     uint32_t vector = 0;
  57     int i;
  58
  59     fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
  60
  61     /* The ETRAX interrupt controller signals interrupts to the core
  62        through an interrupt request wire and an irq vector bus. If
  63        multiple interrupts are simultaneously active it chooses vector
  64        0x30 and lets the sw choose the priorities.  */
  65     if (fs->regs[R_R_MASKED_VECT]) {
  66         uint32_t mv = fs->regs[R_R_MASKED_VECT];
  67         for (i = 0; i < 31; i++) {
  68             if (mv & 1) {
  69                 vector = 0x31 + i;
  70                 /* Check for multiple interrupts.  */
  71                 if (mv > 1)
  72                     vector = 0x30;
  73                 break;
  74             }
  75             mv >>= 1;
  76         }
  77     }
  78
  79     qemu_set_irq(fs->parent_irq, vector);
  80 }
  81
  82 static uint64_t
  83 pic_read(void *opaque, hwaddr addr, unsigned int size)
  84 {
  85     struct etrax_pic *fs = opaque;
  86     uint32_t rval;
  87
  88     rval = fs->regs[addr >> 2];
  89     D(printf("%s %x=%x\n", __func__, addr, rval));
  90     return rval;
  91 }
  92
  93 static void pic_write(void *opaque, hwaddr addr,
  94                       uint64_t value, unsigned int size)
  95 {
  96     struct etrax_pic *fs = opaque;
  97     D(printf("%s addr=%x val=%x\n", __func__, addr, value));
  98
  99     if (addr == R_RW_MASK) {
 100         fs->regs[R_RW_MASK] = value;
 101         pic_update(fs);
 102     }
 103 }
 104
 105 static const MemoryRegionOps pic_ops = {
 106     .read = pic_read,
 107     .write = pic_write,
 108     .endianness = DEVICE_NATIVE_ENDIAN,
 109     .valid = {
 110         .min_access_size = 4,
 111         .max_access_size = 4
 112     }
 113 };
 114
 115 static void nmi_handler(void *opaque, int irq, int level)
 116 {
 117     struct etrax_pic *fs = (void *)opaque;
 118     uint32_t mask;
 119
 120     mask = 1 << irq;
 121     if (level)
 122         fs->regs[R_R_NMI] |= mask;
 123     else
 124         fs->regs[R_R_NMI] &= ~mask;
 125
 126     qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
 127 }
 128
 129 static void irq_handler(void *opaque, int irq, int level)
 130 {
 131     struct etrax_pic *fs = (void *)opaque;
 132
 133     if (irq >= 30) {
 134         nmi_handler(opaque, irq, level);
 135         return;
 136     }
 137
 138     irq -= 1;
 139     fs->regs[R_R_VECT] &= ~(1 << irq);
 140     fs->regs[R_R_VECT] |= (!!level << irq);
 141     pic_update(fs);
 142 }
 143
 144 static void etraxfs_pic_init(Object *obj)
 145 {
 146     DeviceState *dev = DEVICE(obj);
 147     struct etrax_pic *s = ETRAX_FS_PIC(obj);
 148     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 149
 150     qdev_init_gpio_in(dev, irq_handler, 32);
 151     sysbus_init_irq(sbd, &s->parent_irq);
 152     sysbus_init_irq(sbd, &s->parent_nmi);
 153
 154     memory_region_init_io(&s->mmio, obj, &pic_ops, s,
 155                           "etraxfs-pic", R_MAX * 4);
 156     sysbus_init_mmio(sbd, &s->mmio);
 157 }
 158
 159 static const TypeInfo etraxfs_pic_info = {
 160     .name          = TYPE_ETRAX_FS_PIC,
 161     .parent        = TYPE_SYS_BUS_DEVICE,
 162     .instance_size = sizeof(struct etrax_pic),
 163     .instance_init = etraxfs_pic_init,
 164 };
 165
 166 static void etraxfs_pic_register_types(void)
 167 {
 168     type_register_static(&etraxfs_pic_info);
 169 }
 170
 171 type_init(etraxfs_pic_register_types)