iommu: Add IOMMU index argument to notifier APIs
[qemu/ar7.git] / exec.c
blob1fa2cdb874fb8c819c4b1843873b061be469f2a3
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
26 #include "tcg.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
53 #endif
55 #endif
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
68 #ifndef _WIN32
69 #include "qemu/mmap-alloc.h"
70 #endif
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 /* UFFDIO_ZEROPAGE is available on this RAMBlock to atomically
103 * zero the page and wake waiting processes.
104 * (Set during postcopy)
106 #define RAM_UF_ZEROPAGE (1 << 3)
108 /* RAM can be migrated */
109 #define RAM_MIGRATABLE (1 << 4)
110 #endif
112 #ifdef TARGET_PAGE_BITS_VARY
113 int target_page_bits;
114 bool target_page_bits_decided;
115 #endif
117 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
118 /* current CPU in the current thread. It is only valid inside
119 cpu_exec() */
120 __thread CPUState *current_cpu;
121 /* 0 = Do not count executed instructions.
122 1 = Precise instruction counting.
123 2 = Adaptive rate instruction counting. */
124 int use_icount;
126 uintptr_t qemu_host_page_size;
127 intptr_t qemu_host_page_mask;
129 bool set_preferred_target_page_bits(int bits)
131 /* The target page size is the lowest common denominator for all
132 * the CPUs in the system, so we can only make it smaller, never
133 * larger. And we can't make it smaller once we've committed to
134 * a particular size.
136 #ifdef TARGET_PAGE_BITS_VARY
137 assert(bits >= TARGET_PAGE_BITS_MIN);
138 if (target_page_bits == 0 || target_page_bits > bits) {
139 if (target_page_bits_decided) {
140 return false;
142 target_page_bits = bits;
144 #endif
145 return true;
148 #if !defined(CONFIG_USER_ONLY)
150 static void finalize_target_page_bits(void)
152 #ifdef TARGET_PAGE_BITS_VARY
153 if (target_page_bits == 0) {
154 target_page_bits = TARGET_PAGE_BITS_MIN;
156 target_page_bits_decided = true;
157 #endif
160 typedef struct PhysPageEntry PhysPageEntry;
162 struct PhysPageEntry {
163 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
164 uint32_t skip : 6;
165 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
166 uint32_t ptr : 26;
169 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
171 /* Size of the L2 (and L3, etc) page tables. */
172 #define ADDR_SPACE_BITS 64
174 #define P_L2_BITS 9
175 #define P_L2_SIZE (1 << P_L2_BITS)
177 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
179 typedef PhysPageEntry Node[P_L2_SIZE];
181 typedef struct PhysPageMap {
182 struct rcu_head rcu;
184 unsigned sections_nb;
185 unsigned sections_nb_alloc;
186 unsigned nodes_nb;
187 unsigned nodes_nb_alloc;
188 Node *nodes;
189 MemoryRegionSection *sections;
190 } PhysPageMap;
192 struct AddressSpaceDispatch {
193 MemoryRegionSection *mru_section;
194 /* This is a multi-level map on the physical address space.
195 * The bottom level has pointers to MemoryRegionSections.
197 PhysPageEntry phys_map;
198 PhysPageMap map;
201 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
202 typedef struct subpage_t {
203 MemoryRegion iomem;
204 FlatView *fv;
205 hwaddr base;
206 uint16_t sub_section[];
207 } subpage_t;
209 #define PHYS_SECTION_UNASSIGNED 0
210 #define PHYS_SECTION_NOTDIRTY 1
211 #define PHYS_SECTION_ROM 2
212 #define PHYS_SECTION_WATCH 3
214 static void io_mem_init(void);
215 static void memory_map_init(void);
216 static void tcg_commit(MemoryListener *listener);
218 static MemoryRegion io_mem_watch;
221 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
222 * @cpu: the CPU whose AddressSpace this is
223 * @as: the AddressSpace itself
224 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
225 * @tcg_as_listener: listener for tracking changes to the AddressSpace
227 struct CPUAddressSpace {
228 CPUState *cpu;
229 AddressSpace *as;
230 struct AddressSpaceDispatch *memory_dispatch;
231 MemoryListener tcg_as_listener;
234 struct DirtyBitmapSnapshot {
235 ram_addr_t start;
236 ram_addr_t end;
237 unsigned long dirty[];
240 #endif
242 #if !defined(CONFIG_USER_ONLY)
244 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
246 static unsigned alloc_hint = 16;
247 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
248 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
249 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
250 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
251 alloc_hint = map->nodes_nb_alloc;
255 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
257 unsigned i;
258 uint32_t ret;
259 PhysPageEntry e;
260 PhysPageEntry *p;
262 ret = map->nodes_nb++;
263 p = map->nodes[ret];
264 assert(ret != PHYS_MAP_NODE_NIL);
265 assert(ret != map->nodes_nb_alloc);
267 e.skip = leaf ? 0 : 1;
268 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
269 for (i = 0; i < P_L2_SIZE; ++i) {
270 memcpy(&p[i], &e, sizeof(e));
272 return ret;
275 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
276 hwaddr *index, hwaddr *nb, uint16_t leaf,
277 int level)
279 PhysPageEntry *p;
280 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
282 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
283 lp->ptr = phys_map_node_alloc(map, level == 0);
285 p = map->nodes[lp->ptr];
286 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
288 while (*nb && lp < &p[P_L2_SIZE]) {
289 if ((*index & (step - 1)) == 0 && *nb >= step) {
290 lp->skip = 0;
291 lp->ptr = leaf;
292 *index += step;
293 *nb -= step;
294 } else {
295 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
297 ++lp;
301 static void phys_page_set(AddressSpaceDispatch *d,
302 hwaddr index, hwaddr nb,
303 uint16_t leaf)
305 /* Wildly overreserve - it doesn't matter much. */
306 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
308 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
311 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
312 * and update our entry so we can skip it and go directly to the destination.
314 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
316 unsigned valid_ptr = P_L2_SIZE;
317 int valid = 0;
318 PhysPageEntry *p;
319 int i;
321 if (lp->ptr == PHYS_MAP_NODE_NIL) {
322 return;
325 p = nodes[lp->ptr];
326 for (i = 0; i < P_L2_SIZE; i++) {
327 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
328 continue;
331 valid_ptr = i;
332 valid++;
333 if (p[i].skip) {
334 phys_page_compact(&p[i], nodes);
338 /* We can only compress if there's only one child. */
339 if (valid != 1) {
340 return;
343 assert(valid_ptr < P_L2_SIZE);
345 /* Don't compress if it won't fit in the # of bits we have. */
346 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
347 return;
350 lp->ptr = p[valid_ptr].ptr;
351 if (!p[valid_ptr].skip) {
352 /* If our only child is a leaf, make this a leaf. */
353 /* By design, we should have made this node a leaf to begin with so we
354 * should never reach here.
355 * But since it's so simple to handle this, let's do it just in case we
356 * change this rule.
358 lp->skip = 0;
359 } else {
360 lp->skip += p[valid_ptr].skip;
364 void address_space_dispatch_compact(AddressSpaceDispatch *d)
366 if (d->phys_map.skip) {
367 phys_page_compact(&d->phys_map, d->map.nodes);
371 static inline bool section_covers_addr(const MemoryRegionSection *section,
372 hwaddr addr)
374 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
375 * the section must cover the entire address space.
377 return int128_gethi(section->size) ||
378 range_covers_byte(section->offset_within_address_space,
379 int128_getlo(section->size), addr);
382 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
384 PhysPageEntry lp = d->phys_map, *p;
385 Node *nodes = d->map.nodes;
386 MemoryRegionSection *sections = d->map.sections;
387 hwaddr index = addr >> TARGET_PAGE_BITS;
388 int i;
390 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
391 if (lp.ptr == PHYS_MAP_NODE_NIL) {
392 return &sections[PHYS_SECTION_UNASSIGNED];
394 p = nodes[lp.ptr];
395 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
398 if (section_covers_addr(&sections[lp.ptr], addr)) {
399 return &sections[lp.ptr];
400 } else {
401 return &sections[PHYS_SECTION_UNASSIGNED];
405 bool memory_region_is_unassigned(MemoryRegion *mr)
407 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
408 && mr != &io_mem_watch;
411 /* Called from RCU critical section */
412 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
413 hwaddr addr,
414 bool resolve_subpage)
416 MemoryRegionSection *section = atomic_read(&d->mru_section);
417 subpage_t *subpage;
419 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
420 !section_covers_addr(section, addr)) {
421 section = phys_page_find(d, addr);
422 atomic_set(&d->mru_section, section);
424 if (resolve_subpage && section->mr->subpage) {
425 subpage = container_of(section->mr, subpage_t, iomem);
426 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
428 return section;
431 /* Called from RCU critical section */
432 static MemoryRegionSection *
433 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
434 hwaddr *plen, bool resolve_subpage)
436 MemoryRegionSection *section;
437 MemoryRegion *mr;
438 Int128 diff;
440 section = address_space_lookup_region(d, addr, resolve_subpage);
441 /* Compute offset within MemoryRegionSection */
442 addr -= section->offset_within_address_space;
444 /* Compute offset within MemoryRegion */
445 *xlat = addr + section->offset_within_region;
447 mr = section->mr;
449 /* MMIO registers can be expected to perform full-width accesses based only
450 * on their address, without considering adjacent registers that could
451 * decode to completely different MemoryRegions. When such registers
452 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
453 * regions overlap wildly. For this reason we cannot clamp the accesses
454 * here.
456 * If the length is small (as is the case for address_space_ldl/stl),
457 * everything works fine. If the incoming length is large, however,
458 * the caller really has to do the clamping through memory_access_size.
460 if (memory_region_is_ram(mr)) {
461 diff = int128_sub(section->size, int128_make64(addr));
462 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
464 return section;
468 * address_space_translate_iommu - translate an address through an IOMMU
469 * memory region and then through the target address space.
471 * @iommu_mr: the IOMMU memory region that we start the translation from
472 * @addr: the address to be translated through the MMU
473 * @xlat: the translated address offset within the destination memory region.
474 * It cannot be %NULL.
475 * @plen_out: valid read/write length of the translated address. It
476 * cannot be %NULL.
477 * @page_mask_out: page mask for the translated address. This
478 * should only be meaningful for IOMMU translated
479 * addresses, since there may be huge pages that this bit
480 * would tell. It can be %NULL if we don't care about it.
481 * @is_write: whether the translation operation is for write
482 * @is_mmio: whether this can be MMIO, set true if it can
483 * @target_as: the address space targeted by the IOMMU
484 * @attrs: transaction attributes
486 * This function is called from RCU critical section. It is the common
487 * part of flatview_do_translate and address_space_translate_cached.
489 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
490 hwaddr *xlat,
491 hwaddr *plen_out,
492 hwaddr *page_mask_out,
493 bool is_write,
494 bool is_mmio,
495 AddressSpace **target_as,
496 MemTxAttrs attrs)
498 MemoryRegionSection *section;
499 hwaddr page_mask = (hwaddr)-1;
501 do {
502 hwaddr addr = *xlat;
503 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
504 IOMMUTLBEntry iotlb = imrc->translate(iommu_mr, addr, is_write ?
505 IOMMU_WO : IOMMU_RO);
507 if (!(iotlb.perm & (1 << is_write))) {
508 goto unassigned;
511 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
512 | (addr & iotlb.addr_mask));
513 page_mask &= iotlb.addr_mask;
514 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
515 *target_as = iotlb.target_as;
517 section = address_space_translate_internal(
518 address_space_to_dispatch(iotlb.target_as), addr, xlat,
519 plen_out, is_mmio);
521 iommu_mr = memory_region_get_iommu(section->mr);
522 } while (unlikely(iommu_mr));
524 if (page_mask_out) {
525 *page_mask_out = page_mask;
527 return *section;
529 unassigned:
530 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
534 * flatview_do_translate - translate an address in FlatView
536 * @fv: the flat view that we want to translate on
537 * @addr: the address to be translated in above address space
538 * @xlat: the translated address offset within memory region. It
539 * cannot be @NULL.
540 * @plen_out: valid read/write length of the translated address. It
541 * can be @NULL when we don't care about it.
542 * @page_mask_out: page mask for the translated address. This
543 * should only be meaningful for IOMMU translated
544 * addresses, since there may be huge pages that this bit
545 * would tell. It can be @NULL if we don't care about it.
546 * @is_write: whether the translation operation is for write
547 * @is_mmio: whether this can be MMIO, set true if it can
548 * @target_as: the address space targeted by the IOMMU
549 * @attrs: memory transaction attributes
551 * This function is called from RCU critical section
553 static MemoryRegionSection flatview_do_translate(FlatView *fv,
554 hwaddr addr,
555 hwaddr *xlat,
556 hwaddr *plen_out,
557 hwaddr *page_mask_out,
558 bool is_write,
559 bool is_mmio,
560 AddressSpace **target_as,
561 MemTxAttrs attrs)
563 MemoryRegionSection *section;
564 IOMMUMemoryRegion *iommu_mr;
565 hwaddr plen = (hwaddr)(-1);
567 if (!plen_out) {
568 plen_out = &plen;
571 section = address_space_translate_internal(
572 flatview_to_dispatch(fv), addr, xlat,
573 plen_out, is_mmio);
575 iommu_mr = memory_region_get_iommu(section->mr);
576 if (unlikely(iommu_mr)) {
577 return address_space_translate_iommu(iommu_mr, xlat,
578 plen_out, page_mask_out,
579 is_write, is_mmio,
580 target_as, attrs);
582 if (page_mask_out) {
583 /* Not behind an IOMMU, use default page size. */
584 *page_mask_out = ~TARGET_PAGE_MASK;
587 return *section;
590 /* Called from RCU critical section */
591 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
592 bool is_write, MemTxAttrs attrs)
594 MemoryRegionSection section;
595 hwaddr xlat, page_mask;
598 * This can never be MMIO, and we don't really care about plen,
599 * but page mask.
601 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
602 NULL, &page_mask, is_write, false, &as,
603 attrs);
605 /* Illegal translation */
606 if (section.mr == &io_mem_unassigned) {
607 goto iotlb_fail;
610 /* Convert memory region offset into address space offset */
611 xlat += section.offset_within_address_space -
612 section.offset_within_region;
614 return (IOMMUTLBEntry) {
615 .target_as = as,
616 .iova = addr & ~page_mask,
617 .translated_addr = xlat & ~page_mask,
618 .addr_mask = page_mask,
619 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
620 .perm = IOMMU_RW,
623 iotlb_fail:
624 return (IOMMUTLBEntry) {0};
627 /* Called from RCU critical section */
628 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
629 hwaddr *plen, bool is_write,
630 MemTxAttrs attrs)
632 MemoryRegion *mr;
633 MemoryRegionSection section;
634 AddressSpace *as = NULL;
636 /* This can be MMIO, so setup MMIO bit. */
637 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
638 is_write, true, &as, attrs);
639 mr = section.mr;
641 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
642 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
643 *plen = MIN(page, *plen);
646 return mr;
649 /* Called from RCU critical section */
650 MemoryRegionSection *
651 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
652 hwaddr *xlat, hwaddr *plen)
654 MemoryRegionSection *section;
655 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
657 section = address_space_translate_internal(d, addr, xlat, plen, false);
659 assert(!memory_region_is_iommu(section->mr));
660 return section;
662 #endif
664 #if !defined(CONFIG_USER_ONLY)
666 static int cpu_common_post_load(void *opaque, int version_id)
668 CPUState *cpu = opaque;
670 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
671 version_id is increased. */
672 cpu->interrupt_request &= ~0x01;
673 tlb_flush(cpu);
675 /* loadvm has just updated the content of RAM, bypassing the
676 * usual mechanisms that ensure we flush TBs for writes to
677 * memory we've translated code from. So we must flush all TBs,
678 * which will now be stale.
680 tb_flush(cpu);
682 return 0;
685 static int cpu_common_pre_load(void *opaque)
687 CPUState *cpu = opaque;
689 cpu->exception_index = -1;
691 return 0;
694 static bool cpu_common_exception_index_needed(void *opaque)
696 CPUState *cpu = opaque;
698 return tcg_enabled() && cpu->exception_index != -1;
701 static const VMStateDescription vmstate_cpu_common_exception_index = {
702 .name = "cpu_common/exception_index",
703 .version_id = 1,
704 .minimum_version_id = 1,
705 .needed = cpu_common_exception_index_needed,
706 .fields = (VMStateField[]) {
707 VMSTATE_INT32(exception_index, CPUState),
708 VMSTATE_END_OF_LIST()
712 static bool cpu_common_crash_occurred_needed(void *opaque)
714 CPUState *cpu = opaque;
716 return cpu->crash_occurred;
719 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
720 .name = "cpu_common/crash_occurred",
721 .version_id = 1,
722 .minimum_version_id = 1,
723 .needed = cpu_common_crash_occurred_needed,
724 .fields = (VMStateField[]) {
725 VMSTATE_BOOL(crash_occurred, CPUState),
726 VMSTATE_END_OF_LIST()
730 const VMStateDescription vmstate_cpu_common = {
731 .name = "cpu_common",
732 .version_id = 1,
733 .minimum_version_id = 1,
734 .pre_load = cpu_common_pre_load,
735 .post_load = cpu_common_post_load,
736 .fields = (VMStateField[]) {
737 VMSTATE_UINT32(halted, CPUState),
738 VMSTATE_UINT32(interrupt_request, CPUState),
739 VMSTATE_END_OF_LIST()
741 .subsections = (const VMStateDescription*[]) {
742 &vmstate_cpu_common_exception_index,
743 &vmstate_cpu_common_crash_occurred,
744 NULL
748 #endif
750 CPUState *qemu_get_cpu(int index)
752 CPUState *cpu;
754 CPU_FOREACH(cpu) {
755 if (cpu->cpu_index == index) {
756 return cpu;
760 return NULL;
763 #if !defined(CONFIG_USER_ONLY)
764 void cpu_address_space_init(CPUState *cpu, int asidx,
765 const char *prefix, MemoryRegion *mr)
767 CPUAddressSpace *newas;
768 AddressSpace *as = g_new0(AddressSpace, 1);
769 char *as_name;
771 assert(mr);
772 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
773 address_space_init(as, mr, as_name);
774 g_free(as_name);
776 /* Target code should have set num_ases before calling us */
777 assert(asidx < cpu->num_ases);
779 if (asidx == 0) {
780 /* address space 0 gets the convenience alias */
781 cpu->as = as;
784 /* KVM cannot currently support multiple address spaces. */
785 assert(asidx == 0 || !kvm_enabled());
787 if (!cpu->cpu_ases) {
788 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
791 newas = &cpu->cpu_ases[asidx];
792 newas->cpu = cpu;
793 newas->as = as;
794 if (tcg_enabled()) {
795 newas->tcg_as_listener.commit = tcg_commit;
796 memory_listener_register(&newas->tcg_as_listener, as);
800 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
802 /* Return the AddressSpace corresponding to the specified index */
803 return cpu->cpu_ases[asidx].as;
805 #endif
807 void cpu_exec_unrealizefn(CPUState *cpu)
809 CPUClass *cc = CPU_GET_CLASS(cpu);
811 cpu_list_remove(cpu);
813 if (cc->vmsd != NULL) {
814 vmstate_unregister(NULL, cc->vmsd, cpu);
816 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
817 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
821 Property cpu_common_props[] = {
822 #ifndef CONFIG_USER_ONLY
823 /* Create a memory property for softmmu CPU object,
824 * so users can wire up its memory. (This can't go in qom/cpu.c
825 * because that file is compiled only once for both user-mode
826 * and system builds.) The default if no link is set up is to use
827 * the system address space.
829 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
830 MemoryRegion *),
831 #endif
832 DEFINE_PROP_END_OF_LIST(),
835 void cpu_exec_initfn(CPUState *cpu)
837 cpu->as = NULL;
838 cpu->num_ases = 0;
840 #ifndef CONFIG_USER_ONLY
841 cpu->thread_id = qemu_get_thread_id();
842 cpu->memory = system_memory;
843 object_ref(OBJECT(cpu->memory));
844 #endif
847 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
849 CPUClass *cc = CPU_GET_CLASS(cpu);
850 static bool tcg_target_initialized;
852 cpu_list_add(cpu);
854 if (tcg_enabled() && !tcg_target_initialized) {
855 tcg_target_initialized = true;
856 cc->tcg_initialize();
859 #ifndef CONFIG_USER_ONLY
860 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
861 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
863 if (cc->vmsd != NULL) {
864 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
866 #endif
869 const char *parse_cpu_model(const char *cpu_model)
871 ObjectClass *oc;
872 CPUClass *cc;
873 gchar **model_pieces;
874 const char *cpu_type;
876 model_pieces = g_strsplit(cpu_model, ",", 2);
878 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
879 if (oc == NULL) {
880 error_report("unable to find CPU model '%s'", model_pieces[0]);
881 g_strfreev(model_pieces);
882 exit(EXIT_FAILURE);
885 cpu_type = object_class_get_name(oc);
886 cc = CPU_CLASS(oc);
887 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
888 g_strfreev(model_pieces);
889 return cpu_type;
892 #if defined(CONFIG_USER_ONLY)
893 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
895 mmap_lock();
896 tb_lock();
897 tb_invalidate_phys_page_range(pc, pc + 1, 0);
898 tb_unlock();
899 mmap_unlock();
901 #else
902 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
904 MemTxAttrs attrs;
905 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
906 int asidx = cpu_asidx_from_attrs(cpu, attrs);
907 if (phys != -1) {
908 /* Locks grabbed by tb_invalidate_phys_addr */
909 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
910 phys | (pc & ~TARGET_PAGE_MASK), attrs);
913 #endif
915 #if defined(CONFIG_USER_ONLY)
916 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
921 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
922 int flags)
924 return -ENOSYS;
927 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
931 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
932 int flags, CPUWatchpoint **watchpoint)
934 return -ENOSYS;
936 #else
937 /* Add a watchpoint. */
938 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
939 int flags, CPUWatchpoint **watchpoint)
941 CPUWatchpoint *wp;
943 /* forbid ranges which are empty or run off the end of the address space */
944 if (len == 0 || (addr + len - 1) < addr) {
945 error_report("tried to set invalid watchpoint at %"
946 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
947 return -EINVAL;
949 wp = g_malloc(sizeof(*wp));
951 wp->vaddr = addr;
952 wp->len = len;
953 wp->flags = flags;
955 /* keep all GDB-injected watchpoints in front */
956 if (flags & BP_GDB) {
957 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
958 } else {
959 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
962 tlb_flush_page(cpu, addr);
964 if (watchpoint)
965 *watchpoint = wp;
966 return 0;
969 /* Remove a specific watchpoint. */
970 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
971 int flags)
973 CPUWatchpoint *wp;
975 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
976 if (addr == wp->vaddr && len == wp->len
977 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
978 cpu_watchpoint_remove_by_ref(cpu, wp);
979 return 0;
982 return -ENOENT;
985 /* Remove a specific watchpoint by reference. */
986 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
988 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
990 tlb_flush_page(cpu, watchpoint->vaddr);
992 g_free(watchpoint);
995 /* Remove all matching watchpoints. */
996 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
998 CPUWatchpoint *wp, *next;
1000 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1001 if (wp->flags & mask) {
1002 cpu_watchpoint_remove_by_ref(cpu, wp);
1007 /* Return true if this watchpoint address matches the specified
1008 * access (ie the address range covered by the watchpoint overlaps
1009 * partially or completely with the address range covered by the
1010 * access).
1012 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1013 vaddr addr,
1014 vaddr len)
1016 /* We know the lengths are non-zero, but a little caution is
1017 * required to avoid errors in the case where the range ends
1018 * exactly at the top of the address space and so addr + len
1019 * wraps round to zero.
1021 vaddr wpend = wp->vaddr + wp->len - 1;
1022 vaddr addrend = addr + len - 1;
1024 return !(addr > wpend || wp->vaddr > addrend);
1027 #endif
1029 /* Add a breakpoint. */
1030 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1031 CPUBreakpoint **breakpoint)
1033 CPUBreakpoint *bp;
1035 bp = g_malloc(sizeof(*bp));
1037 bp->pc = pc;
1038 bp->flags = flags;
1040 /* keep all GDB-injected breakpoints in front */
1041 if (flags & BP_GDB) {
1042 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1043 } else {
1044 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1047 breakpoint_invalidate(cpu, pc);
1049 if (breakpoint) {
1050 *breakpoint = bp;
1052 return 0;
1055 /* Remove a specific breakpoint. */
1056 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1058 CPUBreakpoint *bp;
1060 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1061 if (bp->pc == pc && bp->flags == flags) {
1062 cpu_breakpoint_remove_by_ref(cpu, bp);
1063 return 0;
1066 return -ENOENT;
1069 /* Remove a specific breakpoint by reference. */
1070 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1072 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1074 breakpoint_invalidate(cpu, breakpoint->pc);
1076 g_free(breakpoint);
1079 /* Remove all matching breakpoints. */
1080 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1082 CPUBreakpoint *bp, *next;
1084 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1085 if (bp->flags & mask) {
1086 cpu_breakpoint_remove_by_ref(cpu, bp);
1091 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1092 CPU loop after each instruction */
1093 void cpu_single_step(CPUState *cpu, int enabled)
1095 if (cpu->singlestep_enabled != enabled) {
1096 cpu->singlestep_enabled = enabled;
1097 if (kvm_enabled()) {
1098 kvm_update_guest_debug(cpu, 0);
1099 } else {
1100 /* must flush all the translated code to avoid inconsistencies */
1101 /* XXX: only flush what is necessary */
1102 tb_flush(cpu);
1107 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1109 va_list ap;
1110 va_list ap2;
1112 va_start(ap, fmt);
1113 va_copy(ap2, ap);
1114 fprintf(stderr, "qemu: fatal: ");
1115 vfprintf(stderr, fmt, ap);
1116 fprintf(stderr, "\n");
1117 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1118 if (qemu_log_separate()) {
1119 qemu_log_lock();
1120 qemu_log("qemu: fatal: ");
1121 qemu_log_vprintf(fmt, ap2);
1122 qemu_log("\n");
1123 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1124 qemu_log_flush();
1125 qemu_log_unlock();
1126 qemu_log_close();
1128 va_end(ap2);
1129 va_end(ap);
1130 replay_finish();
1131 #if defined(CONFIG_USER_ONLY)
1133 struct sigaction act;
1134 sigfillset(&act.sa_mask);
1135 act.sa_handler = SIG_DFL;
1136 act.sa_flags = 0;
1137 sigaction(SIGABRT, &act, NULL);
1139 #endif
1140 abort();
1143 #if !defined(CONFIG_USER_ONLY)
1144 /* Called from RCU critical section */
1145 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1147 RAMBlock *block;
1149 block = atomic_rcu_read(&ram_list.mru_block);
1150 if (block && addr - block->offset < block->max_length) {
1151 return block;
1153 RAMBLOCK_FOREACH(block) {
1154 if (addr - block->offset < block->max_length) {
1155 goto found;
1159 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1160 abort();
1162 found:
1163 /* It is safe to write mru_block outside the iothread lock. This
1164 * is what happens:
1166 * mru_block = xxx
1167 * rcu_read_unlock()
1168 * xxx removed from list
1169 * rcu_read_lock()
1170 * read mru_block
1171 * mru_block = NULL;
1172 * call_rcu(reclaim_ramblock, xxx);
1173 * rcu_read_unlock()
1175 * atomic_rcu_set is not needed here. The block was already published
1176 * when it was placed into the list. Here we're just making an extra
1177 * copy of the pointer.
1179 ram_list.mru_block = block;
1180 return block;
1183 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1185 CPUState *cpu;
1186 ram_addr_t start1;
1187 RAMBlock *block;
1188 ram_addr_t end;
1190 end = TARGET_PAGE_ALIGN(start + length);
1191 start &= TARGET_PAGE_MASK;
1193 rcu_read_lock();
1194 block = qemu_get_ram_block(start);
1195 assert(block == qemu_get_ram_block(end - 1));
1196 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1197 CPU_FOREACH(cpu) {
1198 tlb_reset_dirty(cpu, start1, length);
1200 rcu_read_unlock();
1203 /* Note: start and end must be within the same ram block. */
1204 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1205 ram_addr_t length,
1206 unsigned client)
1208 DirtyMemoryBlocks *blocks;
1209 unsigned long end, page;
1210 bool dirty = false;
1212 if (length == 0) {
1213 return false;
1216 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1217 page = start >> TARGET_PAGE_BITS;
1219 rcu_read_lock();
1221 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1223 while (page < end) {
1224 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1225 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1226 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1228 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1229 offset, num);
1230 page += num;
1233 rcu_read_unlock();
1235 if (dirty && tcg_enabled()) {
1236 tlb_reset_dirty_range_all(start, length);
1239 return dirty;
1242 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1243 (ram_addr_t start, ram_addr_t length, unsigned client)
1245 DirtyMemoryBlocks *blocks;
1246 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1247 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1248 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1249 DirtyBitmapSnapshot *snap;
1250 unsigned long page, end, dest;
1252 snap = g_malloc0(sizeof(*snap) +
1253 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1254 snap->start = first;
1255 snap->end = last;
1257 page = first >> TARGET_PAGE_BITS;
1258 end = last >> TARGET_PAGE_BITS;
1259 dest = 0;
1261 rcu_read_lock();
1263 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1265 while (page < end) {
1266 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1267 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1268 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1270 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1271 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1272 offset >>= BITS_PER_LEVEL;
1274 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1275 blocks->blocks[idx] + offset,
1276 num);
1277 page += num;
1278 dest += num >> BITS_PER_LEVEL;
1281 rcu_read_unlock();
1283 if (tcg_enabled()) {
1284 tlb_reset_dirty_range_all(start, length);
1287 return snap;
1290 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1291 ram_addr_t start,
1292 ram_addr_t length)
1294 unsigned long page, end;
1296 assert(start >= snap->start);
1297 assert(start + length <= snap->end);
1299 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1300 page = (start - snap->start) >> TARGET_PAGE_BITS;
1302 while (page < end) {
1303 if (test_bit(page, snap->dirty)) {
1304 return true;
1306 page++;
1308 return false;
1311 /* Called from RCU critical section */
1312 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1313 MemoryRegionSection *section,
1314 target_ulong vaddr,
1315 hwaddr paddr, hwaddr xlat,
1316 int prot,
1317 target_ulong *address)
1319 hwaddr iotlb;
1320 CPUWatchpoint *wp;
1322 if (memory_region_is_ram(section->mr)) {
1323 /* Normal RAM. */
1324 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1325 if (!section->readonly) {
1326 iotlb |= PHYS_SECTION_NOTDIRTY;
1327 } else {
1328 iotlb |= PHYS_SECTION_ROM;
1330 } else {
1331 AddressSpaceDispatch *d;
1333 d = flatview_to_dispatch(section->fv);
1334 iotlb = section - d->map.sections;
1335 iotlb += xlat;
1338 /* Make accesses to pages with watchpoints go via the
1339 watchpoint trap routines. */
1340 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1341 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1342 /* Avoid trapping reads of pages with a write breakpoint. */
1343 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1344 iotlb = PHYS_SECTION_WATCH + paddr;
1345 *address |= TLB_MMIO;
1346 break;
1351 return iotlb;
1353 #endif /* defined(CONFIG_USER_ONLY) */
1355 #if !defined(CONFIG_USER_ONLY)
1357 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1358 uint16_t section);
1359 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1361 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1362 qemu_anon_ram_alloc;
1365 * Set a custom physical guest memory alloator.
1366 * Accelerators with unusual needs may need this. Hopefully, we can
1367 * get rid of it eventually.
1369 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1371 phys_mem_alloc = alloc;
1374 static uint16_t phys_section_add(PhysPageMap *map,
1375 MemoryRegionSection *section)
1377 /* The physical section number is ORed with a page-aligned
1378 * pointer to produce the iotlb entries. Thus it should
1379 * never overflow into the page-aligned value.
1381 assert(map->sections_nb < TARGET_PAGE_SIZE);
1383 if (map->sections_nb == map->sections_nb_alloc) {
1384 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1385 map->sections = g_renew(MemoryRegionSection, map->sections,
1386 map->sections_nb_alloc);
1388 map->sections[map->sections_nb] = *section;
1389 memory_region_ref(section->mr);
1390 return map->sections_nb++;
1393 static void phys_section_destroy(MemoryRegion *mr)
1395 bool have_sub_page = mr->subpage;
1397 memory_region_unref(mr);
1399 if (have_sub_page) {
1400 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1401 object_unref(OBJECT(&subpage->iomem));
1402 g_free(subpage);
1406 static void phys_sections_free(PhysPageMap *map)
1408 while (map->sections_nb > 0) {
1409 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1410 phys_section_destroy(section->mr);
1412 g_free(map->sections);
1413 g_free(map->nodes);
1416 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1418 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1419 subpage_t *subpage;
1420 hwaddr base = section->offset_within_address_space
1421 & TARGET_PAGE_MASK;
1422 MemoryRegionSection *existing = phys_page_find(d, base);
1423 MemoryRegionSection subsection = {
1424 .offset_within_address_space = base,
1425 .size = int128_make64(TARGET_PAGE_SIZE),
1427 hwaddr start, end;
1429 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1431 if (!(existing->mr->subpage)) {
1432 subpage = subpage_init(fv, base);
1433 subsection.fv = fv;
1434 subsection.mr = &subpage->iomem;
1435 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1436 phys_section_add(&d->map, &subsection));
1437 } else {
1438 subpage = container_of(existing->mr, subpage_t, iomem);
1440 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1441 end = start + int128_get64(section->size) - 1;
1442 subpage_register(subpage, start, end,
1443 phys_section_add(&d->map, section));
1447 static void register_multipage(FlatView *fv,
1448 MemoryRegionSection *section)
1450 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1451 hwaddr start_addr = section->offset_within_address_space;
1452 uint16_t section_index = phys_section_add(&d->map, section);
1453 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1454 TARGET_PAGE_BITS));
1456 assert(num_pages);
1457 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1460 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1462 MemoryRegionSection now = *section, remain = *section;
1463 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1465 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1466 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1467 - now.offset_within_address_space;
1469 now.size = int128_min(int128_make64(left), now.size);
1470 register_subpage(fv, &now);
1471 } else {
1472 now.size = int128_zero();
1474 while (int128_ne(remain.size, now.size)) {
1475 remain.size = int128_sub(remain.size, now.size);
1476 remain.offset_within_address_space += int128_get64(now.size);
1477 remain.offset_within_region += int128_get64(now.size);
1478 now = remain;
1479 if (int128_lt(remain.size, page_size)) {
1480 register_subpage(fv, &now);
1481 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1482 now.size = page_size;
1483 register_subpage(fv, &now);
1484 } else {
1485 now.size = int128_and(now.size, int128_neg(page_size));
1486 register_multipage(fv, &now);
1491 void qemu_flush_coalesced_mmio_buffer(void)
1493 if (kvm_enabled())
1494 kvm_flush_coalesced_mmio_buffer();
1497 void qemu_mutex_lock_ramlist(void)
1499 qemu_mutex_lock(&ram_list.mutex);
1502 void qemu_mutex_unlock_ramlist(void)
1504 qemu_mutex_unlock(&ram_list.mutex);
1507 void ram_block_dump(Monitor *mon)
1509 RAMBlock *block;
1510 char *psize;
1512 rcu_read_lock();
1513 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1514 "Block Name", "PSize", "Offset", "Used", "Total");
1515 RAMBLOCK_FOREACH(block) {
1516 psize = size_to_str(block->page_size);
1517 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1518 " 0x%016" PRIx64 "\n", block->idstr, psize,
1519 (uint64_t)block->offset,
1520 (uint64_t)block->used_length,
1521 (uint64_t)block->max_length);
1522 g_free(psize);
1524 rcu_read_unlock();
1527 #ifdef __linux__
1529 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1530 * may or may not name the same files / on the same filesystem now as
1531 * when we actually open and map them. Iterate over the file
1532 * descriptors instead, and use qemu_fd_getpagesize().
1534 static int find_max_supported_pagesize(Object *obj, void *opaque)
1536 long *hpsize_min = opaque;
1538 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1539 long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj));
1541 if (hpsize < *hpsize_min) {
1542 *hpsize_min = hpsize;
1546 return 0;
1549 long qemu_getrampagesize(void)
1551 long hpsize = LONG_MAX;
1552 long mainrampagesize;
1553 Object *memdev_root;
1555 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1557 /* it's possible we have memory-backend objects with
1558 * hugepage-backed RAM. these may get mapped into system
1559 * address space via -numa parameters or memory hotplug
1560 * hooks. we want to take these into account, but we
1561 * also want to make sure these supported hugepage
1562 * sizes are applicable across the entire range of memory
1563 * we may boot from, so we take the min across all
1564 * backends, and assume normal pages in cases where a
1565 * backend isn't backed by hugepages.
1567 memdev_root = object_resolve_path("/objects", NULL);
1568 if (memdev_root) {
1569 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1571 if (hpsize == LONG_MAX) {
1572 /* No additional memory regions found ==> Report main RAM page size */
1573 return mainrampagesize;
1576 /* If NUMA is disabled or the NUMA nodes are not backed with a
1577 * memory-backend, then there is at least one node using "normal" RAM,
1578 * so if its page size is smaller we have got to report that size instead.
1580 if (hpsize > mainrampagesize &&
1581 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1582 static bool warned;
1583 if (!warned) {
1584 error_report("Huge page support disabled (n/a for main memory).");
1585 warned = true;
1587 return mainrampagesize;
1590 return hpsize;
1592 #else
1593 long qemu_getrampagesize(void)
1595 return getpagesize();
1597 #endif
1599 #ifdef __linux__
1600 static int64_t get_file_size(int fd)
1602 int64_t size = lseek(fd, 0, SEEK_END);
1603 if (size < 0) {
1604 return -errno;
1606 return size;
1609 static int file_ram_open(const char *path,
1610 const char *region_name,
1611 bool *created,
1612 Error **errp)
1614 char *filename;
1615 char *sanitized_name;
1616 char *c;
1617 int fd = -1;
1619 *created = false;
1620 for (;;) {
1621 fd = open(path, O_RDWR);
1622 if (fd >= 0) {
1623 /* @path names an existing file, use it */
1624 break;
1626 if (errno == ENOENT) {
1627 /* @path names a file that doesn't exist, create it */
1628 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1629 if (fd >= 0) {
1630 *created = true;
1631 break;
1633 } else if (errno == EISDIR) {
1634 /* @path names a directory, create a file there */
1635 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1636 sanitized_name = g_strdup(region_name);
1637 for (c = sanitized_name; *c != '\0'; c++) {
1638 if (*c == '/') {
1639 *c = '_';
1643 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1644 sanitized_name);
1645 g_free(sanitized_name);
1647 fd = mkstemp(filename);
1648 if (fd >= 0) {
1649 unlink(filename);
1650 g_free(filename);
1651 break;
1653 g_free(filename);
1655 if (errno != EEXIST && errno != EINTR) {
1656 error_setg_errno(errp, errno,
1657 "can't open backing store %s for guest RAM",
1658 path);
1659 return -1;
1662 * Try again on EINTR and EEXIST. The latter happens when
1663 * something else creates the file between our two open().
1667 return fd;
1670 static void *file_ram_alloc(RAMBlock *block,
1671 ram_addr_t memory,
1672 int fd,
1673 bool truncate,
1674 Error **errp)
1676 void *area;
1678 block->page_size = qemu_fd_getpagesize(fd);
1679 if (block->mr->align % block->page_size) {
1680 error_setg(errp, "alignment 0x%" PRIx64
1681 " must be multiples of page size 0x%zx",
1682 block->mr->align, block->page_size);
1683 return NULL;
1685 block->mr->align = MAX(block->page_size, block->mr->align);
1686 #if defined(__s390x__)
1687 if (kvm_enabled()) {
1688 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1690 #endif
1692 if (memory < block->page_size) {
1693 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1694 "or larger than page size 0x%zx",
1695 memory, block->page_size);
1696 return NULL;
1699 memory = ROUND_UP(memory, block->page_size);
1702 * ftruncate is not supported by hugetlbfs in older
1703 * hosts, so don't bother bailing out on errors.
1704 * If anything goes wrong with it under other filesystems,
1705 * mmap will fail.
1707 * Do not truncate the non-empty backend file to avoid corrupting
1708 * the existing data in the file. Disabling shrinking is not
1709 * enough. For example, the current vNVDIMM implementation stores
1710 * the guest NVDIMM labels at the end of the backend file. If the
1711 * backend file is later extended, QEMU will not be able to find
1712 * those labels. Therefore, extending the non-empty backend file
1713 * is disabled as well.
1715 if (truncate && ftruncate(fd, memory)) {
1716 perror("ftruncate");
1719 area = qemu_ram_mmap(fd, memory, block->mr->align,
1720 block->flags & RAM_SHARED);
1721 if (area == MAP_FAILED) {
1722 error_setg_errno(errp, errno,
1723 "unable to map backing store for guest RAM");
1724 return NULL;
1727 if (mem_prealloc) {
1728 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1729 if (errp && *errp) {
1730 qemu_ram_munmap(area, memory);
1731 return NULL;
1735 block->fd = fd;
1736 return area;
1738 #endif
1740 /* Allocate space within the ram_addr_t space that governs the
1741 * dirty bitmaps.
1742 * Called with the ramlist lock held.
1744 static ram_addr_t find_ram_offset(ram_addr_t size)
1746 RAMBlock *block, *next_block;
1747 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1749 assert(size != 0); /* it would hand out same offset multiple times */
1751 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1752 return 0;
1755 RAMBLOCK_FOREACH(block) {
1756 ram_addr_t candidate, next = RAM_ADDR_MAX;
1758 /* Align blocks to start on a 'long' in the bitmap
1759 * which makes the bitmap sync'ing take the fast path.
1761 candidate = block->offset + block->max_length;
1762 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1764 /* Search for the closest following block
1765 * and find the gap.
1767 RAMBLOCK_FOREACH(next_block) {
1768 if (next_block->offset >= candidate) {
1769 next = MIN(next, next_block->offset);
1773 /* If it fits remember our place and remember the size
1774 * of gap, but keep going so that we might find a smaller
1775 * gap to fill so avoiding fragmentation.
1777 if (next - candidate >= size && next - candidate < mingap) {
1778 offset = candidate;
1779 mingap = next - candidate;
1782 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1785 if (offset == RAM_ADDR_MAX) {
1786 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1787 (uint64_t)size);
1788 abort();
1791 trace_find_ram_offset(size, offset);
1793 return offset;
1796 unsigned long last_ram_page(void)
1798 RAMBlock *block;
1799 ram_addr_t last = 0;
1801 rcu_read_lock();
1802 RAMBLOCK_FOREACH(block) {
1803 last = MAX(last, block->offset + block->max_length);
1805 rcu_read_unlock();
1806 return last >> TARGET_PAGE_BITS;
1809 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1811 int ret;
1813 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1814 if (!machine_dump_guest_core(current_machine)) {
1815 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1816 if (ret) {
1817 perror("qemu_madvise");
1818 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1819 "but dump_guest_core=off specified\n");
1824 const char *qemu_ram_get_idstr(RAMBlock *rb)
1826 return rb->idstr;
1829 bool qemu_ram_is_shared(RAMBlock *rb)
1831 return rb->flags & RAM_SHARED;
1834 /* Note: Only set at the start of postcopy */
1835 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1837 return rb->flags & RAM_UF_ZEROPAGE;
1840 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1842 rb->flags |= RAM_UF_ZEROPAGE;
1845 bool qemu_ram_is_migratable(RAMBlock *rb)
1847 return rb->flags & RAM_MIGRATABLE;
1850 void qemu_ram_set_migratable(RAMBlock *rb)
1852 rb->flags |= RAM_MIGRATABLE;
1855 void qemu_ram_unset_migratable(RAMBlock *rb)
1857 rb->flags &= ~RAM_MIGRATABLE;
1860 /* Called with iothread lock held. */
1861 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1863 RAMBlock *block;
1865 assert(new_block);
1866 assert(!new_block->idstr[0]);
1868 if (dev) {
1869 char *id = qdev_get_dev_path(dev);
1870 if (id) {
1871 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1872 g_free(id);
1875 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1877 rcu_read_lock();
1878 RAMBLOCK_FOREACH(block) {
1879 if (block != new_block &&
1880 !strcmp(block->idstr, new_block->idstr)) {
1881 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1882 new_block->idstr);
1883 abort();
1886 rcu_read_unlock();
1889 /* Called with iothread lock held. */
1890 void qemu_ram_unset_idstr(RAMBlock *block)
1892 /* FIXME: arch_init.c assumes that this is not called throughout
1893 * migration. Ignore the problem since hot-unplug during migration
1894 * does not work anyway.
1896 if (block) {
1897 memset(block->idstr, 0, sizeof(block->idstr));
1901 size_t qemu_ram_pagesize(RAMBlock *rb)
1903 return rb->page_size;
1906 /* Returns the largest size of page in use */
1907 size_t qemu_ram_pagesize_largest(void)
1909 RAMBlock *block;
1910 size_t largest = 0;
1912 RAMBLOCK_FOREACH(block) {
1913 largest = MAX(largest, qemu_ram_pagesize(block));
1916 return largest;
1919 static int memory_try_enable_merging(void *addr, size_t len)
1921 if (!machine_mem_merge(current_machine)) {
1922 /* disabled by the user */
1923 return 0;
1926 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1929 /* Only legal before guest might have detected the memory size: e.g. on
1930 * incoming migration, or right after reset.
1932 * As memory core doesn't know how is memory accessed, it is up to
1933 * resize callback to update device state and/or add assertions to detect
1934 * misuse, if necessary.
1936 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1938 assert(block);
1940 newsize = HOST_PAGE_ALIGN(newsize);
1942 if (block->used_length == newsize) {
1943 return 0;
1946 if (!(block->flags & RAM_RESIZEABLE)) {
1947 error_setg_errno(errp, EINVAL,
1948 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1949 " in != 0x" RAM_ADDR_FMT, block->idstr,
1950 newsize, block->used_length);
1951 return -EINVAL;
1954 if (block->max_length < newsize) {
1955 error_setg_errno(errp, EINVAL,
1956 "Length too large: %s: 0x" RAM_ADDR_FMT
1957 " > 0x" RAM_ADDR_FMT, block->idstr,
1958 newsize, block->max_length);
1959 return -EINVAL;
1962 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1963 block->used_length = newsize;
1964 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1965 DIRTY_CLIENTS_ALL);
1966 memory_region_set_size(block->mr, newsize);
1967 if (block->resized) {
1968 block->resized(block->idstr, newsize, block->host);
1970 return 0;
1973 /* Called with ram_list.mutex held */
1974 static void dirty_memory_extend(ram_addr_t old_ram_size,
1975 ram_addr_t new_ram_size)
1977 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1978 DIRTY_MEMORY_BLOCK_SIZE);
1979 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1980 DIRTY_MEMORY_BLOCK_SIZE);
1981 int i;
1983 /* Only need to extend if block count increased */
1984 if (new_num_blocks <= old_num_blocks) {
1985 return;
1988 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1989 DirtyMemoryBlocks *old_blocks;
1990 DirtyMemoryBlocks *new_blocks;
1991 int j;
1993 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1994 new_blocks = g_malloc(sizeof(*new_blocks) +
1995 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1997 if (old_num_blocks) {
1998 memcpy(new_blocks->blocks, old_blocks->blocks,
1999 old_num_blocks * sizeof(old_blocks->blocks[0]));
2002 for (j = old_num_blocks; j < new_num_blocks; j++) {
2003 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2006 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2008 if (old_blocks) {
2009 g_free_rcu(old_blocks, rcu);
2014 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2016 RAMBlock *block;
2017 RAMBlock *last_block = NULL;
2018 ram_addr_t old_ram_size, new_ram_size;
2019 Error *err = NULL;
2021 old_ram_size = last_ram_page();
2023 qemu_mutex_lock_ramlist();
2024 new_block->offset = find_ram_offset(new_block->max_length);
2026 if (!new_block->host) {
2027 if (xen_enabled()) {
2028 xen_ram_alloc(new_block->offset, new_block->max_length,
2029 new_block->mr, &err);
2030 if (err) {
2031 error_propagate(errp, err);
2032 qemu_mutex_unlock_ramlist();
2033 return;
2035 } else {
2036 new_block->host = phys_mem_alloc(new_block->max_length,
2037 &new_block->mr->align, shared);
2038 if (!new_block->host) {
2039 error_setg_errno(errp, errno,
2040 "cannot set up guest memory '%s'",
2041 memory_region_name(new_block->mr));
2042 qemu_mutex_unlock_ramlist();
2043 return;
2045 memory_try_enable_merging(new_block->host, new_block->max_length);
2049 new_ram_size = MAX(old_ram_size,
2050 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2051 if (new_ram_size > old_ram_size) {
2052 dirty_memory_extend(old_ram_size, new_ram_size);
2054 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2055 * QLIST (which has an RCU-friendly variant) does not have insertion at
2056 * tail, so save the last element in last_block.
2058 RAMBLOCK_FOREACH(block) {
2059 last_block = block;
2060 if (block->max_length < new_block->max_length) {
2061 break;
2064 if (block) {
2065 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2066 } else if (last_block) {
2067 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2068 } else { /* list is empty */
2069 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2071 ram_list.mru_block = NULL;
2073 /* Write list before version */
2074 smp_wmb();
2075 ram_list.version++;
2076 qemu_mutex_unlock_ramlist();
2078 cpu_physical_memory_set_dirty_range(new_block->offset,
2079 new_block->used_length,
2080 DIRTY_CLIENTS_ALL);
2082 if (new_block->host) {
2083 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2084 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2085 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2086 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2087 ram_block_notify_add(new_block->host, new_block->max_length);
2091 #ifdef __linux__
2092 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2093 bool share, int fd,
2094 Error **errp)
2096 RAMBlock *new_block;
2097 Error *local_err = NULL;
2098 int64_t file_size;
2100 if (xen_enabled()) {
2101 error_setg(errp, "-mem-path not supported with Xen");
2102 return NULL;
2105 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2106 error_setg(errp,
2107 "host lacks kvm mmu notifiers, -mem-path unsupported");
2108 return NULL;
2111 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2113 * file_ram_alloc() needs to allocate just like
2114 * phys_mem_alloc, but we haven't bothered to provide
2115 * a hook there.
2117 error_setg(errp,
2118 "-mem-path not supported with this accelerator");
2119 return NULL;
2122 size = HOST_PAGE_ALIGN(size);
2123 file_size = get_file_size(fd);
2124 if (file_size > 0 && file_size < size) {
2125 error_setg(errp, "backing store %s size 0x%" PRIx64
2126 " does not match 'size' option 0x" RAM_ADDR_FMT,
2127 mem_path, file_size, size);
2128 return NULL;
2131 new_block = g_malloc0(sizeof(*new_block));
2132 new_block->mr = mr;
2133 new_block->used_length = size;
2134 new_block->max_length = size;
2135 new_block->flags = share ? RAM_SHARED : 0;
2136 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2137 if (!new_block->host) {
2138 g_free(new_block);
2139 return NULL;
2142 ram_block_add(new_block, &local_err, share);
2143 if (local_err) {
2144 g_free(new_block);
2145 error_propagate(errp, local_err);
2146 return NULL;
2148 return new_block;
2153 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2154 bool share, const char *mem_path,
2155 Error **errp)
2157 int fd;
2158 bool created;
2159 RAMBlock *block;
2161 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2162 if (fd < 0) {
2163 return NULL;
2166 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
2167 if (!block) {
2168 if (created) {
2169 unlink(mem_path);
2171 close(fd);
2172 return NULL;
2175 return block;
2177 #endif
2179 static
2180 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2181 void (*resized)(const char*,
2182 uint64_t length,
2183 void *host),
2184 void *host, bool resizeable, bool share,
2185 MemoryRegion *mr, Error **errp)
2187 RAMBlock *new_block;
2188 Error *local_err = NULL;
2190 size = HOST_PAGE_ALIGN(size);
2191 max_size = HOST_PAGE_ALIGN(max_size);
2192 new_block = g_malloc0(sizeof(*new_block));
2193 new_block->mr = mr;
2194 new_block->resized = resized;
2195 new_block->used_length = size;
2196 new_block->max_length = max_size;
2197 assert(max_size >= size);
2198 new_block->fd = -1;
2199 new_block->page_size = getpagesize();
2200 new_block->host = host;
2201 if (host) {
2202 new_block->flags |= RAM_PREALLOC;
2204 if (resizeable) {
2205 new_block->flags |= RAM_RESIZEABLE;
2207 ram_block_add(new_block, &local_err, share);
2208 if (local_err) {
2209 g_free(new_block);
2210 error_propagate(errp, local_err);
2211 return NULL;
2213 return new_block;
2216 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2217 MemoryRegion *mr, Error **errp)
2219 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2220 false, mr, errp);
2223 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2224 MemoryRegion *mr, Error **errp)
2226 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2227 share, mr, errp);
2230 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2231 void (*resized)(const char*,
2232 uint64_t length,
2233 void *host),
2234 MemoryRegion *mr, Error **errp)
2236 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2237 false, mr, errp);
2240 static void reclaim_ramblock(RAMBlock *block)
2242 if (block->flags & RAM_PREALLOC) {
2244 } else if (xen_enabled()) {
2245 xen_invalidate_map_cache_entry(block->host);
2246 #ifndef _WIN32
2247 } else if (block->fd >= 0) {
2248 qemu_ram_munmap(block->host, block->max_length);
2249 close(block->fd);
2250 #endif
2251 } else {
2252 qemu_anon_ram_free(block->host, block->max_length);
2254 g_free(block);
2257 void qemu_ram_free(RAMBlock *block)
2259 if (!block) {
2260 return;
2263 if (block->host) {
2264 ram_block_notify_remove(block->host, block->max_length);
2267 qemu_mutex_lock_ramlist();
2268 QLIST_REMOVE_RCU(block, next);
2269 ram_list.mru_block = NULL;
2270 /* Write list before version */
2271 smp_wmb();
2272 ram_list.version++;
2273 call_rcu(block, reclaim_ramblock, rcu);
2274 qemu_mutex_unlock_ramlist();
2277 #ifndef _WIN32
2278 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2280 RAMBlock *block;
2281 ram_addr_t offset;
2282 int flags;
2283 void *area, *vaddr;
2285 RAMBLOCK_FOREACH(block) {
2286 offset = addr - block->offset;
2287 if (offset < block->max_length) {
2288 vaddr = ramblock_ptr(block, offset);
2289 if (block->flags & RAM_PREALLOC) {
2291 } else if (xen_enabled()) {
2292 abort();
2293 } else {
2294 flags = MAP_FIXED;
2295 if (block->fd >= 0) {
2296 flags |= (block->flags & RAM_SHARED ?
2297 MAP_SHARED : MAP_PRIVATE);
2298 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2299 flags, block->fd, offset);
2300 } else {
2302 * Remap needs to match alloc. Accelerators that
2303 * set phys_mem_alloc never remap. If they did,
2304 * we'd need a remap hook here.
2306 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2308 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2309 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2310 flags, -1, 0);
2312 if (area != vaddr) {
2313 error_report("Could not remap addr: "
2314 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2315 length, addr);
2316 exit(1);
2318 memory_try_enable_merging(vaddr, length);
2319 qemu_ram_setup_dump(vaddr, length);
2324 #endif /* !_WIN32 */
2326 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2327 * This should not be used for general purpose DMA. Use address_space_map
2328 * or address_space_rw instead. For local memory (e.g. video ram) that the
2329 * device owns, use memory_region_get_ram_ptr.
2331 * Called within RCU critical section.
2333 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2335 RAMBlock *block = ram_block;
2337 if (block == NULL) {
2338 block = qemu_get_ram_block(addr);
2339 addr -= block->offset;
2342 if (xen_enabled() && block->host == NULL) {
2343 /* We need to check if the requested address is in the RAM
2344 * because we don't want to map the entire memory in QEMU.
2345 * In that case just map until the end of the page.
2347 if (block->offset == 0) {
2348 return xen_map_cache(addr, 0, 0, false);
2351 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2353 return ramblock_ptr(block, addr);
2356 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2357 * but takes a size argument.
2359 * Called within RCU critical section.
2361 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2362 hwaddr *size, bool lock)
2364 RAMBlock *block = ram_block;
2365 if (*size == 0) {
2366 return NULL;
2369 if (block == NULL) {
2370 block = qemu_get_ram_block(addr);
2371 addr -= block->offset;
2373 *size = MIN(*size, block->max_length - addr);
2375 if (xen_enabled() && block->host == NULL) {
2376 /* We need to check if the requested address is in the RAM
2377 * because we don't want to map the entire memory in QEMU.
2378 * In that case just map the requested area.
2380 if (block->offset == 0) {
2381 return xen_map_cache(addr, *size, lock, lock);
2384 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2387 return ramblock_ptr(block, addr);
2390 /* Return the offset of a hostpointer within a ramblock */
2391 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2393 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2394 assert((uintptr_t)host >= (uintptr_t)rb->host);
2395 assert(res < rb->max_length);
2397 return res;
2401 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2402 * in that RAMBlock.
2404 * ptr: Host pointer to look up
2405 * round_offset: If true round the result offset down to a page boundary
2406 * *ram_addr: set to result ram_addr
2407 * *offset: set to result offset within the RAMBlock
2409 * Returns: RAMBlock (or NULL if not found)
2411 * By the time this function returns, the returned pointer is not protected
2412 * by RCU anymore. If the caller is not within an RCU critical section and
2413 * does not hold the iothread lock, it must have other means of protecting the
2414 * pointer, such as a reference to the region that includes the incoming
2415 * ram_addr_t.
2417 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2418 ram_addr_t *offset)
2420 RAMBlock *block;
2421 uint8_t *host = ptr;
2423 if (xen_enabled()) {
2424 ram_addr_t ram_addr;
2425 rcu_read_lock();
2426 ram_addr = xen_ram_addr_from_mapcache(ptr);
2427 block = qemu_get_ram_block(ram_addr);
2428 if (block) {
2429 *offset = ram_addr - block->offset;
2431 rcu_read_unlock();
2432 return block;
2435 rcu_read_lock();
2436 block = atomic_rcu_read(&ram_list.mru_block);
2437 if (block && block->host && host - block->host < block->max_length) {
2438 goto found;
2441 RAMBLOCK_FOREACH(block) {
2442 /* This case append when the block is not mapped. */
2443 if (block->host == NULL) {
2444 continue;
2446 if (host - block->host < block->max_length) {
2447 goto found;
2451 rcu_read_unlock();
2452 return NULL;
2454 found:
2455 *offset = (host - block->host);
2456 if (round_offset) {
2457 *offset &= TARGET_PAGE_MASK;
2459 rcu_read_unlock();
2460 return block;
2464 * Finds the named RAMBlock
2466 * name: The name of RAMBlock to find
2468 * Returns: RAMBlock (or NULL if not found)
2470 RAMBlock *qemu_ram_block_by_name(const char *name)
2472 RAMBlock *block;
2474 RAMBLOCK_FOREACH(block) {
2475 if (!strcmp(name, block->idstr)) {
2476 return block;
2480 return NULL;
2483 /* Some of the softmmu routines need to translate from a host pointer
2484 (typically a TLB entry) back to a ram offset. */
2485 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2487 RAMBlock *block;
2488 ram_addr_t offset;
2490 block = qemu_ram_block_from_host(ptr, false, &offset);
2491 if (!block) {
2492 return RAM_ADDR_INVALID;
2495 return block->offset + offset;
2498 /* Called within RCU critical section. */
2499 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2500 CPUState *cpu,
2501 vaddr mem_vaddr,
2502 ram_addr_t ram_addr,
2503 unsigned size)
2505 ndi->cpu = cpu;
2506 ndi->ram_addr = ram_addr;
2507 ndi->mem_vaddr = mem_vaddr;
2508 ndi->size = size;
2509 ndi->locked = false;
2511 assert(tcg_enabled());
2512 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2513 ndi->locked = true;
2514 tb_lock();
2515 tb_invalidate_phys_page_fast(ram_addr, size);
2519 /* Called within RCU critical section. */
2520 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2522 if (ndi->locked) {
2523 tb_unlock();
2526 /* Set both VGA and migration bits for simplicity and to remove
2527 * the notdirty callback faster.
2529 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2530 DIRTY_CLIENTS_NOCODE);
2531 /* we remove the notdirty callback only if the code has been
2532 flushed */
2533 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2534 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2538 /* Called within RCU critical section. */
2539 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2540 uint64_t val, unsigned size)
2542 NotDirtyInfo ndi;
2544 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2545 ram_addr, size);
2547 stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val);
2548 memory_notdirty_write_complete(&ndi);
2551 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2552 unsigned size, bool is_write,
2553 MemTxAttrs attrs)
2555 return is_write;
2558 static const MemoryRegionOps notdirty_mem_ops = {
2559 .write = notdirty_mem_write,
2560 .valid.accepts = notdirty_mem_accepts,
2561 .endianness = DEVICE_NATIVE_ENDIAN,
2562 .valid = {
2563 .min_access_size = 1,
2564 .max_access_size = 8,
2565 .unaligned = false,
2567 .impl = {
2568 .min_access_size = 1,
2569 .max_access_size = 8,
2570 .unaligned = false,
2574 /* Generate a debug exception if a watchpoint has been hit. */
2575 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2577 CPUState *cpu = current_cpu;
2578 CPUClass *cc = CPU_GET_CLASS(cpu);
2579 target_ulong vaddr;
2580 CPUWatchpoint *wp;
2582 assert(tcg_enabled());
2583 if (cpu->watchpoint_hit) {
2584 /* We re-entered the check after replacing the TB. Now raise
2585 * the debug interrupt so that is will trigger after the
2586 * current instruction. */
2587 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2588 return;
2590 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2591 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2592 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2593 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2594 && (wp->flags & flags)) {
2595 if (flags == BP_MEM_READ) {
2596 wp->flags |= BP_WATCHPOINT_HIT_READ;
2597 } else {
2598 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2600 wp->hitaddr = vaddr;
2601 wp->hitattrs = attrs;
2602 if (!cpu->watchpoint_hit) {
2603 if (wp->flags & BP_CPU &&
2604 !cc->debug_check_watchpoint(cpu, wp)) {
2605 wp->flags &= ~BP_WATCHPOINT_HIT;
2606 continue;
2608 cpu->watchpoint_hit = wp;
2610 /* Both tb_lock and iothread_mutex will be reset when
2611 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2612 * back into the cpu_exec main loop.
2614 tb_lock();
2615 tb_check_watchpoint(cpu);
2616 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2617 cpu->exception_index = EXCP_DEBUG;
2618 cpu_loop_exit(cpu);
2619 } else {
2620 /* Force execution of one insn next time. */
2621 cpu->cflags_next_tb = 1 | curr_cflags();
2622 cpu_loop_exit_noexc(cpu);
2625 } else {
2626 wp->flags &= ~BP_WATCHPOINT_HIT;
2631 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2632 so these check for a hit then pass through to the normal out-of-line
2633 phys routines. */
2634 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2635 unsigned size, MemTxAttrs attrs)
2637 MemTxResult res;
2638 uint64_t data;
2639 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2640 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2642 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2643 switch (size) {
2644 case 1:
2645 data = address_space_ldub(as, addr, attrs, &res);
2646 break;
2647 case 2:
2648 data = address_space_lduw(as, addr, attrs, &res);
2649 break;
2650 case 4:
2651 data = address_space_ldl(as, addr, attrs, &res);
2652 break;
2653 case 8:
2654 data = address_space_ldq(as, addr, attrs, &res);
2655 break;
2656 default: abort();
2658 *pdata = data;
2659 return res;
2662 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2663 uint64_t val, unsigned size,
2664 MemTxAttrs attrs)
2666 MemTxResult res;
2667 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2668 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2670 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2671 switch (size) {
2672 case 1:
2673 address_space_stb(as, addr, val, attrs, &res);
2674 break;
2675 case 2:
2676 address_space_stw(as, addr, val, attrs, &res);
2677 break;
2678 case 4:
2679 address_space_stl(as, addr, val, attrs, &res);
2680 break;
2681 case 8:
2682 address_space_stq(as, addr, val, attrs, &res);
2683 break;
2684 default: abort();
2686 return res;
2689 static const MemoryRegionOps watch_mem_ops = {
2690 .read_with_attrs = watch_mem_read,
2691 .write_with_attrs = watch_mem_write,
2692 .endianness = DEVICE_NATIVE_ENDIAN,
2693 .valid = {
2694 .min_access_size = 1,
2695 .max_access_size = 8,
2696 .unaligned = false,
2698 .impl = {
2699 .min_access_size = 1,
2700 .max_access_size = 8,
2701 .unaligned = false,
2705 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2706 MemTxAttrs attrs, uint8_t *buf, int len);
2707 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2708 const uint8_t *buf, int len);
2709 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
2710 bool is_write, MemTxAttrs attrs);
2712 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2713 unsigned len, MemTxAttrs attrs)
2715 subpage_t *subpage = opaque;
2716 uint8_t buf[8];
2717 MemTxResult res;
2719 #if defined(DEBUG_SUBPAGE)
2720 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2721 subpage, len, addr);
2722 #endif
2723 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2724 if (res) {
2725 return res;
2727 *data = ldn_p(buf, len);
2728 return MEMTX_OK;
2731 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2732 uint64_t value, unsigned len, MemTxAttrs attrs)
2734 subpage_t *subpage = opaque;
2735 uint8_t buf[8];
2737 #if defined(DEBUG_SUBPAGE)
2738 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2739 " value %"PRIx64"\n",
2740 __func__, subpage, len, addr, value);
2741 #endif
2742 stn_p(buf, len, value);
2743 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2746 static bool subpage_accepts(void *opaque, hwaddr addr,
2747 unsigned len, bool is_write,
2748 MemTxAttrs attrs)
2750 subpage_t *subpage = opaque;
2751 #if defined(DEBUG_SUBPAGE)
2752 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2753 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2754 #endif
2756 return flatview_access_valid(subpage->fv, addr + subpage->base,
2757 len, is_write, attrs);
2760 static const MemoryRegionOps subpage_ops = {
2761 .read_with_attrs = subpage_read,
2762 .write_with_attrs = subpage_write,
2763 .impl.min_access_size = 1,
2764 .impl.max_access_size = 8,
2765 .valid.min_access_size = 1,
2766 .valid.max_access_size = 8,
2767 .valid.accepts = subpage_accepts,
2768 .endianness = DEVICE_NATIVE_ENDIAN,
2771 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2772 uint16_t section)
2774 int idx, eidx;
2776 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2777 return -1;
2778 idx = SUBPAGE_IDX(start);
2779 eidx = SUBPAGE_IDX(end);
2780 #if defined(DEBUG_SUBPAGE)
2781 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2782 __func__, mmio, start, end, idx, eidx, section);
2783 #endif
2784 for (; idx <= eidx; idx++) {
2785 mmio->sub_section[idx] = section;
2788 return 0;
2791 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2793 subpage_t *mmio;
2795 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2796 mmio->fv = fv;
2797 mmio->base = base;
2798 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2799 NULL, TARGET_PAGE_SIZE);
2800 mmio->iomem.subpage = true;
2801 #if defined(DEBUG_SUBPAGE)
2802 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2803 mmio, base, TARGET_PAGE_SIZE);
2804 #endif
2805 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2807 return mmio;
2810 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2812 assert(fv);
2813 MemoryRegionSection section = {
2814 .fv = fv,
2815 .mr = mr,
2816 .offset_within_address_space = 0,
2817 .offset_within_region = 0,
2818 .size = int128_2_64(),
2821 return phys_section_add(map, &section);
2824 static void readonly_mem_write(void *opaque, hwaddr addr,
2825 uint64_t val, unsigned size)
2827 /* Ignore any write to ROM. */
2830 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
2831 unsigned size, bool is_write,
2832 MemTxAttrs attrs)
2834 return is_write;
2837 /* This will only be used for writes, because reads are special cased
2838 * to directly access the underlying host ram.
2840 static const MemoryRegionOps readonly_mem_ops = {
2841 .write = readonly_mem_write,
2842 .valid.accepts = readonly_mem_accepts,
2843 .endianness = DEVICE_NATIVE_ENDIAN,
2844 .valid = {
2845 .min_access_size = 1,
2846 .max_access_size = 8,
2847 .unaligned = false,
2849 .impl = {
2850 .min_access_size = 1,
2851 .max_access_size = 8,
2852 .unaligned = false,
2856 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
2857 hwaddr index, MemTxAttrs attrs)
2859 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2860 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2861 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2862 MemoryRegionSection *sections = d->map.sections;
2864 return &sections[index & ~TARGET_PAGE_MASK];
2867 static void io_mem_init(void)
2869 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
2870 NULL, NULL, UINT64_MAX);
2871 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2872 NULL, UINT64_MAX);
2874 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2875 * which can be called without the iothread mutex.
2877 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2878 NULL, UINT64_MAX);
2879 memory_region_clear_global_locking(&io_mem_notdirty);
2881 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2882 NULL, UINT64_MAX);
2885 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2887 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2888 uint16_t n;
2890 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2891 assert(n == PHYS_SECTION_UNASSIGNED);
2892 n = dummy_section(&d->map, fv, &io_mem_notdirty);
2893 assert(n == PHYS_SECTION_NOTDIRTY);
2894 n = dummy_section(&d->map, fv, &io_mem_rom);
2895 assert(n == PHYS_SECTION_ROM);
2896 n = dummy_section(&d->map, fv, &io_mem_watch);
2897 assert(n == PHYS_SECTION_WATCH);
2899 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2901 return d;
2904 void address_space_dispatch_free(AddressSpaceDispatch *d)
2906 phys_sections_free(&d->map);
2907 g_free(d);
2910 static void tcg_commit(MemoryListener *listener)
2912 CPUAddressSpace *cpuas;
2913 AddressSpaceDispatch *d;
2915 /* since each CPU stores ram addresses in its TLB cache, we must
2916 reset the modified entries */
2917 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2918 cpu_reloading_memory_map();
2919 /* The CPU and TLB are protected by the iothread lock.
2920 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2921 * may have split the RCU critical section.
2923 d = address_space_to_dispatch(cpuas->as);
2924 atomic_rcu_set(&cpuas->memory_dispatch, d);
2925 tlb_flush(cpuas->cpu);
2928 static void memory_map_init(void)
2930 system_memory = g_malloc(sizeof(*system_memory));
2932 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2933 address_space_init(&address_space_memory, system_memory, "memory");
2935 system_io = g_malloc(sizeof(*system_io));
2936 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2937 65536);
2938 address_space_init(&address_space_io, system_io, "I/O");
2941 MemoryRegion *get_system_memory(void)
2943 return system_memory;
2946 MemoryRegion *get_system_io(void)
2948 return system_io;
2951 #endif /* !defined(CONFIG_USER_ONLY) */
2953 /* physical memory access (slow version, mainly for debug) */
2954 #if defined(CONFIG_USER_ONLY)
2955 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2956 uint8_t *buf, int len, int is_write)
2958 int l, flags;
2959 target_ulong page;
2960 void * p;
2962 while (len > 0) {
2963 page = addr & TARGET_PAGE_MASK;
2964 l = (page + TARGET_PAGE_SIZE) - addr;
2965 if (l > len)
2966 l = len;
2967 flags = page_get_flags(page);
2968 if (!(flags & PAGE_VALID))
2969 return -1;
2970 if (is_write) {
2971 if (!(flags & PAGE_WRITE))
2972 return -1;
2973 /* XXX: this code should not depend on lock_user */
2974 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2975 return -1;
2976 memcpy(p, buf, l);
2977 unlock_user(p, addr, l);
2978 } else {
2979 if (!(flags & PAGE_READ))
2980 return -1;
2981 /* XXX: this code should not depend on lock_user */
2982 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2983 return -1;
2984 memcpy(buf, p, l);
2985 unlock_user(p, addr, 0);
2987 len -= l;
2988 buf += l;
2989 addr += l;
2991 return 0;
2994 #else
2996 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2997 hwaddr length)
2999 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3000 addr += memory_region_get_ram_addr(mr);
3002 /* No early return if dirty_log_mask is or becomes 0, because
3003 * cpu_physical_memory_set_dirty_range will still call
3004 * xen_modified_memory.
3006 if (dirty_log_mask) {
3007 dirty_log_mask =
3008 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3010 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3011 assert(tcg_enabled());
3012 tb_lock();
3013 tb_invalidate_phys_range(addr, addr + length);
3014 tb_unlock();
3015 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3017 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3020 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3022 unsigned access_size_max = mr->ops->valid.max_access_size;
3024 /* Regions are assumed to support 1-4 byte accesses unless
3025 otherwise specified. */
3026 if (access_size_max == 0) {
3027 access_size_max = 4;
3030 /* Bound the maximum access by the alignment of the address. */
3031 if (!mr->ops->impl.unaligned) {
3032 unsigned align_size_max = addr & -addr;
3033 if (align_size_max != 0 && align_size_max < access_size_max) {
3034 access_size_max = align_size_max;
3038 /* Don't attempt accesses larger than the maximum. */
3039 if (l > access_size_max) {
3040 l = access_size_max;
3042 l = pow2floor(l);
3044 return l;
3047 static bool prepare_mmio_access(MemoryRegion *mr)
3049 bool unlocked = !qemu_mutex_iothread_locked();
3050 bool release_lock = false;
3052 if (unlocked && mr->global_locking) {
3053 qemu_mutex_lock_iothread();
3054 unlocked = false;
3055 release_lock = true;
3057 if (mr->flush_coalesced_mmio) {
3058 if (unlocked) {
3059 qemu_mutex_lock_iothread();
3061 qemu_flush_coalesced_mmio_buffer();
3062 if (unlocked) {
3063 qemu_mutex_unlock_iothread();
3067 return release_lock;
3070 /* Called within RCU critical section. */
3071 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3072 MemTxAttrs attrs,
3073 const uint8_t *buf,
3074 int len, hwaddr addr1,
3075 hwaddr l, MemoryRegion *mr)
3077 uint8_t *ptr;
3078 uint64_t val;
3079 MemTxResult result = MEMTX_OK;
3080 bool release_lock = false;
3082 for (;;) {
3083 if (!memory_access_is_direct(mr, true)) {
3084 release_lock |= prepare_mmio_access(mr);
3085 l = memory_access_size(mr, l, addr1);
3086 /* XXX: could force current_cpu to NULL to avoid
3087 potential bugs */
3088 val = ldn_p(buf, l);
3089 result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
3090 } else {
3091 /* RAM case */
3092 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3093 memcpy(ptr, buf, l);
3094 invalidate_and_set_dirty(mr, addr1, l);
3097 if (release_lock) {
3098 qemu_mutex_unlock_iothread();
3099 release_lock = false;
3102 len -= l;
3103 buf += l;
3104 addr += l;
3106 if (!len) {
3107 break;
3110 l = len;
3111 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3114 return result;
3117 /* Called from RCU critical section. */
3118 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3119 const uint8_t *buf, int len)
3121 hwaddr l;
3122 hwaddr addr1;
3123 MemoryRegion *mr;
3124 MemTxResult result = MEMTX_OK;
3126 l = len;
3127 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3128 result = flatview_write_continue(fv, addr, attrs, buf, len,
3129 addr1, l, mr);
3131 return result;
3134 /* Called within RCU critical section. */
3135 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3136 MemTxAttrs attrs, uint8_t *buf,
3137 int len, hwaddr addr1, hwaddr l,
3138 MemoryRegion *mr)
3140 uint8_t *ptr;
3141 uint64_t val;
3142 MemTxResult result = MEMTX_OK;
3143 bool release_lock = false;
3145 for (;;) {
3146 if (!memory_access_is_direct(mr, false)) {
3147 /* I/O case */
3148 release_lock |= prepare_mmio_access(mr);
3149 l = memory_access_size(mr, l, addr1);
3150 result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
3151 stn_p(buf, l, val);
3152 } else {
3153 /* RAM case */
3154 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3155 memcpy(buf, ptr, l);
3158 if (release_lock) {
3159 qemu_mutex_unlock_iothread();
3160 release_lock = false;
3163 len -= l;
3164 buf += l;
3165 addr += l;
3167 if (!len) {
3168 break;
3171 l = len;
3172 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3175 return result;
3178 /* Called from RCU critical section. */
3179 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3180 MemTxAttrs attrs, uint8_t *buf, int len)
3182 hwaddr l;
3183 hwaddr addr1;
3184 MemoryRegion *mr;
3186 l = len;
3187 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3188 return flatview_read_continue(fv, addr, attrs, buf, len,
3189 addr1, l, mr);
3192 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3193 MemTxAttrs attrs, uint8_t *buf, int len)
3195 MemTxResult result = MEMTX_OK;
3196 FlatView *fv;
3198 if (len > 0) {
3199 rcu_read_lock();
3200 fv = address_space_to_flatview(as);
3201 result = flatview_read(fv, addr, attrs, buf, len);
3202 rcu_read_unlock();
3205 return result;
3208 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3209 MemTxAttrs attrs,
3210 const uint8_t *buf, int len)
3212 MemTxResult result = MEMTX_OK;
3213 FlatView *fv;
3215 if (len > 0) {
3216 rcu_read_lock();
3217 fv = address_space_to_flatview(as);
3218 result = flatview_write(fv, addr, attrs, buf, len);
3219 rcu_read_unlock();
3222 return result;
3225 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3226 uint8_t *buf, int len, bool is_write)
3228 if (is_write) {
3229 return address_space_write(as, addr, attrs, buf, len);
3230 } else {
3231 return address_space_read_full(as, addr, attrs, buf, len);
3235 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3236 int len, int is_write)
3238 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3239 buf, len, is_write);
3242 enum write_rom_type {
3243 WRITE_DATA,
3244 FLUSH_CACHE,
3247 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3248 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3250 hwaddr l;
3251 uint8_t *ptr;
3252 hwaddr addr1;
3253 MemoryRegion *mr;
3255 rcu_read_lock();
3256 while (len > 0) {
3257 l = len;
3258 mr = address_space_translate(as, addr, &addr1, &l, true,
3259 MEMTXATTRS_UNSPECIFIED);
3261 if (!(memory_region_is_ram(mr) ||
3262 memory_region_is_romd(mr))) {
3263 l = memory_access_size(mr, l, addr1);
3264 } else {
3265 /* ROM/RAM case */
3266 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3267 switch (type) {
3268 case WRITE_DATA:
3269 memcpy(ptr, buf, l);
3270 invalidate_and_set_dirty(mr, addr1, l);
3271 break;
3272 case FLUSH_CACHE:
3273 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3274 break;
3277 len -= l;
3278 buf += l;
3279 addr += l;
3281 rcu_read_unlock();
3284 /* used for ROM loading : can write in RAM and ROM */
3285 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3286 const uint8_t *buf, int len)
3288 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3291 void cpu_flush_icache_range(hwaddr start, int len)
3294 * This function should do the same thing as an icache flush that was
3295 * triggered from within the guest. For TCG we are always cache coherent,
3296 * so there is no need to flush anything. For KVM / Xen we need to flush
3297 * the host's instruction cache at least.
3299 if (tcg_enabled()) {
3300 return;
3303 cpu_physical_memory_write_rom_internal(&address_space_memory,
3304 start, NULL, len, FLUSH_CACHE);
3307 typedef struct {
3308 MemoryRegion *mr;
3309 void *buffer;
3310 hwaddr addr;
3311 hwaddr len;
3312 bool in_use;
3313 } BounceBuffer;
3315 static BounceBuffer bounce;
3317 typedef struct MapClient {
3318 QEMUBH *bh;
3319 QLIST_ENTRY(MapClient) link;
3320 } MapClient;
3322 QemuMutex map_client_list_lock;
3323 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3324 = QLIST_HEAD_INITIALIZER(map_client_list);
3326 static void cpu_unregister_map_client_do(MapClient *client)
3328 QLIST_REMOVE(client, link);
3329 g_free(client);
3332 static void cpu_notify_map_clients_locked(void)
3334 MapClient *client;
3336 while (!QLIST_EMPTY(&map_client_list)) {
3337 client = QLIST_FIRST(&map_client_list);
3338 qemu_bh_schedule(client->bh);
3339 cpu_unregister_map_client_do(client);
3343 void cpu_register_map_client(QEMUBH *bh)
3345 MapClient *client = g_malloc(sizeof(*client));
3347 qemu_mutex_lock(&map_client_list_lock);
3348 client->bh = bh;
3349 QLIST_INSERT_HEAD(&map_client_list, client, link);
3350 if (!atomic_read(&bounce.in_use)) {
3351 cpu_notify_map_clients_locked();
3353 qemu_mutex_unlock(&map_client_list_lock);
3356 void cpu_exec_init_all(void)
3358 qemu_mutex_init(&ram_list.mutex);
3359 /* The data structures we set up here depend on knowing the page size,
3360 * so no more changes can be made after this point.
3361 * In an ideal world, nothing we did before we had finished the
3362 * machine setup would care about the target page size, and we could
3363 * do this much later, rather than requiring board models to state
3364 * up front what their requirements are.
3366 finalize_target_page_bits();
3367 io_mem_init();
3368 memory_map_init();
3369 qemu_mutex_init(&map_client_list_lock);
3372 void cpu_unregister_map_client(QEMUBH *bh)
3374 MapClient *client;
3376 qemu_mutex_lock(&map_client_list_lock);
3377 QLIST_FOREACH(client, &map_client_list, link) {
3378 if (client->bh == bh) {
3379 cpu_unregister_map_client_do(client);
3380 break;
3383 qemu_mutex_unlock(&map_client_list_lock);
3386 static void cpu_notify_map_clients(void)
3388 qemu_mutex_lock(&map_client_list_lock);
3389 cpu_notify_map_clients_locked();
3390 qemu_mutex_unlock(&map_client_list_lock);
3393 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
3394 bool is_write, MemTxAttrs attrs)
3396 MemoryRegion *mr;
3397 hwaddr l, xlat;
3399 while (len > 0) {
3400 l = len;
3401 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3402 if (!memory_access_is_direct(mr, is_write)) {
3403 l = memory_access_size(mr, l, addr);
3404 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3405 return false;
3409 len -= l;
3410 addr += l;
3412 return true;
3415 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3416 int len, bool is_write,
3417 MemTxAttrs attrs)
3419 FlatView *fv;
3420 bool result;
3422 rcu_read_lock();
3423 fv = address_space_to_flatview(as);
3424 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3425 rcu_read_unlock();
3426 return result;
3429 static hwaddr
3430 flatview_extend_translation(FlatView *fv, hwaddr addr,
3431 hwaddr target_len,
3432 MemoryRegion *mr, hwaddr base, hwaddr len,
3433 bool is_write, MemTxAttrs attrs)
3435 hwaddr done = 0;
3436 hwaddr xlat;
3437 MemoryRegion *this_mr;
3439 for (;;) {
3440 target_len -= len;
3441 addr += len;
3442 done += len;
3443 if (target_len == 0) {
3444 return done;
3447 len = target_len;
3448 this_mr = flatview_translate(fv, addr, &xlat,
3449 &len, is_write, attrs);
3450 if (this_mr != mr || xlat != base + done) {
3451 return done;
3456 /* Map a physical memory region into a host virtual address.
3457 * May map a subset of the requested range, given by and returned in *plen.
3458 * May return NULL if resources needed to perform the mapping are exhausted.
3459 * Use only for reads OR writes - not for read-modify-write operations.
3460 * Use cpu_register_map_client() to know when retrying the map operation is
3461 * likely to succeed.
3463 void *address_space_map(AddressSpace *as,
3464 hwaddr addr,
3465 hwaddr *plen,
3466 bool is_write,
3467 MemTxAttrs attrs)
3469 hwaddr len = *plen;
3470 hwaddr l, xlat;
3471 MemoryRegion *mr;
3472 void *ptr;
3473 FlatView *fv;
3475 if (len == 0) {
3476 return NULL;
3479 l = len;
3480 rcu_read_lock();
3481 fv = address_space_to_flatview(as);
3482 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3484 if (!memory_access_is_direct(mr, is_write)) {
3485 if (atomic_xchg(&bounce.in_use, true)) {
3486 rcu_read_unlock();
3487 return NULL;
3489 /* Avoid unbounded allocations */
3490 l = MIN(l, TARGET_PAGE_SIZE);
3491 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3492 bounce.addr = addr;
3493 bounce.len = l;
3495 memory_region_ref(mr);
3496 bounce.mr = mr;
3497 if (!is_write) {
3498 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3499 bounce.buffer, l);
3502 rcu_read_unlock();
3503 *plen = l;
3504 return bounce.buffer;
3508 memory_region_ref(mr);
3509 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3510 l, is_write, attrs);
3511 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3512 rcu_read_unlock();
3514 return ptr;
3517 /* Unmaps a memory region previously mapped by address_space_map().
3518 * Will also mark the memory as dirty if is_write == 1. access_len gives
3519 * the amount of memory that was actually read or written by the caller.
3521 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3522 int is_write, hwaddr access_len)
3524 if (buffer != bounce.buffer) {
3525 MemoryRegion *mr;
3526 ram_addr_t addr1;
3528 mr = memory_region_from_host(buffer, &addr1);
3529 assert(mr != NULL);
3530 if (is_write) {
3531 invalidate_and_set_dirty(mr, addr1, access_len);
3533 if (xen_enabled()) {
3534 xen_invalidate_map_cache_entry(buffer);
3536 memory_region_unref(mr);
3537 return;
3539 if (is_write) {
3540 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3541 bounce.buffer, access_len);
3543 qemu_vfree(bounce.buffer);
3544 bounce.buffer = NULL;
3545 memory_region_unref(bounce.mr);
3546 atomic_mb_set(&bounce.in_use, false);
3547 cpu_notify_map_clients();
3550 void *cpu_physical_memory_map(hwaddr addr,
3551 hwaddr *plen,
3552 int is_write)
3554 return address_space_map(&address_space_memory, addr, plen, is_write,
3555 MEMTXATTRS_UNSPECIFIED);
3558 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3559 int is_write, hwaddr access_len)
3561 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3564 #define ARG1_DECL AddressSpace *as
3565 #define ARG1 as
3566 #define SUFFIX
3567 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3568 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3569 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3570 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3571 #define RCU_READ_LOCK(...) rcu_read_lock()
3572 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3573 #include "memory_ldst.inc.c"
3575 int64_t address_space_cache_init(MemoryRegionCache *cache,
3576 AddressSpace *as,
3577 hwaddr addr,
3578 hwaddr len,
3579 bool is_write)
3581 AddressSpaceDispatch *d;
3582 hwaddr l;
3583 MemoryRegion *mr;
3585 assert(len > 0);
3587 l = len;
3588 cache->fv = address_space_get_flatview(as);
3589 d = flatview_to_dispatch(cache->fv);
3590 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3592 mr = cache->mrs.mr;
3593 memory_region_ref(mr);
3594 if (memory_access_is_direct(mr, is_write)) {
3595 /* We don't care about the memory attributes here as we're only
3596 * doing this if we found actual RAM, which behaves the same
3597 * regardless of attributes; so UNSPECIFIED is fine.
3599 l = flatview_extend_translation(cache->fv, addr, len, mr,
3600 cache->xlat, l, is_write,
3601 MEMTXATTRS_UNSPECIFIED);
3602 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3603 } else {
3604 cache->ptr = NULL;
3607 cache->len = l;
3608 cache->is_write = is_write;
3609 return l;
3612 void address_space_cache_invalidate(MemoryRegionCache *cache,
3613 hwaddr addr,
3614 hwaddr access_len)
3616 assert(cache->is_write);
3617 if (likely(cache->ptr)) {
3618 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3622 void address_space_cache_destroy(MemoryRegionCache *cache)
3624 if (!cache->mrs.mr) {
3625 return;
3628 if (xen_enabled()) {
3629 xen_invalidate_map_cache_entry(cache->ptr);
3631 memory_region_unref(cache->mrs.mr);
3632 flatview_unref(cache->fv);
3633 cache->mrs.mr = NULL;
3634 cache->fv = NULL;
3637 /* Called from RCU critical section. This function has the same
3638 * semantics as address_space_translate, but it only works on a
3639 * predefined range of a MemoryRegion that was mapped with
3640 * address_space_cache_init.
3642 static inline MemoryRegion *address_space_translate_cached(
3643 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3644 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3646 MemoryRegionSection section;
3647 MemoryRegion *mr;
3648 IOMMUMemoryRegion *iommu_mr;
3649 AddressSpace *target_as;
3651 assert(!cache->ptr);
3652 *xlat = addr + cache->xlat;
3654 mr = cache->mrs.mr;
3655 iommu_mr = memory_region_get_iommu(mr);
3656 if (!iommu_mr) {
3657 /* MMIO region. */
3658 return mr;
3661 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3662 NULL, is_write, true,
3663 &target_as, attrs);
3664 return section.mr;
3667 /* Called from RCU critical section. address_space_read_cached uses this
3668 * out of line function when the target is an MMIO or IOMMU region.
3670 void
3671 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3672 void *buf, int len)
3674 hwaddr addr1, l;
3675 MemoryRegion *mr;
3677 l = len;
3678 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3679 MEMTXATTRS_UNSPECIFIED);
3680 flatview_read_continue(cache->fv,
3681 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3682 addr1, l, mr);
3685 /* Called from RCU critical section. address_space_write_cached uses this
3686 * out of line function when the target is an MMIO or IOMMU region.
3688 void
3689 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3690 const void *buf, int len)
3692 hwaddr addr1, l;
3693 MemoryRegion *mr;
3695 l = len;
3696 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3697 MEMTXATTRS_UNSPECIFIED);
3698 flatview_write_continue(cache->fv,
3699 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3700 addr1, l, mr);
3703 #define ARG1_DECL MemoryRegionCache *cache
3704 #define ARG1 cache
3705 #define SUFFIX _cached_slow
3706 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3707 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3708 #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
3709 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3710 #define RCU_READ_LOCK() ((void)0)
3711 #define RCU_READ_UNLOCK() ((void)0)
3712 #include "memory_ldst.inc.c"
3714 /* virtual memory access for debug (includes writing to ROM) */
3715 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3716 uint8_t *buf, int len, int is_write)
3718 int l;
3719 hwaddr phys_addr;
3720 target_ulong page;
3722 cpu_synchronize_state(cpu);
3723 while (len > 0) {
3724 int asidx;
3725 MemTxAttrs attrs;
3727 page = addr & TARGET_PAGE_MASK;
3728 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3729 asidx = cpu_asidx_from_attrs(cpu, attrs);
3730 /* if no physical page mapped, return an error */
3731 if (phys_addr == -1)
3732 return -1;
3733 l = (page + TARGET_PAGE_SIZE) - addr;
3734 if (l > len)
3735 l = len;
3736 phys_addr += (addr & ~TARGET_PAGE_MASK);
3737 if (is_write) {
3738 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3739 phys_addr, buf, l);
3740 } else {
3741 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3742 MEMTXATTRS_UNSPECIFIED,
3743 buf, l, 0);
3745 len -= l;
3746 buf += l;
3747 addr += l;
3749 return 0;
3753 * Allows code that needs to deal with migration bitmaps etc to still be built
3754 * target independent.
3756 size_t qemu_target_page_size(void)
3758 return TARGET_PAGE_SIZE;
3761 int qemu_target_page_bits(void)
3763 return TARGET_PAGE_BITS;
3766 int qemu_target_page_bits_min(void)
3768 return TARGET_PAGE_BITS_MIN;
3770 #endif
3773 * A helper function for the _utterly broken_ virtio device model to find out if
3774 * it's running on a big endian machine. Don't do this at home kids!
3776 bool target_words_bigendian(void);
3777 bool target_words_bigendian(void)
3779 #if defined(TARGET_WORDS_BIGENDIAN)
3780 return true;
3781 #else
3782 return false;
3783 #endif
3786 #ifndef CONFIG_USER_ONLY
3787 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3789 MemoryRegion*mr;
3790 hwaddr l = 1;
3791 bool res;
3793 rcu_read_lock();
3794 mr = address_space_translate(&address_space_memory,
3795 phys_addr, &phys_addr, &l, false,
3796 MEMTXATTRS_UNSPECIFIED);
3798 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3799 rcu_read_unlock();
3800 return res;
3803 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3805 RAMBlock *block;
3806 int ret = 0;
3808 rcu_read_lock();
3809 RAMBLOCK_FOREACH(block) {
3810 ret = func(block->idstr, block->host, block->offset,
3811 block->used_length, opaque);
3812 if (ret) {
3813 break;
3816 rcu_read_unlock();
3817 return ret;
3820 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func, void *opaque)
3822 RAMBlock *block;
3823 int ret = 0;
3825 rcu_read_lock();
3826 RAMBLOCK_FOREACH(block) {
3827 if (!qemu_ram_is_migratable(block)) {
3828 continue;
3830 ret = func(block->idstr, block->host, block->offset,
3831 block->used_length, opaque);
3832 if (ret) {
3833 break;
3836 rcu_read_unlock();
3837 return ret;
3841 * Unmap pages of memory from start to start+length such that
3842 * they a) read as 0, b) Trigger whatever fault mechanism
3843 * the OS provides for postcopy.
3844 * The pages must be unmapped by the end of the function.
3845 * Returns: 0 on success, none-0 on failure
3848 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3850 int ret = -1;
3852 uint8_t *host_startaddr = rb->host + start;
3854 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3855 error_report("ram_block_discard_range: Unaligned start address: %p",
3856 host_startaddr);
3857 goto err;
3860 if ((start + length) <= rb->used_length) {
3861 bool need_madvise, need_fallocate;
3862 uint8_t *host_endaddr = host_startaddr + length;
3863 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3864 error_report("ram_block_discard_range: Unaligned end address: %p",
3865 host_endaddr);
3866 goto err;
3869 errno = ENOTSUP; /* If we are missing MADVISE etc */
3871 /* The logic here is messy;
3872 * madvise DONTNEED fails for hugepages
3873 * fallocate works on hugepages and shmem
3875 need_madvise = (rb->page_size == qemu_host_page_size);
3876 need_fallocate = rb->fd != -1;
3877 if (need_fallocate) {
3878 /* For a file, this causes the area of the file to be zero'd
3879 * if read, and for hugetlbfs also causes it to be unmapped
3880 * so a userfault will trigger.
3882 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3883 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3884 start, length);
3885 if (ret) {
3886 ret = -errno;
3887 error_report("ram_block_discard_range: Failed to fallocate "
3888 "%s:%" PRIx64 " +%zx (%d)",
3889 rb->idstr, start, length, ret);
3890 goto err;
3892 #else
3893 ret = -ENOSYS;
3894 error_report("ram_block_discard_range: fallocate not available/file"
3895 "%s:%" PRIx64 " +%zx (%d)",
3896 rb->idstr, start, length, ret);
3897 goto err;
3898 #endif
3900 if (need_madvise) {
3901 /* For normal RAM this causes it to be unmapped,
3902 * for shared memory it causes the local mapping to disappear
3903 * and to fall back on the file contents (which we just
3904 * fallocate'd away).
3906 #if defined(CONFIG_MADVISE)
3907 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3908 if (ret) {
3909 ret = -errno;
3910 error_report("ram_block_discard_range: Failed to discard range "
3911 "%s:%" PRIx64 " +%zx (%d)",
3912 rb->idstr, start, length, ret);
3913 goto err;
3915 #else
3916 ret = -ENOSYS;
3917 error_report("ram_block_discard_range: MADVISE not available"
3918 "%s:%" PRIx64 " +%zx (%d)",
3919 rb->idstr, start, length, ret);
3920 goto err;
3921 #endif
3923 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
3924 need_madvise, need_fallocate, ret);
3925 } else {
3926 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3927 "/%zx/" RAM_ADDR_FMT")",
3928 rb->idstr, start, length, rb->used_length);
3931 err:
3932 return ret;
3935 #endif
3937 void page_size_init(void)
3939 /* NOTE: we can always suppose that qemu_host_page_size >=
3940 TARGET_PAGE_SIZE */
3941 if (qemu_host_page_size == 0) {
3942 qemu_host_page_size = qemu_real_host_page_size;
3944 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
3945 qemu_host_page_size = TARGET_PAGE_SIZE;
3947 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
3950 #if !defined(CONFIG_USER_ONLY)
3952 static void mtree_print_phys_entries(fprintf_function mon, void *f,
3953 int start, int end, int skip, int ptr)
3955 if (start == end - 1) {
3956 mon(f, "\t%3d ", start);
3957 } else {
3958 mon(f, "\t%3d..%-3d ", start, end - 1);
3960 mon(f, " skip=%d ", skip);
3961 if (ptr == PHYS_MAP_NODE_NIL) {
3962 mon(f, " ptr=NIL");
3963 } else if (!skip) {
3964 mon(f, " ptr=#%d", ptr);
3965 } else {
3966 mon(f, " ptr=[%d]", ptr);
3968 mon(f, "\n");
3971 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3972 int128_sub((size), int128_one())) : 0)
3974 void mtree_print_dispatch(fprintf_function mon, void *f,
3975 AddressSpaceDispatch *d, MemoryRegion *root)
3977 int i;
3979 mon(f, " Dispatch\n");
3980 mon(f, " Physical sections\n");
3982 for (i = 0; i < d->map.sections_nb; ++i) {
3983 MemoryRegionSection *s = d->map.sections + i;
3984 const char *names[] = { " [unassigned]", " [not dirty]",
3985 " [ROM]", " [watch]" };
3987 mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s",
3989 s->offset_within_address_space,
3990 s->offset_within_address_space + MR_SIZE(s->mr->size),
3991 s->mr->name ? s->mr->name : "(noname)",
3992 i < ARRAY_SIZE(names) ? names[i] : "",
3993 s->mr == root ? " [ROOT]" : "",
3994 s == d->mru_section ? " [MRU]" : "",
3995 s->mr->is_iommu ? " [iommu]" : "");
3997 if (s->mr->alias) {
3998 mon(f, " alias=%s", s->mr->alias->name ?
3999 s->mr->alias->name : "noname");
4001 mon(f, "\n");
4004 mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4005 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
4006 for (i = 0; i < d->map.nodes_nb; ++i) {
4007 int j, jprev;
4008 PhysPageEntry prev;
4009 Node *n = d->map.nodes + i;
4011 mon(f, " [%d]\n", i);
4013 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
4014 PhysPageEntry *pe = *n + j;
4016 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
4017 continue;
4020 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4022 jprev = j;
4023 prev = *pe;
4026 if (jprev != ARRAY_SIZE(*n)) {
4027 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4032 #endif