4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
25 #include "qemu-common.h"
27 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
31 #include "qemu/timer.h"
32 #include "qemu/envlist.h"
42 static const char *cpu_model
;
43 unsigned long mmap_min_addr
;
44 #if defined(CONFIG_USE_GUEST_BASE)
47 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
49 * When running 32-on-64 we should make sure we can fit all of the possible
50 * guest address space into a contiguous chunk of virtual host memory.
52 * This way we will never overlap with our own libraries or binaries or stack
53 * or anything else that QEMU maps.
56 /* MIPS only supports 31 bits of virtual address space for user space */
57 uintptr_t reserved_va
= 0x77000000;
59 uintptr_t reserved_va
= 0xf7000000;
62 uintptr_t reserved_va
;
66 static void usage(void);
68 static const char *interp_prefix
= CONFIG_QEMU_INTERP_PREFIX
;
69 const char *qemu_uname_release
;
71 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
74 unsigned long guest_stack_size
= 8 * 1024 * 1024UL;
76 void gemu_log(const char *fmt
, ...)
81 vfprintf(stderr
, fmt
, ap
);
85 #if defined(TARGET_I386)
86 int cpu_get_pic_interrupt(CPUX86State
*env
)
92 /***********************************************************/
93 /* Helper routines for implementing atomic operations. */
95 /* To implement exclusive operations we force all cpus to syncronise.
96 We don't require a full sync, only that no cpus are executing guest code.
97 The alternative is to map target atomic ops onto host equivalents,
98 which requires quite a lot of per host/target work. */
99 static pthread_mutex_t cpu_list_mutex
= PTHREAD_MUTEX_INITIALIZER
;
100 static pthread_mutex_t exclusive_lock
= PTHREAD_MUTEX_INITIALIZER
;
101 static pthread_cond_t exclusive_cond
= PTHREAD_COND_INITIALIZER
;
102 static pthread_cond_t exclusive_resume
= PTHREAD_COND_INITIALIZER
;
103 static int pending_cpus
;
105 /* Make sure everything is in a consistent state for calling fork(). */
106 void fork_start(void)
108 pthread_mutex_lock(&tcg_ctx
.tb_ctx
.tb_lock
);
109 pthread_mutex_lock(&exclusive_lock
);
113 void fork_end(int child
)
115 mmap_fork_end(child
);
117 CPUState
*cpu
, *next_cpu
;
118 /* Child processes created by fork() only have a single thread.
119 Discard information about the parent threads. */
120 CPU_FOREACH_SAFE(cpu
, next_cpu
) {
121 if (cpu
!= thread_cpu
) {
122 QTAILQ_REMOVE(&cpus
, thread_cpu
, node
);
126 pthread_mutex_init(&exclusive_lock
, NULL
);
127 pthread_mutex_init(&cpu_list_mutex
, NULL
);
128 pthread_cond_init(&exclusive_cond
, NULL
);
129 pthread_cond_init(&exclusive_resume
, NULL
);
130 pthread_mutex_init(&tcg_ctx
.tb_ctx
.tb_lock
, NULL
);
131 gdbserver_fork((CPUArchState
*)thread_cpu
->env_ptr
);
133 pthread_mutex_unlock(&exclusive_lock
);
134 pthread_mutex_unlock(&tcg_ctx
.tb_ctx
.tb_lock
);
138 /* Wait for pending exclusive operations to complete. The exclusive lock
140 static inline void exclusive_idle(void)
142 while (pending_cpus
) {
143 pthread_cond_wait(&exclusive_resume
, &exclusive_lock
);
147 /* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149 static inline void start_exclusive(void)
153 pthread_mutex_lock(&exclusive_lock
);
157 /* Make all other cpus stop executing. */
158 CPU_FOREACH(other_cpu
) {
159 if (other_cpu
->running
) {
164 if (pending_cpus
> 1) {
165 pthread_cond_wait(&exclusive_cond
, &exclusive_lock
);
169 /* Finish an exclusive operation. */
170 static inline void __attribute__((unused
)) end_exclusive(void)
173 pthread_cond_broadcast(&exclusive_resume
);
174 pthread_mutex_unlock(&exclusive_lock
);
177 /* Wait for exclusive ops to finish, and begin cpu execution. */
178 static inline void cpu_exec_start(CPUState
*cpu
)
180 pthread_mutex_lock(&exclusive_lock
);
183 pthread_mutex_unlock(&exclusive_lock
);
186 /* Mark cpu as not executing, and release pending exclusive ops. */
187 static inline void cpu_exec_end(CPUState
*cpu
)
189 pthread_mutex_lock(&exclusive_lock
);
190 cpu
->running
= false;
191 if (pending_cpus
> 1) {
193 if (pending_cpus
== 1) {
194 pthread_cond_signal(&exclusive_cond
);
198 pthread_mutex_unlock(&exclusive_lock
);
201 void cpu_list_lock(void)
203 pthread_mutex_lock(&cpu_list_mutex
);
206 void cpu_list_unlock(void)
208 pthread_mutex_unlock(&cpu_list_mutex
);
213 /***********************************************************/
214 /* CPUX86 core interface */
216 void cpu_smm_update(CPUX86State
*env
)
220 uint64_t cpu_get_tsc(CPUX86State
*env
)
222 return cpu_get_real_ticks();
225 static void write_dt(void *ptr
, unsigned long addr
, unsigned long limit
,
230 e1
= (addr
<< 16) | (limit
& 0xffff);
231 e2
= ((addr
>> 16) & 0xff) | (addr
& 0xff000000) | (limit
& 0x000f0000);
238 static uint64_t *idt_table
;
240 static void set_gate64(void *ptr
, unsigned int type
, unsigned int dpl
,
241 uint64_t addr
, unsigned int sel
)
244 e1
= (addr
& 0xffff) | (sel
<< 16);
245 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
249 p
[2] = tswap32(addr
>> 32);
252 /* only dpl matters as we do only user space emulation */
253 static void set_idt(int n
, unsigned int dpl
)
255 set_gate64(idt_table
+ n
* 2, 0, dpl
, 0, 0);
258 static void set_gate(void *ptr
, unsigned int type
, unsigned int dpl
,
259 uint32_t addr
, unsigned int sel
)
262 e1
= (addr
& 0xffff) | (sel
<< 16);
263 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
269 /* only dpl matters as we do only user space emulation */
270 static void set_idt(int n
, unsigned int dpl
)
272 set_gate(idt_table
+ n
, 0, dpl
, 0, 0);
276 void cpu_loop(CPUX86State
*env
)
278 CPUState
*cs
= CPU(x86_env_get_cpu(env
));
281 target_siginfo_t info
;
289 trapnr
= cpu_x86_exec(env
);
293 /* linux syscall from int $0x80 */
294 env
->regs
[R_EAX
] = do_syscall(env
,
306 /* linux syscall from syscall instruction */
307 env
->regs
[R_EAX
] = do_syscall(env
,
321 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday
):
322 syscall_num
= __NR_gettimeofday
;
324 case TARGET_VSYSCALL_ADDR(__NR_vtime
):
326 syscall_num
= __NR_time
;
328 /* XXX: not yet implemented (arm eabi host) */
329 cpu_abort(cs
, "Unimplemented vsyscall vtime");
332 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu
):
333 /* XXX: not yet implemented */
334 cpu_abort(cs
, "Unimplemented vsyscall vgetcpu");
338 "Invalid vsyscall to address " TARGET_FMT_lx
"\n",
341 env
->regs
[R_EAX
] = do_syscall(env
,
351 get_user_u64(val
, env
->regs
[R_ESP
]);
353 env
->regs
[R_ESP
] += 8;
358 info
.si_signo
= TARGET_SIGBUS
;
360 info
.si_code
= TARGET_SI_KERNEL
;
361 info
._sifields
._sigfault
._addr
= 0;
362 queue_signal(env
, info
.si_signo
, &info
);
365 /* XXX: potential problem if ABI32 */
366 #ifndef TARGET_X86_64
367 if (env
->eflags
& VM_MASK
) {
368 handle_vm86_fault(env
);
372 info
.si_signo
= TARGET_SIGSEGV
;
374 info
.si_code
= TARGET_SI_KERNEL
;
375 info
._sifields
._sigfault
._addr
= 0;
376 queue_signal(env
, info
.si_signo
, &info
);
380 info
.si_signo
= TARGET_SIGSEGV
;
382 if (!(env
->error_code
& 1))
383 info
.si_code
= TARGET_SEGV_MAPERR
;
385 info
.si_code
= TARGET_SEGV_ACCERR
;
386 info
._sifields
._sigfault
._addr
= env
->cr
[2];
387 queue_signal(env
, info
.si_signo
, &info
);
390 #ifndef TARGET_X86_64
391 if (env
->eflags
& VM_MASK
) {
392 handle_vm86_trap(env
, trapnr
);
396 /* division by zero */
397 info
.si_signo
= TARGET_SIGFPE
;
399 info
.si_code
= TARGET_FPE_INTDIV
;
400 info
._sifields
._sigfault
._addr
= env
->eip
;
401 queue_signal(env
, info
.si_signo
, &info
);
406 #ifndef TARGET_X86_64
407 if (env
->eflags
& VM_MASK
) {
408 handle_vm86_trap(env
, trapnr
);
412 info
.si_signo
= TARGET_SIGTRAP
;
414 if (trapnr
== EXCP01_DB
) {
415 info
.si_code
= TARGET_TRAP_BRKPT
;
416 info
._sifields
._sigfault
._addr
= env
->eip
;
418 info
.si_code
= TARGET_SI_KERNEL
;
419 info
._sifields
._sigfault
._addr
= 0;
421 queue_signal(env
, info
.si_signo
, &info
);
426 #ifndef TARGET_X86_64
427 if (env
->eflags
& VM_MASK
) {
428 handle_vm86_trap(env
, trapnr
);
432 info
.si_signo
= TARGET_SIGSEGV
;
434 info
.si_code
= TARGET_SI_KERNEL
;
435 info
._sifields
._sigfault
._addr
= 0;
436 queue_signal(env
, info
.si_signo
, &info
);
440 info
.si_signo
= TARGET_SIGILL
;
442 info
.si_code
= TARGET_ILL_ILLOPN
;
443 info
._sifields
._sigfault
._addr
= env
->eip
;
444 queue_signal(env
, info
.si_signo
, &info
);
447 /* just indicate that signals should be handled asap */
453 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
458 info
.si_code
= TARGET_TRAP_BRKPT
;
459 queue_signal(env
, info
.si_signo
, &info
);
464 pc
= env
->segs
[R_CS
].base
+ env
->eip
;
465 fprintf(stderr
, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
469 process_pending_signals(env
);
476 #define get_user_code_u32(x, gaddr, doswap) \
477 ({ abi_long __r = get_user_u32((x), (gaddr)); \
478 if (!__r && (doswap)) { \
484 #define get_user_code_u16(x, gaddr, doswap) \
485 ({ abi_long __r = get_user_u16((x), (gaddr)); \
486 if (!__r && (doswap)) { \
493 /* Commpage handling -- there is no commpage for AArch64 */
496 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
498 * r0 = pointer to oldval
499 * r1 = pointer to newval
500 * r2 = pointer to target value
503 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
504 * C set if *ptr was changed, clear if no exchange happened
506 * Note segv's in kernel helpers are a bit tricky, we can set the
507 * data address sensibly but the PC address is just the entry point.
509 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
511 uint64_t oldval
, newval
, val
;
513 target_siginfo_t info
;
515 /* Based on the 32 bit code in do_kernel_trap */
517 /* XXX: This only works between threads, not between processes.
518 It's probably possible to implement this with native host
519 operations. However things like ldrex/strex are much harder so
520 there's not much point trying. */
522 cpsr
= cpsr_read(env
);
525 if (get_user_u64(oldval
, env
->regs
[0])) {
526 env
->exception
.vaddress
= env
->regs
[0];
530 if (get_user_u64(newval
, env
->regs
[1])) {
531 env
->exception
.vaddress
= env
->regs
[1];
535 if (get_user_u64(val
, addr
)) {
536 env
->exception
.vaddress
= addr
;
543 if (put_user_u64(val
, addr
)) {
544 env
->exception
.vaddress
= addr
;
554 cpsr_write(env
, cpsr
, CPSR_C
);
560 /* We get the PC of the entry address - which is as good as anything,
561 on a real kernel what you get depends on which mode it uses. */
562 info
.si_signo
= TARGET_SIGSEGV
;
564 /* XXX: check env->error_code */
565 info
.si_code
= TARGET_SEGV_MAPERR
;
566 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
567 queue_signal(env
, info
.si_signo
, &info
);
572 /* Handle a jump to the kernel code page. */
574 do_kernel_trap(CPUARMState
*env
)
580 switch (env
->regs
[15]) {
581 case 0xffff0fa0: /* __kernel_memory_barrier */
582 /* ??? No-op. Will need to do better for SMP. */
584 case 0xffff0fc0: /* __kernel_cmpxchg */
585 /* XXX: This only works between threads, not between processes.
586 It's probably possible to implement this with native host
587 operations. However things like ldrex/strex are much harder so
588 there's not much point trying. */
590 cpsr
= cpsr_read(env
);
592 /* FIXME: This should SEGV if the access fails. */
593 if (get_user_u32(val
, addr
))
595 if (val
== env
->regs
[0]) {
597 /* FIXME: Check for segfaults. */
598 put_user_u32(val
, addr
);
605 cpsr_write(env
, cpsr
, CPSR_C
);
608 case 0xffff0fe0: /* __kernel_get_tls */
609 env
->regs
[0] = cpu_get_tls(env
);
611 case 0xffff0f60: /* __kernel_cmpxchg64 */
612 arm_kernel_cmpxchg64_helper(env
);
618 /* Jump back to the caller. */
619 addr
= env
->regs
[14];
624 env
->regs
[15] = addr
;
629 /* Store exclusive handling for AArch32 */
630 static int do_strex(CPUARMState
*env
)
638 if (env
->exclusive_addr
!= env
->exclusive_test
) {
641 /* We know we're always AArch32 so the address is in uint32_t range
642 * unless it was the -1 exclusive-monitor-lost value (which won't
643 * match exclusive_test above).
645 assert(extract64(env
->exclusive_addr
, 32, 32) == 0);
646 addr
= env
->exclusive_addr
;
647 size
= env
->exclusive_info
& 0xf;
650 segv
= get_user_u8(val
, addr
);
653 segv
= get_user_u16(val
, addr
);
657 segv
= get_user_u32(val
, addr
);
663 env
->exception
.vaddress
= addr
;
668 segv
= get_user_u32(valhi
, addr
+ 4);
670 env
->exception
.vaddress
= addr
+ 4;
673 val
= deposit64(val
, 32, 32, valhi
);
675 if (val
!= env
->exclusive_val
) {
679 val
= env
->regs
[(env
->exclusive_info
>> 8) & 0xf];
682 segv
= put_user_u8(val
, addr
);
685 segv
= put_user_u16(val
, addr
);
689 segv
= put_user_u32(val
, addr
);
693 env
->exception
.vaddress
= addr
;
697 val
= env
->regs
[(env
->exclusive_info
>> 12) & 0xf];
698 segv
= put_user_u32(val
, addr
+ 4);
700 env
->exception
.vaddress
= addr
+ 4;
707 env
->regs
[(env
->exclusive_info
>> 4) & 0xf] = rc
;
713 void cpu_loop(CPUARMState
*env
)
715 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
717 unsigned int n
, insn
;
718 target_siginfo_t info
;
723 trapnr
= cpu_arm_exec(env
);
728 TaskState
*ts
= cs
->opaque
;
732 /* we handle the FPU emulation here, as Linux */
733 /* we get the opcode */
734 /* FIXME - what to do if get_user() fails? */
735 get_user_code_u32(opcode
, env
->regs
[15], env
->bswap_code
);
737 rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
738 if (rc
== 0) { /* illegal instruction */
739 info
.si_signo
= TARGET_SIGILL
;
741 info
.si_code
= TARGET_ILL_ILLOPN
;
742 info
._sifields
._sigfault
._addr
= env
->regs
[15];
743 queue_signal(env
, info
.si_signo
, &info
);
744 } else if (rc
< 0) { /* FP exception */
747 /* translate softfloat flags to FPSR flags */
748 if (-rc
& float_flag_invalid
)
750 if (-rc
& float_flag_divbyzero
)
752 if (-rc
& float_flag_overflow
)
754 if (-rc
& float_flag_underflow
)
756 if (-rc
& float_flag_inexact
)
759 FPSR fpsr
= ts
->fpa
.fpsr
;
760 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
762 if (fpsr
& (arm_fpe
<< 16)) { /* exception enabled? */
763 info
.si_signo
= TARGET_SIGFPE
;
766 /* ordered by priority, least first */
767 if (arm_fpe
& BIT_IXC
) info
.si_code
= TARGET_FPE_FLTRES
;
768 if (arm_fpe
& BIT_UFC
) info
.si_code
= TARGET_FPE_FLTUND
;
769 if (arm_fpe
& BIT_OFC
) info
.si_code
= TARGET_FPE_FLTOVF
;
770 if (arm_fpe
& BIT_DZC
) info
.si_code
= TARGET_FPE_FLTDIV
;
771 if (arm_fpe
& BIT_IOC
) info
.si_code
= TARGET_FPE_FLTINV
;
773 info
._sifields
._sigfault
._addr
= env
->regs
[15];
774 queue_signal(env
, info
.si_signo
, &info
);
779 /* accumulate unenabled exceptions */
780 if ((!(fpsr
& BIT_IXE
)) && (arm_fpe
& BIT_IXC
))
782 if ((!(fpsr
& BIT_UFE
)) && (arm_fpe
& BIT_UFC
))
784 if ((!(fpsr
& BIT_OFE
)) && (arm_fpe
& BIT_OFC
))
786 if ((!(fpsr
& BIT_DZE
)) && (arm_fpe
& BIT_DZC
))
788 if ((!(fpsr
& BIT_IOE
)) && (arm_fpe
& BIT_IOC
))
791 } else { /* everything OK */
802 if (trapnr
== EXCP_BKPT
) {
804 /* FIXME - what to do if get_user() fails? */
805 get_user_code_u16(insn
, env
->regs
[15], env
->bswap_code
);
809 /* FIXME - what to do if get_user() fails? */
810 get_user_code_u32(insn
, env
->regs
[15], env
->bswap_code
);
811 n
= (insn
& 0xf) | ((insn
>> 4) & 0xff0);
816 /* FIXME - what to do if get_user() fails? */
817 get_user_code_u16(insn
, env
->regs
[15] - 2,
821 /* FIXME - what to do if get_user() fails? */
822 get_user_code_u32(insn
, env
->regs
[15] - 4,
828 if (n
== ARM_NR_cacheflush
) {
830 } else if (n
== ARM_NR_semihosting
831 || n
== ARM_NR_thumb_semihosting
) {
832 env
->regs
[0] = do_arm_semihosting (env
);
833 } else if (n
== 0 || n
>= ARM_SYSCALL_BASE
|| env
->thumb
) {
835 if (env
->thumb
|| n
== 0) {
838 n
-= ARM_SYSCALL_BASE
;
841 if ( n
> ARM_NR_BASE
) {
843 case ARM_NR_cacheflush
:
847 cpu_set_tls(env
, env
->regs
[0]);
850 case ARM_NR_breakpoint
:
851 env
->regs
[15] -= env
->thumb
? 2 : 4;
854 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
856 env
->regs
[0] = -TARGET_ENOSYS
;
860 env
->regs
[0] = do_syscall(env
,
876 /* just indicate that signals should be handled asap */
879 if (!do_strex(env
)) {
882 /* fall through for segv */
883 case EXCP_PREFETCH_ABORT
:
884 case EXCP_DATA_ABORT
:
885 addr
= env
->exception
.vaddress
;
887 info
.si_signo
= TARGET_SIGSEGV
;
889 /* XXX: check env->error_code */
890 info
.si_code
= TARGET_SEGV_MAPERR
;
891 info
._sifields
._sigfault
._addr
= addr
;
892 queue_signal(env
, info
.si_signo
, &info
);
900 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
905 info
.si_code
= TARGET_TRAP_BRKPT
;
906 queue_signal(env
, info
.si_signo
, &info
);
910 case EXCP_KERNEL_TRAP
:
911 if (do_kernel_trap(env
))
916 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
918 cpu_dump_state(cs
, stderr
, fprintf
, 0);
921 process_pending_signals(env
);
928 * Handle AArch64 store-release exclusive
930 * rs = gets the status result of store exclusive
931 * rt = is the register that is stored
932 * rt2 = is the second register store (in STP)
935 static int do_strex_a64(CPUARMState
*env
)
946 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
947 size
= extract32(env
->exclusive_info
, 0, 2);
948 is_pair
= extract32(env
->exclusive_info
, 2, 1);
949 rs
= extract32(env
->exclusive_info
, 4, 5);
950 rt
= extract32(env
->exclusive_info
, 9, 5);
951 rt2
= extract32(env
->exclusive_info
, 14, 5);
953 addr
= env
->exclusive_addr
;
955 if (addr
!= env
->exclusive_test
) {
961 segv
= get_user_u8(val
, addr
);
964 segv
= get_user_u16(val
, addr
);
967 segv
= get_user_u32(val
, addr
);
970 segv
= get_user_u64(val
, addr
);
976 env
->exception
.vaddress
= addr
;
979 if (val
!= env
->exclusive_val
) {
984 segv
= get_user_u32(val
, addr
+ 4);
986 segv
= get_user_u64(val
, addr
+ 8);
989 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
992 if (val
!= env
->exclusive_high
) {
996 /* handle the zero register */
997 val
= rt
== 31 ? 0 : env
->xregs
[rt
];
1000 segv
= put_user_u8(val
, addr
);
1003 segv
= put_user_u16(val
, addr
);
1006 segv
= put_user_u32(val
, addr
);
1009 segv
= put_user_u64(val
, addr
);
1016 /* handle the zero register */
1017 val
= rt2
== 31 ? 0 : env
->xregs
[rt2
];
1019 segv
= put_user_u32(val
, addr
+ 4);
1021 segv
= put_user_u64(val
, addr
+ 8);
1024 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
1031 /* rs == 31 encodes a write to the ZR, thus throwing away
1032 * the status return. This is rather silly but valid.
1035 env
->xregs
[rs
] = rc
;
1038 /* instruction faulted, PC does not advance */
1039 /* either way a strex releases any exclusive lock we have */
1040 env
->exclusive_addr
= -1;
1045 /* AArch64 main loop */
1046 void cpu_loop(CPUARMState
*env
)
1048 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1050 target_siginfo_t info
;
1054 trapnr
= cpu_arm_exec(env
);
1059 env
->xregs
[0] = do_syscall(env
,
1069 case EXCP_INTERRUPT
:
1070 /* just indicate that signals should be handled asap */
1073 info
.si_signo
= TARGET_SIGILL
;
1075 info
.si_code
= TARGET_ILL_ILLOPN
;
1076 info
._sifields
._sigfault
._addr
= env
->pc
;
1077 queue_signal(env
, info
.si_signo
, &info
);
1080 if (!do_strex_a64(env
)) {
1083 /* fall through for segv */
1084 case EXCP_PREFETCH_ABORT
:
1085 case EXCP_DATA_ABORT
:
1086 info
.si_signo
= TARGET_SIGSEGV
;
1088 /* XXX: check env->error_code */
1089 info
.si_code
= TARGET_SEGV_MAPERR
;
1090 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
1091 queue_signal(env
, info
.si_signo
, &info
);
1095 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1097 info
.si_signo
= sig
;
1099 info
.si_code
= TARGET_TRAP_BRKPT
;
1100 queue_signal(env
, info
.si_signo
, &info
);
1104 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
1106 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1109 process_pending_signals(env
);
1110 /* Exception return on AArch64 always clears the exclusive monitor,
1111 * so any return to running guest code implies this.
1112 * A strex (successful or otherwise) also clears the monitor, so
1113 * we don't need to specialcase EXCP_STREX.
1115 env
->exclusive_addr
= -1;
1118 #endif /* ndef TARGET_ABI32 */
1122 #ifdef TARGET_UNICORE32
1124 void cpu_loop(CPUUniCore32State
*env
)
1126 CPUState
*cs
= CPU(uc32_env_get_cpu(env
));
1128 unsigned int n
, insn
;
1129 target_siginfo_t info
;
1133 trapnr
= uc32_cpu_exec(env
);
1136 case UC32_EXCP_PRIV
:
1139 get_user_u32(insn
, env
->regs
[31] - 4);
1140 n
= insn
& 0xffffff;
1142 if (n
>= UC32_SYSCALL_BASE
) {
1144 n
-= UC32_SYSCALL_BASE
;
1145 if (n
== UC32_SYSCALL_NR_set_tls
) {
1146 cpu_set_tls(env
, env
->regs
[0]);
1149 env
->regs
[0] = do_syscall(env
,
1164 case UC32_EXCP_DTRAP
:
1165 case UC32_EXCP_ITRAP
:
1166 info
.si_signo
= TARGET_SIGSEGV
;
1168 /* XXX: check env->error_code */
1169 info
.si_code
= TARGET_SEGV_MAPERR
;
1170 info
._sifields
._sigfault
._addr
= env
->cp0
.c4_faultaddr
;
1171 queue_signal(env
, info
.si_signo
, &info
);
1173 case EXCP_INTERRUPT
:
1174 /* just indicate that signals should be handled asap */
1180 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1182 info
.si_signo
= sig
;
1184 info
.si_code
= TARGET_TRAP_BRKPT
;
1185 queue_signal(env
, info
.si_signo
, &info
);
1192 process_pending_signals(env
);
1196 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
1197 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1203 #define SPARC64_STACK_BIAS 2047
1207 /* WARNING: dealing with register windows _is_ complicated. More info
1208 can be found at http://www.sics.se/~psm/sparcstack.html */
1209 static inline int get_reg_index(CPUSPARCState
*env
, int cwp
, int index
)
1211 index
= (index
+ cwp
* 16) % (16 * env
->nwindows
);
1212 /* wrap handling : if cwp is on the last window, then we use the
1213 registers 'after' the end */
1214 if (index
< 8 && env
->cwp
== env
->nwindows
- 1)
1215 index
+= 16 * env
->nwindows
;
1219 /* save the register window 'cwp1' */
1220 static inline void save_window_offset(CPUSPARCState
*env
, int cwp1
)
1225 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1226 #ifdef TARGET_SPARC64
1228 sp_ptr
+= SPARC64_STACK_BIAS
;
1230 #if defined(DEBUG_WIN)
1231 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" save_cwp=%d\n",
1234 for(i
= 0; i
< 16; i
++) {
1235 /* FIXME - what to do if put_user() fails? */
1236 put_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1237 sp_ptr
+= sizeof(abi_ulong
);
1241 static void save_window(CPUSPARCState
*env
)
1243 #ifndef TARGET_SPARC64
1244 unsigned int new_wim
;
1245 new_wim
= ((env
->wim
>> 1) | (env
->wim
<< (env
->nwindows
- 1))) &
1246 ((1LL << env
->nwindows
) - 1);
1247 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1250 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1256 static void restore_window(CPUSPARCState
*env
)
1258 #ifndef TARGET_SPARC64
1259 unsigned int new_wim
;
1261 unsigned int i
, cwp1
;
1264 #ifndef TARGET_SPARC64
1265 new_wim
= ((env
->wim
<< 1) | (env
->wim
>> (env
->nwindows
- 1))) &
1266 ((1LL << env
->nwindows
) - 1);
1269 /* restore the invalid window */
1270 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1271 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1272 #ifdef TARGET_SPARC64
1274 sp_ptr
+= SPARC64_STACK_BIAS
;
1276 #if defined(DEBUG_WIN)
1277 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" load_cwp=%d\n",
1280 for(i
= 0; i
< 16; i
++) {
1281 /* FIXME - what to do if get_user() fails? */
1282 get_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1283 sp_ptr
+= sizeof(abi_ulong
);
1285 #ifdef TARGET_SPARC64
1287 if (env
->cleanwin
< env
->nwindows
- 1)
1295 static void flush_windows(CPUSPARCState
*env
)
1301 /* if restore would invoke restore_window(), then we can stop */
1302 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ offset
);
1303 #ifndef TARGET_SPARC64
1304 if (env
->wim
& (1 << cwp1
))
1307 if (env
->canrestore
== 0)
1312 save_window_offset(env
, cwp1
);
1315 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1316 #ifndef TARGET_SPARC64
1317 /* set wim so that restore will reload the registers */
1318 env
->wim
= 1 << cwp1
;
1320 #if defined(DEBUG_WIN)
1321 printf("flush_windows: nb=%d\n", offset
- 1);
1325 void cpu_loop (CPUSPARCState
*env
)
1327 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1330 target_siginfo_t info
;
1334 trapnr
= cpu_sparc_exec (env
);
1337 /* Compute PSR before exposing state. */
1338 if (env
->cc_op
!= CC_OP_FLAGS
) {
1343 #ifndef TARGET_SPARC64
1350 ret
= do_syscall (env
, env
->gregs
[1],
1351 env
->regwptr
[0], env
->regwptr
[1],
1352 env
->regwptr
[2], env
->regwptr
[3],
1353 env
->regwptr
[4], env
->regwptr
[5],
1355 if ((abi_ulong
)ret
>= (abi_ulong
)(-515)) {
1356 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1357 env
->xcc
|= PSR_CARRY
;
1359 env
->psr
|= PSR_CARRY
;
1363 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1364 env
->xcc
&= ~PSR_CARRY
;
1366 env
->psr
&= ~PSR_CARRY
;
1369 env
->regwptr
[0] = ret
;
1370 /* next instruction */
1372 env
->npc
= env
->npc
+ 4;
1374 case 0x83: /* flush windows */
1379 /* next instruction */
1381 env
->npc
= env
->npc
+ 4;
1383 #ifndef TARGET_SPARC64
1384 case TT_WIN_OVF
: /* window overflow */
1387 case TT_WIN_UNF
: /* window underflow */
1388 restore_window(env
);
1393 info
.si_signo
= TARGET_SIGSEGV
;
1395 /* XXX: check env->error_code */
1396 info
.si_code
= TARGET_SEGV_MAPERR
;
1397 info
._sifields
._sigfault
._addr
= env
->mmuregs
[4];
1398 queue_signal(env
, info
.si_signo
, &info
);
1402 case TT_SPILL
: /* window overflow */
1405 case TT_FILL
: /* window underflow */
1406 restore_window(env
);
1411 info
.si_signo
= TARGET_SIGSEGV
;
1413 /* XXX: check env->error_code */
1414 info
.si_code
= TARGET_SEGV_MAPERR
;
1415 if (trapnr
== TT_DFAULT
)
1416 info
._sifields
._sigfault
._addr
= env
->dmmuregs
[4];
1418 info
._sifields
._sigfault
._addr
= cpu_tsptr(env
)->tpc
;
1419 queue_signal(env
, info
.si_signo
, &info
);
1422 #ifndef TARGET_ABI32
1425 sparc64_get_context(env
);
1429 sparc64_set_context(env
);
1433 case EXCP_INTERRUPT
:
1434 /* just indicate that signals should be handled asap */
1438 info
.si_signo
= TARGET_SIGILL
;
1440 info
.si_code
= TARGET_ILL_ILLOPC
;
1441 info
._sifields
._sigfault
._addr
= env
->pc
;
1442 queue_signal(env
, info
.si_signo
, &info
);
1449 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1452 info
.si_signo
= sig
;
1454 info
.si_code
= TARGET_TRAP_BRKPT
;
1455 queue_signal(env
, info
.si_signo
, &info
);
1460 printf ("Unhandled trap: 0x%x\n", trapnr
);
1461 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1464 process_pending_signals (env
);
1471 static inline uint64_t cpu_ppc_get_tb(CPUPPCState
*env
)
1477 uint64_t cpu_ppc_load_tbl(CPUPPCState
*env
)
1479 return cpu_ppc_get_tb(env
);
1482 uint32_t cpu_ppc_load_tbu(CPUPPCState
*env
)
1484 return cpu_ppc_get_tb(env
) >> 32;
1487 uint64_t cpu_ppc_load_atbl(CPUPPCState
*env
)
1489 return cpu_ppc_get_tb(env
);
1492 uint32_t cpu_ppc_load_atbu(CPUPPCState
*env
)
1494 return cpu_ppc_get_tb(env
) >> 32;
1497 uint32_t cpu_ppc601_load_rtcu(CPUPPCState
*env
)
1498 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1500 uint32_t cpu_ppc601_load_rtcl(CPUPPCState
*env
)
1502 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
1505 /* XXX: to be fixed */
1506 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1511 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1516 #define EXCP_DUMP(env, fmt, ...) \
1518 CPUState *cs = ENV_GET_CPU(env); \
1519 fprintf(stderr, fmt , ## __VA_ARGS__); \
1520 cpu_dump_state(cs, stderr, fprintf, 0); \
1521 qemu_log(fmt, ## __VA_ARGS__); \
1522 if (qemu_log_enabled()) { \
1523 log_cpu_state(cs, 0); \
1527 static int do_store_exclusive(CPUPPCState
*env
)
1530 target_ulong page_addr
;
1531 target_ulong val
, val2
__attribute__((unused
)) = 0;
1535 addr
= env
->reserve_ea
;
1536 page_addr
= addr
& TARGET_PAGE_MASK
;
1539 flags
= page_get_flags(page_addr
);
1540 if ((flags
& PAGE_READ
) == 0) {
1543 int reg
= env
->reserve_info
& 0x1f;
1544 int size
= env
->reserve_info
>> 5;
1547 if (addr
== env
->reserve_addr
) {
1549 case 1: segv
= get_user_u8(val
, addr
); break;
1550 case 2: segv
= get_user_u16(val
, addr
); break;
1551 case 4: segv
= get_user_u32(val
, addr
); break;
1552 #if defined(TARGET_PPC64)
1553 case 8: segv
= get_user_u64(val
, addr
); break;
1555 segv
= get_user_u64(val
, addr
);
1557 segv
= get_user_u64(val2
, addr
+ 8);
1564 if (!segv
&& val
== env
->reserve_val
) {
1565 val
= env
->gpr
[reg
];
1567 case 1: segv
= put_user_u8(val
, addr
); break;
1568 case 2: segv
= put_user_u16(val
, addr
); break;
1569 case 4: segv
= put_user_u32(val
, addr
); break;
1570 #if defined(TARGET_PPC64)
1571 case 8: segv
= put_user_u64(val
, addr
); break;
1573 if (val2
== env
->reserve_val2
) {
1576 val
= env
->gpr
[reg
+1];
1578 val2
= env
->gpr
[reg
+1];
1580 segv
= put_user_u64(val
, addr
);
1582 segv
= put_user_u64(val2
, addr
+ 8);
1595 env
->crf
[0] = (stored
<< 1) | xer_so
;
1596 env
->reserve_addr
= (target_ulong
)-1;
1606 void cpu_loop(CPUPPCState
*env
)
1608 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
1609 target_siginfo_t info
;
1615 trapnr
= cpu_ppc_exec(env
);
1618 case POWERPC_EXCP_NONE
:
1621 case POWERPC_EXCP_CRITICAL
: /* Critical input */
1622 cpu_abort(cs
, "Critical interrupt while in user mode. "
1625 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1626 cpu_abort(cs
, "Machine check exception while in user mode. "
1629 case POWERPC_EXCP_DSI
: /* Data storage exception */
1630 EXCP_DUMP(env
, "Invalid data memory access: 0x" TARGET_FMT_lx
"\n",
1632 /* XXX: check this. Seems bugged */
1633 switch (env
->error_code
& 0xFF000000) {
1635 info
.si_signo
= TARGET_SIGSEGV
;
1637 info
.si_code
= TARGET_SEGV_MAPERR
;
1640 info
.si_signo
= TARGET_SIGILL
;
1642 info
.si_code
= TARGET_ILL_ILLADR
;
1645 info
.si_signo
= TARGET_SIGSEGV
;
1647 info
.si_code
= TARGET_SEGV_ACCERR
;
1650 /* Let's send a regular segfault... */
1651 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1653 info
.si_signo
= TARGET_SIGSEGV
;
1655 info
.si_code
= TARGET_SEGV_MAPERR
;
1658 info
._sifields
._sigfault
._addr
= env
->nip
;
1659 queue_signal(env
, info
.si_signo
, &info
);
1661 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1662 EXCP_DUMP(env
, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1663 "\n", env
->spr
[SPR_SRR0
]);
1664 /* XXX: check this */
1665 switch (env
->error_code
& 0xFF000000) {
1667 info
.si_signo
= TARGET_SIGSEGV
;
1669 info
.si_code
= TARGET_SEGV_MAPERR
;
1673 info
.si_signo
= TARGET_SIGSEGV
;
1675 info
.si_code
= TARGET_SEGV_ACCERR
;
1678 /* Let's send a regular segfault... */
1679 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1681 info
.si_signo
= TARGET_SIGSEGV
;
1683 info
.si_code
= TARGET_SEGV_MAPERR
;
1686 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1687 queue_signal(env
, info
.si_signo
, &info
);
1689 case POWERPC_EXCP_EXTERNAL
: /* External input */
1690 cpu_abort(cs
, "External interrupt while in user mode. "
1693 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1694 EXCP_DUMP(env
, "Unaligned memory access\n");
1695 /* XXX: check this */
1696 info
.si_signo
= TARGET_SIGBUS
;
1698 info
.si_code
= TARGET_BUS_ADRALN
;
1699 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1700 queue_signal(env
, info
.si_signo
, &info
);
1702 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1703 /* XXX: check this */
1704 switch (env
->error_code
& ~0xF) {
1705 case POWERPC_EXCP_FP
:
1706 EXCP_DUMP(env
, "Floating point program exception\n");
1707 info
.si_signo
= TARGET_SIGFPE
;
1709 switch (env
->error_code
& 0xF) {
1710 case POWERPC_EXCP_FP_OX
:
1711 info
.si_code
= TARGET_FPE_FLTOVF
;
1713 case POWERPC_EXCP_FP_UX
:
1714 info
.si_code
= TARGET_FPE_FLTUND
;
1716 case POWERPC_EXCP_FP_ZX
:
1717 case POWERPC_EXCP_FP_VXZDZ
:
1718 info
.si_code
= TARGET_FPE_FLTDIV
;
1720 case POWERPC_EXCP_FP_XX
:
1721 info
.si_code
= TARGET_FPE_FLTRES
;
1723 case POWERPC_EXCP_FP_VXSOFT
:
1724 info
.si_code
= TARGET_FPE_FLTINV
;
1726 case POWERPC_EXCP_FP_VXSNAN
:
1727 case POWERPC_EXCP_FP_VXISI
:
1728 case POWERPC_EXCP_FP_VXIDI
:
1729 case POWERPC_EXCP_FP_VXIMZ
:
1730 case POWERPC_EXCP_FP_VXVC
:
1731 case POWERPC_EXCP_FP_VXSQRT
:
1732 case POWERPC_EXCP_FP_VXCVI
:
1733 info
.si_code
= TARGET_FPE_FLTSUB
;
1736 EXCP_DUMP(env
, "Unknown floating point exception (%02x)\n",
1741 case POWERPC_EXCP_INVAL
:
1742 EXCP_DUMP(env
, "Invalid instruction\n");
1743 info
.si_signo
= TARGET_SIGILL
;
1745 switch (env
->error_code
& 0xF) {
1746 case POWERPC_EXCP_INVAL_INVAL
:
1747 info
.si_code
= TARGET_ILL_ILLOPC
;
1749 case POWERPC_EXCP_INVAL_LSWX
:
1750 info
.si_code
= TARGET_ILL_ILLOPN
;
1752 case POWERPC_EXCP_INVAL_SPR
:
1753 info
.si_code
= TARGET_ILL_PRVREG
;
1755 case POWERPC_EXCP_INVAL_FP
:
1756 info
.si_code
= TARGET_ILL_COPROC
;
1759 EXCP_DUMP(env
, "Unknown invalid operation (%02x)\n",
1760 env
->error_code
& 0xF);
1761 info
.si_code
= TARGET_ILL_ILLADR
;
1765 case POWERPC_EXCP_PRIV
:
1766 EXCP_DUMP(env
, "Privilege violation\n");
1767 info
.si_signo
= TARGET_SIGILL
;
1769 switch (env
->error_code
& 0xF) {
1770 case POWERPC_EXCP_PRIV_OPC
:
1771 info
.si_code
= TARGET_ILL_PRVOPC
;
1773 case POWERPC_EXCP_PRIV_REG
:
1774 info
.si_code
= TARGET_ILL_PRVREG
;
1777 EXCP_DUMP(env
, "Unknown privilege violation (%02x)\n",
1778 env
->error_code
& 0xF);
1779 info
.si_code
= TARGET_ILL_PRVOPC
;
1783 case POWERPC_EXCP_TRAP
:
1784 cpu_abort(cs
, "Tried to call a TRAP\n");
1787 /* Should not happen ! */
1788 cpu_abort(cs
, "Unknown program exception (%02x)\n",
1792 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1793 queue_signal(env
, info
.si_signo
, &info
);
1795 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1796 EXCP_DUMP(env
, "No floating point allowed\n");
1797 info
.si_signo
= TARGET_SIGILL
;
1799 info
.si_code
= TARGET_ILL_COPROC
;
1800 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1801 queue_signal(env
, info
.si_signo
, &info
);
1803 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1804 cpu_abort(cs
, "Syscall exception while in user mode. "
1807 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
1808 EXCP_DUMP(env
, "No APU instruction allowed\n");
1809 info
.si_signo
= TARGET_SIGILL
;
1811 info
.si_code
= TARGET_ILL_COPROC
;
1812 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1813 queue_signal(env
, info
.si_signo
, &info
);
1815 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1816 cpu_abort(cs
, "Decrementer interrupt while in user mode. "
1819 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
1820 cpu_abort(cs
, "Fix interval timer interrupt while in user mode. "
1823 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
1824 cpu_abort(cs
, "Watchdog timer interrupt while in user mode. "
1827 case POWERPC_EXCP_DTLB
: /* Data TLB error */
1828 cpu_abort(cs
, "Data TLB exception while in user mode. "
1831 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
1832 cpu_abort(cs
, "Instruction TLB exception while in user mode. "
1835 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavail. */
1836 EXCP_DUMP(env
, "No SPE/floating-point instruction allowed\n");
1837 info
.si_signo
= TARGET_SIGILL
;
1839 info
.si_code
= TARGET_ILL_COPROC
;
1840 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1841 queue_signal(env
, info
.si_signo
, &info
);
1843 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data IRQ */
1844 cpu_abort(cs
, "Embedded floating-point data IRQ not handled\n");
1846 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round IRQ */
1847 cpu_abort(cs
, "Embedded floating-point round IRQ not handled\n");
1849 case POWERPC_EXCP_EPERFM
: /* Embedded performance monitor IRQ */
1850 cpu_abort(cs
, "Performance monitor exception not handled\n");
1852 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
1853 cpu_abort(cs
, "Doorbell interrupt while in user mode. "
1856 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
1857 cpu_abort(cs
, "Doorbell critical interrupt while in user mode. "
1860 case POWERPC_EXCP_RESET
: /* System reset exception */
1861 cpu_abort(cs
, "Reset interrupt while in user mode. "
1864 case POWERPC_EXCP_DSEG
: /* Data segment exception */
1865 cpu_abort(cs
, "Data segment exception while in user mode. "
1868 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
1869 cpu_abort(cs
, "Instruction segment exception "
1870 "while in user mode. Aborting\n");
1872 /* PowerPC 64 with hypervisor mode support */
1873 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
1874 cpu_abort(cs
, "Hypervisor decrementer interrupt "
1875 "while in user mode. Aborting\n");
1877 case POWERPC_EXCP_TRACE
: /* Trace exception */
1879 * we use this exception to emulate step-by-step execution mode.
1882 /* PowerPC 64 with hypervisor mode support */
1883 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
1884 cpu_abort(cs
, "Hypervisor data storage exception "
1885 "while in user mode. Aborting\n");
1887 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage excp */
1888 cpu_abort(cs
, "Hypervisor instruction storage exception "
1889 "while in user mode. Aborting\n");
1891 case POWERPC_EXCP_HDSEG
: /* Hypervisor data segment exception */
1892 cpu_abort(cs
, "Hypervisor data segment exception "
1893 "while in user mode. Aborting\n");
1895 case POWERPC_EXCP_HISEG
: /* Hypervisor instruction segment excp */
1896 cpu_abort(cs
, "Hypervisor instruction segment exception "
1897 "while in user mode. Aborting\n");
1899 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1900 EXCP_DUMP(env
, "No Altivec instructions allowed\n");
1901 info
.si_signo
= TARGET_SIGILL
;
1903 info
.si_code
= TARGET_ILL_COPROC
;
1904 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1905 queue_signal(env
, info
.si_signo
, &info
);
1907 case POWERPC_EXCP_PIT
: /* Programmable interval timer IRQ */
1908 cpu_abort(cs
, "Programmable interval timer interrupt "
1909 "while in user mode. Aborting\n");
1911 case POWERPC_EXCP_IO
: /* IO error exception */
1912 cpu_abort(cs
, "IO error exception while in user mode. "
1915 case POWERPC_EXCP_RUNM
: /* Run mode exception */
1916 cpu_abort(cs
, "Run mode exception while in user mode. "
1919 case POWERPC_EXCP_EMUL
: /* Emulation trap exception */
1920 cpu_abort(cs
, "Emulation trap exception not handled\n");
1922 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
1923 cpu_abort(cs
, "Instruction fetch TLB exception "
1924 "while in user-mode. Aborting");
1926 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
1927 cpu_abort(cs
, "Data load TLB exception while in user-mode. "
1930 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
1931 cpu_abort(cs
, "Data store TLB exception while in user-mode. "
1934 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
1935 cpu_abort(cs
, "Floating-point assist exception not handled\n");
1937 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
1938 cpu_abort(cs
, "Instruction address breakpoint exception "
1941 case POWERPC_EXCP_SMI
: /* System management interrupt */
1942 cpu_abort(cs
, "System management interrupt while in user mode. "
1945 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1946 cpu_abort(cs
, "Thermal interrupt interrupt while in user mode. "
1949 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor IRQ */
1950 cpu_abort(cs
, "Performance monitor exception not handled\n");
1952 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1953 cpu_abort(cs
, "Vector assist exception not handled\n");
1955 case POWERPC_EXCP_SOFTP
: /* Soft patch exception */
1956 cpu_abort(cs
, "Soft patch exception not handled\n");
1958 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
1959 cpu_abort(cs
, "Maintenance exception while in user mode. "
1962 case POWERPC_EXCP_STOP
: /* stop translation */
1963 /* We did invalidate the instruction cache. Go on */
1965 case POWERPC_EXCP_BRANCH
: /* branch instruction: */
1966 /* We just stopped because of a branch. Go on */
1968 case POWERPC_EXCP_SYSCALL_USER
:
1969 /* system call in user-mode emulation */
1971 * PPC ABI uses overflow flag in cr0 to signal an error
1974 env
->crf
[0] &= ~0x1;
1975 ret
= do_syscall(env
, env
->gpr
[0], env
->gpr
[3], env
->gpr
[4],
1976 env
->gpr
[5], env
->gpr
[6], env
->gpr
[7],
1978 if (ret
== (target_ulong
)(-TARGET_QEMU_ESIGRETURN
)) {
1979 /* Returning from a successful sigreturn syscall.
1980 Avoid corrupting register state. */
1983 if (ret
> (target_ulong
)(-515)) {
1989 case POWERPC_EXCP_STCX
:
1990 if (do_store_exclusive(env
)) {
1991 info
.si_signo
= TARGET_SIGSEGV
;
1993 info
.si_code
= TARGET_SEGV_MAPERR
;
1994 info
._sifields
._sigfault
._addr
= env
->nip
;
1995 queue_signal(env
, info
.si_signo
, &info
);
2002 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2004 info
.si_signo
= sig
;
2006 info
.si_code
= TARGET_TRAP_BRKPT
;
2007 queue_signal(env
, info
.si_signo
, &info
);
2011 case EXCP_INTERRUPT
:
2012 /* just indicate that signals should be handled asap */
2015 cpu_abort(cs
, "Unknown exception 0x%d. Aborting\n", trapnr
);
2018 process_pending_signals(env
);
2025 # ifdef TARGET_ABI_MIPSO32
2026 # define MIPS_SYS(name, args) args,
2027 static const uint8_t mips_syscall_args
[] = {
2028 MIPS_SYS(sys_syscall
, 8) /* 4000 */
2029 MIPS_SYS(sys_exit
, 1)
2030 MIPS_SYS(sys_fork
, 0)
2031 MIPS_SYS(sys_read
, 3)
2032 MIPS_SYS(sys_write
, 3)
2033 MIPS_SYS(sys_open
, 3) /* 4005 */
2034 MIPS_SYS(sys_close
, 1)
2035 MIPS_SYS(sys_waitpid
, 3)
2036 MIPS_SYS(sys_creat
, 2)
2037 MIPS_SYS(sys_link
, 2)
2038 MIPS_SYS(sys_unlink
, 1) /* 4010 */
2039 MIPS_SYS(sys_execve
, 0)
2040 MIPS_SYS(sys_chdir
, 1)
2041 MIPS_SYS(sys_time
, 1)
2042 MIPS_SYS(sys_mknod
, 3)
2043 MIPS_SYS(sys_chmod
, 2) /* 4015 */
2044 MIPS_SYS(sys_lchown
, 3)
2045 MIPS_SYS(sys_ni_syscall
, 0)
2046 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_stat */
2047 MIPS_SYS(sys_lseek
, 3)
2048 MIPS_SYS(sys_getpid
, 0) /* 4020 */
2049 MIPS_SYS(sys_mount
, 5)
2050 MIPS_SYS(sys_umount
, 1)
2051 MIPS_SYS(sys_setuid
, 1)
2052 MIPS_SYS(sys_getuid
, 0)
2053 MIPS_SYS(sys_stime
, 1) /* 4025 */
2054 MIPS_SYS(sys_ptrace
, 4)
2055 MIPS_SYS(sys_alarm
, 1)
2056 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_fstat */
2057 MIPS_SYS(sys_pause
, 0)
2058 MIPS_SYS(sys_utime
, 2) /* 4030 */
2059 MIPS_SYS(sys_ni_syscall
, 0)
2060 MIPS_SYS(sys_ni_syscall
, 0)
2061 MIPS_SYS(sys_access
, 2)
2062 MIPS_SYS(sys_nice
, 1)
2063 MIPS_SYS(sys_ni_syscall
, 0) /* 4035 */
2064 MIPS_SYS(sys_sync
, 0)
2065 MIPS_SYS(sys_kill
, 2)
2066 MIPS_SYS(sys_rename
, 2)
2067 MIPS_SYS(sys_mkdir
, 2)
2068 MIPS_SYS(sys_rmdir
, 1) /* 4040 */
2069 MIPS_SYS(sys_dup
, 1)
2070 MIPS_SYS(sys_pipe
, 0)
2071 MIPS_SYS(sys_times
, 1)
2072 MIPS_SYS(sys_ni_syscall
, 0)
2073 MIPS_SYS(sys_brk
, 1) /* 4045 */
2074 MIPS_SYS(sys_setgid
, 1)
2075 MIPS_SYS(sys_getgid
, 0)
2076 MIPS_SYS(sys_ni_syscall
, 0) /* was signal(2) */
2077 MIPS_SYS(sys_geteuid
, 0)
2078 MIPS_SYS(sys_getegid
, 0) /* 4050 */
2079 MIPS_SYS(sys_acct
, 0)
2080 MIPS_SYS(sys_umount2
, 2)
2081 MIPS_SYS(sys_ni_syscall
, 0)
2082 MIPS_SYS(sys_ioctl
, 3)
2083 MIPS_SYS(sys_fcntl
, 3) /* 4055 */
2084 MIPS_SYS(sys_ni_syscall
, 2)
2085 MIPS_SYS(sys_setpgid
, 2)
2086 MIPS_SYS(sys_ni_syscall
, 0)
2087 MIPS_SYS(sys_olduname
, 1)
2088 MIPS_SYS(sys_umask
, 1) /* 4060 */
2089 MIPS_SYS(sys_chroot
, 1)
2090 MIPS_SYS(sys_ustat
, 2)
2091 MIPS_SYS(sys_dup2
, 2)
2092 MIPS_SYS(sys_getppid
, 0)
2093 MIPS_SYS(sys_getpgrp
, 0) /* 4065 */
2094 MIPS_SYS(sys_setsid
, 0)
2095 MIPS_SYS(sys_sigaction
, 3)
2096 MIPS_SYS(sys_sgetmask
, 0)
2097 MIPS_SYS(sys_ssetmask
, 1)
2098 MIPS_SYS(sys_setreuid
, 2) /* 4070 */
2099 MIPS_SYS(sys_setregid
, 2)
2100 MIPS_SYS(sys_sigsuspend
, 0)
2101 MIPS_SYS(sys_sigpending
, 1)
2102 MIPS_SYS(sys_sethostname
, 2)
2103 MIPS_SYS(sys_setrlimit
, 2) /* 4075 */
2104 MIPS_SYS(sys_getrlimit
, 2)
2105 MIPS_SYS(sys_getrusage
, 2)
2106 MIPS_SYS(sys_gettimeofday
, 2)
2107 MIPS_SYS(sys_settimeofday
, 2)
2108 MIPS_SYS(sys_getgroups
, 2) /* 4080 */
2109 MIPS_SYS(sys_setgroups
, 2)
2110 MIPS_SYS(sys_ni_syscall
, 0) /* old_select */
2111 MIPS_SYS(sys_symlink
, 2)
2112 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_lstat */
2113 MIPS_SYS(sys_readlink
, 3) /* 4085 */
2114 MIPS_SYS(sys_uselib
, 1)
2115 MIPS_SYS(sys_swapon
, 2)
2116 MIPS_SYS(sys_reboot
, 3)
2117 MIPS_SYS(old_readdir
, 3)
2118 MIPS_SYS(old_mmap
, 6) /* 4090 */
2119 MIPS_SYS(sys_munmap
, 2)
2120 MIPS_SYS(sys_truncate
, 2)
2121 MIPS_SYS(sys_ftruncate
, 2)
2122 MIPS_SYS(sys_fchmod
, 2)
2123 MIPS_SYS(sys_fchown
, 3) /* 4095 */
2124 MIPS_SYS(sys_getpriority
, 2)
2125 MIPS_SYS(sys_setpriority
, 3)
2126 MIPS_SYS(sys_ni_syscall
, 0)
2127 MIPS_SYS(sys_statfs
, 2)
2128 MIPS_SYS(sys_fstatfs
, 2) /* 4100 */
2129 MIPS_SYS(sys_ni_syscall
, 0) /* was ioperm(2) */
2130 MIPS_SYS(sys_socketcall
, 2)
2131 MIPS_SYS(sys_syslog
, 3)
2132 MIPS_SYS(sys_setitimer
, 3)
2133 MIPS_SYS(sys_getitimer
, 2) /* 4105 */
2134 MIPS_SYS(sys_newstat
, 2)
2135 MIPS_SYS(sys_newlstat
, 2)
2136 MIPS_SYS(sys_newfstat
, 2)
2137 MIPS_SYS(sys_uname
, 1)
2138 MIPS_SYS(sys_ni_syscall
, 0) /* 4110 was iopl(2) */
2139 MIPS_SYS(sys_vhangup
, 0)
2140 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_idle() */
2141 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_vm86 */
2142 MIPS_SYS(sys_wait4
, 4)
2143 MIPS_SYS(sys_swapoff
, 1) /* 4115 */
2144 MIPS_SYS(sys_sysinfo
, 1)
2145 MIPS_SYS(sys_ipc
, 6)
2146 MIPS_SYS(sys_fsync
, 1)
2147 MIPS_SYS(sys_sigreturn
, 0)
2148 MIPS_SYS(sys_clone
, 6) /* 4120 */
2149 MIPS_SYS(sys_setdomainname
, 2)
2150 MIPS_SYS(sys_newuname
, 1)
2151 MIPS_SYS(sys_ni_syscall
, 0) /* sys_modify_ldt */
2152 MIPS_SYS(sys_adjtimex
, 1)
2153 MIPS_SYS(sys_mprotect
, 3) /* 4125 */
2154 MIPS_SYS(sys_sigprocmask
, 3)
2155 MIPS_SYS(sys_ni_syscall
, 0) /* was create_module */
2156 MIPS_SYS(sys_init_module
, 5)
2157 MIPS_SYS(sys_delete_module
, 1)
2158 MIPS_SYS(sys_ni_syscall
, 0) /* 4130 was get_kernel_syms */
2159 MIPS_SYS(sys_quotactl
, 0)
2160 MIPS_SYS(sys_getpgid
, 1)
2161 MIPS_SYS(sys_fchdir
, 1)
2162 MIPS_SYS(sys_bdflush
, 2)
2163 MIPS_SYS(sys_sysfs
, 3) /* 4135 */
2164 MIPS_SYS(sys_personality
, 1)
2165 MIPS_SYS(sys_ni_syscall
, 0) /* for afs_syscall */
2166 MIPS_SYS(sys_setfsuid
, 1)
2167 MIPS_SYS(sys_setfsgid
, 1)
2168 MIPS_SYS(sys_llseek
, 5) /* 4140 */
2169 MIPS_SYS(sys_getdents
, 3)
2170 MIPS_SYS(sys_select
, 5)
2171 MIPS_SYS(sys_flock
, 2)
2172 MIPS_SYS(sys_msync
, 3)
2173 MIPS_SYS(sys_readv
, 3) /* 4145 */
2174 MIPS_SYS(sys_writev
, 3)
2175 MIPS_SYS(sys_cacheflush
, 3)
2176 MIPS_SYS(sys_cachectl
, 3)
2177 MIPS_SYS(sys_sysmips
, 4)
2178 MIPS_SYS(sys_ni_syscall
, 0) /* 4150 */
2179 MIPS_SYS(sys_getsid
, 1)
2180 MIPS_SYS(sys_fdatasync
, 0)
2181 MIPS_SYS(sys_sysctl
, 1)
2182 MIPS_SYS(sys_mlock
, 2)
2183 MIPS_SYS(sys_munlock
, 2) /* 4155 */
2184 MIPS_SYS(sys_mlockall
, 1)
2185 MIPS_SYS(sys_munlockall
, 0)
2186 MIPS_SYS(sys_sched_setparam
, 2)
2187 MIPS_SYS(sys_sched_getparam
, 2)
2188 MIPS_SYS(sys_sched_setscheduler
, 3) /* 4160 */
2189 MIPS_SYS(sys_sched_getscheduler
, 1)
2190 MIPS_SYS(sys_sched_yield
, 0)
2191 MIPS_SYS(sys_sched_get_priority_max
, 1)
2192 MIPS_SYS(sys_sched_get_priority_min
, 1)
2193 MIPS_SYS(sys_sched_rr_get_interval
, 2) /* 4165 */
2194 MIPS_SYS(sys_nanosleep
, 2)
2195 MIPS_SYS(sys_mremap
, 5)
2196 MIPS_SYS(sys_accept
, 3)
2197 MIPS_SYS(sys_bind
, 3)
2198 MIPS_SYS(sys_connect
, 3) /* 4170 */
2199 MIPS_SYS(sys_getpeername
, 3)
2200 MIPS_SYS(sys_getsockname
, 3)
2201 MIPS_SYS(sys_getsockopt
, 5)
2202 MIPS_SYS(sys_listen
, 2)
2203 MIPS_SYS(sys_recv
, 4) /* 4175 */
2204 MIPS_SYS(sys_recvfrom
, 6)
2205 MIPS_SYS(sys_recvmsg
, 3)
2206 MIPS_SYS(sys_send
, 4)
2207 MIPS_SYS(sys_sendmsg
, 3)
2208 MIPS_SYS(sys_sendto
, 6) /* 4180 */
2209 MIPS_SYS(sys_setsockopt
, 5)
2210 MIPS_SYS(sys_shutdown
, 2)
2211 MIPS_SYS(sys_socket
, 3)
2212 MIPS_SYS(sys_socketpair
, 4)
2213 MIPS_SYS(sys_setresuid
, 3) /* 4185 */
2214 MIPS_SYS(sys_getresuid
, 3)
2215 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_query_module */
2216 MIPS_SYS(sys_poll
, 3)
2217 MIPS_SYS(sys_nfsservctl
, 3)
2218 MIPS_SYS(sys_setresgid
, 3) /* 4190 */
2219 MIPS_SYS(sys_getresgid
, 3)
2220 MIPS_SYS(sys_prctl
, 5)
2221 MIPS_SYS(sys_rt_sigreturn
, 0)
2222 MIPS_SYS(sys_rt_sigaction
, 4)
2223 MIPS_SYS(sys_rt_sigprocmask
, 4) /* 4195 */
2224 MIPS_SYS(sys_rt_sigpending
, 2)
2225 MIPS_SYS(sys_rt_sigtimedwait
, 4)
2226 MIPS_SYS(sys_rt_sigqueueinfo
, 3)
2227 MIPS_SYS(sys_rt_sigsuspend
, 0)
2228 MIPS_SYS(sys_pread64
, 6) /* 4200 */
2229 MIPS_SYS(sys_pwrite64
, 6)
2230 MIPS_SYS(sys_chown
, 3)
2231 MIPS_SYS(sys_getcwd
, 2)
2232 MIPS_SYS(sys_capget
, 2)
2233 MIPS_SYS(sys_capset
, 2) /* 4205 */
2234 MIPS_SYS(sys_sigaltstack
, 2)
2235 MIPS_SYS(sys_sendfile
, 4)
2236 MIPS_SYS(sys_ni_syscall
, 0)
2237 MIPS_SYS(sys_ni_syscall
, 0)
2238 MIPS_SYS(sys_mmap2
, 6) /* 4210 */
2239 MIPS_SYS(sys_truncate64
, 4)
2240 MIPS_SYS(sys_ftruncate64
, 4)
2241 MIPS_SYS(sys_stat64
, 2)
2242 MIPS_SYS(sys_lstat64
, 2)
2243 MIPS_SYS(sys_fstat64
, 2) /* 4215 */
2244 MIPS_SYS(sys_pivot_root
, 2)
2245 MIPS_SYS(sys_mincore
, 3)
2246 MIPS_SYS(sys_madvise
, 3)
2247 MIPS_SYS(sys_getdents64
, 3)
2248 MIPS_SYS(sys_fcntl64
, 3) /* 4220 */
2249 MIPS_SYS(sys_ni_syscall
, 0)
2250 MIPS_SYS(sys_gettid
, 0)
2251 MIPS_SYS(sys_readahead
, 5)
2252 MIPS_SYS(sys_setxattr
, 5)
2253 MIPS_SYS(sys_lsetxattr
, 5) /* 4225 */
2254 MIPS_SYS(sys_fsetxattr
, 5)
2255 MIPS_SYS(sys_getxattr
, 4)
2256 MIPS_SYS(sys_lgetxattr
, 4)
2257 MIPS_SYS(sys_fgetxattr
, 4)
2258 MIPS_SYS(sys_listxattr
, 3) /* 4230 */
2259 MIPS_SYS(sys_llistxattr
, 3)
2260 MIPS_SYS(sys_flistxattr
, 3)
2261 MIPS_SYS(sys_removexattr
, 2)
2262 MIPS_SYS(sys_lremovexattr
, 2)
2263 MIPS_SYS(sys_fremovexattr
, 2) /* 4235 */
2264 MIPS_SYS(sys_tkill
, 2)
2265 MIPS_SYS(sys_sendfile64
, 5)
2266 MIPS_SYS(sys_futex
, 6)
2267 MIPS_SYS(sys_sched_setaffinity
, 3)
2268 MIPS_SYS(sys_sched_getaffinity
, 3) /* 4240 */
2269 MIPS_SYS(sys_io_setup
, 2)
2270 MIPS_SYS(sys_io_destroy
, 1)
2271 MIPS_SYS(sys_io_getevents
, 5)
2272 MIPS_SYS(sys_io_submit
, 3)
2273 MIPS_SYS(sys_io_cancel
, 3) /* 4245 */
2274 MIPS_SYS(sys_exit_group
, 1)
2275 MIPS_SYS(sys_lookup_dcookie
, 3)
2276 MIPS_SYS(sys_epoll_create
, 1)
2277 MIPS_SYS(sys_epoll_ctl
, 4)
2278 MIPS_SYS(sys_epoll_wait
, 3) /* 4250 */
2279 MIPS_SYS(sys_remap_file_pages
, 5)
2280 MIPS_SYS(sys_set_tid_address
, 1)
2281 MIPS_SYS(sys_restart_syscall
, 0)
2282 MIPS_SYS(sys_fadvise64_64
, 7)
2283 MIPS_SYS(sys_statfs64
, 3) /* 4255 */
2284 MIPS_SYS(sys_fstatfs64
, 2)
2285 MIPS_SYS(sys_timer_create
, 3)
2286 MIPS_SYS(sys_timer_settime
, 4)
2287 MIPS_SYS(sys_timer_gettime
, 2)
2288 MIPS_SYS(sys_timer_getoverrun
, 1) /* 4260 */
2289 MIPS_SYS(sys_timer_delete
, 1)
2290 MIPS_SYS(sys_clock_settime
, 2)
2291 MIPS_SYS(sys_clock_gettime
, 2)
2292 MIPS_SYS(sys_clock_getres
, 2)
2293 MIPS_SYS(sys_clock_nanosleep
, 4) /* 4265 */
2294 MIPS_SYS(sys_tgkill
, 3)
2295 MIPS_SYS(sys_utimes
, 2)
2296 MIPS_SYS(sys_mbind
, 4)
2297 MIPS_SYS(sys_ni_syscall
, 0) /* sys_get_mempolicy */
2298 MIPS_SYS(sys_ni_syscall
, 0) /* 4270 sys_set_mempolicy */
2299 MIPS_SYS(sys_mq_open
, 4)
2300 MIPS_SYS(sys_mq_unlink
, 1)
2301 MIPS_SYS(sys_mq_timedsend
, 5)
2302 MIPS_SYS(sys_mq_timedreceive
, 5)
2303 MIPS_SYS(sys_mq_notify
, 2) /* 4275 */
2304 MIPS_SYS(sys_mq_getsetattr
, 3)
2305 MIPS_SYS(sys_ni_syscall
, 0) /* sys_vserver */
2306 MIPS_SYS(sys_waitid
, 4)
2307 MIPS_SYS(sys_ni_syscall
, 0) /* available, was setaltroot */
2308 MIPS_SYS(sys_add_key
, 5)
2309 MIPS_SYS(sys_request_key
, 4)
2310 MIPS_SYS(sys_keyctl
, 5)
2311 MIPS_SYS(sys_set_thread_area
, 1)
2312 MIPS_SYS(sys_inotify_init
, 0)
2313 MIPS_SYS(sys_inotify_add_watch
, 3) /* 4285 */
2314 MIPS_SYS(sys_inotify_rm_watch
, 2)
2315 MIPS_SYS(sys_migrate_pages
, 4)
2316 MIPS_SYS(sys_openat
, 4)
2317 MIPS_SYS(sys_mkdirat
, 3)
2318 MIPS_SYS(sys_mknodat
, 4) /* 4290 */
2319 MIPS_SYS(sys_fchownat
, 5)
2320 MIPS_SYS(sys_futimesat
, 3)
2321 MIPS_SYS(sys_fstatat64
, 4)
2322 MIPS_SYS(sys_unlinkat
, 3)
2323 MIPS_SYS(sys_renameat
, 4) /* 4295 */
2324 MIPS_SYS(sys_linkat
, 5)
2325 MIPS_SYS(sys_symlinkat
, 3)
2326 MIPS_SYS(sys_readlinkat
, 4)
2327 MIPS_SYS(sys_fchmodat
, 3)
2328 MIPS_SYS(sys_faccessat
, 3) /* 4300 */
2329 MIPS_SYS(sys_pselect6
, 6)
2330 MIPS_SYS(sys_ppoll
, 5)
2331 MIPS_SYS(sys_unshare
, 1)
2332 MIPS_SYS(sys_splice
, 6)
2333 MIPS_SYS(sys_sync_file_range
, 7) /* 4305 */
2334 MIPS_SYS(sys_tee
, 4)
2335 MIPS_SYS(sys_vmsplice
, 4)
2336 MIPS_SYS(sys_move_pages
, 6)
2337 MIPS_SYS(sys_set_robust_list
, 2)
2338 MIPS_SYS(sys_get_robust_list
, 3) /* 4310 */
2339 MIPS_SYS(sys_kexec_load
, 4)
2340 MIPS_SYS(sys_getcpu
, 3)
2341 MIPS_SYS(sys_epoll_pwait
, 6)
2342 MIPS_SYS(sys_ioprio_set
, 3)
2343 MIPS_SYS(sys_ioprio_get
, 2)
2344 MIPS_SYS(sys_utimensat
, 4)
2345 MIPS_SYS(sys_signalfd
, 3)
2346 MIPS_SYS(sys_ni_syscall
, 0) /* was timerfd */
2347 MIPS_SYS(sys_eventfd
, 1)
2348 MIPS_SYS(sys_fallocate
, 6) /* 4320 */
2349 MIPS_SYS(sys_timerfd_create
, 2)
2350 MIPS_SYS(sys_timerfd_gettime
, 2)
2351 MIPS_SYS(sys_timerfd_settime
, 4)
2352 MIPS_SYS(sys_signalfd4
, 4)
2353 MIPS_SYS(sys_eventfd2
, 2) /* 4325 */
2354 MIPS_SYS(sys_epoll_create1
, 1)
2355 MIPS_SYS(sys_dup3
, 3)
2356 MIPS_SYS(sys_pipe2
, 2)
2357 MIPS_SYS(sys_inotify_init1
, 1)
2358 MIPS_SYS(sys_preadv
, 6) /* 4330 */
2359 MIPS_SYS(sys_pwritev
, 6)
2360 MIPS_SYS(sys_rt_tgsigqueueinfo
, 4)
2361 MIPS_SYS(sys_perf_event_open
, 5)
2362 MIPS_SYS(sys_accept4
, 4)
2363 MIPS_SYS(sys_recvmmsg
, 5) /* 4335 */
2364 MIPS_SYS(sys_fanotify_init
, 2)
2365 MIPS_SYS(sys_fanotify_mark
, 6)
2366 MIPS_SYS(sys_prlimit64
, 4)
2367 MIPS_SYS(sys_name_to_handle_at
, 5)
2368 MIPS_SYS(sys_open_by_handle_at
, 3) /* 4340 */
2369 MIPS_SYS(sys_clock_adjtime
, 2)
2370 MIPS_SYS(sys_syncfs
, 1)
2375 static int do_store_exclusive(CPUMIPSState
*env
)
2378 target_ulong page_addr
;
2386 page_addr
= addr
& TARGET_PAGE_MASK
;
2389 flags
= page_get_flags(page_addr
);
2390 if ((flags
& PAGE_READ
) == 0) {
2393 reg
= env
->llreg
& 0x1f;
2394 d
= (env
->llreg
& 0x20) != 0;
2396 segv
= get_user_s64(val
, addr
);
2398 segv
= get_user_s32(val
, addr
);
2401 if (val
!= env
->llval
) {
2402 env
->active_tc
.gpr
[reg
] = 0;
2405 segv
= put_user_u64(env
->llnewval
, addr
);
2407 segv
= put_user_u32(env
->llnewval
, addr
);
2410 env
->active_tc
.gpr
[reg
] = 1;
2417 env
->active_tc
.PC
+= 4;
2430 static int do_break(CPUMIPSState
*env
, target_siginfo_t
*info
,
2438 info
->si_signo
= TARGET_SIGFPE
;
2440 info
->si_code
= (code
== BRK_OVERFLOW
) ? FPE_INTOVF
: FPE_INTDIV
;
2441 queue_signal(env
, info
->si_signo
, &*info
);
2445 info
->si_signo
= TARGET_SIGTRAP
;
2447 queue_signal(env
, info
->si_signo
, &*info
);
2455 void cpu_loop(CPUMIPSState
*env
)
2457 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2458 target_siginfo_t info
;
2461 # ifdef TARGET_ABI_MIPSO32
2462 unsigned int syscall_num
;
2467 trapnr
= cpu_mips_exec(env
);
2471 env
->active_tc
.PC
+= 4;
2472 # ifdef TARGET_ABI_MIPSO32
2473 syscall_num
= env
->active_tc
.gpr
[2] - 4000;
2474 if (syscall_num
>= sizeof(mips_syscall_args
)) {
2475 ret
= -TARGET_ENOSYS
;
2479 abi_ulong arg5
= 0, arg6
= 0, arg7
= 0, arg8
= 0;
2481 nb_args
= mips_syscall_args
[syscall_num
];
2482 sp_reg
= env
->active_tc
.gpr
[29];
2484 /* these arguments are taken from the stack */
2486 if ((ret
= get_user_ual(arg8
, sp_reg
+ 28)) != 0) {
2490 if ((ret
= get_user_ual(arg7
, sp_reg
+ 24)) != 0) {
2494 if ((ret
= get_user_ual(arg6
, sp_reg
+ 20)) != 0) {
2498 if ((ret
= get_user_ual(arg5
, sp_reg
+ 16)) != 0) {
2504 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2505 env
->active_tc
.gpr
[4],
2506 env
->active_tc
.gpr
[5],
2507 env
->active_tc
.gpr
[6],
2508 env
->active_tc
.gpr
[7],
2509 arg5
, arg6
, arg7
, arg8
);
2513 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2514 env
->active_tc
.gpr
[4], env
->active_tc
.gpr
[5],
2515 env
->active_tc
.gpr
[6], env
->active_tc
.gpr
[7],
2516 env
->active_tc
.gpr
[8], env
->active_tc
.gpr
[9],
2517 env
->active_tc
.gpr
[10], env
->active_tc
.gpr
[11]);
2519 if (ret
== -TARGET_QEMU_ESIGRETURN
) {
2520 /* Returning from a successful sigreturn syscall.
2521 Avoid clobbering register state. */
2524 if ((abi_ulong
)ret
>= (abi_ulong
)-1133) {
2525 env
->active_tc
.gpr
[7] = 1; /* error flag */
2528 env
->active_tc
.gpr
[7] = 0; /* error flag */
2530 env
->active_tc
.gpr
[2] = ret
;
2536 info
.si_signo
= TARGET_SIGSEGV
;
2538 /* XXX: check env->error_code */
2539 info
.si_code
= TARGET_SEGV_MAPERR
;
2540 info
._sifields
._sigfault
._addr
= env
->CP0_BadVAddr
;
2541 queue_signal(env
, info
.si_signo
, &info
);
2545 info
.si_signo
= TARGET_SIGILL
;
2548 queue_signal(env
, info
.si_signo
, &info
);
2550 case EXCP_INTERRUPT
:
2551 /* just indicate that signals should be handled asap */
2557 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2560 info
.si_signo
= sig
;
2562 info
.si_code
= TARGET_TRAP_BRKPT
;
2563 queue_signal(env
, info
.si_signo
, &info
);
2568 if (do_store_exclusive(env
)) {
2569 info
.si_signo
= TARGET_SIGSEGV
;
2571 info
.si_code
= TARGET_SEGV_MAPERR
;
2572 info
._sifields
._sigfault
._addr
= env
->active_tc
.PC
;
2573 queue_signal(env
, info
.si_signo
, &info
);
2577 info
.si_signo
= TARGET_SIGILL
;
2579 info
.si_code
= TARGET_ILL_ILLOPC
;
2580 queue_signal(env
, info
.si_signo
, &info
);
2582 /* The code below was inspired by the MIPS Linux kernel trap
2583 * handling code in arch/mips/kernel/traps.c.
2587 abi_ulong trap_instr
;
2590 if (env
->hflags
& MIPS_HFLAG_M16
) {
2591 if (env
->insn_flags
& ASE_MICROMIPS
) {
2592 /* microMIPS mode */
2593 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2598 if ((trap_instr
>> 10) == 0x11) {
2599 /* 16-bit instruction */
2600 code
= trap_instr
& 0xf;
2602 /* 32-bit instruction */
2605 ret
= get_user_u16(instr_lo
,
2606 env
->active_tc
.PC
+ 2);
2610 trap_instr
= (trap_instr
<< 16) | instr_lo
;
2611 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2612 /* Unfortunately, microMIPS also suffers from
2613 the old assembler bug... */
2614 if (code
>= (1 << 10)) {
2620 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2624 code
= (trap_instr
>> 6) & 0x3f;
2627 ret
= get_user_ual(trap_instr
, env
->active_tc
.PC
);
2632 /* As described in the original Linux kernel code, the
2633 * below checks on 'code' are to work around an old
2636 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2637 if (code
>= (1 << 10)) {
2642 if (do_break(env
, &info
, code
) != 0) {
2649 abi_ulong trap_instr
;
2650 unsigned int code
= 0;
2652 if (env
->hflags
& MIPS_HFLAG_M16
) {
2653 /* microMIPS mode */
2656 ret
= get_user_u16(instr
[0], env
->active_tc
.PC
) ||
2657 get_user_u16(instr
[1], env
->active_tc
.PC
+ 2);
2659 trap_instr
= (instr
[0] << 16) | instr
[1];
2661 ret
= get_user_ual(trap_instr
, env
->active_tc
.PC
);
2668 /* The immediate versions don't provide a code. */
2669 if (!(trap_instr
& 0xFC000000)) {
2670 if (env
->hflags
& MIPS_HFLAG_M16
) {
2671 /* microMIPS mode */
2672 code
= ((trap_instr
>> 12) & ((1 << 4) - 1));
2674 code
= ((trap_instr
>> 6) & ((1 << 10) - 1));
2678 if (do_break(env
, &info
, code
) != 0) {
2685 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
2687 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2690 process_pending_signals(env
);
2695 #ifdef TARGET_OPENRISC
2697 void cpu_loop(CPUOpenRISCState
*env
)
2699 CPUState
*cs
= CPU(openrisc_env_get_cpu(env
));
2704 trapnr
= cpu_exec(env
);
2710 qemu_log("\nReset request, exit, pc is %#x\n", env
->pc
);
2714 qemu_log("\nBus error, exit, pc is %#x\n", env
->pc
);
2715 gdbsig
= TARGET_SIGBUS
;
2719 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2720 gdbsig
= TARGET_SIGSEGV
;
2723 qemu_log("\nTick time interrupt pc is %#x\n", env
->pc
);
2726 qemu_log("\nAlignment pc is %#x\n", env
->pc
);
2727 gdbsig
= TARGET_SIGBUS
;
2730 qemu_log("\nIllegal instructionpc is %#x\n", env
->pc
);
2731 gdbsig
= TARGET_SIGILL
;
2734 qemu_log("\nExternal interruptpc is %#x\n", env
->pc
);
2738 qemu_log("\nTLB miss\n");
2741 qemu_log("\nRange\n");
2742 gdbsig
= TARGET_SIGSEGV
;
2745 env
->pc
+= 4; /* 0xc00; */
2746 env
->gpr
[11] = do_syscall(env
,
2747 env
->gpr
[11], /* return value */
2748 env
->gpr
[3], /* r3 - r7 are params */
2756 qemu_log("\nFloating point error\n");
2759 qemu_log("\nTrap\n");
2760 gdbsig
= TARGET_SIGTRAP
;
2766 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2768 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2769 gdbsig
= TARGET_SIGILL
;
2773 gdb_handlesig(cs
, gdbsig
);
2774 if (gdbsig
!= TARGET_SIGTRAP
) {
2779 process_pending_signals(env
);
2783 #endif /* TARGET_OPENRISC */
2786 void cpu_loop(CPUSH4State
*env
)
2788 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
2790 target_siginfo_t info
;
2794 trapnr
= cpu_sh4_exec (env
);
2800 ret
= do_syscall(env
,
2809 env
->gregs
[0] = ret
;
2811 case EXCP_INTERRUPT
:
2812 /* just indicate that signals should be handled asap */
2818 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2821 info
.si_signo
= sig
;
2823 info
.si_code
= TARGET_TRAP_BRKPT
;
2824 queue_signal(env
, info
.si_signo
, &info
);
2830 info
.si_signo
= TARGET_SIGSEGV
;
2832 info
.si_code
= TARGET_SEGV_MAPERR
;
2833 info
._sifields
._sigfault
._addr
= env
->tea
;
2834 queue_signal(env
, info
.si_signo
, &info
);
2838 printf ("Unhandled trap: 0x%x\n", trapnr
);
2839 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2842 process_pending_signals (env
);
2848 void cpu_loop(CPUCRISState
*env
)
2850 CPUState
*cs
= CPU(cris_env_get_cpu(env
));
2852 target_siginfo_t info
;
2856 trapnr
= cpu_cris_exec (env
);
2861 info
.si_signo
= TARGET_SIGSEGV
;
2863 /* XXX: check env->error_code */
2864 info
.si_code
= TARGET_SEGV_MAPERR
;
2865 info
._sifields
._sigfault
._addr
= env
->pregs
[PR_EDA
];
2866 queue_signal(env
, info
.si_signo
, &info
);
2869 case EXCP_INTERRUPT
:
2870 /* just indicate that signals should be handled asap */
2873 ret
= do_syscall(env
,
2882 env
->regs
[10] = ret
;
2888 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2891 info
.si_signo
= sig
;
2893 info
.si_code
= TARGET_TRAP_BRKPT
;
2894 queue_signal(env
, info
.si_signo
, &info
);
2899 printf ("Unhandled trap: 0x%x\n", trapnr
);
2900 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2903 process_pending_signals (env
);
2908 #ifdef TARGET_MICROBLAZE
2909 void cpu_loop(CPUMBState
*env
)
2911 CPUState
*cs
= CPU(mb_env_get_cpu(env
));
2913 target_siginfo_t info
;
2917 trapnr
= cpu_mb_exec (env
);
2922 info
.si_signo
= TARGET_SIGSEGV
;
2924 /* XXX: check env->error_code */
2925 info
.si_code
= TARGET_SEGV_MAPERR
;
2926 info
._sifields
._sigfault
._addr
= 0;
2927 queue_signal(env
, info
.si_signo
, &info
);
2930 case EXCP_INTERRUPT
:
2931 /* just indicate that signals should be handled asap */
2934 /* Return address is 4 bytes after the call. */
2936 env
->sregs
[SR_PC
] = env
->regs
[14];
2937 ret
= do_syscall(env
,
2949 env
->regs
[17] = env
->sregs
[SR_PC
] + 4;
2950 if (env
->iflags
& D_FLAG
) {
2951 env
->sregs
[SR_ESR
] |= 1 << 12;
2952 env
->sregs
[SR_PC
] -= 4;
2953 /* FIXME: if branch was immed, replay the imm as well. */
2956 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
2958 switch (env
->sregs
[SR_ESR
] & 31) {
2959 case ESR_EC_DIVZERO
:
2960 info
.si_signo
= TARGET_SIGFPE
;
2962 info
.si_code
= TARGET_FPE_FLTDIV
;
2963 info
._sifields
._sigfault
._addr
= 0;
2964 queue_signal(env
, info
.si_signo
, &info
);
2967 info
.si_signo
= TARGET_SIGFPE
;
2969 if (env
->sregs
[SR_FSR
] & FSR_IO
) {
2970 info
.si_code
= TARGET_FPE_FLTINV
;
2972 if (env
->sregs
[SR_FSR
] & FSR_DZ
) {
2973 info
.si_code
= TARGET_FPE_FLTDIV
;
2975 info
._sifields
._sigfault
._addr
= 0;
2976 queue_signal(env
, info
.si_signo
, &info
);
2979 printf ("Unhandled hw-exception: 0x%x\n",
2980 env
->sregs
[SR_ESR
] & ESR_EC_MASK
);
2981 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2990 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2993 info
.si_signo
= sig
;
2995 info
.si_code
= TARGET_TRAP_BRKPT
;
2996 queue_signal(env
, info
.si_signo
, &info
);
3001 printf ("Unhandled trap: 0x%x\n", trapnr
);
3002 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3005 process_pending_signals (env
);
3012 void cpu_loop(CPUM68KState
*env
)
3014 CPUState
*cs
= CPU(m68k_env_get_cpu(env
));
3017 target_siginfo_t info
;
3018 TaskState
*ts
= cs
->opaque
;
3022 trapnr
= cpu_m68k_exec(env
);
3027 if (ts
->sim_syscalls
) {
3029 get_user_u16(nr
, env
->pc
+ 2);
3031 do_m68k_simcall(env
, nr
);
3037 case EXCP_HALT_INSN
:
3038 /* Semihosing syscall. */
3040 do_m68k_semihosting(env
, env
->dregs
[0]);
3044 case EXCP_UNSUPPORTED
:
3046 info
.si_signo
= TARGET_SIGILL
;
3048 info
.si_code
= TARGET_ILL_ILLOPN
;
3049 info
._sifields
._sigfault
._addr
= env
->pc
;
3050 queue_signal(env
, info
.si_signo
, &info
);
3054 ts
->sim_syscalls
= 0;
3057 env
->dregs
[0] = do_syscall(env
,
3068 case EXCP_INTERRUPT
:
3069 /* just indicate that signals should be handled asap */
3073 info
.si_signo
= TARGET_SIGSEGV
;
3075 /* XXX: check env->error_code */
3076 info
.si_code
= TARGET_SEGV_MAPERR
;
3077 info
._sifields
._sigfault
._addr
= env
->mmu
.ar
;
3078 queue_signal(env
, info
.si_signo
, &info
);
3085 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3088 info
.si_signo
= sig
;
3090 info
.si_code
= TARGET_TRAP_BRKPT
;
3091 queue_signal(env
, info
.si_signo
, &info
);
3096 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
3098 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3101 process_pending_signals(env
);
3104 #endif /* TARGET_M68K */
3107 static void do_store_exclusive(CPUAlphaState
*env
, int reg
, int quad
)
3109 target_ulong addr
, val
, tmp
;
3110 target_siginfo_t info
;
3113 addr
= env
->lock_addr
;
3114 tmp
= env
->lock_st_addr
;
3115 env
->lock_addr
= -1;
3116 env
->lock_st_addr
= 0;
3122 if (quad
? get_user_s64(val
, addr
) : get_user_s32(val
, addr
)) {
3126 if (val
== env
->lock_value
) {
3128 if (quad
? put_user_u64(tmp
, addr
) : put_user_u32(tmp
, addr
)) {
3145 info
.si_signo
= TARGET_SIGSEGV
;
3147 info
.si_code
= TARGET_SEGV_MAPERR
;
3148 info
._sifields
._sigfault
._addr
= addr
;
3149 queue_signal(env
, TARGET_SIGSEGV
, &info
);
3152 void cpu_loop(CPUAlphaState
*env
)
3154 CPUState
*cs
= CPU(alpha_env_get_cpu(env
));
3156 target_siginfo_t info
;
3161 trapnr
= cpu_alpha_exec (env
);
3164 /* All of the traps imply a transition through PALcode, which
3165 implies an REI instruction has been executed. Which means
3166 that the intr_flag should be cleared. */
3171 fprintf(stderr
, "Reset requested. Exit\n");
3175 fprintf(stderr
, "Machine check exception. Exit\n");
3178 case EXCP_SMP_INTERRUPT
:
3179 case EXCP_CLK_INTERRUPT
:
3180 case EXCP_DEV_INTERRUPT
:
3181 fprintf(stderr
, "External interrupt. Exit\n");
3185 env
->lock_addr
= -1;
3186 info
.si_signo
= TARGET_SIGSEGV
;
3188 info
.si_code
= (page_get_flags(env
->trap_arg0
) & PAGE_VALID
3189 ? TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
);
3190 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3191 queue_signal(env
, info
.si_signo
, &info
);
3194 env
->lock_addr
= -1;
3195 info
.si_signo
= TARGET_SIGBUS
;
3197 info
.si_code
= TARGET_BUS_ADRALN
;
3198 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3199 queue_signal(env
, info
.si_signo
, &info
);
3203 env
->lock_addr
= -1;
3204 info
.si_signo
= TARGET_SIGILL
;
3206 info
.si_code
= TARGET_ILL_ILLOPC
;
3207 info
._sifields
._sigfault
._addr
= env
->pc
;
3208 queue_signal(env
, info
.si_signo
, &info
);
3211 env
->lock_addr
= -1;
3212 info
.si_signo
= TARGET_SIGFPE
;
3214 info
.si_code
= TARGET_FPE_FLTINV
;
3215 info
._sifields
._sigfault
._addr
= env
->pc
;
3216 queue_signal(env
, info
.si_signo
, &info
);
3219 /* No-op. Linux simply re-enables the FPU. */
3222 env
->lock_addr
= -1;
3223 switch (env
->error_code
) {
3226 info
.si_signo
= TARGET_SIGTRAP
;
3228 info
.si_code
= TARGET_TRAP_BRKPT
;
3229 info
._sifields
._sigfault
._addr
= env
->pc
;
3230 queue_signal(env
, info
.si_signo
, &info
);
3234 info
.si_signo
= TARGET_SIGTRAP
;
3237 info
._sifields
._sigfault
._addr
= env
->pc
;
3238 queue_signal(env
, info
.si_signo
, &info
);
3242 trapnr
= env
->ir
[IR_V0
];
3243 sysret
= do_syscall(env
, trapnr
,
3244 env
->ir
[IR_A0
], env
->ir
[IR_A1
],
3245 env
->ir
[IR_A2
], env
->ir
[IR_A3
],
3246 env
->ir
[IR_A4
], env
->ir
[IR_A5
],
3248 if (trapnr
== TARGET_NR_sigreturn
3249 || trapnr
== TARGET_NR_rt_sigreturn
) {
3252 /* Syscall writes 0 to V0 to bypass error check, similar
3253 to how this is handled internal to Linux kernel.
3254 (Ab)use trapnr temporarily as boolean indicating error. */
3255 trapnr
= (env
->ir
[IR_V0
] != 0 && sysret
< 0);
3256 env
->ir
[IR_V0
] = (trapnr
? -sysret
: sysret
);
3257 env
->ir
[IR_A3
] = trapnr
;
3261 /* ??? We can probably elide the code using page_unprotect
3262 that is checking for self-modifying code. Instead we
3263 could simply call tb_flush here. Until we work out the
3264 changes required to turn off the extra write protection,
3265 this can be a no-op. */
3269 /* Handled in the translator for usermode. */
3273 /* Handled in the translator for usermode. */
3277 info
.si_signo
= TARGET_SIGFPE
;
3278 switch (env
->ir
[IR_A0
]) {
3279 case TARGET_GEN_INTOVF
:
3280 info
.si_code
= TARGET_FPE_INTOVF
;
3282 case TARGET_GEN_INTDIV
:
3283 info
.si_code
= TARGET_FPE_INTDIV
;
3285 case TARGET_GEN_FLTOVF
:
3286 info
.si_code
= TARGET_FPE_FLTOVF
;
3288 case TARGET_GEN_FLTUND
:
3289 info
.si_code
= TARGET_FPE_FLTUND
;
3291 case TARGET_GEN_FLTINV
:
3292 info
.si_code
= TARGET_FPE_FLTINV
;
3294 case TARGET_GEN_FLTINE
:
3295 info
.si_code
= TARGET_FPE_FLTRES
;
3297 case TARGET_GEN_ROPRAND
:
3301 info
.si_signo
= TARGET_SIGTRAP
;
3306 info
._sifields
._sigfault
._addr
= env
->pc
;
3307 queue_signal(env
, info
.si_signo
, &info
);
3314 info
.si_signo
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3315 if (info
.si_signo
) {
3316 env
->lock_addr
= -1;
3318 info
.si_code
= TARGET_TRAP_BRKPT
;
3319 queue_signal(env
, info
.si_signo
, &info
);
3324 do_store_exclusive(env
, env
->error_code
, trapnr
- EXCP_STL_C
);
3326 case EXCP_INTERRUPT
:
3327 /* Just indicate that signals should be handled asap. */
3330 printf ("Unhandled trap: 0x%x\n", trapnr
);
3331 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3334 process_pending_signals (env
);
3337 #endif /* TARGET_ALPHA */
3340 void cpu_loop(CPUS390XState
*env
)
3342 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
3344 target_siginfo_t info
;
3349 trapnr
= cpu_s390x_exec(env
);
3352 case EXCP_INTERRUPT
:
3353 /* Just indicate that signals should be handled asap. */
3357 n
= env
->int_svc_code
;
3359 /* syscalls > 255 */
3362 env
->psw
.addr
+= env
->int_svc_ilen
;
3363 env
->regs
[2] = do_syscall(env
, n
, env
->regs
[2], env
->regs
[3],
3364 env
->regs
[4], env
->regs
[5],
3365 env
->regs
[6], env
->regs
[7], 0, 0);
3369 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3371 n
= TARGET_TRAP_BRKPT
;
3376 n
= env
->int_pgm_code
;
3379 case PGM_PRIVILEGED
:
3380 sig
= TARGET_SIGILL
;
3381 n
= TARGET_ILL_ILLOPC
;
3383 case PGM_PROTECTION
:
3384 case PGM_ADDRESSING
:
3385 sig
= TARGET_SIGSEGV
;
3386 /* XXX: check env->error_code */
3387 n
= TARGET_SEGV_MAPERR
;
3388 addr
= env
->__excp_addr
;
3391 case PGM_SPECIFICATION
:
3392 case PGM_SPECIAL_OP
:
3395 sig
= TARGET_SIGILL
;
3396 n
= TARGET_ILL_ILLOPN
;
3399 case PGM_FIXPT_OVERFLOW
:
3400 sig
= TARGET_SIGFPE
;
3401 n
= TARGET_FPE_INTOVF
;
3403 case PGM_FIXPT_DIVIDE
:
3404 sig
= TARGET_SIGFPE
;
3405 n
= TARGET_FPE_INTDIV
;
3409 n
= (env
->fpc
>> 8) & 0xff;
3411 /* compare-and-trap */
3414 /* An IEEE exception, simulated or otherwise. */
3416 n
= TARGET_FPE_FLTINV
;
3417 } else if (n
& 0x40) {
3418 n
= TARGET_FPE_FLTDIV
;
3419 } else if (n
& 0x20) {
3420 n
= TARGET_FPE_FLTOVF
;
3421 } else if (n
& 0x10) {
3422 n
= TARGET_FPE_FLTUND
;
3423 } else if (n
& 0x08) {
3424 n
= TARGET_FPE_FLTRES
;
3426 /* ??? Quantum exception; BFP, DFP error. */
3429 sig
= TARGET_SIGFPE
;
3434 fprintf(stderr
, "Unhandled program exception: %#x\n", n
);
3435 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3441 addr
= env
->psw
.addr
;
3443 info
.si_signo
= sig
;
3446 info
._sifields
._sigfault
._addr
= addr
;
3447 queue_signal(env
, info
.si_signo
, &info
);
3451 fprintf(stderr
, "Unhandled trap: 0x%x\n", trapnr
);
3452 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3455 process_pending_signals (env
);
3459 #endif /* TARGET_S390X */
3461 THREAD CPUState
*thread_cpu
;
3463 void task_settid(TaskState
*ts
)
3465 if (ts
->ts_tid
== 0) {
3466 ts
->ts_tid
= (pid_t
)syscall(SYS_gettid
);
3470 void stop_all_tasks(void)
3473 * We trust that when using NPTL, start_exclusive()
3474 * handles thread stopping correctly.
3479 /* Assumes contents are already zeroed. */
3480 void init_task_state(TaskState
*ts
)
3485 ts
->first_free
= ts
->sigqueue_table
;
3486 for (i
= 0; i
< MAX_SIGQUEUE_SIZE
- 1; i
++) {
3487 ts
->sigqueue_table
[i
].next
= &ts
->sigqueue_table
[i
+ 1];
3489 ts
->sigqueue_table
[i
].next
= NULL
;
3492 CPUArchState
*cpu_copy(CPUArchState
*env
)
3494 CPUState
*cpu
= ENV_GET_CPU(env
);
3495 CPUState
*new_cpu
= cpu_init(cpu_model
);
3496 CPUArchState
*new_env
= cpu
->env_ptr
;
3500 /* Reset non arch specific state */
3503 memcpy(new_env
, env
, sizeof(CPUArchState
));
3505 /* Clone all break/watchpoints.
3506 Note: Once we support ptrace with hw-debug register access, make sure
3507 BP_CPU break/watchpoints are handled correctly on clone. */
3508 QTAILQ_INIT(&cpu
->breakpoints
);
3509 QTAILQ_INIT(&cpu
->watchpoints
);
3510 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
3511 cpu_breakpoint_insert(new_cpu
, bp
->pc
, bp
->flags
, NULL
);
3513 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
3514 cpu_watchpoint_insert(new_cpu
, wp
->vaddr
, wp
->len
, wp
->flags
, NULL
);
3520 static void handle_arg_help(const char *arg
)
3525 static void handle_arg_log(const char *arg
)
3529 mask
= qemu_str_to_log_mask(arg
);
3531 qemu_print_log_usage(stdout
);
3537 static void handle_arg_log_filename(const char *arg
)
3539 qemu_set_log_filename(arg
);
3542 static void handle_arg_set_env(const char *arg
)
3544 char *r
, *p
, *token
;
3545 r
= p
= strdup(arg
);
3546 while ((token
= strsep(&p
, ",")) != NULL
) {
3547 if (envlist_setenv(envlist
, token
) != 0) {
3554 static void handle_arg_unset_env(const char *arg
)
3556 char *r
, *p
, *token
;
3557 r
= p
= strdup(arg
);
3558 while ((token
= strsep(&p
, ",")) != NULL
) {
3559 if (envlist_unsetenv(envlist
, token
) != 0) {
3566 static void handle_arg_argv0(const char *arg
)
3568 argv0
= strdup(arg
);
3571 static void handle_arg_stack_size(const char *arg
)
3574 guest_stack_size
= strtoul(arg
, &p
, 0);
3575 if (guest_stack_size
== 0) {
3580 guest_stack_size
*= 1024 * 1024;
3581 } else if (*p
== 'k' || *p
== 'K') {
3582 guest_stack_size
*= 1024;
3586 static void handle_arg_ld_prefix(const char *arg
)
3588 interp_prefix
= strdup(arg
);
3591 static void handle_arg_pagesize(const char *arg
)
3593 qemu_host_page_size
= atoi(arg
);
3594 if (qemu_host_page_size
== 0 ||
3595 (qemu_host_page_size
& (qemu_host_page_size
- 1)) != 0) {
3596 fprintf(stderr
, "page size must be a power of two\n");
3601 static void handle_arg_randseed(const char *arg
)
3603 unsigned long long seed
;
3605 if (parse_uint_full(arg
, &seed
, 0) != 0 || seed
> UINT_MAX
) {
3606 fprintf(stderr
, "Invalid seed number: %s\n", arg
);
3612 static void handle_arg_gdb(const char *arg
)
3614 gdbstub_port
= atoi(arg
);
3617 static void handle_arg_uname(const char *arg
)
3619 qemu_uname_release
= strdup(arg
);
3622 static void handle_arg_cpu(const char *arg
)
3624 cpu_model
= strdup(arg
);
3625 if (cpu_model
== NULL
|| is_help_option(cpu_model
)) {
3626 /* XXX: implement xxx_cpu_list for targets that still miss it */
3627 #if defined(cpu_list_id)
3628 cpu_list_id(stdout
, &fprintf
, "");
3629 #elif defined(cpu_list)
3630 cpu_list(stdout
, &fprintf
); /* deprecated */
3632 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
3633 printf("Target ignores cpu selection\n");
3639 #if defined(CONFIG_USE_GUEST_BASE)
3640 static void handle_arg_guest_base(const char *arg
)
3642 guest_base
= strtol(arg
, NULL
, 0);
3643 have_guest_base
= 1;
3646 static void handle_arg_reserved_va(const char *arg
)
3650 reserved_va
= strtoul(arg
, &p
, 0);
3664 unsigned long unshifted
= reserved_va
;
3666 reserved_va
<<= shift
;
3667 if (((reserved_va
>> shift
) != unshifted
)
3668 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3669 || (reserved_va
> (1ul << TARGET_VIRT_ADDR_SPACE_BITS
))
3672 fprintf(stderr
, "Reserved virtual address too big\n");
3677 fprintf(stderr
, "Unrecognised -R size suffix '%s'\n", p
);
3683 static void handle_arg_singlestep(const char *arg
)
3688 static void handle_arg_strace(const char *arg
)
3693 static void handle_arg_version(const char *arg
)
3695 printf("qemu-" TARGET_NAME
" version " QEMU_VERSION QEMU_PKGVERSION
3696 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3700 struct qemu_argument
{
3704 void (*handle_opt
)(const char *arg
);
3705 const char *example
;
3709 static const struct qemu_argument arg_table
[] = {
3710 {"h", "", false, handle_arg_help
,
3711 "", "print this help"},
3712 {"g", "QEMU_GDB", true, handle_arg_gdb
,
3713 "port", "wait gdb connection to 'port'"},
3714 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix
,
3715 "path", "set the elf interpreter prefix to 'path'"},
3716 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size
,
3717 "size", "set the stack size to 'size' bytes"},
3718 {"cpu", "QEMU_CPU", true, handle_arg_cpu
,
3719 "model", "select CPU (-cpu help for list)"},
3720 {"E", "QEMU_SET_ENV", true, handle_arg_set_env
,
3721 "var=value", "sets targets environment variable (see below)"},
3722 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env
,
3723 "var", "unsets targets environment variable (see below)"},
3724 {"0", "QEMU_ARGV0", true, handle_arg_argv0
,
3725 "argv0", "forces target process argv[0] to be 'argv0'"},
3726 {"r", "QEMU_UNAME", true, handle_arg_uname
,
3727 "uname", "set qemu uname release string to 'uname'"},
3728 #if defined(CONFIG_USE_GUEST_BASE)
3729 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base
,
3730 "address", "set guest_base address to 'address'"},
3731 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va
,
3732 "size", "reserve 'size' bytes for guest virtual address space"},
3734 {"d", "QEMU_LOG", true, handle_arg_log
,
3735 "item[,...]", "enable logging of specified items "
3736 "(use '-d help' for a list of items)"},
3737 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename
,
3738 "logfile", "write logs to 'logfile' (default stderr)"},
3739 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize
,
3740 "pagesize", "set the host page size to 'pagesize'"},
3741 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep
,
3742 "", "run in singlestep mode"},
3743 {"strace", "QEMU_STRACE", false, handle_arg_strace
,
3744 "", "log system calls"},
3745 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed
,
3746 "", "Seed for pseudo-random number generator"},
3747 {"version", "QEMU_VERSION", false, handle_arg_version
,
3748 "", "display version information and exit"},
3749 {NULL
, NULL
, false, NULL
, NULL
, NULL
}
3752 static void QEMU_NORETURN
usage(void)
3754 const struct qemu_argument
*arginfo
;
3758 printf("usage: qemu-" TARGET_NAME
" [options] program [arguments...]\n"
3759 "Linux CPU emulator (compiled for " TARGET_NAME
" emulation)\n"
3761 "Options and associated environment variables:\n"
3764 /* Calculate column widths. We must always have at least enough space
3765 * for the column header.
3767 maxarglen
= strlen("Argument");
3768 maxenvlen
= strlen("Env-variable");
3770 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3771 int arglen
= strlen(arginfo
->argv
);
3772 if (arginfo
->has_arg
) {
3773 arglen
+= strlen(arginfo
->example
) + 1;
3775 if (strlen(arginfo
->env
) > maxenvlen
) {
3776 maxenvlen
= strlen(arginfo
->env
);
3778 if (arglen
> maxarglen
) {
3783 printf("%-*s %-*s Description\n", maxarglen
+1, "Argument",
3784 maxenvlen
, "Env-variable");
3786 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3787 if (arginfo
->has_arg
) {
3788 printf("-%s %-*s %-*s %s\n", arginfo
->argv
,
3789 (int)(maxarglen
- strlen(arginfo
->argv
) - 1),
3790 arginfo
->example
, maxenvlen
, arginfo
->env
, arginfo
->help
);
3792 printf("-%-*s %-*s %s\n", maxarglen
, arginfo
->argv
,
3793 maxenvlen
, arginfo
->env
,
3800 "QEMU_LD_PREFIX = %s\n"
3801 "QEMU_STACK_SIZE = %ld byte\n",
3806 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3807 "QEMU_UNSET_ENV environment variables to set and unset\n"
3808 "environment variables for the target process.\n"
3809 "It is possible to provide several variables by separating them\n"
3810 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3811 "provide the -E and -U options multiple times.\n"
3812 "The following lines are equivalent:\n"
3813 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3814 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3815 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3816 "Note that if you provide several changes to a single variable\n"
3817 "the last change will stay in effect.\n");
3822 static int parse_args(int argc
, char **argv
)
3826 const struct qemu_argument
*arginfo
;
3828 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3829 if (arginfo
->env
== NULL
) {
3833 r
= getenv(arginfo
->env
);
3835 arginfo
->handle_opt(r
);
3841 if (optind
>= argc
) {
3850 if (!strcmp(r
, "-")) {
3854 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3855 if (!strcmp(r
, arginfo
->argv
)) {
3856 if (arginfo
->has_arg
) {
3857 if (optind
>= argc
) {
3860 arginfo
->handle_opt(argv
[optind
]);
3863 arginfo
->handle_opt(NULL
);
3869 /* no option matched the current argv */
3870 if (arginfo
->handle_opt
== NULL
) {
3875 if (optind
>= argc
) {
3879 filename
= argv
[optind
];
3880 exec_path
= argv
[optind
];
3885 int main(int argc
, char **argv
)
3887 struct target_pt_regs regs1
, *regs
= ®s1
;
3888 struct image_info info1
, *info
= &info1
;
3889 struct linux_binprm bprm
;
3894 char **target_environ
, **wrk
;
3901 module_call_init(MODULE_INIT_QOM
);
3903 if ((envlist
= envlist_create()) == NULL
) {
3904 (void) fprintf(stderr
, "Unable to allocate envlist\n");
3908 /* add current environment into the list */
3909 for (wrk
= environ
; *wrk
!= NULL
; wrk
++) {
3910 (void) envlist_setenv(envlist
, *wrk
);
3913 /* Read the stack limit from the kernel. If it's "unlimited",
3914 then we can do little else besides use the default. */
3917 if (getrlimit(RLIMIT_STACK
, &lim
) == 0
3918 && lim
.rlim_cur
!= RLIM_INFINITY
3919 && lim
.rlim_cur
== (target_long
)lim
.rlim_cur
) {
3920 guest_stack_size
= lim
.rlim_cur
;
3925 #if defined(cpudef_setup)
3926 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3931 optind
= parse_args(argc
, argv
);
3934 memset(regs
, 0, sizeof(struct target_pt_regs
));
3936 /* Zero out image_info */
3937 memset(info
, 0, sizeof(struct image_info
));
3939 memset(&bprm
, 0, sizeof (bprm
));
3941 /* Scan interp_prefix dir for replacement files. */
3942 init_paths(interp_prefix
);
3944 init_qemu_uname_release();
3946 if (cpu_model
== NULL
) {
3947 #if defined(TARGET_I386)
3948 #ifdef TARGET_X86_64
3949 cpu_model
= "qemu64";
3951 cpu_model
= "qemu32";
3953 #elif defined(TARGET_ARM)
3955 #elif defined(TARGET_UNICORE32)
3957 #elif defined(TARGET_M68K)
3959 #elif defined(TARGET_SPARC)
3960 #ifdef TARGET_SPARC64
3961 cpu_model
= "TI UltraSparc II";
3963 cpu_model
= "Fujitsu MB86904";
3965 #elif defined(TARGET_MIPS)
3966 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3971 #elif defined TARGET_OPENRISC
3972 cpu_model
= "or1200";
3973 #elif defined(TARGET_PPC)
3974 # ifdef TARGET_PPC64
3975 cpu_model
= "POWER7";
3984 cpu_exec_init_all();
3985 /* NOTE: we need to init the CPU at this stage to get
3986 qemu_host_page_size */
3987 cpu
= cpu_init(cpu_model
);
3989 fprintf(stderr
, "Unable to find CPU definition\n");
3997 if (getenv("QEMU_STRACE")) {
4001 if (getenv("QEMU_RAND_SEED")) {
4002 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4005 target_environ
= envlist_to_environ(envlist
, NULL
);
4006 envlist_free(envlist
);
4008 #if defined(CONFIG_USE_GUEST_BASE)
4010 * Now that page sizes are configured in cpu_init() we can do
4011 * proper page alignment for guest_base.
4013 guest_base
= HOST_PAGE_ALIGN(guest_base
);
4015 if (reserved_va
|| have_guest_base
) {
4016 guest_base
= init_guest_space(guest_base
, reserved_va
, 0,
4018 if (guest_base
== (unsigned long)-1) {
4019 fprintf(stderr
, "Unable to reserve 0x%lx bytes of virtual address "
4020 "space for use as guest address space (check your virtual "
4021 "memory ulimit setting or reserve less using -R option)\n",
4027 mmap_next_start
= reserved_va
;
4030 #endif /* CONFIG_USE_GUEST_BASE */
4033 * Read in mmap_min_addr kernel parameter. This value is used
4034 * When loading the ELF image to determine whether guest_base
4035 * is needed. It is also used in mmap_find_vma.
4040 if ((fp
= fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL
) {
4042 if (fscanf(fp
, "%lu", &tmp
) == 1) {
4043 mmap_min_addr
= tmp
;
4044 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr
);
4051 * Prepare copy of argv vector for target.
4053 target_argc
= argc
- optind
;
4054 target_argv
= calloc(target_argc
+ 1, sizeof (char *));
4055 if (target_argv
== NULL
) {
4056 (void) fprintf(stderr
, "Unable to allocate memory for target_argv\n");
4061 * If argv0 is specified (using '-0' switch) we replace
4062 * argv[0] pointer with the given one.
4065 if (argv0
!= NULL
) {
4066 target_argv
[i
++] = strdup(argv0
);
4068 for (; i
< target_argc
; i
++) {
4069 target_argv
[i
] = strdup(argv
[optind
+ i
]);
4071 target_argv
[target_argc
] = NULL
;
4073 ts
= g_malloc0 (sizeof(TaskState
));
4074 init_task_state(ts
);
4075 /* build Task State */
4081 execfd
= qemu_getauxval(AT_EXECFD
);
4083 execfd
= open(filename
, O_RDONLY
);
4085 printf("Error while loading %s: %s\n", filename
, strerror(errno
));
4090 ret
= loader_exec(execfd
, filename
, target_argv
, target_environ
, regs
,
4093 printf("Error while loading %s: %s\n", filename
, strerror(-ret
));
4097 for (wrk
= target_environ
; *wrk
; wrk
++) {
4101 free(target_environ
);
4103 if (qemu_log_enabled()) {
4104 #if defined(CONFIG_USE_GUEST_BASE)
4105 qemu_log("guest_base 0x%" PRIxPTR
"\n", guest_base
);
4109 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx
"\n", info
->start_brk
);
4110 qemu_log("end_code 0x" TARGET_ABI_FMT_lx
"\n", info
->end_code
);
4111 qemu_log("start_code 0x" TARGET_ABI_FMT_lx
"\n",
4113 qemu_log("start_data 0x" TARGET_ABI_FMT_lx
"\n",
4115 qemu_log("end_data 0x" TARGET_ABI_FMT_lx
"\n", info
->end_data
);
4116 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx
"\n",
4118 qemu_log("brk 0x" TARGET_ABI_FMT_lx
"\n", info
->brk
);
4119 qemu_log("entry 0x" TARGET_ABI_FMT_lx
"\n", info
->entry
);
4122 target_set_brk(info
->brk
);
4126 #if defined(CONFIG_USE_GUEST_BASE)
4127 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4128 generating the prologue until now so that the prologue can take
4129 the real value of GUEST_BASE into account. */
4130 tcg_prologue_init(&tcg_ctx
);
4133 #if defined(TARGET_I386)
4134 env
->cr
[0] = CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
;
4135 env
->hflags
|= HF_PE_MASK
| HF_CPL_MASK
;
4136 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
4137 env
->cr
[4] |= CR4_OSFXSR_MASK
;
4138 env
->hflags
|= HF_OSFXSR_MASK
;
4140 #ifndef TARGET_ABI32
4141 /* enable 64 bit mode if possible */
4142 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
)) {
4143 fprintf(stderr
, "The selected x86 CPU does not support 64 bit mode\n");
4146 env
->cr
[4] |= CR4_PAE_MASK
;
4147 env
->efer
|= MSR_EFER_LMA
| MSR_EFER_LME
;
4148 env
->hflags
|= HF_LMA_MASK
;
4151 /* flags setup : we activate the IRQs by default as in user mode */
4152 env
->eflags
|= IF_MASK
;
4154 /* linux register setup */
4155 #ifndef TARGET_ABI32
4156 env
->regs
[R_EAX
] = regs
->rax
;
4157 env
->regs
[R_EBX
] = regs
->rbx
;
4158 env
->regs
[R_ECX
] = regs
->rcx
;
4159 env
->regs
[R_EDX
] = regs
->rdx
;
4160 env
->regs
[R_ESI
] = regs
->rsi
;
4161 env
->regs
[R_EDI
] = regs
->rdi
;
4162 env
->regs
[R_EBP
] = regs
->rbp
;
4163 env
->regs
[R_ESP
] = regs
->rsp
;
4164 env
->eip
= regs
->rip
;
4166 env
->regs
[R_EAX
] = regs
->eax
;
4167 env
->regs
[R_EBX
] = regs
->ebx
;
4168 env
->regs
[R_ECX
] = regs
->ecx
;
4169 env
->regs
[R_EDX
] = regs
->edx
;
4170 env
->regs
[R_ESI
] = regs
->esi
;
4171 env
->regs
[R_EDI
] = regs
->edi
;
4172 env
->regs
[R_EBP
] = regs
->ebp
;
4173 env
->regs
[R_ESP
] = regs
->esp
;
4174 env
->eip
= regs
->eip
;
4177 /* linux interrupt setup */
4178 #ifndef TARGET_ABI32
4179 env
->idt
.limit
= 511;
4181 env
->idt
.limit
= 255;
4183 env
->idt
.base
= target_mmap(0, sizeof(uint64_t) * (env
->idt
.limit
+ 1),
4184 PROT_READ
|PROT_WRITE
,
4185 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4186 idt_table
= g2h(env
->idt
.base
);
4209 /* linux segment setup */
4211 uint64_t *gdt_table
;
4212 env
->gdt
.base
= target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES
,
4213 PROT_READ
|PROT_WRITE
,
4214 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4215 env
->gdt
.limit
= sizeof(uint64_t) * TARGET_GDT_ENTRIES
- 1;
4216 gdt_table
= g2h(env
->gdt
.base
);
4218 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4219 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4220 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4222 /* 64 bit code segment */
4223 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4224 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4226 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4228 write_dt(&gdt_table
[__USER_DS
>> 3], 0, 0xfffff,
4229 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4230 (3 << DESC_DPL_SHIFT
) | (0x2 << DESC_TYPE_SHIFT
));
4232 cpu_x86_load_seg(env
, R_CS
, __USER_CS
);
4233 cpu_x86_load_seg(env
, R_SS
, __USER_DS
);
4235 cpu_x86_load_seg(env
, R_DS
, __USER_DS
);
4236 cpu_x86_load_seg(env
, R_ES
, __USER_DS
);
4237 cpu_x86_load_seg(env
, R_FS
, __USER_DS
);
4238 cpu_x86_load_seg(env
, R_GS
, __USER_DS
);
4239 /* This hack makes Wine work... */
4240 env
->segs
[R_FS
].selector
= 0;
4242 cpu_x86_load_seg(env
, R_DS
, 0);
4243 cpu_x86_load_seg(env
, R_ES
, 0);
4244 cpu_x86_load_seg(env
, R_FS
, 0);
4245 cpu_x86_load_seg(env
, R_GS
, 0);
4247 #elif defined(TARGET_AARCH64)
4251 if (!(arm_feature(env
, ARM_FEATURE_AARCH64
))) {
4253 "The selected ARM CPU does not support 64 bit mode\n");
4257 for (i
= 0; i
< 31; i
++) {
4258 env
->xregs
[i
] = regs
->regs
[i
];
4261 env
->xregs
[31] = regs
->sp
;
4263 #elif defined(TARGET_ARM)
4266 cpsr_write(env
, regs
->uregs
[16], 0xffffffff);
4267 for(i
= 0; i
< 16; i
++) {
4268 env
->regs
[i
] = regs
->uregs
[i
];
4270 #ifdef TARGET_WORDS_BIGENDIAN
4272 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
4273 && (info
->elf_flags
& EF_ARM_BE8
)) {
4274 env
->bswap_code
= 1;
4278 #elif defined(TARGET_UNICORE32)
4281 cpu_asr_write(env
, regs
->uregs
[32], 0xffffffff);
4282 for (i
= 0; i
< 32; i
++) {
4283 env
->regs
[i
] = regs
->uregs
[i
];
4286 #elif defined(TARGET_SPARC)
4290 env
->npc
= regs
->npc
;
4292 for(i
= 0; i
< 8; i
++)
4293 env
->gregs
[i
] = regs
->u_regs
[i
];
4294 for(i
= 0; i
< 8; i
++)
4295 env
->regwptr
[i
] = regs
->u_regs
[i
+ 8];
4297 #elif defined(TARGET_PPC)
4301 #if defined(TARGET_PPC64)
4302 #if defined(TARGET_ABI32)
4303 env
->msr
&= ~((target_ulong
)1 << MSR_SF
);
4305 env
->msr
|= (target_ulong
)1 << MSR_SF
;
4308 env
->nip
= regs
->nip
;
4309 for(i
= 0; i
< 32; i
++) {
4310 env
->gpr
[i
] = regs
->gpr
[i
];
4313 #elif defined(TARGET_M68K)
4316 env
->dregs
[0] = regs
->d0
;
4317 env
->dregs
[1] = regs
->d1
;
4318 env
->dregs
[2] = regs
->d2
;
4319 env
->dregs
[3] = regs
->d3
;
4320 env
->dregs
[4] = regs
->d4
;
4321 env
->dregs
[5] = regs
->d5
;
4322 env
->dregs
[6] = regs
->d6
;
4323 env
->dregs
[7] = regs
->d7
;
4324 env
->aregs
[0] = regs
->a0
;
4325 env
->aregs
[1] = regs
->a1
;
4326 env
->aregs
[2] = regs
->a2
;
4327 env
->aregs
[3] = regs
->a3
;
4328 env
->aregs
[4] = regs
->a4
;
4329 env
->aregs
[5] = regs
->a5
;
4330 env
->aregs
[6] = regs
->a6
;
4331 env
->aregs
[7] = regs
->usp
;
4333 ts
->sim_syscalls
= 1;
4335 #elif defined(TARGET_MICROBLAZE)
4337 env
->regs
[0] = regs
->r0
;
4338 env
->regs
[1] = regs
->r1
;
4339 env
->regs
[2] = regs
->r2
;
4340 env
->regs
[3] = regs
->r3
;
4341 env
->regs
[4] = regs
->r4
;
4342 env
->regs
[5] = regs
->r5
;
4343 env
->regs
[6] = regs
->r6
;
4344 env
->regs
[7] = regs
->r7
;
4345 env
->regs
[8] = regs
->r8
;
4346 env
->regs
[9] = regs
->r9
;
4347 env
->regs
[10] = regs
->r10
;
4348 env
->regs
[11] = regs
->r11
;
4349 env
->regs
[12] = regs
->r12
;
4350 env
->regs
[13] = regs
->r13
;
4351 env
->regs
[14] = regs
->r14
;
4352 env
->regs
[15] = regs
->r15
;
4353 env
->regs
[16] = regs
->r16
;
4354 env
->regs
[17] = regs
->r17
;
4355 env
->regs
[18] = regs
->r18
;
4356 env
->regs
[19] = regs
->r19
;
4357 env
->regs
[20] = regs
->r20
;
4358 env
->regs
[21] = regs
->r21
;
4359 env
->regs
[22] = regs
->r22
;
4360 env
->regs
[23] = regs
->r23
;
4361 env
->regs
[24] = regs
->r24
;
4362 env
->regs
[25] = regs
->r25
;
4363 env
->regs
[26] = regs
->r26
;
4364 env
->regs
[27] = regs
->r27
;
4365 env
->regs
[28] = regs
->r28
;
4366 env
->regs
[29] = regs
->r29
;
4367 env
->regs
[30] = regs
->r30
;
4368 env
->regs
[31] = regs
->r31
;
4369 env
->sregs
[SR_PC
] = regs
->pc
;
4371 #elif defined(TARGET_MIPS)
4375 for(i
= 0; i
< 32; i
++) {
4376 env
->active_tc
.gpr
[i
] = regs
->regs
[i
];
4378 env
->active_tc
.PC
= regs
->cp0_epc
& ~(target_ulong
)1;
4379 if (regs
->cp0_epc
& 1) {
4380 env
->hflags
|= MIPS_HFLAG_M16
;
4383 #elif defined(TARGET_OPENRISC)
4387 for (i
= 0; i
< 32; i
++) {
4388 env
->gpr
[i
] = regs
->gpr
[i
];
4394 #elif defined(TARGET_SH4)
4398 for(i
= 0; i
< 16; i
++) {
4399 env
->gregs
[i
] = regs
->regs
[i
];
4403 #elif defined(TARGET_ALPHA)
4407 for(i
= 0; i
< 28; i
++) {
4408 env
->ir
[i
] = ((abi_ulong
*)regs
)[i
];
4410 env
->ir
[IR_SP
] = regs
->usp
;
4413 #elif defined(TARGET_CRIS)
4415 env
->regs
[0] = regs
->r0
;
4416 env
->regs
[1] = regs
->r1
;
4417 env
->regs
[2] = regs
->r2
;
4418 env
->regs
[3] = regs
->r3
;
4419 env
->regs
[4] = regs
->r4
;
4420 env
->regs
[5] = regs
->r5
;
4421 env
->regs
[6] = regs
->r6
;
4422 env
->regs
[7] = regs
->r7
;
4423 env
->regs
[8] = regs
->r8
;
4424 env
->regs
[9] = regs
->r9
;
4425 env
->regs
[10] = regs
->r10
;
4426 env
->regs
[11] = regs
->r11
;
4427 env
->regs
[12] = regs
->r12
;
4428 env
->regs
[13] = regs
->r13
;
4429 env
->regs
[14] = info
->start_stack
;
4430 env
->regs
[15] = regs
->acr
;
4431 env
->pc
= regs
->erp
;
4433 #elif defined(TARGET_S390X)
4436 for (i
= 0; i
< 16; i
++) {
4437 env
->regs
[i
] = regs
->gprs
[i
];
4439 env
->psw
.mask
= regs
->psw
.mask
;
4440 env
->psw
.addr
= regs
->psw
.addr
;
4443 #error unsupported target CPU
4446 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4447 ts
->stack_base
= info
->start_stack
;
4448 ts
->heap_base
= info
->brk
;
4449 /* This will be filled in on the first SYS_HEAPINFO call. */
4454 if (gdbserver_start(gdbstub_port
) < 0) {
4455 fprintf(stderr
, "qemu: could not open gdbserver on port %d\n",
4459 gdb_handlesig(cpu
, 0);