2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/pci/pci.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/ppc/spapr.h"
31 #include "hw/pci-host/spapr.h"
32 #include "exec/address-spaces.h"
35 #include "qemu/error-report.h"
36 #include "qapi/qmp/qerror.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/ppc/spapr_drc.h"
40 #include "sysemu/device_tree.h"
42 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
43 #define RTAS_QUERY_FN 0
44 #define RTAS_CHANGE_FN 1
45 #define RTAS_RESET_FN 2
46 #define RTAS_CHANGE_MSI_FN 3
47 #define RTAS_CHANGE_MSIX_FN 4
49 /* Interrupt types to return on RTAS_CHANGE_* */
50 #define RTAS_TYPE_MSI 1
51 #define RTAS_TYPE_MSIX 2
61 sPAPRPHBState
*spapr_pci_find_phb(sPAPREnvironment
*spapr
, uint64_t buid
)
65 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
66 if (sphb
->buid
!= buid
) {
75 PCIDevice
*spapr_pci_find_dev(sPAPREnvironment
*spapr
, uint64_t buid
,
78 sPAPRPHBState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
79 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
80 int bus_num
= (config_addr
>> 16) & 0xFF;
81 int devfn
= (config_addr
>> 8) & 0xFF;
87 return pci_find_device(phb
->bus
, bus_num
, devfn
);
90 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
92 /* This handles the encoding of extended config space addresses */
93 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
96 static void finish_read_pci_config(sPAPREnvironment
*spapr
, uint64_t buid
,
97 uint32_t addr
, uint32_t size
,
103 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
104 /* access must be 1, 2 or 4 bytes */
105 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
109 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
110 addr
= rtas_pci_cfgaddr(addr
);
112 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
113 /* Access must be to a valid device, within bounds and
114 * naturally aligned */
115 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
119 val
= pci_host_config_read_common(pci_dev
, addr
,
120 pci_config_size(pci_dev
), size
);
122 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
123 rtas_st(rets
, 1, val
);
126 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, sPAPREnvironment
*spapr
,
127 uint32_t token
, uint32_t nargs
,
129 uint32_t nret
, target_ulong rets
)
134 if ((nargs
!= 4) || (nret
!= 2)) {
135 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
139 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
140 size
= rtas_ld(args
, 3);
141 addr
= rtas_ld(args
, 0);
143 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
146 static void rtas_read_pci_config(PowerPCCPU
*cpu
, sPAPREnvironment
*spapr
,
147 uint32_t token
, uint32_t nargs
,
149 uint32_t nret
, target_ulong rets
)
153 if ((nargs
!= 2) || (nret
!= 2)) {
154 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
158 size
= rtas_ld(args
, 1);
159 addr
= rtas_ld(args
, 0);
161 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
164 static void finish_write_pci_config(sPAPREnvironment
*spapr
, uint64_t buid
,
165 uint32_t addr
, uint32_t size
,
166 uint32_t val
, target_ulong rets
)
170 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
171 /* access must be 1, 2 or 4 bytes */
172 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
176 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
177 addr
= rtas_pci_cfgaddr(addr
);
179 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
180 /* Access must be to a valid device, within bounds and
181 * naturally aligned */
182 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
186 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
189 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
192 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, sPAPREnvironment
*spapr
,
193 uint32_t token
, uint32_t nargs
,
195 uint32_t nret
, target_ulong rets
)
198 uint32_t val
, size
, addr
;
200 if ((nargs
!= 5) || (nret
!= 1)) {
201 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
205 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
206 val
= rtas_ld(args
, 4);
207 size
= rtas_ld(args
, 3);
208 addr
= rtas_ld(args
, 0);
210 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
213 static void rtas_write_pci_config(PowerPCCPU
*cpu
, sPAPREnvironment
*spapr
,
214 uint32_t token
, uint32_t nargs
,
216 uint32_t nret
, target_ulong rets
)
218 uint32_t val
, size
, addr
;
220 if ((nargs
!= 3) || (nret
!= 1)) {
221 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
226 val
= rtas_ld(args
, 2);
227 size
= rtas_ld(args
, 1);
228 addr
= rtas_ld(args
, 0);
230 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
234 * Set MSI/MSIX message data.
235 * This is required for msi_notify()/msix_notify() which
236 * will write at the addresses via spapr_msi_write().
238 * If hwaddr == 0, all entries will have .data == first_irq i.e.
239 * table will be reset.
241 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
242 unsigned first_irq
, unsigned req_num
)
245 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
248 msi_set_message(pdev
, msg
);
249 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
253 for (i
= 0; i
< req_num
; ++i
) {
254 msix_set_message(pdev
, i
, msg
);
255 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
262 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, sPAPREnvironment
*spapr
,
263 uint32_t token
, uint32_t nargs
,
264 target_ulong args
, uint32_t nret
,
267 uint32_t config_addr
= rtas_ld(args
, 0);
268 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
269 unsigned int func
= rtas_ld(args
, 3);
270 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
271 unsigned int seq_num
= rtas_ld(args
, 5);
272 unsigned int ret_intr_type
;
273 unsigned int irq
, max_irqs
= 0, num
= 0;
274 sPAPRPHBState
*phb
= NULL
;
275 PCIDevice
*pdev
= NULL
;
277 int *config_addr_key
;
280 case RTAS_CHANGE_MSI_FN
:
282 ret_intr_type
= RTAS_TYPE_MSI
;
284 case RTAS_CHANGE_MSIX_FN
:
285 ret_intr_type
= RTAS_TYPE_MSIX
;
288 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
289 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
293 /* Fins sPAPRPHBState */
294 phb
= spapr_pci_find_phb(spapr
, buid
);
296 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
299 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
305 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
307 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
308 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
312 xics_free(spapr
->icp
, msi
->first_irq
, msi
->num
);
313 if (msi_present(pdev
)) {
314 spapr_msi_setmsg(pdev
, 0, false, 0, num
);
316 if (msix_present(pdev
)) {
317 spapr_msi_setmsg(pdev
, 0, true, 0, num
);
319 g_hash_table_remove(phb
->msi
, &config_addr
);
321 trace_spapr_pci_msi("Released MSIs", config_addr
);
322 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
329 /* Check if the device supports as many IRQs as requested */
330 if (ret_intr_type
== RTAS_TYPE_MSI
) {
331 max_irqs
= msi_nr_vectors_allocated(pdev
);
332 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
333 max_irqs
= pdev
->msix_entries_nr
;
336 error_report("Requested interrupt type %d is not enabled for device %x",
337 ret_intr_type
, config_addr
);
338 rtas_st(rets
, 0, -1); /* Hardware error */
341 /* Correct the number if the guest asked for too many */
342 if (req_num
> max_irqs
) {
343 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
345 irq
= 0; /* to avoid misleading trace */
350 irq
= xics_alloc_block(spapr
->icp
, 0, req_num
, false,
351 ret_intr_type
== RTAS_TYPE_MSI
);
353 error_report("Cannot allocate MSIs for device %x", config_addr
);
354 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
358 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
359 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
362 /* Add MSI device to cache */
363 msi
= g_new(spapr_pci_msi
, 1);
364 msi
->first_irq
= irq
;
366 config_addr_key
= g_new(int, 1);
367 *config_addr_key
= config_addr
;
368 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
371 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
372 rtas_st(rets
, 1, req_num
);
373 rtas_st(rets
, 2, ++seq_num
);
374 rtas_st(rets
, 3, ret_intr_type
);
376 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
379 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
380 sPAPREnvironment
*spapr
,
387 uint32_t config_addr
= rtas_ld(args
, 0);
388 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
389 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
390 sPAPRPHBState
*phb
= NULL
;
391 PCIDevice
*pdev
= NULL
;
394 /* Find sPAPRPHBState */
395 phb
= spapr_pci_find_phb(spapr
, buid
);
397 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
400 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
404 /* Find device descriptor and start IRQ */
405 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
406 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
407 trace_spapr_pci_msi("Failed to return vector", config_addr
);
408 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
411 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
412 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
415 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
416 rtas_st(rets
, 1, intr_src_num
);
417 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
420 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
421 sPAPREnvironment
*spapr
,
422 uint32_t token
, uint32_t nargs
,
423 target_ulong args
, uint32_t nret
,
428 uint32_t addr
, option
;
432 if ((nargs
!= 4) || (nret
!= 1)) {
433 goto param_error_exit
;
436 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
437 addr
= rtas_ld(args
, 0);
438 option
= rtas_ld(args
, 3);
440 sphb
= spapr_pci_find_phb(spapr
, buid
);
442 goto param_error_exit
;
445 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
446 if (!spc
->eeh_set_option
) {
447 goto param_error_exit
;
450 ret
= spc
->eeh_set_option(sphb
, addr
, option
);
451 rtas_st(rets
, 0, ret
);
455 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
458 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
459 sPAPREnvironment
*spapr
,
460 uint32_t token
, uint32_t nargs
,
461 target_ulong args
, uint32_t nret
,
467 uint32_t addr
, option
;
470 if ((nargs
!= 4) || (nret
!= 2)) {
471 goto param_error_exit
;
474 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
475 sphb
= spapr_pci_find_phb(spapr
, buid
);
477 goto param_error_exit
;
480 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
481 if (!spc
->eeh_set_option
) {
482 goto param_error_exit
;
486 * We always have PE address of form "00BB0001". "BB"
487 * represents the bus number of PE's primary bus.
489 option
= rtas_ld(args
, 3);
491 case RTAS_GET_PE_ADDR
:
492 addr
= rtas_ld(args
, 0);
493 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
495 goto param_error_exit
;
498 rtas_st(rets
, 1, (pci_bus_num(pdev
->bus
) << 16) + 1);
500 case RTAS_GET_PE_MODE
:
501 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
504 goto param_error_exit
;
507 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
511 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
514 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
515 sPAPREnvironment
*spapr
,
516 uint32_t token
, uint32_t nargs
,
517 target_ulong args
, uint32_t nret
,
525 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
526 goto param_error_exit
;
529 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
530 sphb
= spapr_pci_find_phb(spapr
, buid
);
532 goto param_error_exit
;
535 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
536 if (!spc
->eeh_get_state
) {
537 goto param_error_exit
;
540 ret
= spc
->eeh_get_state(sphb
, &state
);
541 rtas_st(rets
, 0, ret
);
542 if (ret
!= RTAS_OUT_SUCCESS
) {
546 rtas_st(rets
, 1, state
);
547 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
548 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
550 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
555 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
558 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
559 sPAPREnvironment
*spapr
,
560 uint32_t token
, uint32_t nargs
,
561 target_ulong args
, uint32_t nret
,
570 if ((nargs
!= 4) || (nret
!= 1)) {
571 goto param_error_exit
;
574 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
575 option
= rtas_ld(args
, 3);
576 sphb
= spapr_pci_find_phb(spapr
, buid
);
578 goto param_error_exit
;
581 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
582 if (!spc
->eeh_reset
) {
583 goto param_error_exit
;
586 ret
= spc
->eeh_reset(sphb
, option
);
587 rtas_st(rets
, 0, ret
);
591 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
594 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
595 sPAPREnvironment
*spapr
,
596 uint32_t token
, uint32_t nargs
,
597 target_ulong args
, uint32_t nret
,
605 if ((nargs
!= 3) || (nret
!= 1)) {
606 goto param_error_exit
;
609 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
610 sphb
= spapr_pci_find_phb(spapr
, buid
);
612 goto param_error_exit
;
615 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
616 if (!spc
->eeh_configure
) {
617 goto param_error_exit
;
620 ret
= spc
->eeh_configure(sphb
);
621 rtas_st(rets
, 0, ret
);
625 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
628 /* To support it later */
629 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
630 sPAPREnvironment
*spapr
,
631 uint32_t token
, uint32_t nargs
,
632 target_ulong args
, uint32_t nret
,
640 if ((nargs
!= 8) || (nret
!= 1)) {
641 goto param_error_exit
;
644 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
645 sphb
= spapr_pci_find_phb(spapr
, buid
);
647 goto param_error_exit
;
650 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
651 if (!spc
->eeh_set_option
) {
652 goto param_error_exit
;
655 option
= rtas_ld(args
, 7);
657 case RTAS_SLOT_TEMP_ERR_LOG
:
658 case RTAS_SLOT_PERM_ERR_LOG
:
661 goto param_error_exit
;
664 /* We don't have error log yet */
665 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
669 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
672 static int pci_spapr_swizzle(int slot
, int pin
)
674 return (slot
+ pin
) % PCI_NUM_PINS
;
677 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
680 * Here we need to convert pci_dev + irq_num to some unique value
681 * which is less than number of IRQs on the specific bus (4). We
682 * use standard PCI swizzling, that is (slot number + pin number)
685 return pci_spapr_swizzle(PCI_SLOT(pci_dev
->devfn
), irq_num
);
688 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
691 * Here we use the number returned by pci_spapr_map_irq to find a
692 * corresponding qemu_irq.
694 sPAPRPHBState
*phb
= opaque
;
696 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
697 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
700 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
702 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
705 route
.mode
= PCI_INTX_ENABLED
;
706 route
.irq
= sphb
->lsi_table
[pin
].irq
;
712 * MSI/MSIX memory region implementation.
713 * The handler handles both MSI and MSIX.
714 * For MSI-X, the vector number is encoded as a part of the address,
716 * For MSI, the vector number is encoded in least bits in data.
718 static void spapr_msi_write(void *opaque
, hwaddr addr
,
719 uint64_t data
, unsigned size
)
723 trace_spapr_pci_msi_write(addr
, data
, irq
);
725 qemu_irq_pulse(xics_get_qirq(spapr
->icp
, irq
));
728 static const MemoryRegionOps spapr_msi_ops
= {
729 /* There is no .read as the read result is undefined by PCI spec */
731 .write
= spapr_msi_write
,
732 .endianness
= DEVICE_LITTLE_ENDIAN
738 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
740 sPAPRPHBState
*phb
= opaque
;
742 return &phb
->iommu_as
;
745 /* Macros to operate with address in OF binding to PCI */
746 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
747 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
748 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
749 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
750 #define b_ss(x) b_x((x), 24, 2) /* the space code */
751 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
752 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
753 #define b_fff(x) b_x((x), 8, 3) /* function number */
754 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
756 /* for 'reg'/'assigned-addresses' OF properties */
757 #define RESOURCE_CELLS_SIZE 2
758 #define RESOURCE_CELLS_ADDRESS 3
760 typedef struct ResourceFields
{
766 } QEMU_PACKED ResourceFields
;
768 typedef struct ResourceProps
{
769 ResourceFields reg
[8];
770 ResourceFields assigned
[7];
772 uint32_t assigned_len
;
775 /* fill in the 'reg'/'assigned-resources' OF properties for
776 * a PCI device. 'reg' describes resource requirements for a
777 * device's IO/MEM regions, 'assigned-addresses' describes the
778 * actual resource assignments.
780 * the properties are arrays of ('phys-addr', 'size') pairs describing
781 * the addressable regions of the PCI device, where 'phys-addr' is a
782 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
783 * (phys.hi, phys.mid, phys.lo), and 'size' is a
784 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
786 * phys.hi = 0xYYXXXXZZ, where:
789 * ||| +-- space code: 1 if IO region, 2 if MEM region
790 * ||+------ for non-relocatable IO: 1 if aliased
791 * || for relocatable IO: 1 if below 64KB
792 * || for MEM: 1 if below 1MB
793 * |+------- 1 if region is prefetchable
794 * +-------- 1 if region is non-relocatable
795 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
797 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
800 * phys.mid and phys.lo correspond respectively to the hi/lo portions
801 * of the actual address of the region.
803 * how the phys-addr/size values are used differ slightly between
804 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
805 * an additional description for the config space region of the
806 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
807 * to describe the region as relocatable, with an address-mapping
808 * that corresponds directly to the PHB's address space for the
809 * resource. 'assigned-addresses' always has n=1 set with an absolute
810 * address assigned for the resource. in general, 'assigned-addresses'
811 * won't be populated, since addresses for PCI devices are generally
812 * unmapped initially and left to the guest to assign.
814 * note also that addresses defined in these properties are, at least
815 * for PAPR guests, relative to the PHBs IO/MEM windows, and
816 * correspond directly to the addresses in the BARs.
818 * in accordance with PCI Bus Binding to Open Firmware,
819 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
822 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
824 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
825 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
826 b_ddddd(PCI_SLOT(d
->devfn
)) |
827 b_fff(PCI_FUNC(d
->devfn
)));
828 ResourceFields
*reg
, *assigned
;
829 int i
, reg_idx
= 0, assigned_idx
= 0;
831 /* config space region */
832 reg
= &rp
->reg
[reg_idx
++];
833 reg
->phys_hi
= cpu_to_be32(dev_id
);
839 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
840 if (!d
->io_regions
[i
].size
) {
844 reg
= &rp
->reg
[reg_idx
++];
846 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
847 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
848 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
850 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
854 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
855 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
857 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
861 assigned
= &rp
->assigned
[assigned_idx
++];
862 assigned
->phys_hi
= cpu_to_be32(reg
->phys_hi
| b_n(1));
863 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
864 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
865 assigned
->size_hi
= reg
->size_hi
;
866 assigned
->size_lo
= reg
->size_lo
;
869 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
870 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
873 static int spapr_populate_pci_child_dt(PCIDevice
*dev
, void *fdt
, int offset
,
874 int phb_index
, int drc_index
,
875 const char *drc_name
)
878 bool is_bridge
= false;
881 if (pci_default_read_config(dev
, PCI_HEADER_TYPE
, 1) ==
882 PCI_HEADER_TYPE_BRIDGE
) {
886 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
887 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id",
888 pci_default_read_config(dev
, PCI_VENDOR_ID
, 2)));
889 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id",
890 pci_default_read_config(dev
, PCI_DEVICE_ID
, 2)));
891 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id",
892 pci_default_read_config(dev
, PCI_REVISION_ID
, 1)));
893 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code",
894 pci_default_read_config(dev
, PCI_CLASS_DEVICE
, 2)
896 if (pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)) {
897 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts",
898 pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)));
902 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant",
903 pci_default_read_config(dev
, PCI_MIN_GNT
, 1)));
904 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency",
905 pci_default_read_config(dev
, PCI_MAX_LAT
, 1)));
908 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)) {
909 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id",
910 pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)));
913 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)) {
914 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
915 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)));
918 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size",
919 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1)));
921 /* the following fdt cells are masked off the pci status register */
922 pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
923 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
924 PCI_STATUS_DEVSEL_MASK
& pci_status
));
926 if (pci_status
& PCI_STATUS_FAST_BACK
) {
927 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
929 if (pci_status
& PCI_STATUS_66MHZ
) {
930 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
932 if (pci_status
& PCI_STATUS_UDF
) {
933 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
936 /* NOTE: this is normally generated by firmware via path/unit name,
937 * but in our case we must set it manually since it does not get
938 * processed by OF beforehand
940 _FDT(fdt_setprop_string(fdt
, offset
, "name", "pci"));
941 _FDT(fdt_setprop(fdt
, offset
, "ibm,loc-code", drc_name
, strlen(drc_name
)));
942 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
));
944 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
945 RESOURCE_CELLS_ADDRESS
));
946 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
947 RESOURCE_CELLS_SIZE
));
948 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x",
949 RESOURCE_CELLS_SIZE
));
951 populate_resource_props(dev
, &rp
);
952 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
953 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
954 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
959 /* create OF node for pci device and required OF DT properties */
960 static void *spapr_create_pci_child_dt(sPAPRPHBState
*phb
, PCIDevice
*dev
,
961 int drc_index
, const char *drc_name
,
965 int offset
, ret
, fdt_size
;
966 int slot
= PCI_SLOT(dev
->devfn
);
967 int func
= PCI_FUNC(dev
->devfn
);
970 fdt
= create_device_tree(&fdt_size
);
972 sprintf(nodename
, "pci@%d,%d", slot
, func
);
974 sprintf(nodename
, "pci@%d", slot
);
976 offset
= fdt_add_subnode(fdt
, 0, nodename
);
977 ret
= spapr_populate_pci_child_dt(dev
, fdt
, offset
, phb
->index
, drc_index
,
985 static void spapr_phb_add_pci_device(sPAPRDRConnector
*drc
,
990 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
991 DeviceState
*dev
= DEVICE(pdev
);
992 int drc_index
= drck
->get_index(drc
);
993 const char *drc_name
= drck
->get_name(drc
);
995 int fdt_start_offset
= 0;
997 /* boot-time devices get their device tree node created by SLOF, but for
998 * hotplugged devices we need QEMU to generate it so the guest can fetch
1001 if (dev
->hotplugged
) {
1002 fdt
= spapr_create_pci_child_dt(phb
, pdev
, drc_index
, drc_name
,
1006 drck
->attach(drc
, DEVICE(pdev
),
1007 fdt
, fdt_start_offset
, !dev
->hotplugged
, errp
);
1013 static void spapr_phb_remove_pci_device_cb(DeviceState
*dev
, void *opaque
)
1015 /* some version guests do not wait for completion of a device
1016 * cleanup (generally done asynchronously by the kernel) before
1017 * signaling to QEMU that the device is safe, but instead sleep
1018 * for some 'safe' period of time. unfortunately on a busy host
1019 * this sleep isn't guaranteed to be long enough, resulting in
1020 * bad things like IRQ lines being left asserted during final
1021 * device removal. to deal with this we call reset just prior
1022 * to finalizing the device, which will put the device back into
1023 * an 'idle' state, as the device cleanup code expects.
1025 pci_device_reset(PCI_DEVICE(dev
));
1026 object_unparent(OBJECT(dev
));
1029 static void spapr_phb_remove_pci_device(sPAPRDRConnector
*drc
,
1034 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1036 drck
->detach(drc
, DEVICE(pdev
), spapr_phb_remove_pci_device_cb
, phb
, errp
);
1039 static sPAPRDRConnector
*spapr_phb_get_pci_drc(sPAPRPHBState
*phb
,
1042 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
1043 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI
,
1044 (phb
->index
<< 16) |
1049 static void spapr_phb_hot_plug_child(HotplugHandler
*plug_handler
,
1050 DeviceState
*plugged_dev
, Error
**errp
)
1052 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1053 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1054 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1055 Error
*local_err
= NULL
;
1057 /* if DR is disabled we don't need to do anything in the case of
1058 * hotplug or coldplug callbacks
1060 if (!phb
->dr_enabled
) {
1061 /* if this is a hotplug operation initiated by the user
1062 * we need to let them know it's not enabled
1064 if (plugged_dev
->hotplugged
) {
1065 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1066 object_get_typename(OBJECT(phb
)));
1073 spapr_phb_add_pci_device(drc
, phb
, pdev
, &local_err
);
1075 error_propagate(errp
, local_err
);
1078 if (plugged_dev
->hotplugged
) {
1079 spapr_hotplug_req_add_event(drc
);
1083 static void spapr_phb_hot_unplug_child(HotplugHandler
*plug_handler
,
1084 DeviceState
*plugged_dev
, Error
**errp
)
1086 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1087 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1088 sPAPRDRConnectorClass
*drck
;
1089 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1090 Error
*local_err
= NULL
;
1092 if (!phb
->dr_enabled
) {
1093 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1094 object_get_typename(OBJECT(phb
)));
1100 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1101 if (!drck
->release_pending(drc
)) {
1102 spapr_phb_remove_pci_device(drc
, phb
, pdev
, &local_err
);
1104 error_propagate(errp
, local_err
);
1107 spapr_hotplug_req_remove_event(drc
);
1111 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1113 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1114 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1115 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1116 sPAPRPHBClass
*info
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s
);
1120 uint64_t msi_window_size
= 4096;
1122 if (sphb
->index
!= (uint32_t)-1) {
1123 hwaddr windows_base
;
1125 if ((sphb
->buid
!= (uint64_t)-1) || (sphb
->dma_liobn
!= (uint32_t)-1)
1126 || (sphb
->mem_win_addr
!= (hwaddr
)-1)
1127 || (sphb
->io_win_addr
!= (hwaddr
)-1)) {
1128 error_setg(errp
, "Either \"index\" or other parameters must"
1129 " be specified for PAPR PHB, not both");
1133 if (sphb
->index
> SPAPR_PCI_MAX_INDEX
) {
1134 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
1135 SPAPR_PCI_MAX_INDEX
);
1139 sphb
->buid
= SPAPR_PCI_BASE_BUID
+ sphb
->index
;
1140 sphb
->dma_liobn
= SPAPR_PCI_LIOBN(sphb
->index
, 0);
1142 windows_base
= SPAPR_PCI_WINDOW_BASE
1143 + sphb
->index
* SPAPR_PCI_WINDOW_SPACING
;
1144 sphb
->mem_win_addr
= windows_base
+ SPAPR_PCI_MMIO_WIN_OFF
;
1145 sphb
->io_win_addr
= windows_base
+ SPAPR_PCI_IO_WIN_OFF
;
1148 if (sphb
->buid
== (uint64_t)-1) {
1149 error_setg(errp
, "BUID not specified for PHB");
1153 if (sphb
->dma_liobn
== (uint32_t)-1) {
1154 error_setg(errp
, "LIOBN not specified for PHB");
1158 if (sphb
->mem_win_addr
== (hwaddr
)-1) {
1159 error_setg(errp
, "Memory window address not specified for PHB");
1163 if (sphb
->io_win_addr
== (hwaddr
)-1) {
1164 error_setg(errp
, "IO window address not specified for PHB");
1168 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1169 error_setg(errp
, "PCI host bridges must have unique BUIDs");
1173 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1175 namebuf
= alloca(strlen(sphb
->dtbusname
) + 32);
1177 /* Initialize memory regions */
1178 sprintf(namebuf
, "%s.mmio", sphb
->dtbusname
);
1179 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1181 sprintf(namebuf
, "%s.mmio-alias", sphb
->dtbusname
);
1182 memory_region_init_alias(&sphb
->memwindow
, OBJECT(sphb
),
1183 namebuf
, &sphb
->memspace
,
1184 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1185 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1188 /* Initialize IO regions */
1189 sprintf(namebuf
, "%s.io", sphb
->dtbusname
);
1190 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1191 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1193 sprintf(namebuf
, "%s.io-alias", sphb
->dtbusname
);
1194 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1195 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1196 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1199 bus
= pci_register_bus(dev
, NULL
,
1200 pci_spapr_set_irq
, pci_spapr_map_irq
, sphb
,
1201 &sphb
->memspace
, &sphb
->iospace
,
1202 PCI_DEVFN(0, 0), PCI_NUM_PINS
, TYPE_PCI_BUS
);
1204 qbus_set_hotplug_handler(BUS(phb
->bus
), DEVICE(sphb
), NULL
);
1207 * Initialize PHB address space.
1208 * By default there will be at least one subregion for default
1210 * Later the guest might want to create another DMA window
1211 * which will become another memory subregion.
1213 sprintf(namebuf
, "%s.iommu-root", sphb
->dtbusname
);
1215 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1216 namebuf
, UINT64_MAX
);
1217 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1221 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1222 * we need to allocate some memory to catch those writes coming
1223 * from msi_notify()/msix_notify().
1224 * As MSIMessage:addr is going to be the same and MSIMessage:data
1225 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1228 * For KVM we want to ensure that this memory is a full page so that
1229 * our memory slot is of page size granularity.
1232 if (kvm_enabled()) {
1233 msi_window_size
= getpagesize();
1237 memory_region_init_io(&sphb
->msiwindow
, NULL
, &spapr_msi_ops
, spapr
,
1238 "msi", msi_window_size
);
1239 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1242 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1244 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1246 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1248 /* Initialize the LSI table */
1249 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1252 irq
= xics_alloc_block(spapr
->icp
, 0, 1, true, false);
1254 error_setg(errp
, "spapr_allocate_lsi failed");
1258 sphb
->lsi_table
[i
].irq
= irq
;
1261 /* allocate connectors for child PCI devices */
1262 if (sphb
->dr_enabled
) {
1263 for (i
= 0; i
< PCI_SLOT_MAX
* 8; i
++) {
1264 spapr_dr_connector_new(OBJECT(phb
),
1265 SPAPR_DR_CONNECTOR_TYPE_PCI
,
1266 (sphb
->index
<< 16) | i
);
1270 if (!info
->finish_realize
) {
1271 error_setg(errp
, "finish_realize not defined");
1275 info
->finish_realize(sphb
, errp
);
1277 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
1280 static void spapr_phb_finish_realize(sPAPRPHBState
*sphb
, Error
**errp
)
1282 sPAPRTCETable
*tcet
;
1285 nb_table
= SPAPR_PCI_DMA32_SIZE
>> SPAPR_TCE_PAGE_SHIFT
;
1286 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
,
1287 0, SPAPR_TCE_PAGE_SHIFT
, nb_table
, false);
1289 error_setg(errp
, "Unable to create TCE table for %s",
1294 /* Register default 32bit DMA window */
1295 memory_region_add_subregion(&sphb
->iommu_root
, 0,
1296 spapr_tce_get_iommu(tcet
));
1299 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
1301 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
1310 static void spapr_phb_reset(DeviceState
*qdev
)
1312 /* Reset the IOMMU state */
1313 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
1316 static Property spapr_phb_properties
[] = {
1317 DEFINE_PROP_UINT32("index", sPAPRPHBState
, index
, -1),
1318 DEFINE_PROP_UINT64("buid", sPAPRPHBState
, buid
, -1),
1319 DEFINE_PROP_UINT32("liobn", sPAPRPHBState
, dma_liobn
, -1),
1320 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState
, mem_win_addr
, -1),
1321 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState
, mem_win_size
,
1322 SPAPR_PCI_MMIO_WIN_SIZE
),
1323 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState
, io_win_addr
, -1),
1324 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState
, io_win_size
,
1325 SPAPR_PCI_IO_WIN_SIZE
),
1326 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState
, dr_enabled
,
1328 DEFINE_PROP_END_OF_LIST(),
1331 static const VMStateDescription vmstate_spapr_pci_lsi
= {
1332 .name
= "spapr_pci/lsi",
1334 .minimum_version_id
= 1,
1335 .fields
= (VMStateField
[]) {
1336 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
),
1338 VMSTATE_END_OF_LIST()
1342 static const VMStateDescription vmstate_spapr_pci_msi
= {
1343 .name
= "spapr_pci/msi",
1345 .minimum_version_id
= 1,
1346 .fields
= (VMStateField
[]) {
1347 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
1348 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
1349 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
1350 VMSTATE_END_OF_LIST()
1354 static void spapr_pci_fill_msi_devs(gpointer key
, gpointer value
,
1357 sPAPRPHBState
*sphb
= opaque
;
1359 sphb
->msi_devs
[sphb
->msi_devs_num
].key
= *(uint32_t *)key
;
1360 sphb
->msi_devs
[sphb
->msi_devs_num
].value
= *(spapr_pci_msi
*)value
;
1361 sphb
->msi_devs_num
++;
1364 static void spapr_pci_pre_save(void *opaque
)
1366 sPAPRPHBState
*sphb
= opaque
;
1369 if (sphb
->msi_devs
) {
1370 g_free(sphb
->msi_devs
);
1371 sphb
->msi_devs
= NULL
;
1373 sphb
->msi_devs_num
= 0;
1374 msi_devs_num
= g_hash_table_size(sphb
->msi
);
1375 if (!msi_devs_num
) {
1378 sphb
->msi_devs
= g_malloc(msi_devs_num
* sizeof(spapr_pci_msi_mig
));
1380 g_hash_table_foreach(sphb
->msi
, spapr_pci_fill_msi_devs
, sphb
);
1381 assert(sphb
->msi_devs_num
== msi_devs_num
);
1384 static int spapr_pci_post_load(void *opaque
, int version_id
)
1386 sPAPRPHBState
*sphb
= opaque
;
1387 gpointer key
, value
;
1390 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
1391 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
1392 sizeof(sphb
->msi_devs
[i
].key
));
1393 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
1394 sizeof(sphb
->msi_devs
[i
].value
));
1395 g_hash_table_insert(sphb
->msi
, key
, value
);
1397 if (sphb
->msi_devs
) {
1398 g_free(sphb
->msi_devs
);
1399 sphb
->msi_devs
= NULL
;
1401 sphb
->msi_devs_num
= 0;
1406 static const VMStateDescription vmstate_spapr_pci
= {
1407 .name
= "spapr_pci",
1409 .minimum_version_id
= 2,
1410 .pre_save
= spapr_pci_pre_save
,
1411 .post_load
= spapr_pci_post_load
,
1412 .fields
= (VMStateField
[]) {
1413 VMSTATE_UINT64_EQUAL(buid
, sPAPRPHBState
),
1414 VMSTATE_UINT32_EQUAL(dma_liobn
, sPAPRPHBState
),
1415 VMSTATE_UINT64_EQUAL(mem_win_addr
, sPAPRPHBState
),
1416 VMSTATE_UINT64_EQUAL(mem_win_size
, sPAPRPHBState
),
1417 VMSTATE_UINT64_EQUAL(io_win_addr
, sPAPRPHBState
),
1418 VMSTATE_UINT64_EQUAL(io_win_size
, sPAPRPHBState
),
1419 VMSTATE_STRUCT_ARRAY(lsi_table
, sPAPRPHBState
, PCI_NUM_PINS
, 0,
1420 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
1421 VMSTATE_INT32(msi_devs_num
, sPAPRPHBState
),
1422 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, sPAPRPHBState
, msi_devs_num
, 0,
1423 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
1424 VMSTATE_END_OF_LIST()
1428 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
1431 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
1433 return sphb
->dtbusname
;
1436 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
1438 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
1439 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1440 sPAPRPHBClass
*spc
= SPAPR_PCI_HOST_BRIDGE_CLASS(klass
);
1441 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
1443 hc
->root_bus_path
= spapr_phb_root_bus_path
;
1444 dc
->realize
= spapr_phb_realize
;
1445 dc
->props
= spapr_phb_properties
;
1446 dc
->reset
= spapr_phb_reset
;
1447 dc
->vmsd
= &vmstate_spapr_pci
;
1448 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1449 dc
->cannot_instantiate_with_device_add_yet
= false;
1450 spc
->finish_realize
= spapr_phb_finish_realize
;
1451 hp
->plug
= spapr_phb_hot_plug_child
;
1452 hp
->unplug
= spapr_phb_hot_unplug_child
;
1455 static const TypeInfo spapr_phb_info
= {
1456 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
1457 .parent
= TYPE_PCI_HOST_BRIDGE
,
1458 .instance_size
= sizeof(sPAPRPHBState
),
1459 .class_init
= spapr_phb_class_init
,
1460 .class_size
= sizeof(sPAPRPHBClass
),
1461 .interfaces
= (InterfaceInfo
[]) {
1462 { TYPE_HOTPLUG_HANDLER
},
1467 PCIHostState
*spapr_create_phb(sPAPREnvironment
*spapr
, int index
)
1471 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1472 qdev_prop_set_uint32(dev
, "index", index
);
1473 qdev_init_nofail(dev
);
1475 return PCI_HOST_BRIDGE(dev
);
1478 int spapr_populate_pci_dt(sPAPRPHBState
*phb
,
1479 uint32_t xics_phandle
,
1482 int bus_off
, i
, j
, ret
;
1484 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
1485 const uint64_t mmiosize
= memory_region_size(&phb
->memwindow
);
1486 const uint64_t w32max
= (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET
;
1487 const uint64_t w32size
= MIN(w32max
, mmiosize
);
1488 const uint64_t w64size
= (mmiosize
> w32size
) ? (mmiosize
- w32size
) : 0;
1494 } QEMU_PACKED ranges
[] = {
1496 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
1497 cpu_to_be64(phb
->io_win_addr
),
1498 cpu_to_be64(memory_region_size(&phb
->iospace
)),
1501 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
1502 cpu_to_be64(phb
->mem_win_addr
),
1503 cpu_to_be64(w32size
),
1506 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32),
1507 cpu_to_be64(phb
->mem_win_addr
+ w32size
),
1508 cpu_to_be64(w64size
)
1511 const unsigned sizeof_ranges
= (w64size
? 3 : 2) * sizeof(ranges
[0]);
1512 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
1513 uint32_t interrupt_map_mask
[] = {
1514 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
1515 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
1516 sPAPRTCETable
*tcet
;
1518 /* Start populating the FDT */
1519 sprintf(nodename
, "pci@%" PRIx64
, phb
->buid
);
1520 bus_off
= fdt_add_subnode(fdt
, 0, nodename
);
1525 /* Write PHB properties */
1526 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
1527 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
1528 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
1529 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
1530 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
1531 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
1532 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
1533 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
1534 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
1535 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
1536 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", XICS_IRQS
));
1538 /* Build the interrupt-map, this must matches what is done
1539 * in pci_spapr_map_irq
1541 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
1542 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
1543 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
1544 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
1545 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
1546 int lsi_num
= pci_spapr_swizzle(i
, j
);
1548 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
1551 irqmap
[3] = cpu_to_be32(j
+1);
1552 irqmap
[4] = cpu_to_be32(xics_phandle
);
1553 irqmap
[5] = cpu_to_be32(phb
->lsi_table
[lsi_num
].irq
);
1554 irqmap
[6] = cpu_to_be32(0x8);
1557 /* Write interrupt map */
1558 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
1559 sizeof(interrupt_map
)));
1561 tcet
= spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb
->index
, 0));
1562 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
1563 tcet
->liobn
, tcet
->bus_offset
,
1564 tcet
->nb_table
<< tcet
->page_shift
);
1566 ret
= spapr_drc_populate_dt(fdt
, bus_off
, OBJECT(phb
),
1567 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1575 void spapr_pci_rtas_init(void)
1577 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
1578 rtas_read_pci_config
);
1579 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
1580 rtas_write_pci_config
);
1581 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
1582 rtas_ibm_read_pci_config
);
1583 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
1584 rtas_ibm_write_pci_config
);
1585 if (msi_supported
) {
1586 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
1587 "ibm,query-interrupt-source-number",
1588 rtas_ibm_query_interrupt_source_number
);
1589 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
1590 rtas_ibm_change_msi
);
1593 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
1594 "ibm,set-eeh-option",
1595 rtas_ibm_set_eeh_option
);
1596 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
1597 "ibm,get-config-addr-info2",
1598 rtas_ibm_get_config_addr_info2
);
1599 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
1600 "ibm,read-slot-reset-state2",
1601 rtas_ibm_read_slot_reset_state2
);
1602 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
1603 "ibm,set-slot-reset",
1604 rtas_ibm_set_slot_reset
);
1605 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
1607 rtas_ibm_configure_pe
);
1608 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
1609 "ibm,slot-error-detail",
1610 rtas_ibm_slot_error_detail
);
1613 static void spapr_pci_register_types(void)
1615 type_register_static(&spapr_phb_info
);
1618 type_init(spapr_pci_register_types
)
1620 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
1622 bool be
= *(bool *)opaque
;
1624 if (object_dynamic_cast(OBJECT(dev
), "VGA")
1625 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
1626 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
1632 void spapr_pci_switch_vga(bool big_endian
)
1634 sPAPRPHBState
*sphb
;
1637 * For backward compatibility with existing guests, we switch
1638 * the endianness of the VGA controller when changing the guest
1641 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
1642 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
1643 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,