2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, Error
**errp
)
98 Error
*local_err
= NULL
;
100 obj
= object_new(TYPE_ICS_SPAPR
);
101 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
102 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
104 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
,
105 "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_SPAPR(obj
);
115 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
118 ICSState
*ics
= spapr
->ics
;
121 assert(ics_valid_irq(ics
, irq
));
123 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
124 error_setg(errp
, "IRQ %d is not free", irq
);
128 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
132 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
)
134 ICSState
*ics
= spapr
->ics
;
135 uint32_t srcno
= irq
- ics
->offset
;
137 assert(ics_valid_irq(ics
, irq
));
139 memset(&ics
->irqs
[srcno
], 0, sizeof(ICSIRQState
));
142 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
147 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
149 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
152 ics_pic_print_info(spapr
->ics
, mon
);
155 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
156 PowerPCCPU
*cpu
, Error
**errp
)
158 Error
*local_err
= NULL
;
160 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
162 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
165 error_propagate(errp
, local_err
);
169 spapr_cpu
->icp
= ICP(obj
);
172 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
174 if (!kvm_irqchip_in_kernel()) {
177 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
178 icp_resend(spapr_cpu_state(cpu
)->icp
);
184 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
186 SpaprMachineState
*spapr
= opaque
;
187 uint32_t srcno
= irq
- spapr
->ics
->offset
;
189 ics_set_irq(spapr
->ics
, srcno
, val
);
192 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
194 Error
*local_err
= NULL
;
196 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
198 error_propagate(errp
, local_err
);
203 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
206 xics_kvm_connect(spapr
, errp
);
210 SpaprIrq spapr_irq_xics
= {
211 .nr_xirqs
= SPAPR_NR_XIRQS
,
212 .nr_msis
= SPAPR_NR_MSIS
,
216 .init
= spapr_irq_init_xics
,
217 .claim
= spapr_irq_claim_xics
,
218 .free
= spapr_irq_free_xics
,
219 .print_info
= spapr_irq_print_info_xics
,
220 .dt_populate
= spapr_dt_xics
,
221 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
222 .post_load
= spapr_irq_post_load_xics
,
223 .reset
= spapr_irq_reset_xics
,
224 .set_irq
= spapr_irq_set_irq_xics
,
225 .init_kvm
= spapr_irq_init_kvm_xics
,
231 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, Error
**errp
)
233 uint32_t nr_servers
= spapr_max_server_number(spapr
);
237 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
238 qdev_prop_set_uint32(dev
, "nr-irqs",
239 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
241 * 8 XIVE END structures per CPU. One for each available priority
243 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
244 qdev_init_nofail(dev
);
246 spapr
->xive
= SPAPR_XIVE(dev
);
248 /* Enable the CPU IPIs */
249 for (i
= 0; i
< nr_servers
; ++i
) {
250 if (spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
,
256 spapr_xive_hcall_init(spapr
);
259 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
262 return spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
, errp
);
265 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
)
267 spapr_xive_irq_free(spapr
->xive
, irq
);
270 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
276 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
278 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
281 spapr_xive_pic_print_info(spapr
->xive
, mon
);
284 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
285 PowerPCCPU
*cpu
, Error
**errp
)
287 Error
*local_err
= NULL
;
289 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
291 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
293 error_propagate(errp
, local_err
);
297 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
300 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
301 * don't beneficiate from the reset of the XIVE IRQ backend
303 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
306 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
308 return spapr_xive_post_load(spapr
->xive
, version_id
);
311 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
314 Error
*local_err
= NULL
;
317 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
319 /* (TCG) Set the OS CAM line of the thread interrupt context. */
320 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
323 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
325 error_propagate(errp
, local_err
);
329 /* Activate the XIVE MMIOs */
330 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
333 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
335 SpaprMachineState
*spapr
= opaque
;
337 if (kvm_irqchip_in_kernel()) {
338 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
340 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
344 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
347 kvmppc_xive_connect(spapr
->xive
, errp
);
351 SpaprIrq spapr_irq_xive
= {
352 .nr_xirqs
= SPAPR_NR_XIRQS
,
353 .nr_msis
= SPAPR_NR_MSIS
,
357 .init
= spapr_irq_init_xive
,
358 .claim
= spapr_irq_claim_xive
,
359 .free
= spapr_irq_free_xive
,
360 .print_info
= spapr_irq_print_info_xive
,
361 .dt_populate
= spapr_dt_xive
,
362 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
363 .post_load
= spapr_irq_post_load_xive
,
364 .reset
= spapr_irq_reset_xive
,
365 .set_irq
= spapr_irq_set_irq_xive
,
366 .init_kvm
= spapr_irq_init_kvm_xive
,
370 * Dual XIVE and XICS IRQ backend.
372 * Both interrupt mode, XIVE and XICS, objects are created but the
373 * machine starts in legacy interrupt mode (XICS). It can be changed
374 * by the CAS negotiation process and, in that case, the new mode is
375 * activated after an extra machine reset.
379 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
382 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
384 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
385 &spapr_irq_xive
: &spapr_irq_xics
;
388 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, Error
**errp
)
390 Error
*local_err
= NULL
;
392 spapr_irq_xics
.init(spapr
, &local_err
);
394 error_propagate(errp
, local_err
);
398 spapr_irq_xive
.init(spapr
, &local_err
);
400 error_propagate(errp
, local_err
);
405 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
408 Error
*local_err
= NULL
;
411 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
413 error_propagate(errp
, local_err
);
417 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
419 error_propagate(errp
, local_err
);
426 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
)
428 spapr_irq_xics
.free(spapr
, irq
);
429 spapr_irq_xive
.free(spapr
, irq
);
432 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
434 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
437 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
438 uint32_t nr_servers
, void *fdt
,
441 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
444 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
445 PowerPCCPU
*cpu
, Error
**errp
)
447 Error
*local_err
= NULL
;
449 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
451 error_propagate(errp
, local_err
);
455 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
458 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
461 * Force a reset of the XIVE backend after migration. The machine
462 * defaults to XICS at startup.
464 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
465 if (kvm_irqchip_in_kernel()) {
466 xics_kvm_disconnect(spapr
, &error_fatal
);
468 spapr_irq_xive
.reset(spapr
, &error_fatal
);
471 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
474 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
476 Error
*local_err
= NULL
;
479 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
482 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
484 /* Destroy all KVM devices */
485 if (kvm_irqchip_in_kernel()) {
486 xics_kvm_disconnect(spapr
, &local_err
);
488 error_propagate(errp
, local_err
);
489 error_prepend(errp
, "KVM XICS disconnect failed: ");
492 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
494 error_propagate(errp
, local_err
);
495 error_prepend(errp
, "KVM XIVE disconnect failed: ");
500 spapr_irq_current(spapr
)->reset(spapr
, errp
);
503 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
505 SpaprMachineState
*spapr
= opaque
;
507 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
511 * Define values in sync with the XIVE and XICS backend
513 SpaprIrq spapr_irq_dual
= {
514 .nr_xirqs
= SPAPR_NR_XIRQS
,
515 .nr_msis
= SPAPR_NR_MSIS
,
519 .init
= spapr_irq_init_dual
,
520 .claim
= spapr_irq_claim_dual
,
521 .free
= spapr_irq_free_dual
,
522 .print_info
= spapr_irq_print_info_dual
,
523 .dt_populate
= spapr_irq_dt_populate_dual
,
524 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
525 .post_load
= spapr_irq_post_load_dual
,
526 .reset
= spapr_irq_reset_dual
,
527 .set_irq
= spapr_irq_set_irq_dual
,
528 .init_kvm
= NULL
, /* should not be used */
532 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
534 MachineState
*machine
= MACHINE(spapr
);
537 * Sanity checks on non-P9 machines. On these, XIVE is not
538 * advertised, see spapr_dt_ov5_platform_support()
540 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
541 0, spapr
->max_compat_pvr
)) {
543 * If the 'dual' interrupt mode is selected, force XICS as CAS
544 * negotiation is useless.
546 if (spapr
->irq
== &spapr_irq_dual
) {
547 spapr
->irq
= &spapr_irq_xics
;
552 * Non-P9 machines using only XIVE is a bogus setup. We have two
553 * scenarios to take into account because of the compat mode:
555 * 1. POWER7/8 machines should fail to init later on when creating
556 * the XIVE interrupt presenters because a POWER9 exception
559 * 2. POWER9 machines using the POWER8 compat mode won't fail and
560 * will let the OS boot with a partial XIVE setup : DT
561 * properties but no hcalls.
563 * To cover both and not confuse the OS, add an early failure in
566 if (spapr
->irq
== &spapr_irq_xive
) {
567 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
573 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
574 * re-created. Detect that early to avoid QEMU to exit later when the
578 spapr
->irq
== &spapr_irq_dual
&&
579 machine_kernel_irqchip_required(machine
) &&
580 xics_kvm_has_broken_disconnect(spapr
)) {
581 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
587 * sPAPR IRQ frontend routines for devices
589 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
591 MachineState
*machine
= MACHINE(spapr
);
592 Error
*local_err
= NULL
;
594 if (machine_kernel_irqchip_split(machine
)) {
595 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
599 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
601 "kernel_irqchip requested but only available with KVM");
605 spapr_irq_check(spapr
, &local_err
);
607 error_propagate(errp
, local_err
);
611 /* Initialize the MSI IRQ allocator. */
612 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
613 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
616 spapr
->irq
->init(spapr
, errp
);
618 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
619 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
622 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
624 assert(irq
>= SPAPR_XIRQ_BASE
);
625 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
627 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
630 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
634 assert(irq
>= SPAPR_XIRQ_BASE
);
635 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
637 for (i
= irq
; i
< (irq
+ num
); i
++) {
638 spapr
->irq
->free(spapr
, i
);
642 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
645 * This interface is basically for VIO and PHB devices to find the
646 * right qemu_irq to manipulate, so we only allow access to the
647 * external irqs for now. Currently anything which needs to
648 * access the IPIs most naturally gets there via the guest side
649 * interfaces, we can change this if we need to in future.
651 assert(irq
>= SPAPR_XIRQ_BASE
);
652 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
655 assert(ics_valid_irq(spapr
->ics
, irq
));
658 assert(irq
< spapr
->xive
->nr_irqs
);
659 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
662 return spapr
->qirqs
[irq
];
665 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
667 return spapr
->irq
->post_load(spapr
, version_id
);
670 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
672 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
674 if (spapr
->irq
->reset
) {
675 spapr
->irq
->reset(spapr
, errp
);
679 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
681 const char *nodename
= "interrupt-controller";
684 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
686 error_setg(errp
, "Can't find node \"%s\": %s",
687 nodename
, fdt_strerror(offset
));
691 phandle
= fdt_get_phandle(fdt
, offset
);
693 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
701 * XICS legacy routines - to deprecate one day
704 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
708 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
709 if (num
> (ics
->nr_irqs
- first
)) {
712 for (i
= first
; i
< first
+ num
; ++i
) {
713 if (!ics_irq_free(ics
, i
)) {
717 if (i
== (first
+ num
)) {
725 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
727 ICSState
*ics
= spapr
->ics
;
733 * MSIMesage::data is used for storing VIRQ so
734 * it has to be aligned to num to support multiple
735 * MSI vectors. MSI-X is not affected by this.
736 * The hint is used for the first IRQ, the rest should
737 * be allocated continuously.
740 assert((num
== 1) || (num
== 2) || (num
== 4) ||
741 (num
== 8) || (num
== 16) || (num
== 32));
742 first
= ics_find_free_block(ics
, num
, num
);
744 first
= ics_find_free_block(ics
, num
, 1);
748 error_setg(errp
, "can't find a free %d-IRQ block", num
);
752 return first
+ ics
->offset
;
755 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
757 SpaprIrq spapr_irq_xics_legacy
= {
758 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
759 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
763 .init
= spapr_irq_init_xics
,
764 .claim
= spapr_irq_claim_xics
,
765 .free
= spapr_irq_free_xics
,
766 .print_info
= spapr_irq_print_info_xics
,
767 .dt_populate
= spapr_dt_xics
,
768 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
769 .post_load
= spapr_irq_post_load_xics
,
770 .reset
= spapr_irq_reset_xics
,
771 .set_irq
= spapr_irq_set_irq_xics
,
772 .init_kvm
= spapr_irq_init_kvm_xics
,